WO2019043895A1 - シリコンウェーハの両面研磨方法 - Google Patents
シリコンウェーハの両面研磨方法 Download PDFInfo
- Publication number
- WO2019043895A1 WO2019043895A1 PCT/JP2017/031496 JP2017031496W WO2019043895A1 WO 2019043895 A1 WO2019043895 A1 WO 2019043895A1 JP 2017031496 W JP2017031496 W JP 2017031496W WO 2019043895 A1 WO2019043895 A1 WO 2019043895A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- polishing
- double
- silicon wafer
- liquid
- plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H10P52/00—
-
- H10P90/124—
-
- H10P90/129—
Definitions
- the present invention relates to a double-side polishing method for a silicon wafer in which the front and back surfaces of the silicon wafer are simultaneously polished.
- the process for producing a silicon wafer mainly includes a single crystal pulling-up step for producing a single crystal ingot and a processing step of the produced single crystal ingot.
- This processing step generally includes a slicing step, a lapping step, a chamfering step, an etching step, a polishing step, a cleaning step, and the like, and a silicon wafer having a mirror-finished surface is manufactured through these steps.
- CMP mechanochemical polishing
- the mechanical polishing action by the abrasive grains in the polishing solution and the chemical polishing action by the polishing solution are combined, and it is known that excellent smoothness can be obtained.
- a double-sided polishing step (rough polishing step) for simultaneously polishing the front and back surfaces of a silicon wafer using a double-sided polishing apparatus as shown in FIG. 5 and a final polishing step for mirror polishing at least one surface of the silicon wafer thereafter Such multistage polishing is performed.
- Rough polishing in the initial stage is performed for the purpose of polishing a silicon wafer to a desired thickness, and polishing is performed using a hard polishing cloth such as polyurethane under a condition where the polishing rate is relatively fast, and silicon after polishing Double-side polishing is performed to reduce variation in wafer thickness and planarize the wafer.
- the final polishing step is intended to improve the roughness of the silicon wafer surface, using soft abrasive cloth such as suede and fine sized loose abrasives, silicon such as nanotopography and haze Single-side polishing is performed to reduce minute variations in surface roughness on the wafer surface.
- Patent Document 1 has a rough polishing step of simultaneously polishing the front and back surfaces of a silicon wafer, and a final polishing step of finish polishing the rough polished surface thereafter.
- the rough polishing is performed by primary polishing in which a natural oxide film is removed using a polishing solution containing loose abrasive particles, and an amine aqueous solution containing no loose abrasive particles after the primary polishing.
- a silicon wafer comprising secondary polishing in which the front and back surfaces of the silicon wafer from which the natural oxide film has been removed are polished to have a polishing amount of 5 to 10 ⁇ m on one side using a polishing solution to which a water-soluble polymer is added.
- the polishing method of is described.
- secondary polish is performed using the double-sided polish device used for primary polish.
- Patent No. 5754659 gazette
- the two-step rough polishing described in Patent Document 1 is performed based on the following design concept. That is, in the rough polishing process using the double-side polishing apparatus, the polishing amount of the outer peripheral portion is likely to be larger than that of the central portion of the wafer, and as a result, the outer peripheral portion of the wafer becomes a problem. Therefore, in Patent Document 1, rough polishing is performed using a polishing solution that does not contain abrasive grains and that contains a water-soluble polymer, and the amount of sag on the outer peripheral portion of the wafer (ROA: Roll Off Amount) by the action of this water-soluble polymer. ) Is suppressed.
- ROA Roll Off Amount
- Example 1 of Patent Document 1 the primary polishing with a polishing amount of 0.5 ⁇ m on one side (1 ⁇ m on both sides) including the removal of the natural oxide film, and then the secondary polishing with a polishing amount of 5 ⁇ m on one side (10 ⁇ m on both surfaces) It is carried out.
- an object of this invention is to provide the double-sided polishing method of the silicon wafer which can suppress that micro scratch generate
- double-side polishing it is general to collect used polishing liquid, return it to a polishing liquid supply tank and circulate it, and use it repeatedly as a polishing liquid. Therefore, when primary polishing and secondary polishing are performed with a common double-side polishing apparatus, after primary polishing is finished, polishing cloth is used so that the polishing liquid used in primary polishing and the polishing liquid used in secondary polishing do not mix. It is conceivable to stop the supply of the polishing solution and supply pure water to the polishing pad to remove the abrasive grains attached to the wafer and the carrier plate, and further to wash the polishing pad with high pressure water.
- the present invention has been completed based on the above findings, and the gist configuration is as follows. (1) Both sides having a carrier plate having one or more holding holes for holding a silicon wafer, and an upper surface plate and a lower surface plate opposite to each other with the carrier plate interposed therebetween and provided with a polishing cloth on the surface The upper surface plate and the lower surface plate, and the surface plate and the lower surface plate, with the polishing cloths of the upper surface plate and the lower surface plate being in contact with the front and back surfaces of the silicon wafer loaded in the holding holes using a polishing apparatus.
- a double-side polishing method for a silicon wafer wherein the front and back surfaces of the silicon wafer are simultaneously polished by rotating the carrier plate relative to the carrier plate,
- a method for double-sided polishing of a silicon wafer characterized in that
- the first polishing step double-sided polishing is performed with a first surface pressure, and the surface pressure is reduced at the end of the polishing, to a second surface pressure lower than the first surface pressure at the end of the surface pressure, The method for double-sided polishing of a silicon wafer according to (1), wherein double-sided polishing is performed at the second surface pressure in the second polishing step.
- double-side polishing is performed with a polishing amount of 80% to 99.5% of the total polishing amount in the first and second polishing steps
- the first polishing step after the used first polishing liquid is recovered, it is supplied again to the polishing pad, In the second polishing step, the used polishing liquid is recovered and then discarded, and the double-side polishing method for a silicon wafer according to any one of the above (1) to (4).
- the double-side polishing method for a silicon wafer of the present invention the generation of microscratches on the front and back surfaces of the silicon wafer after polishing can be suppressed.
- FIG. 2 is a flow diagram of a method for double-sided polishing of a silicon wafer according to an embodiment of the present invention.
- FIG. 6 is a flowchart of a method for polishing silicon wafers on both sides according to Comparative Example 1;
- FIG. 8 is a flowchart of a method for polishing silicon wafers on both sides according to Comparative Example 2; It is a figure explaining switching of the surface pressure added to a silicon wafer, switching of a slurry supply, and switching of the processing method of a used polishing liquid in the double-sided grinding method of the silicon wafer by one Embodiment of this invention.
- FIG. 1 is a schematic view of a double-sided polishing apparatus 100 used in a double-sided polishing method of a silicon wafer according to an embodiment of the present invention.
- the double-side polishing apparatus 100 has a carrier plate 10, and an upper surface plate 14 and a lower surface plate 16 positioned opposite to each other with the carrier plate 10 interposed therebetween.
- the carrier plate 10 is provided with a plurality of holding holes 12 (one representatively shown in FIG. 5) for holding the silicon wafers W, and the silicon wafers W are loaded one by one here.
- Abrasive cloths 18 and 20 are provided on the surfaces of the upper and lower surface plates 14 and 16, respectively.
- a sun gear 22 is provided at the central portion of the upper and lower surface plates 14 and 16, and an internal gear 24 is provided at the outer peripheral portion.
- the polishing liquid is supplied from the polishing liquid supply line 26 between the upper and lower surface plates 14 and 16 via a flow path penetrating the upper surface plate 14 in the vertical direction.
- the details of the polishing liquid supply and recovery mechanism will be described later.
- this double-side polishing apparatus 100 a plurality of silicon wafers W loaded in the plurality of holes 12 are sandwiched between the upper surface plate 14 and the lower surface plate 16 and the polishing cloths 18 and 20 are brought into contact with the front and back surfaces of the silicon wafer W, respectively.
- the upper surface plate 14 and the lower surface plate 16 and the carrier plate 10 are relatively rotated by rotating the sun gear 22 and the internal gear 24. Thereby, the front and back surfaces of the plurality of silicon wafers W can be polished simultaneously.
- the configuration of the double-side polishing apparatus that can be used for the double-side polishing method of a silicon wafer according to the present invention is not limited to the above, and a sun gear (planet gear) type or carrier plate performs circular motion without rotation.
- a sun gear system can be adopted.
- a first polishing process is performed in which double-sided polishing is performed while supplying a first polishing solution made of an alkaline aqueous solution containing abrasive grains to the polishing pads 18 and 20.
- a second polishing liquid comprising an alkaline aqueous solution not containing abrasive particles and containing a water-soluble polymer to the polishing pads 18 and 20;
- a second polishing step is performed.
- the natural oxide film having a thickness of about 5 to 20 ⁇ formed on the surface layer of the silicon wafer W is removed by a polishing solution containing abrasive grains, The purpose is to polish the wafer W.
- the total polishing amount in the first and second polishing steps is set in the range of approximately 2.5 ⁇ m to 10 ⁇ m per side.
- double-side polishing with a polishing amount of 80% to 99.5% of the total polishing amount in the first and second polishing steps is performed. If the polishing amount in the first polishing step is less than 80% of the total polishing amount, it is necessary to perform many second polishing steps having a low polishing rate to achieve the target thickness, which impairs productivity. On the other hand, when the polishing amount in the first polishing step exceeds 99.5% of the total polishing amount, the polishing removal amount in the second polishing step becomes too small, so the amount of sagging in the outer peripheral portion of the wafer is suppressed. Effect is not enough.
- the polishing of the outer peripheral portion of the wafer is performed by slightly polishing both surfaces of the silicon wafer W using a polishing solution which does not contain abrasive grains and contains a water-soluble polymer.
- the purpose is to control the amount.
- double-side polishing with a polishing amount of 0.05 ⁇ m to 0.5 ⁇ m per side is performed. If the amount of polishing per side is less than 0.05 ⁇ m, the effect of suppressing the amount of sagging of the outer peripheral portion of the wafer is not sufficient.
- the polishing rate which does not contain abrasive grains and which contains a water-soluble polymer has a low polishing rate, if the polishing amount per one side exceeds 0.5 ⁇ m, productivity is impaired.
- the primary polishing using a polishing solution containing abrasive grains is mainly intended to remove a natural oxide film, so the polishing amount is 0.5 ⁇ m per side, and it does not contain abrasive grains.
- the target thickness is achieved by performing double-side polishing with a polishing amount of 5 to 10 ⁇ m on one side by secondary polishing using a polishing solution containing a water-soluble polymer.
- high productivity is realized by mainly performing primary polishing with a high polishing rate to achieve a target thickness.
- the secondary polishing if the polishing amount of 0.05 ⁇ m or more per one surface is secured, the amount of sagging of the outer peripheral portion of the wafer can be sufficiently suppressed.
- both the first polishing liquid and the second polishing liquid have a pH adjusted in the range of 9-12. If the pH is less than 9, the etching action becomes too low, and processing defects such as scratches and scratches are easily generated on the surface of the silicon wafer. When the pH exceeds 12, handling of the solution itself becomes difficult.
- the alkaline agent it is preferable to use an alkaline aqueous solution or an alkaline carbonate aqueous solution to which any of a basic ammonium salt, a basic potassium salt and a basic sodium salt is added, or an alkaline aqueous solution to which an amine is added.
- an aqueous solution of hydrazine or amines can be employed, and from the viewpoint of enhancing the polishing rate, it is particularly desirable to use an amine.
- the abrasive those made of silica, alumina, diamond, etc. can be used, but reasons such as low cost, dispersibility in the polishing liquid, ease of controlling particle diameter of abrasive, etc. It is preferable to contain SiO 2 particles.
- the average primary particle size of the abrasive grains can be 30 to 100 nm as measured by the BET method.
- the water-soluble polymer it is preferable to use one or more selected from nonionics.
- nonionics examples include hydroxyethyl cellulose (HEC), polyethylene glycol (PEG), and polypropylene glycol (PPG).
- the concentration of the water-soluble polymer is preferably 1 ppm or more, and more preferably 10 ppm or more, from the viewpoint of sufficiently suppressing the amount of sagging of the outer peripheral portion of the wafer.
- 200 ppm or less is preferable, and 100 ppm or less is more preferable.
- polishing cloths 18 and 20 examples include polishing cloths made of non-woven cloth made of polyester, polishing cloths made of polyurethane, and the like, and in particular, polishing cloth made of foamable polyurethane excellent in mirror surface precision of polishing surface of silicon wafer. Is desirable.
- the polishing cloths 18 and 20 preferably have a Shore D hardness of 70 to 90 and a compression ratio of 1 to 5%, particularly 2 to 3%, as defined by JIS K 6253-1997 / ISO 7619.
- the polishing rate in the first polishing step is preferably 0.1 to 1.0 ⁇ m / min, and the polishing rate in the second polishing step is 0.03 to 0.5 ⁇ m / min. preferable.
- the rotational speed of the upper and lower surface plates, the rotational speed of the silicon wafer, the surface pressure, and the supply amount of the polishing liquid may be appropriately set so as to realize the above-mentioned polishing rate.
- the rotational speed of the upper and lower platens can be in the range of 5 rpm to 40 rpm throughout the first and second polishing steps.
- the surface pressure may be set in the range of 50 g / cm 2 to 300 g / cm 2 , and in the second polishing step, a polishing liquid containing no abrasive is used to increase the frictional resistance. It is desirable to set the surface pressure in the second polishing process to be 5% to 40% lower than the surface pressure in.
- the present embodiment is characterized in the switching method between the first polishing liquid and the second polishing liquid when the first polishing step and the second polishing step are performed using the same double-side polishing apparatus 100 in common.
- a double-side polishing method according to Comparative Examples 1 and 2 will be described with reference to FIGS.
- the first polishing liquid is supplied while the upper and lower platens are in contact with the wafer (landing) and are rotated.
- the polishing process is performed (step S1), and the supply of the first polishing liquid is stopped after the set time has elapsed.
- pure water rinse treatment and polishing cloth cleaning are performed after the first polishing step so that the first polishing liquid is not mixed with the second polishing liquid.
- pure water is supplied from the upper surface plate to the polishing cloth while the upper and lower surface plates are attached to the wafer and rotated, thereby removing the abrasive grains attached to the wafer and the carrier plate (step S2).
- step S3 stop the rotation of the upper and lower surface plates and stop the supply of pure water, then raise the upper surface plate to separate the upper surface plate from the wafer (release), and from the lower surface plate (on the polishing cloth)
- the carrier plate and the wafer are taken out (step S3).
- high pressure water is sprayed onto the polishing pad to remove polishing debris, abrasive grains and the like adhering to the polishing pad (step S4).
- step S5 After cleaning the polishing cloth, the carrier plate and the silicon wafer are returned to their original positions.
- Step S6 the supply of the second polishing liquid is started, and then the rotation of the upper and lower platens is restarted to perform the second polishing process.
- Step S6 the supply of the second polishing liquid is stopped.
- step S10 a new unpolished wafer is loaded.
- the upper and lower plates are mounted on the wafer, and the rotation is stopped, the supply of the first polishing liquid is started, and thereafter, the process returns to step S1 to perform double-side polishing of the new batch.
- step S2 In the double-side polishing method according to Comparative Example 2, after the first polishing step, in order to shorten the process while preventing the first polishing solution from mixing with the second polishing solution. , Pure water rinse processing is performed (step S2). Thereafter, the supply of the second polishing liquid is started, the rotation of the upper and lower surface plates is restarted, and the second polishing step is performed (step S6).
- the other steps are the same as in FIG. In this method, since the polishing pad cleaning step is not provided between the first polishing step and the second polishing step, it is not necessary to release the upper surface plate from the wafer and re-land the same.
- Step S6 vibration of the carrier plate occurs at the start of the second polishing step. This means that the rotation of the upper and lower platens is resumed without abrasive particles, so the frictional resistance between the wafer and the carrier plate and the polishing pad is increased, and the pressure load from the upper and lower platens to the wafer is large. It is thought that it originates in becoming.
- the second polishing step is directly performed without performing the pure water rinse treatment and the polishing cloth cleaning. That is, after the first polishing step (step S1), the supply of the first polishing liquid is stopped at the same time as stopping the supply of the first polishing liquid while keeping the upper and lower surface plates on the wafer and continuing the rotation. Supply of polishing liquid is started (step S20: polishing liquid switching step). Then, a second polishing step (step S6) is performed.
- the first polishing liquid containing abrasive grains and the second polishing liquid not containing abrasive grains are mixed for a predetermined period of time from the start. Therefore, it is preferable to avoid the recovery, circulation, and reuse of the polishing liquid. Therefore, as shown in FIG. 4, in the first polishing step, the recovery line is turned on to recover the used first polishing liquid, and then supplied again to the polishing pad to start the second polishing step. Sometimes, it is preferable to turn off the recovery line and turn on the waste line, and always discard the used polishing liquid after collecting used polishing liquid in the second polishing step. As described above, in the present embodiment, since the second polishing process is performed for a very short time, the cost of the polishing solution is not significantly increased even if the used polishing solution is not reused.
- a polishing liquid supply and recovery mechanism for realizing such switching of the method of processing used polishing liquid will be described with reference to FIG.
- the first polishing liquid is supplied from the first polishing liquid supply tank 32 to the first polishing liquid supply line 30, and the second polishing liquid is supplied from the second polishing liquid supply tank 36 for the second polishing liquid. It is supplied to the line 34.
- a switching valve 28 is provided at the junction of the lines 30 and 34. By controlling the switching valve, it is possible to control which polishing liquid is supplied to the polishing liquid supply line 26. Meanwhile, the used polishing fluid enters the used polishing fluid recovery line 38 from a recovery mechanism (not shown) located below the lower platen.
- This line 38 is provided with a switching valve 40 and a waste fluid line 46 branched therefrom, and by controlling the switching valve 40, whether the used polishing liquid is transferred to the recovery tank 42 to which the line 38 is connected , Transfer to the waste line 46 can be controlled.
- the spent waste liquid transferred to the recovery tank 42 is returned to the first polishing liquid supply tank 32 via the recycling line 44.
- the switching valve 28 is controlled to supply the first polishing liquid containing abrasive grains from the first polishing liquid supply line 30, and the switching valve 40 is controlled to use the first used polishing agent.
- the polishing liquid is collected in the collection tank 42 and reused.
- the switching valve 28 is controlled to supply the second polishing liquid from the second polishing liquid supply line 34, and the switching valve 40 is controlled to use the used polishing liquid from the waste liquid line 46. Discard.
- the second polishing step is performed using a second polishing solution which does not contain abrasive grains, the frictional resistance between the wafer and the carrier plate and the polishing pad tends to increase. Therefore, with regard to the surface pressure applied by the upper and lower surface plates to the surface of the silicon wafer, in the second polishing step, it is preferable to carry out at a surface pressure lower than that in the first polishing step. Thereby, the vibration of the carrier plate can be reliably prevented. As a result, the occurrence of microscratches on the front and back surfaces of the silicon wafer after polishing can be sufficiently suppressed.
- the first polishing step and the second polishing step are continuously performed, as shown in FIG. 4, the surface pressure is reduced at the end of the first polishing step. At the end of the polishing process, the surface pressure of the second polishing process is reduced.
- the rotational speed of the upper and lower platens was 15 rpm, the surface pressure was 250 g / cm 2 , and the polishing amount was 5 ⁇ m per side.
- the rotational speed of the upper and lower platens was 15 rpm, the surface pressure was 250 g / cm 2 , and the polishing amount was 0.5 ⁇ m per side.
- a 30-second pure water rinse process and a 60-second polishing cloth cleaning process were performed between the first polishing process and the second polishing process.
- the rotational speed of the upper and lower platens was 15 rpm
- the surface pressure was 250 g / cm 2
- the polishing amount was 0.5 ⁇ m per side.
- the recovery line was turned on, and at the start of the second polishing step, the recovery line was turned off and the waste line was turned on.
- micro scratch can be reduced in Inventive Example 1, and micro scratch is further reduced in Inventive Example 2 as compared to Inventive Example 1. We were able to.
- ESFQR edge site front least squares range
- ESFQR targets a unit area (site) obtained by evenly dividing a ring-shaped area along the edge of a wafer in the circumferential direction, and is a reference plane determined by the least-squares method from the thickness distribution in the site It is defined as the difference between the maximum value and the minimum value of deviation from (Site Best Fit Surface).
- site a unit area obtained by evenly dividing a ring-shaped area along the edge of a wafer in the circumferential direction
- the ESFQR of the site where the ring-shaped outer peripheral area set in the range of 2 to 32 mm from the outermost periphery of the wafer (sector length 30 mm) is divided into 72 in the circumferential direction is measured, and the average value ESFQR_mean of all the sites is calculated.
- the double-side polishing method for a silicon wafer of the present invention the generation of microscratches on the front and back surfaces of the silicon wafer after polishing can be suppressed.
- polishing apparatus 100 double-sided polishing apparatus 10 carrier plate 12 holding hole 14 upper surface plate 16 lower surface plate 18, 20 polishing cloth 22 sun gear 24 internal gear 26 polishing liquid supply line 28 switching valve 30 first polishing liquid supply line 32 first polishing liquid supply Tank 34 Second polishing liquid supply line 36 Second polishing liquid supply tank 38 Used polishing liquid recovery line 40 Switching valve 42 Recovery tank 44 Recycling line 46 Waste line W Silicon wafer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Grinding-Machine Dressing And Accessory Apparatuses (AREA)
Abstract
Description
(1)シリコンウェーハを保持する1以上の保持孔を有するキャリアプレートと、前記キャリアプレートを挟んで対向して位置し、表面に研磨布が設けられた上定盤および下定盤と、を有する両面研磨装置を用いて、前記保持孔内に装填したシリコンウェーハの表面および裏面に、それぞれ前記上定盤および前記下定盤の研磨布を接触させた状態で、前記上定盤および前記下定盤と前記キャリアプレートとを相対回転させることで、前記シリコンウェーハの表面および裏面を同時に研磨するシリコンウェーハの両面研磨方法であって、
砥粒を含むアルカリ水溶液からなる第1の研磨液を前記研磨布に供給しながら両面研磨を行う第1の研磨工程と、
前記第1の研磨工程の後、前記シリコンウェーハの表面および裏面に、それぞれ前記上定盤および前記下定盤の研磨布を接触させたまま、かつ、前記上定盤および前記下定盤の回転を継続した状態で、前記第1の研磨液の供給を停止するとともに、砥粒を含まず水溶性高分子を含むアルカリ水溶液からなる第2の研磨液の供給を開始する研磨液切替え工程と、
前記研磨液切り替え工程の後、前記第2の研磨液を前記研磨布に供給しながら両面研磨を行う第2の研磨工程と、
を連続して有することを特徴とするシリコンウェーハの両面研磨方法。
前記第1の研磨工程では、第1の面圧力で両面研磨を行い、その終期において前記面圧力を低下させて、終了時に前記第1の面圧力よりも低い第2の面圧力とし、
前記第2の研磨工程では前記第2の面圧力で両面研磨を行う、上記(1)に記載のシリコンウェーハの両面研磨方法。
前記第2の研磨工程では、片面あたり0.05μm~0.5μmの研磨量の両面研磨を行う、上記(1)~(3)のいずれか一項に記載のシリコンウェーハの両面研磨方法。
前記第2の研磨工程では、使用済みの研磨液を回収した後、廃棄する、上記(1)~(4)のいずれか一項に記載のシリコンウェーハの両面研磨方法。
図5に示す両面研磨装置を用いて、図2に示すフローに従って、直径300mmのシリコンウェーハ(5枚/バッチ×2バッチ=10枚)の両面研磨を行った。第1の研磨液としては、平均一次粒径70nmのコロイダルシリカ粒子を砥粒として5質量%含むKOH水溶液を用いた。第2の研磨液としては、砥粒を含まず、ヒドロキシエチルセルロース(HEC)を10質量ppm含むピペリジン水溶液を用いた。第1の研磨工程では、上下定盤の回転速度を15rpm、面圧力を250g/cm2、研磨量は片面あたり5μmの研磨処理を行った。第2の研磨工程では、上下定盤の回転速度を15rpm、面圧力を250g/cm2、研磨量は片面あたり0.5μmの研磨処理を行った。第1の研磨工程と第2の研磨工程との間に、30秒間の純水リンス工程と、60秒間の研磨布洗浄工程を行った。
図5に示す両面研磨装置を用いて、図3に示すフローに従って、直径300mmのシリコンウェーハ(5枚/バッチ×2バッチ=10枚)の両面研磨を行った。すなわち、第1の研磨工程と第2の研磨工程との間で、研磨布の洗浄を行わなかったこと以外は、比較例1と同様の条件・フローである。
図5に示す両面研磨装置を用いて、図1に示すフローに従って、直径300mmのシリコンウェーハ(5枚/バッチ×2バッチ=10枚)の両面研磨を行った。第1の研磨液および第2の研磨液は、比較例1,2と同じものを用いた。第1の研磨工程では、上下定盤の回転速度を15rpm、面圧力を250g/cm2、研磨量は片面あたり5μmの研磨処理を行った。その後、上下定盤をウェーハに着盤させたまま、かつ、回転を継続した状態で、第1の研磨液の供給を停止したと同時に、第2の研磨液の供給を開始した。第2の研磨工程では、上下定盤の回転速度を15rpm、面圧力を250g/cm2、研磨量は片面あたり0.5μmの研磨処理を行った。図4に示すように、第1の研磨工程では回収ラインをオンにして、第2の研磨工程の開始時には、回収ラインをオフにすると同時に廃棄ラインをオンにした。
図4に示すように、第1の研磨工程の最後の10秒間で面圧力を250g/cm2から200g/cm2に低下させて、第2の研磨工程は面圧力200g/cm2で行った。それ以外は、発明例1と同様の条件・フローで両面研磨を行った。
表面欠陥検査装置(KLA-Tencor社製:Surfscan SP-2)を用いてDWOモード(Dark Field Composite Obliqueモード)を用いて、両面研磨された各ウェーハの裏面を観察し、ウェーハ面内で観察される、欠陥サイズが160nm以上のLPD(Light Point Defect)の数をマイクロスクラッチの発生個数としてカウントした。その結果を表1に示す。
平坦度測定器(KLA-Tencor社製:Wafer Sight)を用いて、両面研磨された発明例1,2のシリコンウェーハについてESFQR(Edge Site Front least sQuares Range)を評価した。ESFQRは、平坦度の悪化しやすいエッジの平坦度の評価指標(サイトフラットネス)であり、エッジロールオフ量の大きさを示すものである。ESFQRは、ウェーハのエッジに沿ったリング状の領域を周方向にさらに均等に分割して得られる単位領域(サイト)を対象とし、サイト内の厚さ分布から最小二乗法により求められた基準面(Site Best Fit Surface)からの偏差の最大値と最小値との差として定義される。ここでは、ウェーハ最外周から2~32mmの範囲(セクター長30mm)に設定されたリング状の外周領域が周方向に72分割されたサイトのESFQRを測定し、さらに全サイトの平均値ESFQR_meanを求めた。
10 キャリアプレート
12 保持孔
14 上定盤
16 下定盤
18,20 研磨布
22 サンギア
24 インターナルギア
26 研磨液供給ライン
28 切替え弁
30 第1研磨液用供給ライン
32 第1研磨液用供給タンク
34 第2研磨液用供給ライン
36 第2研磨液用供給タンク
38 使用済み研磨液回収ライン
40 切替え弁
42 回収タンク
44 再利用ライン
46 廃液ライン
W シリコンウェーハ
Claims (5)
- シリコンウェーハを保持する1以上の保持孔を有するキャリアプレートと、前記キャリアプレートを挟んで対向して位置し、表面に研磨布が設けられた上定盤および下定盤と、を有する両面研磨装置を用いて、前記保持孔内に装填したシリコンウェーハの表面および裏面に、それぞれ前記上定盤および前記下定盤の研磨布を接触させた状態で、前記上定盤および前記下定盤と前記キャリアプレートとを相対回転させることで、前記シリコンウェーハの表面および裏面を同時に研磨するシリコンウェーハの両面研磨方法であって、
砥粒を含むアルカリ水溶液からなる第1の研磨液を前記研磨布に供給しながら両面研磨を行う第1の研磨工程と、
前記第1の研磨工程の後、前記シリコンウェーハの表面および裏面に、それぞれ前記上定盤および前記下定盤の研磨布を接触させたまま、かつ、前記上定盤および前記下定盤の回転を継続した状態で、前記第1の研磨液の供給を停止するとともに、砥粒を含まず水溶性高分子を含むアルカリ水溶液からなる第2の研磨液の供給を開始する研磨液切替え工程と、
前記研磨液切り替え工程の後、前記第2の研磨液を前記研磨布に供給しながら両面研磨を行う第2の研磨工程と、
を連続して有することを特徴とするシリコンウェーハの両面研磨方法。 - 前記上定盤および前記下定盤が前記シリコンウェーハの表面および裏面に加える面圧力に関して、
前記第1の研磨工程では、第1の面圧力で両面研磨を行い、その終期において前記面圧力を低下させて、終了時に前記第1の面圧力よりも低い第2の面圧力とし、
前記第2の研磨工程では前記第2の面圧力で両面研磨を行う、請求項1に記載のシリコンウェーハの両面研磨方法。 - 前記第1の面圧力の値に対して前記第2の面圧力の値が5%~40%小さい、請求項2に記載のシリコンウェーハの両面研磨方法。
- 前記第1の研磨工程では、前記第1および第2の研磨工程での合計研磨量の80%~99.5%の研磨量の両面研磨を行い、
前記第2の研磨工程では、片面あたり0.05μm~0.5μmの研磨量の両面研磨を行う、請求項1~3のいずれか一項に記載のシリコンウェーハの両面研磨方法。 - 前記第1の研磨工程では、使用済みの第1の研磨液を回収した後、前記研磨布に再度供給し、
前記第2の研磨工程では、使用済みの研磨液を回収した後、廃棄する、請求項1~4のいずれか一項に記載のシリコンウェーハの両面研磨方法。
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/638,796 US11170988B2 (en) | 2017-08-31 | 2017-08-31 | Method of double-side polishing silicon wafer |
| JP2019538866A JP6747599B2 (ja) | 2017-08-31 | 2017-08-31 | シリコンウェーハの両面研磨方法 |
| DE112017007968.3T DE112017007968T5 (de) | 2017-08-31 | 2017-08-31 | Doppelseitiges polierverfahren für einen siliziumwafer |
| PCT/JP2017/031496 WO2019043895A1 (ja) | 2017-08-31 | 2017-08-31 | シリコンウェーハの両面研磨方法 |
| CN201780094468.3A CN111095491B (zh) | 2017-08-31 | 2017-08-31 | 硅晶片的双面抛光方法 |
| KR1020207002188A KR102287116B1 (ko) | 2017-08-31 | 2017-08-31 | 실리콘 웨이퍼의 양면 연마 방법 |
| TW107122734A TWI672190B (zh) | 2017-08-31 | 2018-07-02 | 矽晶圓的兩面研磨方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2017/031496 WO2019043895A1 (ja) | 2017-08-31 | 2017-08-31 | シリコンウェーハの両面研磨方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2019043895A1 true WO2019043895A1 (ja) | 2019-03-07 |
Family
ID=65525264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2017/031496 Ceased WO2019043895A1 (ja) | 2017-08-31 | 2017-08-31 | シリコンウェーハの両面研磨方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US11170988B2 (ja) |
| JP (1) | JP6747599B2 (ja) |
| KR (1) | KR102287116B1 (ja) |
| CN (1) | CN111095491B (ja) |
| DE (1) | DE112017007968T5 (ja) |
| TW (1) | TWI672190B (ja) |
| WO (1) | WO2019043895A1 (ja) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200306922A1 (en) * | 2017-10-17 | 2020-10-01 | Sumco Corporation | Method of polishing silicon wafer |
| WO2023218812A1 (ja) * | 2022-05-11 | 2023-11-16 | 信越半導体株式会社 | 両面研磨方法 |
| JP2024034423A (ja) * | 2022-08-31 | 2024-03-13 | 株式会社Sumco | 半導体ウェーハの両面研磨方法、研磨ウェーハの製造方法、及び半導体ウェーハの両面研磨装置 |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI722478B (zh) * | 2019-07-05 | 2021-03-21 | 新代科技股份有限公司 | 具有砂輪之磨床及其砂輪加工地圖的最佳化方法 |
| JP7424768B2 (ja) * | 2019-08-08 | 2024-01-30 | 株式会社フジミインコーポレーテッド | 研磨用添加剤含有液の濾過方法、研磨用添加剤含有液、研磨用組成物、研磨用組成物の製造方法およびフィルタ |
| JP7040591B1 (ja) * | 2020-12-16 | 2022-03-23 | 株式会社Sumco | シリコンウェーハの研磨方法及びシリコンウェーハの製造方法 |
| CN120883509A (zh) | 2023-03-28 | 2025-10-31 | 日本碍子株式会社 | 接合体的制造方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001001242A (ja) * | 1999-06-16 | 2001-01-09 | Daido Steel Co Ltd | ガラス基板の研磨方法 |
| JP2010021487A (ja) * | 2008-07-14 | 2010-01-28 | Sumco Corp | 半導体ウェーハおよびその製造方法 |
| JP2011042536A (ja) * | 2009-08-21 | 2011-03-03 | Sumco Corp | エピタキシャルシリコンウェーハの製造方法 |
| JP2017104958A (ja) * | 2015-12-11 | 2017-06-15 | 信越半導体株式会社 | ウェーハの両面研磨方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5594041A (en) | 1978-12-30 | 1980-07-17 | Nhk Spring Co Ltd | Spring type reciprocating mechanism |
| US5010692A (en) * | 1987-12-22 | 1991-04-30 | Sintobrator, Ltd. | Polishing device |
| JP2001260013A (ja) * | 2000-03-14 | 2001-09-25 | Speedfam Co Ltd | 両面研磨方法 |
| JP3791302B2 (ja) * | 2000-05-31 | 2006-06-28 | 株式会社Sumco | 両面研磨装置を用いた半導体ウェーハの研磨方法 |
| JP2003229392A (ja) * | 2001-11-28 | 2003-08-15 | Shin Etsu Handotai Co Ltd | シリコンウエーハの製造方法及びシリコンウエーハ並びにsoiウエーハ |
| US8143148B1 (en) * | 2008-07-14 | 2012-03-27 | Soraa, Inc. | Self-aligned multi-dielectric-layer lift off process for laser diode stripes |
| TWI498954B (zh) * | 2009-08-21 | 2015-09-01 | 勝高股份有限公司 | 磊晶矽晶圓的製造方法 |
| SG185085A1 (en) * | 2010-04-30 | 2012-12-28 | Sumco Corp | Method for polishing silicon wafer and polishing liquid therefor |
| JP5890088B2 (ja) * | 2010-07-26 | 2016-03-22 | 山口精研工業株式会社 | 研磨剤組成物 |
| DE102013204839A1 (de) * | 2013-03-19 | 2014-09-25 | Siltronic Ag | Verfahren zum Polieren einer Scheibe aus Halbleitermaterial |
| JP6160579B2 (ja) * | 2014-08-05 | 2017-07-12 | 信越半導体株式会社 | シリコンウェーハの仕上げ研磨方法 |
-
2017
- 2017-08-31 WO PCT/JP2017/031496 patent/WO2019043895A1/ja not_active Ceased
- 2017-08-31 KR KR1020207002188A patent/KR102287116B1/ko active Active
- 2017-08-31 JP JP2019538866A patent/JP6747599B2/ja active Active
- 2017-08-31 CN CN201780094468.3A patent/CN111095491B/zh active Active
- 2017-08-31 US US16/638,796 patent/US11170988B2/en active Active
- 2017-08-31 DE DE112017007968.3T patent/DE112017007968T5/de active Pending
-
2018
- 2018-07-02 TW TW107122734A patent/TWI672190B/zh active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001001242A (ja) * | 1999-06-16 | 2001-01-09 | Daido Steel Co Ltd | ガラス基板の研磨方法 |
| JP2010021487A (ja) * | 2008-07-14 | 2010-01-28 | Sumco Corp | 半導体ウェーハおよびその製造方法 |
| JP2011042536A (ja) * | 2009-08-21 | 2011-03-03 | Sumco Corp | エピタキシャルシリコンウェーハの製造方法 |
| JP2017104958A (ja) * | 2015-12-11 | 2017-06-15 | 信越半導体株式会社 | ウェーハの両面研磨方法 |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20200306922A1 (en) * | 2017-10-17 | 2020-10-01 | Sumco Corporation | Method of polishing silicon wafer |
| US11890719B2 (en) * | 2017-10-17 | 2024-02-06 | Sumco Corporation | Method of polishing silicon wafer |
| WO2023218812A1 (ja) * | 2022-05-11 | 2023-11-16 | 信越半導体株式会社 | 両面研磨方法 |
| JP2023167038A (ja) * | 2022-05-11 | 2023-11-24 | 信越半導体株式会社 | 両面研磨方法 |
| JP2024034423A (ja) * | 2022-08-31 | 2024-03-13 | 株式会社Sumco | 半導体ウェーハの両面研磨方法、研磨ウェーハの製造方法、及び半導体ウェーハの両面研磨装置 |
| JP7464088B2 (ja) | 2022-08-31 | 2024-04-09 | 株式会社Sumco | 半導体ウェーハの両面研磨方法、研磨ウェーハの製造方法、及び半導体ウェーハの両面研磨装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20200021518A (ko) | 2020-02-28 |
| JP6747599B2 (ja) | 2020-08-26 |
| US20200185215A1 (en) | 2020-06-11 |
| TW201912302A (zh) | 2019-04-01 |
| KR102287116B1 (ko) | 2021-08-05 |
| JPWO2019043895A1 (ja) | 2020-03-26 |
| CN111095491A (zh) | 2020-05-01 |
| CN111095491B (zh) | 2023-05-30 |
| DE112017007968T5 (de) | 2020-06-10 |
| US11170988B2 (en) | 2021-11-09 |
| TWI672190B (zh) | 2019-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2019043895A1 (ja) | シリコンウェーハの両面研磨方法 | |
| CN107155368B (zh) | 硅晶圆的研磨方法 | |
| JP5622124B2 (ja) | シリコンウェーハの研磨方法 | |
| CN106170847B (zh) | 半导体晶片的制造方法 | |
| JP5754659B2 (ja) | シリコンウェーハの研磨方法 | |
| JP5585652B2 (ja) | シリコンウェーハの研磨方法 | |
| JP5493956B2 (ja) | 半導体ウェーハの製造方法 | |
| JP3317330B2 (ja) | 半導体鏡面ウェーハの製造方法 | |
| TW200921773A (en) | Method for producing a semiconductor wafer with a polished edge | |
| JP2023065426A (ja) | 基板の研磨方法および研磨用組成物セット | |
| JP2002231669A (ja) | 半導体ウェーハ用研磨布およびこれを用いた半導体ウェーハの研磨方法 | |
| KR20020017910A (ko) | 재생웨이퍼를 반도체웨이퍼로 변환시키는 방법 | |
| CN108966673B (zh) | 硅基板的研磨方法和研磨用组合物套组 | |
| JP2010040643A (ja) | 両面鏡面半導体ウェーハおよびその製造方法 | |
| JP4366928B2 (ja) | 片面鏡面ウェーハの製造方法 | |
| JP2007067179A (ja) | 半導体ウエーハの鏡面研磨方法及び鏡面研磨システム | |
| JP7464088B2 (ja) | 半導体ウェーハの両面研磨方法、研磨ウェーハの製造方法、及び半導体ウェーハの両面研磨装置 | |
| JP5803601B2 (ja) | 研磨スラリーの供給方法及び供給装置、並びに研磨装置 | |
| TW202311459A (zh) | 雙面研磨方法及雙面研磨矽晶圓 | |
| TWI775622B (zh) | 矽晶圓的研磨方法及矽晶圓的製造方法 | |
| JP2009135180A (ja) | 半導体ウェーハの製造方法 | |
| JPH10321566A (ja) | 半導体装置の研磨方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17922928 Country of ref document: EP Kind code of ref document: A1 |
|
| ENP | Entry into the national phase |
Ref document number: 2019538866 Country of ref document: JP Kind code of ref document: A |
|
| ENP | Entry into the national phase |
Ref document number: 20207002188 Country of ref document: KR Kind code of ref document: A |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 17922928 Country of ref document: EP Kind code of ref document: A1 |