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WO2019042314A1 - 移位寄存器、栅极驱动电路、显示面板及驱动方法 - Google Patents

移位寄存器、栅极驱动电路、显示面板及驱动方法 Download PDF

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Publication number
WO2019042314A1
WO2019042314A1 PCT/CN2018/102937 CN2018102937W WO2019042314A1 WO 2019042314 A1 WO2019042314 A1 WO 2019042314A1 CN 2018102937 W CN2018102937 W CN 2018102937W WO 2019042314 A1 WO2019042314 A1 WO 2019042314A1
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WIPO (PCT)
Prior art keywords
output
pull
transistor
signal
pole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/102937
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English (en)
French (fr)
Inventor
冯思林
董职福
薛伟
李红敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/339,554 priority Critical patent/US11069272B2/en
Priority to EP18850721.4A priority patent/EP3678138A4/en
Publication of WO2019042314A1 publication Critical patent/WO2019042314A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • Embodiments of the present disclosure relate to a shift register, a gate driving circuit, a display panel, and a driving method.
  • the Gate-Driver on Array (GOA) technology directly integrates the gate driving circuit on the array substrate of the display device by a photolithography process, and the GOA circuit usually includes a plurality of cascaded shift registers, each of which The shift registers are each corresponding to one row of gate lines (for example, each shift register provides a scan driving signal to one row of gate lines) to implement scan driving of the display panel.
  • This integrated technology can save the bonding area of the integrated circuit (IC) and the space of the fan-out area, thereby achieving a narrow border of the display panel, and at the same time reducing product cost and improving Product yield.
  • An embodiment of the present disclosure provides a shift register, including: an input circuit respectively connected to a pull-up node and an input signal end; and an output circuit respectively connected to the pull-up node, a clock signal end, a DC signal end, and an output end
  • the clock signal terminal provides a clock signal
  • the DC signal terminal provides a DC signal
  • the output circuit outputs a scan signal from the output terminal
  • an output pull-down circuit is coupled to the output circuit.
  • the output circuit is configured to, when the first output condition is satisfied, a scan signal output from the output terminal is one of the DC signal and the clock signal; the output pull-down circuit is configured to satisfy When the two conditions are output, the scan signal is pulled down.
  • the output circuit includes a storage capacitor, a first output transistor, and a second output transistor.
  • the output circuit when the first output condition is satisfied, is configured to output a DC signal from the DC signal terminal from the output terminal; a first pole of the first output transistor and the clock signal terminal Connecting, a control electrode of the first output transistor is connected to the pull-up node, a second pole of the first output transistor is connected to a control electrode of the second output transistor, and the first end of the storage capacitor is The pull-up node is connected, the second end of the storage capacitor is connected to the second pole of the first output transistor; the first pole of the second output transistor is connected to the DC signal end, the second a second pole of the output transistor is coupled to the output; and the first output condition is satisfied when the second output transistor is turned on.
  • the shift register further includes a pull-down control circuit, wherein the pull-down control circuit includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor, the first control transistor One pole is connected to the second voltage terminal, the second pole of the first control transistor is connected to the pull-down node; the first pole of the second control transistor is connected to the pull-down node, and the second control transistor is a control electrode is connected to the pull-up node, a second pole of the second control transistor is connected to the first voltage terminal; a first pole of the third control transistor is connected to the second voltage terminal, the third a control electrode of the control transistor is coupled to the second voltage terminal, a second electrode of the third control transistor is coupled to a control electrode of the first control transistor; a first pole of the fourth control transistor and the first a second pole of the control transistor is connected, a gate of the fourth control transistor is connected to the pull-up node, and a second pole of the fourth control transistor is connected to the first voltage terminal
  • the output circuit when the first output condition is satisfied, is configured to output a clock signal from the clock signal terminal from the output terminal; a first pole of the first output transistor and the DC signal terminal Connecting, a control electrode of the first output transistor is connected to the pull-up node, a second pole of the first output transistor is connected to a control electrode of the second output transistor, and the first end of the storage capacitor is The pull-up node is connected, the second end of the storage capacitor is connected to the second pole of the first output transistor; the first pole of the second output transistor is connected to the clock signal end, the second a second pole of the output transistor is coupled to the output; and the first output condition is satisfied when the second output transistor is turned on.
  • the shift register further includes a pull-down control circuit, wherein the pull-down control circuit includes a first control transistor and a second control transistor; and the first pole of the first control transistor is connected to the second voltage terminal, a control electrode of the first control transistor is connected to the second voltage terminal, a second pole of the first control transistor is connected to the pull-down node, and a first pole of the second control transistor is connected to the pull-down node.
  • the second pole of the second control transistor is connected to the first voltage terminal, and the control pole of the second control transistor is connected to the pull-up node.
  • the output pull-down circuit includes a first output pull-down transistor and a second output pull-down transistor; a first pole of the first output pull-down transistor is coupled to a second pole of the first output transistor, the first output pull-down a control electrode of the transistor is connected to the pull-down node, a second pole of the first output pull-down transistor is connected to the first voltage terminal; a first pole of the second output pull-down transistor is connected to the output terminal, the second output A control electrode of the pull-down transistor is coupled to the pull-down node, and a second electrode of the second output pull-down transistor is coupled to the first voltage terminal.
  • the second output condition is satisfied when the second output pull-down transistor is turned on.
  • the shift register further includes a reset circuit connected to the pull-up node, the reset signal terminal, and the third voltage terminal, wherein the reset circuit is configured to receive from the first A third voltage signal at the three voltage terminals to reset the output circuit.
  • the reset circuit includes a reset transistor; a control electrode of the reset transistor is connected to the reset signal terminal, a first pole of the reset transistor is connected to the pull-up node, and a second pole of the reset transistor is The third voltage terminal is connected.
  • the shift register further includes a pull-down holding circuit configured to pull down a potential of the pull-up node when a pull-down condition of the pull-up node is satisfied.
  • the shift register wherein the pull-down holding circuit includes a pull-down holding transistor; a control electrode of the pull-down holding transistor is connected to a pull-down node, and a first pole of the pull-down holding transistor is connected to the pull-up node The second pole of the pull-down holding circuit is connected to the first voltage terminal.
  • Embodiments of the present disclosure provide a gate driving circuit including a plurality of cascaded shift registers, wherein each shift register is a shift register provided by any of the embodiments of the present disclosure, wherein In addition to the last stage shift register, the input signal terminal of the shift register of the current stage is connected to the output end of the shift register of the previous stage; the reset signal end of the shift register of the current stage is connected to the output end of the shift register of the next stage.
  • Embodiments of the present disclosure provide a display panel including a gate driving circuit provided by any of the embodiments of the present disclosure.
  • An embodiment of the present disclosure provides a driving method for driving a shift register provided by any one of the embodiments of the present disclosure, including: in an input stage, setting a reset signal input by a reset signal terminal to an invalid signal, and setting the input of the clock signal end
  • the clock signal is an invalid signal
  • the input signal input to the input signal terminal is set to be a valid signal to pull the potential of the pull-up node high
  • the output stage the input signal is set to be an invalid signal
  • the reset signal is set to be an invalid signal.
  • the clock signal is set to be a valid signal to output a scan signal from the output end, wherein the scan signal is one of a DC signal or a clock signal; in the reset phase, setting the input signal to be an invalid signal, and setting the clock signal For the invalid signal, the reset signal is set to be a valid signal to pull the potential of the pull-up node and the potential of the output terminal to be low, and the potential of the pull-down node is pulled high; in the holding phase, the input signal is set to be an invalid signal. Setting the clock signal to an invalid signal, setting the reset signal to an invalid signal to maintain The potential of the pull-down node that is pulled high and the potential of the pull-up node that is pulled low and the potential of the output terminal.
  • the valid signal is a high voltage signal and the invalid signal is a low voltage signal.
  • the present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method, such that a display area uses a DC signal to drive a gate of a switching transistor of a display area, compared to driving with a clock signal CLK.
  • the gate can reduce dynamic power consumption.
  • the shift register, the gate driving circuit, the display panel, and the driving method provided by the present disclosure can block the influence of the storage capacitor on the scan output signal and improve the display quality.
  • FIG. 1 is a schematic diagram of a shift register provided by an embodiment of the present disclosure
  • 2A is a second schematic diagram of a shift register according to an embodiment of the present disclosure.
  • 2B is a third schematic diagram of a shift register according to an embodiment of the present disclosure.
  • 2C is a fourth schematic diagram of a shift register according to an embodiment of the present disclosure.
  • 2D-2F are schematic diagrams of an output circuit in an embodiment of the present disclosure.
  • FIG. 3 is a schematic circuit structural diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 4 is a driving timing diagram of the shift register shown in FIG. 3 according to an embodiment of the present disclosure
  • FIG. 5 is one of cascade diagrams of a shift register according to an embodiment of the present disclosure
  • FIG. 6 is a schematic circuit structural diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 7 is a timing chart of driving of the shift register shown in FIG. 6 according to an embodiment of the present disclosure.
  • FIG. 8 is a second cascade diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register 100 that includes an input circuit 110, an output circuit 120, and an output pull-down circuit 130, as shown in FIG.
  • the input circuit 110 is connected to the pull-up node PU and the input signal terminal INPUT, respectively; the output circuit 120 is connected to the pull-up node PU, the clock signal terminal CLK, the DC signal terminal GCH, and the output terminal OUTPUT, respectively.
  • the clock signal terminal CLK provides a clock signal
  • the DC signal terminal GCH provides a DC signal
  • the output circuit 120 outputs a scan signal from the output terminal OUTPUT.
  • the output pull-down circuit 130 is connected to the output circuit 120.
  • the output circuit 120 is configured to, when the first output condition is satisfied, the scan signal output from the output terminal OUTPUT is one of the DC signal and the clock signal; the output pull-down circuit 130 is configured to Pulling down the scan signal when the second output condition is satisfied.
  • the output pull-down circuit 130 is configured to write the voltage provided by the first power supply terminal VGL to the output terminal OUTPUT. For example, the scan signal outputted from the output terminal OUTPUT is pulled down by the output pull-down circuit 130 to the voltage VGL supplied from the first power supply terminal VGL.
  • shift register 100 can also include one or more of pull-down control circuit 140, reset circuit 150, and pull-down hold circuit 160.
  • the shift register 100 may include an input circuit 110, an output circuit 120, an output pull-down circuit 130, and a reset circuit 150.
  • the reset circuit 150 is configured to pull down the potential of the pull-up node PU and control the output pull-down circuit 130 through a reset signal input from the reset terminal RESET.
  • the shift register 100 can include an input circuit 110, an output circuit 120, an output pull-down circuit 130, and a pull-down control circuit 140.
  • the pull-down control circuit 140 can be configured to pull the output voltage of the output terminal OUTPUT low by controlling the output pull-down circuit 130.
  • the reset circuit 150 can be configured to pull down the voltage of the pull-up node PU.
  • the pull-down hold circuit 160 can be configured to pull down the potential of the pull-up node PU and keep the pull-up node PU low while the shift register is operating in the hold phase.
  • the output circuit 120 includes a first output sub-circuit 121, a second output sub-circuit 122, and a storage sub-circuit 123.
  • the storage sub-circuit 123 is no longer directly connected to the output terminal OUTPUT, but is connected to the output terminal OUTPUT through the second output sub-circuit 122, so that the load of the storage sub-circuit 123 on the output terminal OUTPUT can be reduced. influences.
  • the first output sub-circuit 121 is connected to the pull-up node PU, the storage sub-circuit 123, the output control node A, and the clock signal terminal CLK or the DC signal terminal GCH. Under the control of the pull-up node PU, the clock signal terminal CLK is connected. Or the signal of the DC signal terminal GCH is output to the output control node A to control its level.
  • the second output sub-circuit 122 is connected to the output control node A, the output terminal OUTPUT, and the DC signal terminal GCH or the clock signal terminal CLK, and can be connected to the DC signal terminal GCH or the clock under the control of the level of the output control node A.
  • the signal of the signal terminal CLK is output to the output terminal OUTPUT as an output signal. That is, one of the first output sub-circuit 121 and the second output sub-circuit 122 is connected to the clock signal terminal CLK, and the other is connected to the DC signal terminal GCH.
  • the storage sub-circuit 123 is connected to the pull-up node PU and the output control node A for storing the level of the pull-up node PU, and can also bootstrap the pull-up node PU when the clock signal terminal CLK is output to the output control node A. To further control the level of the pull-up node PU, or to maintain the level of the pull-up node PU when the signal of the DC signal terminal GCH is output to the output control node A.
  • the output circuit 120 includes a storage capacitor C1, a first output transistor T1, and a second output transistor T2 for implementing the storage sub-circuit 123, the first output sub-circuit 121, and the second output, respectively.
  • Subcircuit 122 includes a storage capacitor C1, a first output transistor T1, and a second output transistor T2 for implementing the storage sub-circuit 123, the first output sub-circuit 121, and the second output, respectively.
  • the first pole of the first output transistor T1 is connected to the clock signal terminal CLK, the control pole of the first output transistor T1 is connected to the pull-up node PU, and the second pole of the first output transistor T1 is connected to the output control node G_N, thereby
  • the control terminal of the two output transistors T2 is connected, the first end of the storage capacitor C1 is connected to the pull-up node PU, and the second end of the storage capacitor C1 is connected to the second pole of the first output transistor T1.
  • the first pole of the second output transistor T2 is connected to the DC signal terminal GCH, and the second pole of the second output transistor T2 is connected to the output terminal OUTPUT.
  • the clock signal terminal CLK is not directly connected to the output terminal OUTPUT, that is, the clock signal terminal CLK is separated from the load of the display area of the driven display panel, but
  • the DC voltage terminal GCH is directly connected to the output terminal OUTPUT, that is, the DC voltage signal GCH is used to drive the load of the display area, thereby reducing the dynamic power consumption of the clock signal terminal CLK.
  • the output circuit 120 includes a storage capacitor C1, a first output transistor T1, and a second output transistor T2 for implementing the storage sub-circuit 123, the first output sub-circuit 121, and the second output sub-circuit 122, respectively. .
  • the first pole of the first output transistor T1 is connected to the DC signal terminal GCH, the control pole of the first output transistor T1 is connected to the pull-up node PU, and the second pole of the first output transistor T1 is connected to the output control node P2, thereby
  • the control terminal of the two output transistors T2 is connected, the first end of the storage capacitor C1 is connected to the pull-up node PU, the second end of the storage capacitor C1 is connected to the second pole of the first output transistor T1, and the first end of the second output transistor T2
  • the pole is connected to the clock signal terminal CLK, and the second pole of the second output transistor T2 is connected to the output terminal OUTPUT.
  • the output circuit 120 cancels the bootstrap action of the storage capacitor C1 during operation of the output circuit 120, and the gate of the second output transistor T2 is driven by the DC voltage input through the first output transistor T1. Therefore, it is possible to block the influence of the storage capacitor C1 on the load (output) of the output terminal OUTPUT.
  • Another embodiment of the present disclosure provides a shift register including an input circuit, an output circuit, and an output pull-down circuit.
  • the input circuit is respectively connected with the pull-up node and the input signal end; the output circuit is respectively connected with the pull-up node, the clock signal end, the DC signal end and the output end; and the output pull-down circuit is connected with the output circuit.
  • the clock signal terminal provides a clock signal
  • the DC signal terminal provides a DC signal
  • the output circuit outputs a scan signal from the output terminal.
  • the output circuit includes a first output sub-circuit, a second output sub-circuit, and a storage sub-circuit.
  • the first output sub-circuit and the storage sub-circuit are connected to the pull-up node, and cooperate with the level of the control output control node, the second output sub-circuit is connected to the output end, and the level of the control node controls whether the scan signal is output at the output end. .
  • the shift register 100 includes an input circuit 110, an output circuit 120, and an output pull-down circuit 130.
  • the output circuit 120 may include a storage capacitor C1, a first output transistor T1, and a second output transistor T2.
  • the output circuit 120 may be configured to output a DC signal from the DC signal terminal GCH from the output terminal OUTPUT.
  • the first electrode of the first output transistor T1 is connected to the clock signal terminal CLK
  • the control electrode of the first output transistor T1 is connected to the pull-up node PU
  • the second electrode of the first output transistor T1 is connected to the control electrode of the second output transistor T2.
  • the first end of the storage capacitor C1 is connected to the pull-up node PU
  • the second end of the storage capacitor C1 is connected to the second pole of the first output transistor T1.
  • the first pole of the second output transistor T2 is connected to the DC signal terminal GCH
  • the second pole of the second output transistor T2 is connected to the output terminal OUTPUT.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the control of the transistor is extremely the gate of the transistor.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • one of the first poles and the other pole are directly described, so the first pole of all or part of the transistors in the embodiment of the present disclosure
  • the second pole is interchangeable as needed.
  • the first pole of the transistor of the embodiment of the present disclosure may be a source, and the second pole may be a drain; or the first extreme drain of the transistor and the second source of the second.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low level voltage (eg, 0V, -5V, or other value)
  • the turn-off voltage is a high level voltage (eg, 5V, 10V, or other value)
  • the turn-on voltage is a high level voltage (for example, 5V, 10V, or other value)
  • the turn-off voltage is a low level voltage (for example, 0V, -5V, or other values).
  • each transistor is an N-type transistor.
  • those skilled in the art can realize the implementation of the P-type transistor or the combination of the N-type and P-type transistors in the embodiments of the present disclosure without creative efforts. Therefore, these Implementations are also within the scope of the present disclosure.
  • pull-down control circuit 140 is coupled to first voltage terminal VGL and second voltage terminal PCH.
  • the voltage input by the second voltage terminal PCH and the voltage input by the DC voltage terminal GCH may be the same.
  • the second voltage terminal PCH and the DC voltage terminal GCH are the same voltage terminal.
  • the pull-down control circuit 140 may include a first control transistor M1, a second control transistor M2, a third control transistor M3, and a fourth control transistor M4.
  • the first pole of the first control transistor M1 is connected to the second voltage terminal PCH
  • the second pole of the first control transistor M1 is connected to the pull-down node PD
  • the first pole of the second control transistor M2 is connected to the pull-down node PD
  • the second control The gate of the transistor M2 is connected to the pull-up node PU
  • the second pole of the second control transistor M2 is connected to the first voltage terminal VGL
  • the first pole of the third control transistor M3 is connected to the second voltage terminal PCH
  • the control electrode of M3 is connected to the second voltage terminal PCH
  • the second electrode of the third control transistor M3 is connected to the control electrode of the first control transistor M1
  • the second electrode of the fourth control transistor M4 is connected to the second electrode of the third control transistor M3.
  • the pole is connected, the gate of the fourth
  • pull-down control circuit 140 shown in FIG. 3 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 3.
  • the output pull-down circuit 130 can include a first output pull-down transistor K1 and a second output pull-down transistor K2.
  • the first pole of the first output pull-down transistor K1 is connected to the second pole of the first output transistor T1, the gate of the first output pull-down transistor K1 is connected to the pull-down node PD, and the second pole of the first output pull-down transistor K1 is first
  • the voltage terminal VGL is connected;
  • the first output of the second output pull-down transistor K2 is connected to the output terminal OUTPUT, the control electrode of the second output pull-down transistor K2 is connected to the pull-down node PD, and the second output of the second output pull-down transistor K2 is connected to the first voltage End VGL connection.
  • the output pull-down circuit 130 is configured to pull the scan signal down to the potential of VGL.
  • the reset circuit 150 is configured to receive a third from the third voltage terminal VSS when a reset condition is satisfied (eg, when the reset transistor T4 shown in FIG. 3 is turned on) A three voltage signal is applied to reset the output circuit 120.
  • reset circuit 150 includes reset transistor T4 as shown in FIG.
  • the control electrode of the reset transistor T4 is connected to the reset signal terminal RESET, the first electrode of the reset transistor T4 is connected to the pull-up node PU, and the second electrode of the reset transistor T4 is connected to the third power supply terminal VSS.
  • the control electrodes of the first output pull-down transistor K1 and the second output pull-down transistor K2 of the pull-down circuit 130 may both be Connected to the reset signal terminal RESET.
  • reset circuit 150 shown in FIG. 3 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 3.
  • the pull-down hold circuit 160 is configured to pull down the potential of the pull-up node PU when the pull-down condition of the pull-up node PU is satisfied.
  • the pull-down holding circuit 160 may include a pull-down holding transistor T5; the control electrode of the pull-down holding transistor T5 is connected to the pull-down node PD, and the first pole of the pull-down holding transistor T5 is connected to the pull-up node PU, and the pull-down holding transistor The second pole of T5 is coupled to the first voltage terminal VGL.
  • the pull-down condition of the pull-up node PU is satisfied (eg, when the pull-down holding transistor T5 is turned on or turned on), the potential of the pull-up node PU is pulled down to the potential of VGL.
  • pull-down holding circuit 160 shown in FIG. 3 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 3.
  • the input circuit 110 may include an input transistor T3, the control electrode of the input transistor T3 is connected to the input signal terminal INPUT, and the first electrode of the input transistor T3 is connected to the fourth voltage terminal VDD.
  • the input transistor T3 is connected to the pull-up node PU.
  • the input circuit 110 shown in FIG. 3 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 3.
  • the process of driving the circuit of FIG. 3 is exemplarily described below in conjunction with the timing diagrams of FIGS. 3 and 4.
  • the node of the second electrode of the first output transistor T1 and the gate of the second output transistor T2 is a G_N node.
  • the first stage is the input stage.
  • the reset signal of the reset signal terminal RESET, the clock signal of the clock signal terminal CLK are set to a low level, and the input signal of the input terminal INPUT is a high level.
  • the reset transistor T4 Since the reset signal is low level, the reset transistor T4 is turned off; the input signal is high level, the input transistor T3 is turned on, and the storage capacitor C1 is charged through the input transistor T3, at this time, the pull-up node PU point is high level, second The control transistor M2 and the fourth control transistor M4 are turned on.
  • the PD point of the pull-down node is low, and the first pull-down transistor K1, the second pull-down transistor K2, and the pull-down holding transistor T5 are all turned off to ensure normal input.
  • the first output transistor T1 Since the PU point of the pull-up node is high, the first output transistor T1 is turned on, and the clock signal is low level, so the G_N node outputs a low level, the second output transistor T2 is turned off, and the output terminal OUTPUT outputs a low level.
  • the second phase is the output phase, the input signal and the reset signal are low, and the clock signal is high. Due to the holding function of the storage capacitor C1, the PU of the pull-up node is at a high level, the first output transistor T1 is turned on, and the clock signal is at a high level, the node G_N outputs a high level, and the second output transistor T2 is turned on, so the output The OUTPUT output is high. At this time, the pull-down node PD potential is low, and the pull-down holding transistor T5, the first pull-down transistor K1, and the second pull-down transistor K2 are all turned off to ensure normal output.
  • the third phase is the reset phase.
  • the clock signal and the input signal are at a low level, and the reset signal is at a high level. Since the reset signal is at a high level, the reset transistor T4 is turned on, the pull-up node PU is at a low level, and the second control transistor M2 and the fourth control transistor M4 are turned off.
  • the pull-down node PD is at a high level, and the pull-down holding transistor T5, the first pull-down transistor K1, and the second pull-down transistor K2 are turned on.
  • the signals of the pull-up node PU, the node G_N, and the output are all low.
  • the fourth stage is the hold phase, and the clock signal, the input signal, and the reset signal are all low. Since the clock signal, the input signal, and the reset signal are both low, the input transistor T3 and the reset transistor T4 are turned off.
  • the pull-up node PU is at a low level, and the second control transistor M2 and the fourth control transistor M4 are turned off.
  • the pull-down node PD is at a high level, and the pull-down holding transistor T5, the first pull-down transistor K1, and the second pull-down transistor K2 are turned on, and the potentials of the pull-up node PU, the node G_N, and the output terminal OUTPUT are kept at a low level.
  • the gate drive circuit including the shift register 100 described above operates in the fourth stage after entering the fourth stage and before the arrival of the next frame.
  • gate drive circuit 10 can include a plurality of cascaded shift registers (eg, two cascaded shift registers 100 in FIG. 5). Each shift register can be the shift register 100 provided by any of the embodiments of the present disclosure.
  • the input signal terminal INPUT of the shift register 100 of the present stage is connected to the node G_N in the shift register 100 of the previous stage; the reset signal terminal RESET of the shift register of this stage It is connected to the node G_N of the next stage shift register 100.
  • the gate driving circuit 10 includes n stages of shift registers 100, and the output terminals OUTPUT of each stage shift register are respectively connected to the gate lines G1, G2, ..., Gi, G(i+1)...Gn of the display panel, wherein The value range of i is greater than or equal to 0 and less than or equal to n, and both i and n are positive integers.
  • the first clock signal terminal CLK1 and the second clock signal terminal CLK2 in FIG. 5 are complementary, and the cascade of shift registers can be implemented.
  • the second voltage terminal PCH and the DC voltage terminal GCH of each shift register are the same voltage terminal.
  • the above embodiment of the present disclosure provides that the output of the second output transistor T2 is controlled by the potential of the node G_N shown in FIG. 3, which can effectively avoid the use of the storage capacitor C1 to control the output delay of the output transistor and the like.
  • the shift register and the gate driving circuit provided by the above embodiments of the present disclosure can block the influence of the storage capacitor C1 on the scan signal outputted by the output terminal OUTPUT, thereby improving the display quality.
  • the clock signal terminal CLK is not directly connected to the output terminal OUTPUT in the output stage, that is, the load of the clock signal terminal CLK and the display area of the driven display panel (loading)
  • the DC voltage terminal GCH is directly connected to the output terminal OUTPUT, that is, the DC voltage signal GCH is used to drive the load of the display area. Therefore, this embodiment can reduce the dynamic power consumption of the clock signal terminal CLK, and contribute to improving the display quality of the display panel.
  • the gate driving circuit 10 provided by the embodiment of the present disclosure can implement forward scanning and reverse scanning, when the scanning direction is switched, the “upper level” and “next level” in the timing are changed accordingly. Therefore, the above-mentioned “upper level” and “lower level” do not refer to the upper level and the lower level in the scanning timing, but refer to the upper level and the lower level on the physical connection.
  • the shift register 100 and the gate driving circuit 10 provided by the embodiments of the present disclosure enable the display area to use a DC signal to drive the gate of the switching transistor of the display area, compared to using a clock.
  • the signal CLK drives the gate to reduce dynamic power consumption.
  • the output circuit 120 may include a storage capacitor C1, a first output transistor T1, and a second output transistor T2.
  • the output circuit 120 when the first output condition is met (eg, when the second output transistor T2 in FIG. 6 is turned on), the output circuit 120 is configured to output a clock signal from the clock signal terminal CLK from the output terminal OUTPUT.
  • the first pole of the first output transistor T1 is connected to the DC signal terminal GCH
  • the control pole of the first output transistor T1 is connected to the pull-up node PU
  • the second pole P2 of the first output transistor T1 and the control pole of the second output transistor T2 connection The first end of the storage capacitor C1 is connected to the pull-up node PU
  • the second end of the storage capacitor C1 is connected to the second pole of the first output transistor T1.
  • the first electrode of the second output transistor T2 is connected to the clock signal terminal CLK
  • the second electrode of the second output transistor T2 is connected to the output terminal OUTPUT.
  • the pull-down control circuit 140 can include a first control transistor M1 and a second control transistor M2.
  • the first pole of the first control transistor M1 is connected to the second voltage terminal PCH
  • the control pole of the first control transistor M1 is connected to the second voltage terminal PCH
  • the second pole of the first control transistor M1 is connected to the pull-down node PD
  • the first pole of the control transistor M2 is connected to the pull-down node PD
  • the second pole of the second control transistor M2 is connected to the first voltage terminal VGL
  • the gate of the second control transistor M2 is connected to the pull-up node PU.
  • the voltage input by the second power terminal PCH and the voltage input by the DC power terminal CGH may be the same.
  • the second voltage terminal PCH and the DC voltage terminal GCH are the same voltage terminal.
  • pull-down control circuit 140 shown in FIG. 6 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 6.
  • the output pull-down circuit 130 can include a first output pull-down transistor K1 and a second output pull-down transistor K2.
  • the first pole of the first output pull-down transistor K1 is connected to the second pole of the first output transistor T1, the gate of the first output pull-down transistor K1 is connected to the pull-down node PD, and the second pole of the first output pull-down transistor K1 is first
  • the voltage terminal VGL is connected;
  • the first output of the second output pull-down transistor K2 is connected to the output terminal OUTPUT, the control electrode of the second output pull-down transistor K2 is connected to the pull-down node PD, and the second output of the second output pull-down transistor K2 is connected to the first voltage End VGL connection.
  • the output pull-down circuit 130 is configured to pull the scan signal down to the potential of VGL.
  • the circuit structure of the output pull-down control circuit 140 in FIG. 6 can also adopt the circuit structure of the pull-down control circuit 140 shown in FIG. 3.
  • the circuit structure of the pull-down control circuit 140 of FIG. 3 can also use the pull-down of FIG. The circuit structure of the control circuit 140.
  • the reset circuit 150 is configured to receive a third voltage signal from the third voltage terminal VSS when a reset condition is satisfied (eg, when the reset transistor T4 shown in FIG. 5 is turned on), The output circuit 120 is reset.
  • reset circuit 150 includes a reset transistor T4.
  • the control electrode of the reset transistor T4 is connected to the reset signal terminal RESET, the first electrode of the reset transistor T4 is connected to the pull-up node PU, and the second electrode of the reset transistor T4 is connected to the third power supply terminal VSS.
  • the control electrodes of the first output pull-down transistor K1 and the second output pull-down transistor K2 of the pull-down circuit 130 are both reset and reset signals.
  • the terminal RESET is connected.
  • reset circuit 150 shown in FIG. 6 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 6.
  • the pull-down hold circuit 160 is configured to pull down the potential of the pull-up node PU when the pull-down condition of the pull-up node PU is satisfied.
  • the pull-down hold circuit 160 can include a pull-down hold transistor T5.
  • the control electrode of the pull-down holding transistor T5 is connected to the pull-down node PD
  • the first pole of the pull-down holding transistor T5 is connected to the pull-up node PU
  • the second pole of the pull-down holding transistor T5 is connected to the first voltage terminal VGL.
  • the pull-down condition of the pull-up node PU is satisfied (eg, when the pull-down holding transistor T5 is turned on or turned on)
  • the potential of the pull-up node PU is pulled down to the potential of VGL.
  • pull-down holding circuit 160 shown in FIG. 6 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 6.
  • the input circuit 110 may include an input transistor T3 , the control electrode of the input transistor T3 is connected to the input signal terminal INPUT, and the first electrode of the input transistor T3 is connected to the fourth voltage terminal VDD.
  • the input transistor T3 is connected to the pull-up node PU.
  • the input circuit 110 shown in FIG. 6 is only one example of the embodiment of the present disclosure, and the embodiments of the present disclosure include but are not limited to the case shown in FIG. 6.
  • the second voltage terminal PCH and the DC voltage terminal GCH shown in FIG. 6 are combined into one DC voltage input.
  • the process of driving the circuit of FIG. 6 is exemplarily described below in conjunction with the timing diagram of FIG.
  • the node of the second output of the first output transistor T1 and the gate of the second output transistor T2 in FIG. 6 is a P2 node.
  • the forward scan control signal In the forward scan, the forward scan control signal is high, and the reverse scan control signal is low; in reverse scan, the forward scan control signal is low, and the reverse scan control signal is high. level.
  • the following uses the forward scan as an example to illustrate the driving principle:
  • Input phase The input signal of the input terminal INPUT is high level, the reset signal of the reset signal terminal RESET and the clock signal of the clock signal terminal CLK are low level.
  • the reset transistor T4 When the reset signal is low, the reset transistor T4 is turned off.
  • the input signal is high, the input transistor T3 is turned on, the storage capacitor C1 is charged, and the pull-up node PU is at a high level.
  • the second control transistor M2 When the pull-up node is high, the second control transistor M2 is turned on.
  • the pull-down node PD point is pulled down to the voltage VGL of the first voltage terminal.
  • the pull-down node PD When the pull-down node PD is at a low level, the first pull-down transistor K1, the second pull-down transistor K2, and the pull-down holding transistor T5 are turned off to ensure normal input.
  • the pull-up node PU When the pull-up node PU is at a high level, the first output transistor T1 is turned on, the potential of the node P2 is at a high level, and the second output transistor T2 is turned on. Since the clock signal is low, the output OUTPUT outputs a low level.
  • Output phase The clock signal is high, and the input signal and reset signal are low.
  • the input transistor T3 and the reset transistor T4 are turned off. Due to the holding function of the storage capacitor C1, the pull-up node PU is at a high level, the second control transistor M2 and the first output transistor T1 are turned on; the pull-down node PD point is still at a low level, and the first pull-down transistor K1, the second The pull-down transistor K2 and the pull-down holding transistor T5 are turned off to ensure a normal output. Since the node P2 is still at a high level, the second output transistor T2 is turned on, and the clock signal is at a high level, and the output terminal OUTPUT outputs a high level.
  • Reset phase The reset signal is high, the input signal and the clock signal are low.
  • the input signal is low level, the input transistor T3 is turned off; the reset signal is high level, the reset transistor T4 is turned on, the storage capacitor C1 is discharged through the reset transistor T4; the pull-up node PU is low level, and the second control transistor M2 And the first output transistor T1 is turned off; the pull-down node PD is at a high level, and the first pull-down transistor K1, the second pull-down transistor K2, and the pull-down holding transistor T5 are turned on. Pull-up node PU, node P2, and output OUTPUT are pulled low.
  • the input signal and the reset signal are low, the input transistor T3 and the reset transistor T4 are turned off; at this time, the pull-up node PU is at a low level, the second control transistor M2 and the first output transistor T1 are turned off; the pull-down node PD When the level is high, the first pull-down transistor K1, the second pull-down transistor K2, and the pull-down holding transistor T5 are turned on to ensure that the pull-up node PU point, the node P2, and the output terminal bit are kept at a low level to ensure normal display.
  • the shift register 100 repeats the fourth phase after entering the fourth phase and before the next frame arrives.
  • the embodiment of the present disclosure provides to control the output of the second output transistor T2 by using the potential of the node P2 shown in FIG. 6, which can effectively avoid the use of the storage capacitor C1 to control the output delay of the output transistor and the like.
  • the shift register and the gate driving circuit provided by the above embodiments of the present disclosure cancel the bootstrap function of the storage capacitor C1 during the operation of the output circuit, and the gate of the second output transistor T2 is The DC voltage input from the first output transistor T1 is driven, so that the influence of the storage capacitor C1 on the load (output) of the output terminal OUTPUT can be blocked, and the display quality can be improved.
  • the gate drive circuit 10 can include a plurality of cascaded shift registers 100 provided by any of the embodiments of the present disclosure.
  • the input signal terminal INPUT of the shift register 100 of the present stage is connected to the output terminal OUTPUT of the shift register of the previous stage; the reset signal terminal RESET of the shift register of the present stage is The output of the next stage shift register is connected to OUTPUT.
  • the forward scanning control signal terminal FW is input to a high level, and the reverse scanning control signal terminal BW is input to a low level; when the gate driving circuit is used 10 In the reverse scan, the reverse scan control signal terminal BW input is a high level signal, and the forward scan control signal terminal FW input is a low level.
  • the input circuit of the shift register 100 is interchanged with the function of the reset circuit.
  • the gate driving circuit 10 includes n stages of shift registers SR(1), SR(2), ..., SR(n), SR(n+1), ..., SR(N), where n has a value range greater than Equal to zero and less than or equal to the total number of stages N (n ⁇ N) of the cascade of shift registers 100, n and N are both positive integers, and these shift registers may each be the shift register 100 provided by any of the embodiments of the present disclosure.
  • the output terminals OUTPUT of the shift registers SR(1), SR(2), ...SR(n), SR(n+1)...SR(N) are respectively connected to the gate lines Gate(1), Gate(2), ... Gate(n), Gate(n+1)...Gate(N) are connected.
  • the first clock signal terminal CLK1 and the second clock signal terminal CLK2 in FIG. 8 are complementary, and the cascade of shift registers can be implemented.
  • the gate driving circuit 10 provided by the embodiment of the present disclosure can implement forward scanning and reverse scanning, when the scanning direction is switched, the “upper level” and “next level” in the timing are changed accordingly. Therefore, the above-mentioned “upper level” and “lower level” do not refer to the upper level and the lower level in the scanning timing, but refer to the upper level and the lower level on the physical connection.
  • the second voltage terminal PCH and the DC voltage terminal GCH of each shift register are the same voltage terminal.
  • an embodiment of the present disclosure further provides a display panel 1 including a gate driving circuit 10 provided by any embodiment of the present disclosure.
  • the display panel 1 provided by the embodiment of the present disclosure further includes a gate line 11 , a data line 12 , and a plurality of pixel units 13 defined by the intersection of the gate line 11 and the data line 12 , and the gate driving circuit 10 is
  • the gate line 11 is configured to provide a gate drive signal (ie, a scan signal).
  • the gate line 11 may include the gate lines Gate(1), Gate(2), ..., Gate(n), Gate(n+1), ..., Gate(N), and the shift register SR (1) shown in FIG.
  • Each stage shift register is used to the corresponding gate line Gate(1), Gate(2)...Gate (n), Gate(n+1)... Gate(N) outputs a gate drive signal.
  • an embodiment of the present disclosure further provides a driving method of the shift register 100 according to any of the embodiments of the present disclosure.
  • the shift register driving method may include: step S10, in the input stage, setting a reset signal of the reset signal terminal RESET input to an invalid signal, setting a clock signal input by the clock signal terminal CLK to an invalid signal, and setting an input signal terminal INPUT input
  • the input signal is a valid signal to pull the potential of the pull-up node PU high; in step S20, in the output stage, the input signal is set to be an invalid signal, the reset signal is set to be an invalid signal, and the clock signal CLK is set to be effective.
  • step S30 in the reset phase, the input signal is set to be an invalid signal, and the clock signal is set to be an invalid signal.
  • step S40 in the holding phase, setting the The input signal is an invalid signal, the clock signal is set to be an invalid signal, and the reset signal is set to be an invalid signal. No. to maintain the potential of the pull-down node PD that is pulled high and the potential of the pull-up node PU and the potential of the output terminal OUTPUT that are pulled low.
  • the active signal is a high voltage signal and the invalid signal is a low voltage signal.
  • the effective signal is a low voltage signal and the invalid signal is a high voltage signal.
  • the present disclosure provides a shift register, a gate drive circuit, a display panel, and a driving method such that a display region uses a DC signal to drive a gate of a switching transistor of a display region. Dynamic power consumption can be reduced compared to driving the gate with the clock signal CLK.
  • the shift register, the gate driving circuit, the display panel, and the driving method provided by the present disclosure can block the influence of the storage capacitor on the load of the scan output signal, and improve Display quality.

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Abstract

一种移位寄存器(100)、栅极驱动电路(10)、显示面板(1)及驱动方法。该移位寄存器(100)包括：输入电路(110)，与上拉节点(PU)和输入信号端(INPUT)分别连接；输出电路(120)，与所述上拉节点(PU)、时钟信号端(CLK)、直流信号端(GCH)及输出端(OUTPUT)分别连接，其中，所述时钟信号端(CLK)提供时钟信号，所述直流信号端(GCH)提供直流信号，所述输出电路(120)从所述输出端(OUTPUT)输出扫描信号；以及输出下拉电路(130)，与所述输出电路(120)连接。所述输出电路(120)被配置为，在满足第一输出条件时，从所述输出端(OUTPUT)输出的扫描信号为所述直流信号和所述时钟信号之一；所述输出下拉电路(130)被配置为，在满足第二输出条件时，下拉所述扫描信号。

Description

移位寄存器、栅极驱动电路、显示面板及驱动方法 技术领域
本公开的实施例涉及一种移位寄存器、栅极驱动电路、显示面板及驱动方法。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。栅极驱动电路基板(Gate-driver on Array，GOA)技术是通过光刻工艺将栅极驱动电路直接集成在显示装置的阵列基板上，GOA电路通常包括多个级联的移位寄存器，每个移位寄存器均对应一行栅线(例如，每个移位寄存器给一行栅线提供扫描驱动信号)，以实现对显示面板的扫描驱动。这种集成技术可以节省栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的空间，从而实现显示面板的窄边框，同时可以降低产品成本、提高产品的良率。
发明内容
本公开的实施例提供一种移位寄存器，包括：输入电路，与上拉节点和输入信号端分别连接；输出电路，与所述上拉节点、时钟信号端、直流信号端及输出端分别连接，其中，所述时钟信号端提供时钟信号，所述直流信号端提供直流信号，所述输出电路从所述输出端输出扫描信号；以及输出下拉电路，与所述输出电路连接。所述输出电路被配置为，在满足第一输出条件时，从所述输出端输出的扫描信号为所述直流信号和所述时钟信号之一；所述输出下拉电路被配置为，在满足第二输出条件时，下拉所述扫描信号。
例如，所述输出电路包括存储电容、第一输出晶体管以及第二输出晶体管。
例如，在满足所述第一输出条件时，所述输出电路被配置为从所述输出端输出来自所述直流信号端的直流信号；所述第一输出晶体管的第一极与所述时钟信号端连接，所述第一输出晶体管的控制极与所述上拉节点连接，所 述第一输出晶体管的第二极与所述第二输出晶体管的控制极连接，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述第一输出晶体管的第二极连接；所述第二输出晶体管的第一极与所述直流信号端连接，所述第二输出晶体管的第二极与所述输出端连接；以及在所述第二输出晶体管导通时，满足所述第一输出条件。
例如，所述的移位寄存器还包括下拉控制电路，其中，所述下拉控制电路包括第一控制晶体管、第二控制晶体管、第三控制晶体管和第四控制晶体管，所述第一控制晶体管的第一极与第二电压端连接，所述第一控制晶体管的第二极与所述下拉节点连接；所述第二控制晶体管的第一极与所述下拉节点连接，所述第二控制晶体管的控制极与所述上拉节点连接，所述第二控制晶体管的第二极与第一电压端连接；所述第三控制晶体管的第一极与所述第二电压端连接，所述第三控制晶体管的控制极与所述第二电压端连接，所述第三控制晶体管的第二极与所述第一控制晶体管的控制极连接；所述第四控制晶体管的第一极与所述第三控制晶体管的第二极连接，所述第四控制晶体管的控制极与所述上拉节点连接，所述第四控制晶体管的第二极与所述第一电压端连接。
例如，在满足所述第一输出条件时，所述输出电路被配置为从所述输出端输出来自所述时钟信号端的时钟信号；所述第一输出晶体管的第一极与所述直流信号端连接，所述第一输出晶体管的控制极与所述上拉节点连接，所述第一输出晶体管的第二极与所述第二输出晶体管的控制极连接，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述第一输出晶体管的第二极连接；所述第二输出晶体管的第一极与所述时钟信号端连接，所述第二输出晶体管的第二极与所述输出端连接；以及在所述第二输出晶体管导通时，满足所述第一输出条件。
例如，所述的移位寄存器还包括下拉控制电路，其中，所述下拉控制电路包括第一控制晶体管、第二控制晶体管；所述第一控制晶体管的第一极与第二电压端连接，所述第一控制晶体管的控制极与所述第二电压端连接，所述第一控制晶体管的第二极与下拉节点连接；所述第二控制晶体管的第一极与所述下拉节点连接，所述第二控制晶体管的第二极与第一电压端连接，所述第二控制晶体管的控制极与所述上拉节点连接。
例如，所述输出下拉电路包括第一输出下拉晶体管和第二输出下拉晶体管；所述第一输出下拉晶体管的第一极与所述第一输出晶体管的第二极连接，所述第一输出下拉晶体管的控制极与下拉节点连接，所述第一输出下拉晶体管的第二极与第一电压端连接；所述第二输出下拉晶体管的第一极与所述输出端连接，所述第二输出下拉晶体管的控制极与所述下拉节点连接，所述第二输出下拉晶体管的第二极与所述第一电压端连接。
例如，在所述第二输出下拉晶体管导通时，满足所述第二输出条件。
例如，所述的移位寄存器还包括复位电路，与所述上拉节点、复位信号端及第三电压端连接，其中，所述复位电路被配置为在满足复位条件时，接收来自所述第三电压端的第三电压信号，以对所述输出电路进行复位。
例如，所述复位电路包括复位晶体管；所述复位晶体管的控制极与所述复位信号端连接，所述复位晶体管的第一极与所述上拉节点连接，所述复位晶体管的第二极与所述第三电压端连接。
例如，所述的移位寄存器还包括下拉保持电路，所述下拉保持电路被配置为在所述上拉节点的下拉条件被满足时，下拉所述上拉节点的电位。
例如，所述的移位寄存器，其中，所述下拉保持电路包括下拉保持晶体管；所述下拉保持晶体管的控制极与下拉节点连接，所述下拉保持晶体管的第一极与所述上拉节点连接，所述下拉保持电路的第二极与所述第一电压端连接。
本公开的实施例提供一种栅极驱动电路，包括级联的多个移位寄存器，其中，每个移位寄存器为本公开任一实施例提供的移位寄存器，其中，除第一级和最后一级移位寄存器之外，本级移位寄存器的输入信号端与上一级移位寄存器的输出端连接；本级移位寄存器的复位信号端与下一级移位寄存器的输出端连接。
本公开的实施例提供一种显示面板，包括本公开任一实施例提供的栅极驱动电路。
本公开的实施例提供一种驱动本公开任一实施例提供的移位寄存器的驱动方法，包括：在输入阶段，设置复位信号端输入的复位信号为无效信号，设置所述时钟信号端输入的时钟信号为无效信号，设置输入信号端输入的输入信号为有效信号，以将上拉节点的电位拉高；在输出阶段，设置所述输入 信号为无效信号，设置所述复位信号为无效信号，设置所述时钟信号为有效信号，以从输出端输出扫描信号，其中，所述扫描信号为直流信号或者时钟信号之一；在复位阶段，设置所述输入信号为无效信号，设置所述时钟信号为无效信号，设置所述复位信号为有效信号，以将所述上拉节点的电位和所述输出端的电位拉低，下拉节点的电位拉高；在保持阶段，设置所述输入信号为无效信号，设置所述时钟信号为无效信号，设置所述复位信号为无效信号，以保持被拉高的所述下拉节点的电位和被拉低的所述上拉节点的电位和所述输出端的电位。
例如，所述有效信号为高电压信号，所述无效信号为低电压信号。
在一些实施例中，本公开提供的移位寄存器、栅极驱动电路、显示面板及驱动方法，使得显示区采用直流信号来驱动显示区的开关晶体管的栅极，相比于采用时钟信号CLK驱动栅极，可以减低动态功耗。在一些实施例中，本公开提供的移位寄存器、栅极驱动电路、显示面板及驱动方法，可以隔断存储电容对扫描输出信号的影响，提升显示质量。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开实施例提供的一种移位寄存器的示意图之一；
图2A是本公开实施例提供的一种移位寄存器的示意图之二；
图2B是本公开实施例提供的一种移位寄存器的示意图之三；
图2C是本公开实施例提供的一种移位寄存器的示意图之四；
图2D-图2F是本公开实施例中的输出电路的示意图；
图3是本公开实施例提供的一种移位寄存器的示意性的电路结构图之一；
图4是本公开实施例提供的图3所示的移位寄存器的驱动时序图；
图5是本公开实施例提供的移位寄存器的级联图之一；
图6是本公开实施例提供的一种移位寄存器的示意性的电路结构图之二；
图7是本公开实施例提供的图6所示的移位寄存器的驱动时序图；
图8是本公开实施例提供的移位寄存器的级联图之二；
图9是本公开实施例提供的一种显示面板的示意图；
图10是本公开实施例提供的一种移位寄存器的驱动方法的流程图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。本公开的实施例提供一种移位寄存器100，如图1所示，该移位寄存器100包括输入电路110、输出电路120和输出下拉电路130。输入电路110与上拉节点PU和输入信号端INPUT分别连接；输出电路120与上拉节点PU、时钟信号端CLK、直流信号端GCH及输出端OUTPUT分别连接。所述时钟信号端CLK提供时钟信号，所述直流信号端GCH提供直流信号，所述输出电路120从所述输出端OUTPUT输出扫描信号。输出下拉电路130与输出电路120连接。
上述移位寄存器100中，输出电路120被配置为，在满足第一输出条件时，从输出端OUTPUT输出的扫描信号为所述直流信号和所述时钟信号之一；输出下拉电路130被配置为，在满足第二输出条件时，下拉所述扫描信号。
在一些实施例中，输出下拉电路130被配置为将第一电源端VGL提供的电压写入输出端OUTPUT。例如，从输出端OUTPUT输出的扫描信号被 所述输出下拉电路130下拉为第一电源端VGL提供的电压VGL。
例如，如图2A所示，在一些实施例中，移位寄存器100还可以包括下拉控制电路140、复位电路150以及下拉保持电路160中的一个或多个。
例如，如图2B所示，移位寄存器100可以包括输入电路110、输出电路120、输出下拉电路130以及复位电路150。复位电路150被配置为下拉上拉节点PU的电位，并通过复位端RESET输入的复位信号控制输出下拉电路130。
例如，如图2C所示，移位寄存器100可以包括输入电路110、输出电路120、输出下拉电路130以及下拉控制电路140。
在一些实施例中，下拉控制电路140可以被配置为通过控制输出下拉电路130而拉低输出端OUTPUT的输出电压。复位电路150可以被配置为拉低上拉节点PU的电压。下拉保持电路160可以被配置为拉低上拉节点PU的电位，并在移位寄存器工作在保持阶段时使上拉节点PU保持低电位。
如图2D所示，在本公开的这些实施例的示例中，输出电路120包括第一输出子电路121、第二输出子电路122、存储子电路123。在该输出电路120中，存储子电路123不再与输出端OUTPUT直接相连，而是通过第二输出子电路122与输出端OUTPUT相连，从而可以降低存储子电路123对于输出端OUTPUT的负载的不利影响。
第一输出子电路121与上拉节点PU、存储子电路123、输出控制节点A连接，以及与时钟信号端CLK或直流信号端GCH连接，在上拉节点PU的控制下，将时钟信号端CLK或直流信号端GCH的信号输出至输出控制节点A以控制其电平。
第二输出子电路122与输出控制节点A、输出端OUTPUT连接，以及与直流信号端GCH或时钟信号端CLK连接，可以在输出控制节点A的电平的控制下，将直流信号端GCH或时钟信号端CLK的信号输出至输出端OUTPUT，以作为输出信号。也即，第一输出子电路121和第二输出子电路122之一与时钟信号端CLK连接，则另一个与直流信号端GCH连接。
存储子电路123与上拉节点PU以及输出控制节点A连接，用于存储上拉节点PU的电平，还可以在时钟信号端CLK被输出至输出控制节点A时对上拉节点PU进行自举，以进一步控制上拉节点PU的电平，或者在直流 信号端GCH的信号被输出至输出控制节点A时，保持上拉节点PU的电平。
在一个示例中，如图2E所示，输出电路120包括存储电容C1、第一输出晶体管T1以及第二输出晶体管T2，分别用于实现存储子电路123、第一输出子电路121以及第二输出子电路122。第一输出晶体管T1的第一极与时钟信号端CLK连接，第一输出晶体管T1的控制极与上拉节点PU连接，第一输出晶体管T1的第二极与输出控制节点G_N连接，从而与第二输出晶体管T2的控制极连接，存储电容C1的第一端与上拉节点PU连接，存储电容C1的第二端与第一输出晶体管T1的第二极连接。第二输出晶体管T2的第一极与直流信号端GCH连接，第二输出晶体管T2的第二极与输出端OUTPUT连接。
在图2E所示的示例中，输出电路工作过程中，时钟信号端CLK不直接与输出端OUTPUT相连，即时钟信号端CLK与被驱动的显示面板的显示区的负载(loading)分开，而是将直流电压端GCH直接与输出端OUTPUT相连，即采用直流电压信号GCH驱动显示区的负载，因此可以降低时钟信号端CLK的动态功耗。
或者，如图2F所示，输出电路120包括存储电容C1、第一输出晶体管T1以及第二输出晶体管T2，分别用于实现存储子电路123、第一输出子电路121以及第二输出子电路122。第一输出晶体管T1的第一极与直流信号端GCH连接，第一输出晶体管T1的控制极与上拉节点PU连接，第一输出晶体管T1的第二极与输出控制节点P2连接，从而与第二输出晶体管T2的控制极连接，存储电容C1的第一端与上拉节点PU连接，存储电容C1的第二端与第一输出晶体管T1的第二极连接；第二输出晶体管T2的第一极与时钟信号端CLK连接，第二输出晶体管T2的第二极与输出端OUTPUT连接。
在图2E所示的示例中，输出电路120取消了存储电容C1在该输出电路120工作过程中的自举作用，第二输出晶体管T2的栅极由通过第一输出晶体管T1输入的直流电压驱动，因此可以隔断存储电容C1对输出端OUTPUT输出的扫描信号(的负载)的影响。
本公开的另一个实施例提供一种移位寄存器，其包括输入电路、输出电路与输出下拉电路。输入电路与上拉节点和输入信号端分别连接；输出电路与上拉节点、时钟信号端、直流信号端及输出端分别连接；输出下拉电路与 输出电路连接。时钟信号端提供时钟信号，直流信号端提供直流信号，输出电路从输出端输出扫描信号。输出电路包括第一输出子电路、第二输出子电路、存储子电路。第一输出子电路和存储子电路与上拉节点相连，且配合控制输出控制节点的电平，第二输出子电路与输出端连接，且由控制节点的电平控制是否在输出端输出扫描信号。
下面将结合图3-4对移位寄存器100和栅极驱动电路10的示例性的电路结构进行详细的说明。
如图3所示，该移位寄存器100包括输入电路110、输出电路120和输出下拉电路130。输出电路120可以包括存储电容C1、第一输出晶体管T1以及第二输出晶体管T2。
在满足第一输出条件时(例如，图3中的第二输出晶体管T2导通或开启时)，输出电路120可以被配置为从输出端OUTPUT输出来自直流信号端GCH的直流信号。第一输出晶体管T1的第一极与时钟信号端CLK连接，第一输出晶体管T1的控制极与上拉节点PU连接，第一输出晶体管T1的第二极与第二输出晶体管T2的控制极连接。存储电容C1的第一端与上拉节点PU连接，存储电容C1的第二端与第一输出晶体管T1的第二极连接。第二输出晶体管T2的第一极与直流信号端GCH连接，第二输出晶体管T2的第二极与输出端OUTPUT连接。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。晶体管的控制极为晶体管的栅极。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、或其他数值)，关闭电压为高电平电压(例如，5V、10V、或其他数值)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他数值)，关闭电压为低电平电压(例如，0V、-5V 或其他数值)。
需要说明的是，本公开的实施例以各个晶体管均为N型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够想到本公开实施例采用P型晶体管或N型和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，如图3所示，在一些实施例中，下拉控制电路140与第一电压端VGL和第二电压端PCH连接。在一些实施例中，第二电压端PCH输入的电压与直流电压端GCH输入的电压可以相同。例如，第二电压端PCH和直流电压端GCH为同一电压端。
如图3所示，下拉控制电路140可以包括第一控制晶体管M1、第二控制晶体管M2、第三控制晶体管M3和第四控制晶体管M4。第一控制晶体管M1的第一极与第二电压端PCH连接，第一控制晶体管M1的第二极与下拉节点PD连接；第二控制晶体管M2的第一极与下拉节点PD连接，第二控制晶体管M2的控制极与上拉节点PU连接，第二控制晶体管M2的第二极与第一电压端VGL连接；第三控制晶体管M3的第一极与第二电压端PCH连接，第三控制晶体管M3的控制极与第二电压端PCH连接，第三控制晶体管M3的第二极与第一控制晶体管M1的控制极连接；第四控制晶体管M4的第一极与第三控制晶体管M3的第二极连接，第四控制晶体管M4的控制极与上拉节点PU连接，第四控制晶体管M4的第二极与第一电压端VGL连接。
需要说明的是，图3所示的下拉控制电路140仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图3所示的情形。
如图3所示，在一些实施例中，输出下拉电路130可以包括第一输出下拉晶体管K1和第二输出下拉晶体管K2。第一输出下拉晶体管K1的第一极与第一输出晶体管T1的第二极连接，第一输出下拉晶体管K1的控制极与下拉节点PD连接，第一输出下拉晶体管K1的第二极与第一电压端VGL连接；第二输出下拉晶体管K2的第一极与输出端OUTPUT连接，第二输出下拉晶体管K2的控制极与下拉节点PD连接，第二输出下拉晶体管K2的第二极与第一电压端VGL连接。
例如，在满足第二输出条件时(即，第二输出下拉晶体管K2导通或开启时)，所述输出下拉电路130被配置为将所述扫描信号下拉至VGL的电 位。
如图3所示，在一些实施例中，复位电路150被配置为在满足复位条件时(例如，图3所示的复位晶体管T4导通时)，接收来自所述第三电压端VSS的第三电压信号，以对所述输出电路120进行复位。
例如，如图3所示复位电路150包括复位晶体管T4。复位晶体管T4的控制极与复位信号端RESET相连，复位晶体管T4的第一极与上拉节点PU相连，复位晶体管T4的第二极与第三电源端VSS相连。
例如，在一些实施例中，如果移位寄存器100不包括下拉控制电路140时(如图2B所示)，下拉电路130的第一输出下拉晶体管K1以及第二输出下拉晶体管K2的控制极可以均与复位信号端RESET相连。
需要说明的是，图3所示的复位电路150仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图3所示的情形。
如图3所示，在一些实施例中，下拉保持电路160被配置为在上拉节点PU的下拉条件被满足时，下拉上拉节点PU的电位。
例如，如图3所示，下拉保持电路160可以包括下拉保持晶体管T5；下拉保持晶体管T5的控制极与下拉节点PD连接，下拉保持晶体管T5的第一极与上拉节点PU连接，下拉保持晶体管T5的第二极与第一电压端VGL连接。例如，在上拉节点PU的下拉条件被满足时(例如，当下拉保持晶体管T5导通或开启时)，上拉节点PU的电位被下拉至VGL的电位。
需要说明的是，图3所示的下拉保持电路160仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图3所示的情形。
如图3所示，在一些实施例中，输入电路110可以包括输入晶体管T3，该输入晶体管T3的控制极与输入信号端INPUT连接，输入晶体管T3的第一极与第四电压端VDD连接，输入晶体管T3与上拉节点PU连接。
需要说明的是，图3所示的输入电路110仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图3所示的情形。
下面结合图3以及图4的时序图示范性说明驱动图3电路的过程。在图3中，第一输出晶体管T1的第二极与第二输出晶体管T2的控制极相连的节点为G_N节点。
第一阶段为输入阶段，在输入阶段时设置复位信号端RESET的复位信 号、时钟信号端CLK的时钟信号为低电平，输入端INPUT的输入信号为高电平。
由于复位信号为低电平，复位晶体管T4关断；输入信号为高电平，输入晶体管T3导通，存储电容C1通过输入晶体管T3充电，此时上拉节点PU点为高电平，第二控制晶体管M2和第四控制晶体管M4导通。下拉节点PD点为低电平，第一下拉晶体管K1、第二下拉晶体管K2和下拉保持晶体管T5均关断，保证正常输入。由于上拉节点PU点为高电平，第一输出晶体管T1导通，时钟信号为低电平，所以G_N节点输出低电平，第二输出晶体管T2关断，输出端OUTPUT输出低电平。
第二阶段为输出阶段，输入信号、复位信号为低电平，时钟信号为高电平。由于存储电容C1的保持作用，上拉节点PU点为高电平，第一输出晶体管T1导通，时钟信号为高电平，则节点G_N输出高电平，第二输出晶体管T2打开，所以输出端OUTPUT输出高电平。此时下拉节点PD电位为低电平，下拉保持晶体管T5、第一下拉晶体管K1、第二下拉晶体管K2均关断，保证正常输出。
第三阶段为复位阶段，此时时钟信号、输入信号为低电平，复位信号为高电平。由于复位信号为高电平，复位晶体管T4导通，上拉节点PU为低电平，第二控制晶体管M2和第四控制晶体管M4关断。下拉节点PD为高电平，下拉保持晶体管T5、第一下拉晶体管K1、第二下拉晶体管K2导通。上拉节点PU、节点G_N以及输出端的信号均为低电平。
第四阶段为保持阶段，时钟信号、输入信号以及复位信号均为低电平。由于时钟信号、输入信号以及复位信号均为低电平，则输入晶体管T3、复位晶体管T4关断。上拉节点PU为低电平，第二控制晶体管M2和第四控制晶体管M4关断。下拉节点PD为高电平，下拉保持晶体管T5、第一下拉晶体管K1以及第二下拉晶体管K2导通，将上拉节点PU、节点G_N和输出端OUTPUT的电位继续保持为低电平。
在进入第四阶段之后以及下一帧到来之前的这段时间，包含上述移位寄存器100的栅极驱动电路一直工作于第四阶段。
下面结合图5说明包含上述图3所示的移位寄存器100的栅极驱动电路10的结构。
如图5所示，栅极驱动电路10可以包括级联的多个移位寄存器(例如图5中的两个级联的移位寄存器100)。每个移位寄存器均可以为本公开任一实施例提供的移位寄存器100。除第一级和最后一级移位寄存器100之外，本级移位寄存器100的输入信号端INPUT与上一级移位寄存器100中的节点G_N连接；本级移位寄存器的复位信号端RESET与下一级移位寄存器100的节点G_N连接。
例如，栅极驱动电路10包括n级移位寄存器100，每一级移位寄存器的输出端OUTPUT分别与显示面板的栅线G1、G2…Gi，G(i+1)…Gn对应连接，其中i的取值范围为大于等于0且小于等于n，i和n均为正整数。例如，图5中的第一时钟信号端CLK1与第二时钟信号端CLK2为互补关系，可以实现移位寄存器的级联。
在图5中，各移位寄存器的第二电压端PCH和直流电压端GCH为同一电压端。
本公开上述实施例提供采用图3示出的节点G_N的电位控制第二输出晶体管T2的输出，这样能够有效避免采用存储电容C1控制输出晶体管的输出延时等缺陷。结合图3-5的描述，本公开的上述实施例提供的移位寄存器和栅极驱动电路，可以隔断存储电容C1对输出端OUTPUT输出的扫描信号的影响，提升显示质量。
而且，在本实施例中，将通过增加第二输出晶体管T2，在输出阶段时钟信号端CLK不直接与输出端OUTPUT相连，即时钟信号端CLK与被驱动的显示面板的显示区的负载(loading)分开，而是将直流电压端GCH直接与输出端OUTPUT相连，即采用直流电压信号GCH驱动显示区的负载。因此，该实施例可以降低时钟信号端CLK的动态功耗，有助于提高显示面板的显示质量。
需要说明的是，由于本公开实施例提供的栅极驱动电路10可以实现正向扫描和逆向扫描，在扫描方向切换时，时序上的“上一级”和“下一级”会相应变换，因此，上述的“上一级”和“下一级”并不是指扫描时序上的上一级和下一级，而是指物理连接上的上一级和下一级。
结合上面对图3-5的描述，本公开实施例提供的移位寄存器100和栅极驱动电路10，使得显示区采用直流信号来驱动显示区的开关晶体管的栅极， 相比于采用时钟信号CLK驱动栅极，可以减低动态功耗。
下面将结合图6-8对移位寄存器100和栅极驱动电路10的另一示例性的电路结构进行详细的说明。如图6所示，输出电路120可以包括存储电容C1、第一输出晶体管T1以及第二输出晶体管T2。
在一些实施例中，在满足第一输出条件时(例如图6中的第二输出晶体管T2导通时)，输出电路120被配置为从输出端OUTPUT输出来自时钟信号端CLK的时钟信号。第一输出晶体管T1的第一极与直流信号端GCH连接，第一输出晶体管T1的控制极与上拉节点PU连接，第一输出晶体管T1的第二极P2与第二输出晶体管T2的控制极连接。存储电容C1的第一端与上拉节点PU连接，存储电容C1的第二端与第一输出晶体管T1的第二极连接。第二输出晶体管T2的第一极与时钟信号端CLK连接，第二输出晶体管T2的第二极与输出端OUTPUT连接。
例如，如图6所示，在一些实施例中，下拉控制电路140可以包括第一控制晶体管M1和第二控制晶体管M2。第一控制晶体管M1的第一极与第二电压端PCH连接，第一控制晶体管M1的控制极与第二电压端PCH连接，第一控制晶体管M1的第二极与下拉节点PD连接；第二控制晶体管M2的第一极与下拉节点PD连接，第二控制晶体管M2的第二极与第一电压端VGL连接，第二控制晶体管M2的控制极与上拉节点PU连接。例如，第二电源端PCH输入的电压与直流电源端CGH输入的电压可以相同。例如，第二电压端PCH和直流电压端GCH为同一电压端。
需要说明的是，图6所示的下拉控制电路140仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图6所示的情形。
例如，如图6所示，在一些实施例中，输出下拉电路130可以包括第一输出下拉晶体管K1和第二输出下拉晶体管K2。第一输出下拉晶体管K1的第一极与第一输出晶体管T1的第二极连接，第一输出下拉晶体管K1的控制极与下拉节点PD连接，第一输出下拉晶体管K1的第二极与第一电压端VGL连接；第二输出下拉晶体管K2的第一极与输出端OUTPUT连接，第二输出下拉晶体管K2的控制极与下拉节点PD连接，第二输出下拉晶体管K2的第二极与第一电压端VGL连接。
例如，在满足第二输出条件时(即，第二输出下拉晶体管K2导通或开 启时)，所述输出下拉电路130被配置为将所述扫描信号下拉至VGL的电位。
例如，图6中的输出下拉控制电路140的电路结构也可以采用图3示出的下拉控制电路140的电路结构，同样地，图3的下拉控制电路140的电路结构也可以采用图6的下拉控制电路140的电路结构。
例如，在一些实施例中，复位电路150被配置为在满足复位条件时(例如，图5所示的复位晶体管T4导通时)，接收来自所述第三电压端VSS的第三电压信号，以对所述输出电路120进行复位。
例如，如图6所示，在一些实施例中，复位电路150包括复位晶体管T4。复位晶体管T4的控制极与复位信号端RESET相连，复位晶体管T4的第一极与上拉节点PU相连，复位晶体管T4的第二极与第三电源端VSS相连。
在一些实施例中，如果移位寄存器100不包括下拉控制电路140时(如图2B所示)，下拉电路130的第一输出下拉晶体管K1以及第二输出下拉晶体管K2的控制极均与复位信号端RESET相连。
需要说明的是，图6所示的复位电路150仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图6所示的情形。
如图6所示，在一些实施例中，下拉保持电路160被配置为在上拉节点PU的下拉条件被满足时，下拉上拉节点PU的电位。
例如，如图6所示，在一些实施例中，下拉保持电路160可以包括下拉保持晶体管T5。下拉保持晶体管T5的控制极与下拉节点PD连接，下拉保持晶体管T5的第一极与上拉节点PU连接，下拉保持晶体管T5的第二极与第一电压端VGL连接。例如，在上拉节点PU的下拉条件被满足时(例如，当下拉保持晶体管T5导通或开启时)，上拉节点PU的电位被下拉至VGL的电位。
需要说明的是，图6所示的下拉保持电路160仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图6所示的情形。
如图6所示，在一些实施例中，输入电路110可以包括输入晶体管T3，该输入晶体管T3的控制极与输入信号端INPUT连接，输入晶体管T3的第一极与第四电压端VDD连接，输入晶体管T3与上拉节点PU连接。
需要说明的是，图6所示的输入电路110仅为本公开实施例的一个示例， 本公开的实施例包括但不局限于图6所示的情形。
在一些实施例中，图6中示出的第二电压端PCH与直流电压端GCH合并为一个直流电压输入端。
下面结合图7的时序图示范性说明驱动图6电路的过程。图6中第一输出晶体管T1的第二极与第二输出晶体管T2的控制极相连的节点为P2节点。
在正向扫描时，正向扫描控制信号为高电平，反向扫描控制信号为低电平；在反向扫描时，正向扫描控制信号为低电平，反向扫描控制信号为高电平。以下以正向扫描为例说明驱动原理：
输入阶段：输入端INPUT的输入信号为高电平，复位信号端RESET的复位信号和时钟信号端CLK的时钟信号为低电平。
复位信号为低电平，则复位晶体管T4关断。输入信号为高电平，输入晶体管T3导通，存储电容C1充电，上拉节点PU为高电平。上拉节点为高电平时则第二控制晶体管M2导通。当第二控制晶体管M2导通时，下拉节点PD点被拉低至第一电压端的电压VGL。当下拉节点PD为低电平时则第一下拉晶体管K1、第二下拉晶体管K2以及下拉保持晶体管T5关断，保证正常输入。当上拉节点PU为高电平，第一输出晶体管T1导通，节点P2点的电位为高电平，第二输出晶体管T2打开。由于时钟信号为低电平，所以输出端OUTPUT输出低电平。
输出阶段：时钟信号为高电平，输入信号和复位信号为低电平。
由于复位信号、输入信号为低电平，输入晶体管T3和复位晶体管T4关断。由于存储电容C1的保持作用，上拉节点PU为高电平，第二控制晶体管M2以及第一输出晶体管T1导通；下拉节点PD点仍为低电平，第一下拉晶体管K1、第二下拉晶体管K2以及下拉保持晶体管T5关断，保证正常的输出。由于节点P2仍为高电平，第二输出晶体管T2导通，时钟信号为高电平，则输出端OUTPUT输出高电平。
复位阶段：复位信号为高电平，输入信号以及时钟信号为低电平。
由于输入信号为低电平，输入晶体管T3关断；复位信号为高电平，复位晶体管T4导通，存储电容C1通过复位晶体管T4放电；上拉节点PU为低电平,第二控制晶体管M2以及第一输出晶体管T1关断；下拉节点PD点为高电平，第一下拉晶体管K1、第二下拉晶体管K2以及下拉保持晶体管T5导 通。上拉节点PU、节点P2、输出端OUTPUT被拉低至低电平。
保持阶段：输入信号以及复位信号均为低电平。
此时输入信号以及复位信号为低电平，输入晶体管T3以及复位晶体管T4关断；此时上拉节点PU为低电平，第二控制晶体管M2以及第一输出晶体管T1关断；下拉节点PD为高电平，第一下拉晶体管K1、第二下拉晶体管K2以及下拉保持晶体管T5导通，保证上拉节点PU点、节点P2、输出端点位保持为低电平，保证正常显示。
在进入第四阶段之后以及下一帧到来之前的这段时间，移位寄存器100一直重复第四阶段。
本公开实施例提供采用图6示出的节点P2的电位控制第二输出晶体管T2的输出，这样能够有效避免采用存储电容C1控制输出晶体管的输出延时等缺陷。结合图6-8的描述，本公开的上述实施例提供的移位寄存器和栅极驱动电路，取消了存储电容C1在输出电路工作过程中的自举作用，第二输出晶体管T2的栅极由通过第一输出晶体管T1输入的直流电压驱动，因此可以隔断存储电容C1对输出端OUTPUT输出的扫描信号(的负载)的影响，提升显示质量。
如图8所示，该图提供一种栅极驱动电路10。栅极驱动电路10可以包括级联的多个本公开任一实施例提供的移位寄存器100。除第一级和最后一级移位寄存器100之外，本级移位寄存器100的输入信号端INPUT与上一级移位寄存器的输出端OUTPUT连接；本级移位寄存器的复位信号端RESET与下一级移位寄存器的输出端OUTPUT连接。
例如，如图8所示，当栅极驱动电路10正向扫描时，正向扫描控制信号端FW输入为高电平，反向扫描控制信号端BW输入为低电平；当栅极驱动电路10反向扫描时，反向扫描控制信号端BW输入为高电平信号，正向扫描控制信号端FW输入为低电平。例如，在正向扫描和反向扫描切换时，移位寄存器100的输入电路与复位电路的功能互换。
例如，栅极驱动电路10包括n级移位寄存器SR(1)、SR(2)……SR(n),SR(n+1)……SR(N)，其中n的取值范围为大于等于零且小于等于移位寄存器100级联的总级数N(n≤N)，n和N均为正整数，这些移位寄存器均可以是本公开任一实施例提供的移位寄存器100。移位寄存器SR(1)、SR(2)……SR(n), SR(n+1)……SR(N)的输出端OUTPUT分别与栅线Gate(1)、Gate(2)……Gate(n)、Gate(n+1)……Gate(N)对应连接。例如，图8中的第一时钟信号端CLK1与第二时钟信号端CLK2为互补关系，可以实现移位寄存器的级联。
需要说明的是，由于本公开实施例提供的栅极驱动电路10可以实现正向扫描和逆向扫描，在扫描方向切换时，时序上的“上一级”和“下一级”会相应变换，因此，上述的“上一级”和“下一级”并不是指扫描时序上的上一级和下一级，而是指物理连接上的上一级和下一级。
在图8中，各移位寄存器的第二电压端PCH和直流电压端GCH为同一电压端。
如图9所示，本公开的实施例还提供一种显示面板1，显示面板1包括本公开任一实施例提供的栅极驱动电路10。
例如，如图9所示，本公开实施例提供的显示面板1还包括栅线11、数据线12以及由栅线11和数据线12交叉限定的多个像素单元13，栅极驱动电路10被配置为向栅线11提供栅极驱动信号(即，扫描信号)。例如，栅线11可以包括图8中所示的栅线Gate(1)、Gate(2)……Gate(n)、Gate(n+1)……Gate(N)，移位寄存器SR(1)、SR(2)……SR(n),SR(n+1)……SR(N)中每级移位寄存器用于向对应的栅线Gate(1)、Gate(2)……Gate(n)、Gate(n+1)……Gate(N)输出栅极驱动信号。
如图10所示，本公开实施例还提供一种如本公开任一实施例的移位寄存器100的驱动方法。移位寄存器驱动方法可以包括：步骤S10，在输入阶段，设置复位信号端RESET输入的复位信号为无效信号，设置所述时钟信号端CLK输入的时钟信号为无效信号，设置输入信号端INPUT输入的输入信号为有效信号，以将上拉节点PU的电位拉高；步骤S20，在输出阶段，设置所述输入信号为无效信号，设置所述复位信号为无效信号，设置所述时钟信号CLK为有效信号，以从输出端OUTPUT输出扫描信号，其中，所述扫描信号为直流信号或者时钟信号之一；步骤S30，在复位阶段，设置所述输入信号为无效信号，设置所述时钟信号为无效信号，设置所述复位信号为有效信号，以将所述上拉节点PU的电位和所述输出端OUTPUT的电位拉低，下拉节点PD的电位拉高；以及步骤S40，在保持阶段，设置所述输入信号为无效信号，设置所述时钟信号为无效信号，设置所述复位信号为无效信号， 以保持被拉高的所述下拉节点PD的电位和被拉低的所述上拉节点PU的电位和所述输出端OUTPUT的电位。
例如，对于N型晶体管而言，有效信号为高电压信号，无效信号为低电压信号。而对于P型晶体管而言，有效信号为低电压信号，无效信号为高电压信号。
在一些实施例中(例如，结合图3-5)，本公开提供的移位寄存器、栅极驱动电路、显示面板及驱动方法，使得显示区采用直流信号来驱动显示区的开关晶体管的栅极，相比于采用时钟信号CLK驱动栅极，可以减低动态功耗。在一些实施例中(例如，结合图6-8)，本公开提供的移位寄存器、栅极驱动电路、显示面板及驱动方法，可以隔断存储电容对扫描输出信号(的负载)的影响，提升显示质量。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本公开要求于2017年8月29日递交的中国专利申请第201710755253.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (16)

  1. 一种移位寄存器，包括：
    输入电路，与上拉节点和输入信号端分别连接；
    输出电路，与所述上拉节点、时钟信号端、直流信号端及输出端分别连接，其中，所述时钟信号端提供时钟信号，所述直流信号端提供直流信号，所述输出电路从所述输出端输出扫描信号；以及
    输出下拉电路，与所述输出电路连接，其中，
    所述输出电路被配置为，在满足第一输出条件时，从所述输出端输出的扫描信号为所述直流信号和所述时钟信号之一；
    所述输出下拉电路被配置为，在满足第二输出条件时，下拉所述扫描信号。
  2. 如权利要求1所述的移位寄存器，其中，所述输出电路包括存储电容、第一输出晶体管以及第二输出晶体管。
  3. 如权利要求2所述的移位寄存器，其中，
    在满足所述第一输出条件时，所述输出电路被配置为从所述输出端输出来自所述直流信号端的直流信号；
    所述第一输出晶体管的第一极与所述时钟信号端连接，所述第一输出晶体管的控制极与所述上拉节点连接，所述第一输出晶体管的第二极与所述第二输出晶体管的控制极连接，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述第一输出晶体管的第二极连接；
    所述第二输出晶体管的第一极与所述直流信号端连接，所述第二输出晶体管的第二极与所述输出端连接；以及
    在所述第二输出晶体管导通时，满足所述第一输出条件。
  4. 根据权利要求1-3任一项所述的移位寄存器，还包括下拉控制电路，其中，所述下拉控制电路包括第一控制晶体管、第二控制晶体管、第三控制晶体管和第四控制晶体管；
    所述第一控制晶体管的第一极与第二电压端连接，所述第一控制晶体管的第二极与下拉节点连接；
    所述第二控制晶体管的第一极与所述下拉节点连接，所述第二控制晶体 管的控制极与所述上拉节点连接，所述第二控制晶体管的第二极与第一电压端连接；
    所述第三控制晶体管的第一极与所述第二电压端连接，所述第三控制晶体管的控制极与所述第二电压端连接，所述第三控制晶体管的第二极与所述第一控制晶体管的控制极连接；
    所述第四控制晶体管的第一极与所述第三控制晶体管的第二极连接，所述第四控制晶体管的控制极与所述上拉节点连接，所述第四控制晶体管的第二极与所述第一电压端连接。
  5. 根据权利要求2所述的移位寄存器，其中，在满足所述第一输出条件时，所述输出电路被配置为从所述输出端输出来自所述时钟信号端的时钟信号；
    所述第一输出晶体管的第一极与所述直流信号端连接，所述第一输出晶体管的控制极与所述上拉节点连接，所述第一输出晶体管的第二极与所述第二输出晶体管的控制极连接，所述存储电容的第一端与所述上拉节点连接，所述存储电容的第二端与所述第一输出晶体管的第二极连接；
    所述第二输出晶体管的第一极与所述时钟信号端连接，所述第二输出晶体管的第二极与所述输出端连接；以及
    在所述第二输出晶体管导通时，满足所述第一输出条件。
  6. 根据权利要求1-3以及5中任一项所述的移位寄存器，还包括下拉控制电路，其中，所述下拉控制电路包括第一控制晶体管、第二控制晶体管；
    所述第一控制晶体管的第一极与第二电压端连接，所述第一控制晶体管的控制极与所述第二电压端连接，所述第一控制晶体管的第二极与下拉节点连接；
    所述第二控制晶体管的第一极与所述下拉节点连接，所述第二控制晶体管的第二极与第一电压端连接，所述第二控制晶体管的控制极与所述上拉节点连接。
  7. 根据权利要求1-6任一项所述的移位寄存器，其中，所述输出下拉电路包括第一输出下拉晶体管和第二输出下拉晶体管；
    所述第一输出下拉晶体管的第一极与所述第一输出晶体管的第二极连接，所述第一输出下拉晶体管的控制极与下拉节点连接，所述第一输出下拉 晶体管的第二极与第一电压端连接；
    所述第二输出下拉晶体管的第一极与所述输出端连接，所述第二输出下拉晶体管的控制极与所述下拉节点连接，所述第二输出下拉晶体管的第二极与所述第一电压端连接。
  8. 根据权利要求7所述的移位寄存器，其中，在所述第二输出下拉晶体管导通时，满足所述第二输出条件。
  9. 根据权利要求1-7任一项所述的移位寄存器，还包括复位电路，所述复位电路与所述上拉节点、复位信号端及第三电压端连接，
    其中，所述复位电路被配置为在满足复位条件时，接收来自所述第三电压端的第三电压信号，以对所述输出电路进行复位。
  10. 如权利要求9所述的移位寄存器，其中，所述复位电路包括复位晶体管；
    所述复位晶体管的控制极与所述复位信号端连接，所述复位晶体管的第一极与所述上拉节点连接，所述复位晶体管的第二极与所述第三电压端连接。
  11. 根据权利要求1-10任一项所述的移位寄存器，还包括下拉保持电路，所述下拉保持电路被配置为在所述上拉节点的下拉条件被满足时，下拉所述上拉节点的电位。
  12. 根据权利要求11所述的移位寄存器，其中，所述下拉保持电路包括下拉保持晶体管；
    所述下拉保持晶体管的控制极与下拉节点连接，所述下拉保持晶体管的第一极与所述上拉节点连接，所述下拉保持电路的第二极与所述第一电压端连接。
  13. 一种栅极驱动电路，包括级联的多个移位寄存器，其中，每个移位寄存器为如权利要求1-11任一项所述的移位寄存器，其中，除第一级和最后一级移位寄存器之外，本级移位寄存器的输入信号端与上一级移位寄存器的输出端连接；本级移位寄存器的复位信号端与下一级移位寄存器的输出端连接。
  14. 一种显示面板，包括如权利要求13所述的栅极驱动电路。
  15. 一种如权利要求1-12任一项所述的移位寄存器的驱动方法，包括：
    在输入阶段，设置复位信号端输入的复位信号为无效信号，设置所述时 钟信号端输入的时钟信号为无效信号，设置输入信号端输入的输入信号为有效信号，以将上拉节点的电位拉高；
    在输出阶段，设置所述输入信号为无效信号，设置所述复位信号为无效信号，设置所述时钟信号为有效信号，以从输出端输出扫描信号，其中，所述扫描信号为直流信号或者时钟信号之一；
    在复位阶段，设置所述输入信号为无效信号，设置所述时钟信号为无效信号，设置所述复位信号为有效信号，以将所述上拉节点的电位和所述输出端的电位拉低，下拉节点的电位拉高；
    在保持阶段，设置所述输入信号为无效信号，设置所述时钟信号为无效信号，设置所述复位信号为无效信号，以保持被拉高的所述下拉节点的电位和被拉低的所述上拉节点的电位和所述输出端的电位。
  16. 如权利要求15所述的移位寄存器驱动方法，其中，所述有效信号为高电压信号，所述无效信号为低电压信号。
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