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WO2019205663A1 - 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2019205663A1
WO2019205663A1 PCT/CN2018/121116 CN2018121116W WO2019205663A1 WO 2019205663 A1 WO2019205663 A1 WO 2019205663A1 CN 2018121116 W CN2018121116 W CN 2018121116W WO 2019205663 A1 WO2019205663 A1 WO 2019205663A1
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WIPO (PCT)
Prior art keywords
circuit
node
control
clock signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/121116
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English (en)
French (fr)
Inventor
陶健
王栋
李红敏
王书锋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/475,777 priority Critical patent/US11217148B2/en
Publication of WO2019205663A1 publication Critical patent/WO2019205663A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • the display device When displaying the image, the display device needs to scan the pixel array by using a gate driver circuit (English: Gate Driver on Array; GOA), and the gate driving circuit (also called a shift register) includes a plurality of cascaded shifts.
  • the register unit, each shift register unit corresponds to a row of pixel units in the pixel array, and the progressive scan driving of each row of pixel units in the pixel array of the display device is implemented by the plurality of shift register units to display an image.
  • each shift register unit includes a large number of components, resulting in a large layout area occupied by the gate driving circuit in the display device.
  • At least one embodiment of the present disclosure provides a shift register unit, the shift register unit comprising:
  • Input sub-circuits respectively connected to the input signal end, the first clock signal end and the first node, wherein the input sub-circuit is used to control the first clock signal from the first clock signal end to the first
  • the node inputs an input signal from the input signal terminal
  • control sub-circuit which is respectively connected to the first clock signal end, the first node, the power supply end, and the second node, where the control sub-circuit is used to control the first clock signal to the first a second node inputs the first clock signal, and, under the control of the first node, inputs a power signal from the power terminal to the second node;
  • the input sub-circuit includes: a first transistor
  • a gate of the first transistor is connected to the first clock signal end, a first pole of the first transistor is connected to the input signal end, and a second pole of the first transistor is connected to the first node connection.
  • the output subcircuit includes: a second transistor
  • a gate of the second transistor is connected to the first node, a first pole of the second transistor is connected to the second clock signal end, and a second pole of the second transistor is connected to the output end .
  • the output sub-circuit further includes: a first capacitor;
  • One end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the output end.
  • control sub-circuit includes: a first control sub-circuit and a second control sub-circuit;
  • the first control sub-circuit is respectively connected to the first node, the second node, and the power terminal, and the first control sub-circuit is configured to, under the control of the first node, to the Two nodes input the power signal;
  • the second control sub-circuit is respectively connected to the first clock signal end and the second node, and the second control sub-circuit is configured to be sent to the second node under the control of the first clock signal The first clock signal is input.
  • the first control sub-circuit includes: a third transistor
  • a gate of the third transistor is connected to the first node, a first pole of the third transistor is connected to the power terminal, and a second pole of the third transistor is connected to the second node;
  • the second control subcircuit includes: a fourth transistor
  • the gate and the first pole of the fourth transistor are both connected to the first clock signal end, and the second pole of the fourth transistor is connected to the second node.
  • control sub-circuit further includes: a second capacitor
  • One end of the second capacitor is connected to the second node, and the other end of the second capacitor is connected to the power terminal.
  • the holding subcircuit includes: a fifth transistor
  • the gate of the fifth transistor is connected to the second node, the first pole of the fifth transistor is connected to the power terminal, and the second pole of the fifth transistor is connected to the output terminal.
  • At least one embodiment of the present disclosure provides a driving method of a shift register unit for driving any of the above shift register units, the method comprising:
  • a first clock signal at an effective potential is input to the first clock signal terminal, and an input signal at an effective potential is input to the input signal terminal to cause the input sub-circuit to be controlled at the first clock signal Inputting an input signal at an effective potential to the first node;
  • a second clock signal at an effective potential is input to the second clock signal terminal such that the output sub-circuit inputs an effective potential to the output terminal under the control of the first node at an active potential Second clock signal;
  • the second clock signal at an inactive potential is input to the second clock terminal such that the output sub-circuit is input to the output terminal under the control of the first node at an active potential a second clock signal of an inactive potential;
  • the first clock signal at the effective potential is input to the first clock terminal
  • the input signal at the inactive potential is input to the input signal terminal
  • the power supply signal at the inactive potential is input to the power supply terminal
  • the input sub-circuit inputs an input signal at an invalid potential to the first node under the control of the first clock signal
  • the control sub-circuit is controlled to the second under the control of the first clock signal
  • the node inputs a first clock signal at an active potential
  • the holding sub-circuit inputs a power supply signal at an inactive potential to the output terminal under the control of the second node.
  • control sub-circuit includes a first control sub-circuit and a second control sub-circuit
  • the method further includes:
  • the first control sub-circuit inputs a power supply signal at an inactive potential to the second node under control of a first node at an active potential
  • the second control sub-circuit A first clock signal at an active potential is input to the second node under control of a first clock signal at an active potential to control the potential of the second node to be an inactive potential.
  • control subcircuit includes a first control subcircuit and a second control subcircuit
  • the method further includes: in the output phase and the reset phase, the first controller The circuit inputs a power supply signal at an inactive potential to the second node under control of the first node at an active potential.
  • the method further includes: in the maintaining phase, the second control sub-circuit is at an effective potential
  • the first clock signal at an effective potential is input to the second node under control of the first clock signal.
  • At least one embodiment of the present disclosure provides a gate drive circuit including: a plurality of cascaded any of the above shift register units.
  • an output end of the jth shift register unit is connected to an input signal end of the j+1th shift register unit, and the j is a positive integer.
  • At least one embodiment of the present disclosure provides a display device including the above-described gate driving circuit.
  • At least one embodiment of the present disclosure provides a nonvolatile storage medium having a computer program stored therein, the computer program being implemented by a processor to implement the above-described control method of the shift register unit.
  • FIG. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure
  • FIG. 6 is a timing diagram of a driving process of a shift register unit according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics, and the transistors employed in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present disclosure, the source is referred to as a first pole, and the drain is referred to as a second pole. However, it should be understood that in other embodiments, the source may also be a second pole, and the drain may also be the first The embodiment of the present disclosure does not limit this.
  • the middle end of the transistor is the gate
  • the signal input end is the source
  • the signal output end is the drain.
  • the switching transistor employed in the embodiments of the present disclosure may include a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level, and the N-type switching transistor is turned off. Turns on when the gate is high and turns off when the gate is low.
  • the plurality of signals in the various embodiments of the present disclosure correspond to a high potential and a low potential
  • the effective potential of the signal is a potential that turns on the switching transistor, for example, for a P-type switching transistor, the low potential is an effective potential, for N Type switching transistor, high potential is the effective potential.
  • pulse-up means charging one node or one electrode of a transistor such that the level of the node or the electrode is absolute. The value is increased to achieve the operation of the corresponding transistor (eg, conduction); “pull-down” means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby achieving corresponding Operation of the transistor (eg cut-off).
  • pulse-up means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby implementing the corresponding transistor.
  • Operation eg, conduction
  • pulse-down means charging one node or one electrode of a transistor to increase the absolute value of the level of the node or the electrode to achieve operation of the corresponding transistor (eg, cutoff) .
  • the shift register unit in the related art usually includes a large number of components, resulting in a large layout area occupied by the gate driving circuit in the display device.
  • Input sub-circuits respectively connected to the input signal end, the first clock signal end and the first node, wherein the input sub-circuit is used to control the first clock signal from the first clock signal end to the first
  • the node inputs an input signal from the input signal terminal
  • control sub-circuit which is respectively connected to the first clock signal end, the first node, the power supply end, and the second node, where the control sub-circuit is used to control the first clock signal to the first a second node inputs the first clock signal, and, under the control of the first node, inputs a power signal from the power terminal to the second node;
  • the shift register unit may include: an input sub-circuit 10, an output sub-circuit 20, a pull-down control sub-circuit 30, and a pull-down sub-circuit. 40.
  • the input sub-circuit 10 is respectively connected to the input signal terminal IN, the first clock signal terminal CLK1 and the pull-up node Q, and the input sub-circuit 10 is configured to be up under the control of the first clock signal from the first clock signal terminal CLK1.
  • the pull node Q inputs an input signal from the input signal terminal IN.
  • the pull-up node Q is a specific example of the first node described above.
  • the input sub-circuit 10 when the potential of the first clock signal is an effective potential and the potential of the input signal is an effective potential, the input sub-circuit 10 is used to input an input signal at an effective potential to the pull-up node Q.
  • the input sub-circuit 10 is used to input an input signal at an inactive potential to the pull-up node Q.
  • the output sub-circuit 20 is respectively connected to the second clock signal terminal CLK2, the pull-up node Q and the output terminal OUT.
  • the output sub-circuit 20 is configured to input the second clock signal to the output terminal OUT under the control of the pull-up node Q.
  • the output sub-circuit 20 when the potential of the pull-up node Q is an effective potential and the potential of the second clock signal is an effective potential, the output sub-circuit 20 is configured to input a second clock signal at an effective potential to the output terminal OUT.
  • the output sub-circuit 20 is configured to input a second clock signal at an inactive potential to the output terminal OUT.
  • the pull-down control sub-circuit 30 is respectively connected to the first clock signal terminal CLK1, the pull-up node Q, the power supply terminal VGL and the pull-down node P, and the pull-down control sub-circuit 30 is configured to pull down the node P under the control of the first clock signal.
  • the first clock signal is input, and under the control of the pull-up node Q, a power supply signal from the power supply terminal VGL is input to the pull-down node P.
  • the pull-down sub-circuit 40 inputs a first clock signal to the pull-down node P
  • the pull-down sub-circuit 40 inputs a power signal to the pull-down node P
  • the pull-down node P remains at an inactive potential.
  • the potential of the power signal is an inactive potential.
  • the pull-down node P is a specific example of the above-described second node
  • the pull-down control sub-circuit 30 is a specific example of the above-described control sub-circuit.
  • the pull-down sub-circuit 40 is respectively connected to the power supply terminal VGL, the pull-down node P and the output terminal OUT, and the pull-down sub-circuit 40 is configured to input a power signal to the output terminal OUT under the control of the pull-down node P.
  • the pull-down sub-circuit 40 is a specific example of the above-described holding sub-circuit.
  • the shift register unit provided by the embodiment of the present disclosure includes an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit, and the circuit structure of the shift register unit is simple.
  • the input sub-circuit in the shift register unit is capable of charging and resetting the pull-up node according to the potential of the input signal, without additionally setting a circuit for resetting the pull-up node, and reducing the shift register unit compared to the related art
  • the number of components and the space occupied by the signal lines effectively reduce the layout area occupied by the gate driving circuit in the display device, which is advantageous for the implementation of the narrow bezel.
  • FIG. 2 is a schematic structural diagram of another shift register unit according to some embodiments of the present disclosure.
  • the pull-down control sub-circuit 30 includes a first control sub-circuit 301 and a second control sub-circuit 302.
  • the first control sub-circuit 301 is connected to the pull-up node Q, the pull-down node P and the power supply terminal VGL, respectively, and the first control sub-circuit 301 is configured to input a power signal to the pull-down node P under the control of the pull-up node Q.
  • the second control sub-circuit 302 is respectively connected to the first clock signal terminal CLK1 and the pull-down node P, and the second control sub-circuit 302 is configured to input the first clock signal to the pull-down node P under the control of the first clock signal.
  • FIG. 3 is a schematic structural diagram of still another shift register unit according to some embodiments of the present disclosure.
  • the first control sub-circuit 301 includes: a third transistor M3.
  • the gate of the third transistor M3 is connected to the pull-up node Q, the first pole of the third transistor M3 is connected to the power supply terminal VGL, and the second pole of the third transistor M3 is connected to the pull-down node P.
  • the second control sub-circuit 302 includes a fourth transistor M4.
  • the gate and the first pole of the fourth transistor M4 are both connected to the first clock signal terminal CLK1, and the second electrode of the fourth transistor M4 is connected to the pull-down node P.
  • the input sub-circuit 10 may include a first transistor M1.
  • the gate of the first transistor M1 is connected to the first clock signal terminal CLK1, the first electrode of the first transistor M1 is connected to the input signal terminal IN, and the second electrode of the first transistor M1 is connected to the pull-up node Q.
  • the input sub-circuit 10 is capable of charging and resetting the pull-up node Q in accordance with the potential of the input signal, reducing the number of components in the shift register unit and the space occupied by the signal lines.
  • the output sub-circuit 20 includes: a second transistor M2.
  • the gate of the second transistor M2 is connected to the pull-up node Q, the first pole of the second transistor M2 is connected to the second clock signal terminal CLK2, and the second pole of the second transistor M2 is connected to the output terminal OUT.
  • FIG. 4 is a schematic structural diagram of still another shift register unit according to some embodiments of the present disclosure.
  • the output sub-circuit 20 further includes: a first capacitor C1.
  • One end of the first capacitor C1 is connected to the pull-up node Q, and the other end of the first capacitor C1 is connected to the output terminal OUT.
  • the first capacitor C1 can further increase the voltage of the pull-up node Q to maintain the second transistor M2 in an on state, thereby ensuring a stable output of the output sub-circuit 20.
  • the pull-down control sub-circuit 30 further includes: a second capacitor C2.
  • One end of the second capacitor C2 is connected to the pull-down node P, and the other end of the second capacitor C2 is connected to the power supply terminal VGL.
  • the second capacitor C2 is used to stabilize the voltage of the pull-down node P.
  • the pull-down sub-circuit 40 includes a fifth transistor M5.
  • the gate of the fifth transistor M5 is connected to the pull-down node P, the first electrode of the fifth transistor M5 is connected to the power supply terminal VGL, and the second electrode of the fifth transistor M5 is connected to the output terminal OUT.
  • the shift register unit provided by the embodiment of the present disclosure includes an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit, and the circuit structure of the shift register unit is simple.
  • the input sub-circuit in the shift register unit is capable of charging and resetting the pull-up node according to the potential of the input signal, without additionally setting a circuit for resetting the pull-up node, and reducing the shift register unit compared to the related art
  • the number of components and the space occupied by the signal lines effectively reduce the layout area occupied by the gate driving circuit in the display device, which is advantageous for the implementation of the narrow bezel.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit for driving any of the above shift register units, the method comprising:
  • a first clock signal at an effective potential is input to the first clock signal terminal, and an input signal at an effective potential is input to the input signal terminal, so that the input sub-circuit is under the control of the first clock signal a node inputs an input signal at an active potential;
  • a second clock signal at an effective potential is input to the second clock signal terminal, so that the output sub-circuit inputs a second clock signal at an effective potential to the output terminal under the control of the first node at the effective potential.
  • a first clock signal at an effective potential is input to the first clock terminal, an input signal at an inactive potential is input to the input signal terminal, and a power supply signal at an inactive potential is input to the power supply terminal, so that the input sub-circuit is at the An input signal at an inactive potential is input to the first node under control of a clock signal; the control sub-circuit inputs a first clock signal at an effective potential to the second node under control of the first clock signal; and the holding sub-circuit is Under the control of the second node, a power signal at an inactive potential is input to the output terminal.
  • FIG. 5 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure, which may be used to drive a shift register unit as shown in any one of FIG. 1 to FIG. 4, the shift register unit includes The input sub-circuit 10, the output sub-circuit 20, the pull-down control sub-circuit 30, and the pull-down sub-circuit 40, as shown in FIG. 5, the method may include:
  • Step 501 In the charging phase, inputting a first clock signal at an effective potential to the first clock signal end, and inputting an input signal at an effective potential to the input signal end, so that the input sub-circuit is under the control of the first clock signal. Pull up the node to input the input signal at the active potential.
  • This charging phase is a specific example of the above-described potential control phase.
  • Step 502 In the output stage, inputting and outputting the second clock signal at the effective potential to the second clock signal end, so that the output sub-circuit inputs the effective potential to the output terminal under the control of the pull-up node at the effective potential Two clock signals.
  • This output stage is a specific example of the output stage described above.
  • step 503 in the reset phase, the second clock signal at the inactive potential is input to the second clock terminal, so that the output sub-circuit inputs the inactive potential to the output terminal under the control of the pull-up node whose potential is the effective potential.
  • This reset phase is a specific example of the reset phase described above.
  • Step 504 In the holding phase, inputting a first clock signal at an effective potential to the first clock terminal, inputting an input signal at an invalid potential to the input signal terminal, and inputting a power signal at an invalid potential to the power terminal to cause the input signal
  • the circuit inputs an input signal at an inactive potential to the pull-up node under control of the first clock signal; the pull-down control sub-circuit inputs a first clock signal at an effective potential to the pull-down node under control of the first clock signal;
  • the pull-down sub-circuit inputs a power supply signal at an inactive potential to the output terminal under the control of the pull-down node.
  • the pull-down control sub-circuit 30 includes: a first control sub-circuit 301 and a second control sub-circuit 302. Accordingly, the method further includes:
  • the first control sub-circuit 301 inputs a power supply signal at an inactive potential to the pull-down node P under the control of the pull-up node Q at an effective potential, and the second control sub-circuit 302 is at the effective potential Under the control of a clock signal, a first clock signal at an effective potential is input to the pull-down node P to control the potential of the pull-down node P to be an inactive potential.
  • the first control sub-circuit 301 inputs a power supply signal at an inactive potential to the pull-down node P under control of the pull-up node Q at an active potential, and the first control sub-circuit 302 is at a first clock at an inactive potential.
  • the signal is turned off under control (ie, no signal is output).
  • the first control sub-circuit 301 inputs a power supply signal at an inactive potential to the pull-down node P under the control of the pull-up node Q at an effective potential, and the first control sub-circuit 302 is at the first clock at the inactive potential The signal is turned off under control (ie, no signal is output).
  • the first control sub-circuit 301 is turned off under the control of the pull-up node Q whose potential is the inactive potential (ie, no signal is input), and the second control sub-circuit 302 is in control of the first clock signal at the active potential.
  • a first clock signal at an effective potential is input to the pull-down node P.
  • the output sub-circuit in the reset phase, inputs a second ineffective potential to the output terminal under the control of the pull-up node at the effective potential.
  • a clock signal the resetting of the output terminal is performed, so that the thin film transistor in the display area is kept in an off state
  • the input sub-circuit inputs an input signal at an inactive potential to the pull-up node under the control of the first clock signal;
  • the pull-down control sub-circuit inputs a first clock signal at an effective potential to the pull-down node under control of the first clock signal; and the pull-down sub-circuit inputs a power supply signal at an inactive potential to the output terminal under the control of the pull-down node, so that the output The potential of the terminal is kept at an inactive potential, thereby achieving continuous noise reduction at the output.
  • FIG. 6 is a timing diagram of a driving process of a shift register unit according to an embodiment of the present disclosure, in which the shift register unit shown in FIG. 4 and each transistor in the shift register unit are N-type transistors.
  • the driving principle of the shift register unit provided by the embodiment of the present disclosure is described in detail by taking the effective potential as a high potential with respect to the ineffective potential.
  • the potential of the first clock signal input from the first clock signal terminal CLK1 is an effective potential
  • the potential of the second clock signal input from the second clock signal terminal CLK2 is an inactive potential, from the input.
  • the potential of the input signal input by the signal terminal IN is an effective potential
  • the potential of the power signal input from the power supply terminal VGL is an inactive potential
  • the first transistor M1 is turned on under the control of the first clock signal, and the input signal terminal IN passes the first
  • the second transistor M2 is micro-conducted under the control of the pull-up node Q at the effective potential
  • the second clock signal terminal CLK2 inputs the second clock signal at the inactive potential to the output terminal OUT through the second transistor M2.
  • the third transistor M3 under the control of the pull-up node Q at the effective potential, the third transistor M3 is turned on, and the power terminal VGL inputs the power signal at the inactive potential to the pull-down node P through the third transistor M3, and is at the effective potential.
  • the fourth transistor M4 Under the control of the first clock signal, the fourth transistor M4 is turned on, and the first clock signal terminal CLK1 inputs a first clock signal at an effective potential to the pull-down node P through the fourth transistor M4, and at this time, the power signal In conjunction with the first clock signal, the potential of the pull-down node P remains at an inactive potential.
  • the fifth transistor M5 under the control of the potential of the pull-down node P at the ineffective potential, the fifth transistor M5 is turned off, and the voltage stability of the output terminal OUT can be ensured.
  • the potential of the pull-down node P is maintained as an inactive potential by the combination of the power signal and the first clock signal, and the channel width of the third transistor M3 is pre-designed.
  • the ratio is smaller than the channel width to length ratio of the fourth transistor M4.
  • the ratio of the channel width to length ratio of the third transistor M3 to the channel width to length ratio of the fourth transistor M4 may be 1:5 or the like.
  • the potential of the first clock signal input from the first clock signal terminal CLK1 is an inactive potential
  • the potential of the input signal input from the input signal terminal IN is an inactive potential
  • the second potential is input from the second clock signal terminal CLK2.
  • the potential of the clock signal is an effective potential
  • the potential of the power signal input from the power supply terminal VGL is an inactive potential
  • the potential of the pull-up node Q is an effective potential
  • the potential of the pull-down node P is an inactive potential
  • the second transistor M2 is micro-conducted, and the second clock signal terminal CLK2 inputs a second clock signal at an inactive potential to the output terminal OUT.
  • the third transistor M3 is turned on under the control of the pull-up node Q at the effective potential, and the power supply terminal VGL inputs a power supply signal at an inactive potential to the pull-down node P through the third transistor M3, so that The potential of the pull-down node P remains at an inactive potential.
  • the potential of the first clock signal input from the first clock signal terminal CLK1 is an inactive potential
  • the potential of the input signal input from the input signal terminal IN is an inactive potential
  • the second potential is input from the second clock signal terminal CLK2.
  • the potential of the clock signal is an inactive potential
  • the potential of the power signal input from the power supply terminal VGL is an inactive potential
  • the potential of the pull-up node Q is maintained at an effective potential
  • the second transistor M2 is kept turned on under the control of the pull-up node Q.
  • the second clock signal terminal CLK2 inputs a second clock signal at an inactive potential to the output terminal OUT through the second transistor M2 to implement resetting of the output terminal OUT, so that thin film transistors (TFTs) in the display region are both Keep it in the off state.
  • TFTs thin film transistors
  • the potential of the first clock signal input from the first clock signal terminal CLK1 is the effective potential
  • the potential of the input signal input from the input signal terminal IN is the inactive potential
  • the second input from the second clock signal terminal CLK2 The potential of the clock signal is an inactive potential
  • the potential of the power signal input from the power supply terminal VGL is an inactive potential
  • the first transistor M1 is turned on under the control of the first clock signal
  • the input signal terminal IN is pulled up through the first transistor M1.
  • Node Q inputs an input signal at an inactive potential to effect a reset of pull-up node Q.
  • the fourth transistor M4 is turned on under the control of the first clock signal, and the first clock signal terminal CLK1 inputs the first clock signal at the effective potential to the pull-down node P through the fourth transistor M4, and charges the second capacitor C2.
  • the potential of the pull-down node P is maintained at an effective potential
  • the fifth transistor M5 is turned on under the control of the pull-down node P at the effective potential
  • the power terminal VGL inputs the power source at the inactive potential to the output terminal OUT through the fifth transistor M5.
  • the signal is such that the potential of the output terminal OUT is maintained at an inactive potential, that is, continuous noise reduction of the output terminal OUT is achieved.
  • the specific level values of the signals outputted by the respective power terminals VGL and the signal terminals can be adjusted according to actual circuit requirements.
  • the level of the first power signal can be 8 volts (V)
  • the second power signal is
  • the level of the present invention may be -8V, which is not limited by the embodiment of the present disclosure.
  • the output sub-circuit in the reset phase, inputs a second ineffective potential to the output terminal under the control of the pull-up node at the effective potential.
  • a clock signal the resetting of the output terminal is performed, so that the thin film transistor in the display area is kept in an off state
  • the input sub-circuit inputs an input signal at an inactive potential to the pull-up node under the control of the first clock signal;
  • the pull-down control sub-circuit inputs a first clock signal at an effective potential to the pull-down node under control of the first clock signal; and the pull-down sub-circuit inputs a power supply signal at an inactive potential to the output terminal under the control of the pull-down node, so that the output The potential of the terminal is kept at an inactive potential, thereby achieving continuous noise reduction at the output.
  • An embodiment of the present disclosure provides a gate driving circuit, which may include a plurality of cascaded shift register units, and each shift register unit is shifted as shown in any of FIGS. 1 to 4. Bit register unit.
  • the output terminal OUT of the jth shift register unit is connected to the input signal terminal IN of the j+1th shift register unit, and j is a positive integer.
  • FIG. 7 is a partial structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the structure shown in FIG. 7 includes three cascaded shift register units, and the three cascaded shifts.
  • each shift register unit may be a shift register unit as shown in any of FIG. 1 to FIG. 4, as shown in FIG. 7, the gate drive circuit may be provided with a start signal terminal and three clock signals.
  • the terminal, the effective potential power signal terminal VG1 and the ineffective potential power terminal VG2, the power terminal VGL of each shift register unit is connected to the invalid potential power terminal VG2, and the power supply terminal VDD of each shift register unit is connected to the effective potential
  • the power signal terminal VG1, the effective potential power signal terminal VG1 is used to supply power to the shift register unit, the start signal terminal outputs the start signal STV, and the three clock signal terminals respectively output clock signals CK1, CK2 and CK3, the CK1, CK2 and CK3
  • the duty ratios are the same, and CK1, CK2, and CK3 sequentially output a clock signal at an effective potential.
  • the input signal terminal IN of the first stage shift register unit GOA1 The input signal is the start signal STV, the first clock signal input by the first clock signal terminal CLK1 of the first stage shift register unit GOA1 is the clock signal CK1, and the second clock signal terminal CLK2 of the first stage shift register unit GOA1
  • the input second clock signal is the clock signal CK2;
  • the input signal input to the input signal terminal IN of the second stage shift register unit GOA2 is the output signal of the first stage shift register unit GOA1, and the second stage shift register unit GOA2
  • the first clock signal input by the first clock signal terminal CLK1 is the clock signal CK2
  • the second clock signal input by the second clock signal terminal CLK2 of the second stage shift register unit GOA2 is the clock signal CK3;
  • the third stage shift register unit The input signal input to the input signal terminal IN of the GOA3 is the output signal of the second stage shift register unit GOA2, and the first clock signal input by the first clock signal terminal CLK1 of the third stage shift register unit GOA
  • the gate driving circuit includes a plurality of cascaded shift register units, each of which includes an input sub-circuit, an output sub-circuit, a pull-down control sub-circuit, and a pull-down sub-circuit.
  • the circuit structure of the shift register unit is relatively simple, and the input sub-circuit in the shift register unit can charge and reset the pull-up node according to the potential of the input signal, without additionally setting a circuit for resetting the pull-up node, Compared with the related art, the number of components in the shift register unit and the space occupied by the signal lines are reduced, thereby effectively reducing the layout area occupied by the gate driving circuit in the display device, which is advantageous for the implementation of the narrow bezel.
  • An embodiment of the present disclosure provides a display device, which may include a gate driving circuit provided by an embodiment of the present disclosure.
  • the display device can be: liquid crystal panel, electronic paper, organic light emitting diode (English: Organic Light-Emitting Diode, OLED) panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. A product or part that has a display function.
  • the embodiment of the present disclosure further provides a non-volatile storage medium, in which a computer program is stored, and when the computer program is executed by the processor, the driving method of the shift register unit provided by the embodiment of the present disclosure is implemented.

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Abstract

一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。移位寄存器单元包括：输入子电路(10)、输出子电路(20)、下拉控制子电路(30)和下拉子电路(40)；输入子电路(10)用于在来自第一时钟信号端(CLK1)的第一时钟信号的控制下，向上拉节点(Q)输入来自输入信号端(IN)的输入信号；输出子电路(20)用于在上拉节点(Q)的控制下，向输出端(OUT)输入来自第二时钟信号端(CLK2)的第二时钟信号；下拉控制子电路(30)用于在第一时钟信号(CLK1)的控制下，向下拉节点(P)输入第一时钟信号(CLK1)，以及在上拉节点(Q)的控制下，向下拉节点(P)输入来自电源端(VGL)的电源信号；下拉子电路(40)用于在下拉节点(P)的控制下，向输出端(OUT)输入电源信号。移位寄存器单元减少了栅极驱动电路在显示装置中所占用的版图面积，有利于窄边框的实现。

Description

移位寄存器单元、驱动方法、栅极驱动电路及显示装置
相关申请的交叉引用
本申请要求于2018年4月25日递交的第201810380946.3号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器单元、驱动方法、栅极驱动电路及显示装置。
背景技术
显示装置在显示图像时，需要利用栅极驱动电路(英文：Gate Driver on Array；简称：GOA)对像素阵列进行扫描，栅极驱动电路(也称移位寄存器)包括多个级联的移位寄存器单元，每个移位寄存器单元对应像素阵列中的一行像素单元，由多个移位寄存器单元实现对显示装置像素阵列中各行像素单元的逐行扫描驱动，以显示图像。
但随着显示装置中像素单元数目的提高，栅极驱动电路在一帧时间内所需扫描的行数增加，以及对超窄边框显示装置的需求，这就要求移位寄存器单元的版图面积要更小。相关技术中有一种移位寄存器单元，它通常通过多个晶体管和电容器来控制电路输出信号的电位的高低。
但是，相关技术中每个移位寄存器单元所包括的元件较多，导致栅极驱动电路在显示装置中所占用的版图面积较大。
发明内容
本公开的至少一个实施例提供了一种移位寄存器单元，所述移位寄存器单元包括：
输入子电路，分别与输入信号端、第一时钟信号端和第一节点连接，所述输入子电路用于在来自所述第一时钟信号端的第一时钟信号的控制下，向 所述第一节点输入来自所述输入信号端的输入信号；
输出子电路，分别与第二时钟信号端、所述第一节点和输出端连接，所述输出子电路用于在所述第一节点的控制下，向所述输出端输入来自所述第二时钟信号端的第二时钟信号；
控制子电路，分别与所述第一时钟信号端、所述第一节点、电源端和第二节点连接，所述控制子电路用于在所述第一时钟信号的控制下，向所述第二节点输入所述第一时钟信号，以及在所述第一节点的控制下，向所述第二节点输入来自所述电源端的电源信号；以及
保持子电路，分别与所述电源端、所述第二节点和所述输出端连接，所述保持子电路用于在所述第二节点的控制下，向所述输出端输入所述电源信号。
可选地，所述输入子电路包括：第一晶体管；
所述第一晶体管的栅极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述输入信号端连接，所述第一晶体管的第二极与所述第一节点连接。
可选地，所述输出子电路包括：第二晶体管；
所述第二晶体管的栅极与所述第一节点连接，所述第二晶体管的第一极与所述第二时钟信号端连接，所述第二晶体管的第二极与所述输出端连接。
可选地，所述输出子电路还包括：第一电容器；
所述第一电容器的一端与所述第一节点连接，所述第一电容器的另一端与所述输出端连接。
可选地，所述控制子电路包括：第一控制子电路和第二控制子电路；
所述第一控制子电路分别与所述第一节点、所述第二节点和所述电源端连接，所述第一控制子电路用于在所述第一节点的控制下，向所述第二节点输入所述电源信号；
所述第二控制子电路分别与所述第一时钟信号端和所述第二节点连接，所述第二控制子电路用于在所述第一时钟信号的控制下，向所述第二节点输入所述第一时钟信号。
可选地，所述第一控制子电路包括：第三晶体管；
所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极 与所述电源端连接，所述第三晶体管的第二极与所述第二节点连接；
所述第二控制子电路包括：第四晶体管；
所述第四晶体管的栅极和第一极均与所述第一时钟信号端连接，所述第四晶体管的第二极与所述第二节点连接。
可选地，所述控制子电路还包括：第二电容器；
所述第二电容器的一端与所述第二节点连接，所述第二电容器的另一端与所述电源端连接。
可选地，所述保持子电路包括：第五晶体管；
所述第五晶体管的栅极与所述第二节点连接，所述第五晶体管的第一极与所述电源端连接，所述第五晶体管的第二极与所述输出端连接。
本公开的至少一个实施例提供了一种移位寄存器单元的驱动方法，所述方法用于驱动任一上述的移位寄存器单元，所述方法包括：
在电位控制阶段中，向第一时钟信号端输入处于有效电位的第一时钟信号，向输入信号端输入处于有效电位的输入信号，以使得所述输入子电路在所述第一时钟信号的控制下，向第一节点输入处于有效电位的输入信号；
在输出阶段中，向第二时钟信号端输入处于有效电位的第二时钟信号，以使得所述输出子电路在处于有效电位的所述第一节点的控制下，向输出端输入处于有效电位的第二时钟信号；
在复位阶段中，向第二时钟端输入处于无效电位的所述第二时钟信号，以使得所述输出子电路在处于有效电位的所述第一节点的控制下，向所述输出端输入处于无效电位的第二时钟信号；
在保持阶段中，向第一时钟端输入处于有效电位的所述第一时钟信号，向输入信号端输入处于无效电位的所述输入信号，向电源端输入处于无效电位的电源信号，以使得所述输入子电路在所述第一时钟信号的控制下，向所述第一节点输入处于无效电位的输入信号；所述控制子电路在所述第一时钟信号的控制下，向所述第二节点输入处于有效电位的第一时钟信号；以及所述保持子电路在所述第二节点的控制下，向所述输出端输入处于无效电位的电源信号。
可选地，在所述控制子电路包括第一控制子电路和第二控制子电路的情况下，所述方法还包括：
在所述电位控制阶段中，所述第一控制子电路在处于有效电位的第一节点的控制下，向所述第二节点输入处于无效电位的电源信号，以及，所述第二控制子电路在处于有效电位的第一时钟信号的控制下，向所述第二节点输入处于有效电位的第一时钟信号，以控制所述第二节点的电位为无效电位。
可选地，在所述控制子电路包括第一控制子电路和第二控制子电路的情况下，所述方法还包括：在所述输出阶段和所述复位阶段中，所述第一控制子电路在处于有效电位的所述第一节点的控制下向所述第二节点输入处于无效电位的电源信号。
可选地，在所述控制子电路包括第一控制子电路和第二控制子电路的情况下，该方法还包括：在所述保持阶段中，所述第二控制子电路在处于有效电位的所述第一时钟信号的控制下，向所述第二节点输入处于有效电位的所述第一时钟信号。
本公开的至少一个实施例提供了一种栅极驱动电路，所述栅极驱动电路包括：多个级联的任一上述的移位寄存器单元。
可选地，所述多个级联的移位寄存器单元中，第j个移位寄存器单元的输出端与第j+1个移位寄存器单元的输入信号端连接，所述j为正整数。
本公开的至少一个实施例提供了一种显示装置，所述显示装置包括上述的栅极驱动电路。
本公开的至少一个实施例提供了一种非易失性存储介质，所述存储介质内存储有计算机程序，所述计算机程序被处理器执行时实现上述的移位寄存器单元的控制方法。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图；
图2是本公开实施例提供的另一种移位寄存器单元的结构示意图；
图3是本公开实施例提供的又一种移位寄存器单元的结构示意图；
图4是本公开实施例提供的再一种移位寄存器单元的结构示意图；
图5是本公开实施例提供的一种移位寄存器单元的驱动方法的流程图；
图6是本公开实施例提供的一种移位寄存器单元的驱动过程的时序图；
图7是本公开实施例提供的一种栅极驱动电路的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一极，漏极称为第二极，然而应理解在其他实施例中，源极还可以是第二极，漏极还可以是第一极，本公开的实施例对此不作限制。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有高电位和低电位，信号的有效电位为使开关晶体管导通的电位，例如：对于P型开关晶体管，低电位为有效电位，对于N型开关晶体管，高电位为有效电位。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对 值升高，从而实现相应晶体管的操作(例如截止)。
并且，术语“上拉”、“下拉”的具体含义也将根据所采用的晶体管的具体类型而相应调整，只要能实现对于晶体管的控制以实现相应的开关功能。如上所述，相关技术中的移位寄存器单元通常包括的元件较多，导致栅极驱动电路在显示装置中所占用的版图面积较大。
本公开的至少一个实施例提供了一种移位寄存器单元，其包括：
输入子电路，分别与输入信号端、第一时钟信号端和第一节点连接，所述输入子电路用于在来自所述第一时钟信号端的第一时钟信号的控制下，向所述第一节点输入来自所述输入信号端的输入信号；
输出子电路，分别与第二时钟信号端、所述第一节点和输出端连接，所述输出子电路用于在所述第一节点的控制下，向所述输出端输入来自所述第二时钟信号端的第二时钟信号；
控制子电路，分别与所述第一时钟信号端、所述第一节点、电源端和第二节点连接，所述控制子电路用于在所述第一时钟信号的控制下，向所述第二节点输入所述第一时钟信号，以及在所述第一节点的控制下，向所述第二节点输入来自所述电源端的电源信号；以及
保持子电路，分别与所述电源端、所述第二节点和所述输出端连接，所述保持子电路用于在所述第二节点的控制下，向所述输出端输入所述电源信号。
图1是本公开实施例提供的一种移位寄存器单元的结构示意图，参考图1，该移位寄存器单元可以包括：输入子电路10、输出子电路20、下拉控制子电路30和下拉子电路40。
该输入子电路10分别与输入信号端IN、第一时钟信号端CLK1和上拉节点Q连接，该输入子电路10用于在来自第一时钟信号端CLK1的第一时钟信号的控制下，向上拉节点Q输入来自输入信号端IN的输入信号。上拉节点Q为上述的第一节点的具体示例。
例如：当第一时钟信号的电位为有效电位，且输入信号的电位为有效电位时，该输入子电路10用于向上拉节点Q输入处于有效电位的输入信号。当第一时钟信号的电位为有效电位，且输入信号的电位为无效电位时，该输入子电路10用于向上拉节点Q输入处于无效电位的输入信号。
该输出子电路20分别与第二时钟信号端CLK2、上拉节点Q和输出端OUT连接，该输出子电路20用于在上拉节点Q的控制下，向输出端OUT输入来自第二时钟信号端CLK2的第二时钟信号。
例如：当上拉节点Q的电位为有效电位，且第二时钟信号的电位为有效电位时，该输出子电路20用于向输出端OUT输入处于有效电位的第二时钟信号。当上拉节点Q的电位为有效电位，且第二时钟信号的电位为无效电位时，该输出子电路20用于向输出端OUT输入处于无效电位的第二时钟信号。
该下拉控制子电路30分别与第一时钟信号端CLK1、上拉节点Q、电源端VGL和下拉节点P连接，该下拉控制子电路30用于在第一时钟信号的控制下，向下拉节点P输入第一时钟信号，以及，在上拉节点Q的控制下，向下拉节点P输入来自电源端VGL的电源信号。并且，当该下拉子电路40向下拉节点P输入第一时钟信号，且该下拉子电路40向下拉节点P输入电源信号时，该下拉节点P保持为无效电位。其中，电源信号的电位为无效电位。下拉节点P为上述的第二节点的具体示例，以及下拉控制子电路30为上述的控制子电路的具体示例。
该下拉子电路40分别与电源端VGL、下拉节点P和输出端OUT连接，该下拉子电路40用于在下拉节点P的控制下，向输出端OUT输入电源信号。下拉子电路40为上述的保持子电路的具体示例。
应理解在本公开中使用某些术语是为了说明，不应被解释为限制。例如，在本公开实施例提供的移位寄存器单元通过不同类型的晶体管实现时，上述的“上拉节点”、“下拉节点”、“下拉控制子电路”和“下拉子电路”等也可被称为“下拉节点”、“上拉节点”、“上拉控制子电路”和“上拉子电路”等。
综上所述，本公开实施例提供的移位寄存器单元，该移位寄存器单元中包括输入子电路、输出子电路、下拉控制子电路和下拉子电路，该移位寄存器单元的电路结构简单，且该移位寄存器单元中的输入子电路能够根据输入信号的电位对上拉节点进行充电和复位，无需额外设置对上拉节点进行复位的电路，相较于相关技术，减少了移位寄存器单元中的元件数和信号线占用的空间，进而有效减少了栅极驱动电路在显示装置中所占用的版图面积，有利于窄边框的实现。
图2是本公开一些实施例提供的另一种移位寄存器单元的结构示意图。 请参考图2，在本公开的一些实施例中，下拉控制子电路30包括：第一控制子电路301和第二控制子电路302。
第一控制子电路301分别与上拉节点Q、下拉节点P和电源端VGL连接，第一控制子电路301用于在上拉节点Q的控制下，向下拉节点P输入电源信号。
第二控制子电路302分别与第一时钟信号端CLK1和下拉节点P连接，第二控制子电路302用于在第一时钟信号的控制下，向下拉节点P输入第一时钟信号。
图3是本公开一些实施例提供的又一种移位寄存器单元的结构示意图。可选地，请参考图3，在本公开的一些实施例中，第一控制子电路301包括：第三晶体管M3。
第三晶体管M3的栅极与上拉节点Q连接，第三晶体管M3的第一极与电源端VGL连接，第三晶体管M3的第二极与下拉节点P连接。
请继续参考图3，在本公开的一些实施例中，第二控制子电路302包括：第四晶体管M4。
第四晶体管M4的栅极和第一极均与第一时钟信号端CLK1连接，第四晶体管M4的第二极与下拉节点P连接。
请参考图3，在本公开的一些实施例中，该输入子电路10可以包括：第一晶体管M1。第一晶体管M1的栅极与第一时钟信号端CLK1连接，第一晶体管M1的第一极与输入信号端IN连接，第一晶体管M1的第二极与上拉节点Q连接。该输入子电路10能够根据输入信号的电位对上拉节点Q进行充电和复位，减少了移位寄存器单元中的元件数和信号线占用的空间。
可选地，请继续参考图3，在本公开的一些实施例中，该输出子电路20包括：第二晶体管M2。第二晶体管M2的栅极与上拉节点Q连接，第二晶体管M2的第一极与第二时钟信号端CLK2连接，第二晶体管M2的第二极与输出端OUT连接。
图4是本公开一些实施例提供的再一种移位寄存器单元的结构示意图。请参考图4，在本公开的一些实施例中，该输出子电路20还包括：第一电容器C1。第一电容器C1的一端与上拉节点Q连接，第一电容器C1的另一端与输出端OUT连接。第一电容器C1能够进一步提高上拉节点Q的电压，使 第二晶体管M2保持导通状态，从而保证该输出子电路20的稳定输出。
可选地，请继续参考图4，在本公开的一些实施例中，该下拉控制子电路30还包括：第二电容器C2。第二电容器C2的一端与下拉节点P连接，第二电容器C2的另一端与电源端VGL连接。第二电容器C2用于稳定下拉节点P的电压。
请继续参考图3和图4，在本公开的一些实施例中，该下拉子电路40包括：第五晶体管M5。
第五晶体管M5的栅极与下拉节点P连接，第五晶体管M5的第一极与电源端VGL连接，第五晶体管M5的第二极与输出端OUT连接。
综上所述，本公开实施例提供的移位寄存器单元，该移位寄存器单元中包括输入子电路、输出子电路、下拉控制子电路和下拉子电路，该移位寄存器单元的电路结构简单，且该移位寄存器单元中的输入子电路能够根据输入信号的电位对上拉节点进行充电和复位，无需额外设置对上拉节点进行复位的电路，相较于相关技术，减少了移位寄存器单元中的元件数和信号线占用的空间，进而有效减少了栅极驱动电路在显示装置中所占用的版图面积，有利于窄边框的实现。
本公开的至少一个实施例还提供了一种移位寄存器单元的驱动方法，其用于驱动任一上述的移位寄存器单元，该方法包括：
在电位控制阶段中，向第一时钟信号端输入处于有效电位的第一时钟信号，向输入信号端输入处于有效电位的输入信号，以使得输入子电路在第一时钟信号的控制下，向第一节点输入处于有效电位的输入信号；
在输出阶段中，向第二时钟信号端输入处于有效电位的第二时钟信号，以使得输出子电路在处于有效电位的第一节点的控制下，向输出端输入处于有效电位的第二时钟信号；
在复位阶段中，向第二时钟端输入处于无效电位的第二时钟信号，以使得输出子电路在处于有效电位的第一节点的控制下，向输出端输入处于无效电位的第二时钟信号；
在保持阶段中，向第一时钟端输入处于有效电位的第一时钟信号，向输入信号端输入处于无效电位的输入信号，向电源端输入处于无效电位的电源信号，以使得输入子电路在第一时钟信号的控制下，向第一节点输入处于无 效电位的输入信号；控制子电路在第一时钟信号的控制下，向第二节点输入处于有效电位的第一时钟信号；以及保持子电路在第二节点的控制下，向输出端输入处于无效电位的电源信号。
图5是本公开实施例提供的一种移位寄存器单元的驱动方法的流程图，该方法可以用于驱动如图1至图4任一所示的移位寄存器单元，该移位寄存器单元包括：该输入子电路10、该输出子电路20、该下拉控制子电路30和该下拉子电路40，如图5所示，该方法可以包括：
步骤501、充电阶段中，向第一时钟信号端输入处于有效电位的第一时钟信号，向输入信号端输入处于有效电位的输入信号，以使得该输入子电路在第一时钟信号的控制下，向上拉节点输入处于有效电位的输入信号。该充电阶段为上述的电位控制阶段的具体示例。
步骤502、输出阶段中，向第二时钟信号端输入输出处于有效电位第二时钟信号，以使得该输出子电路在处于有效电位的上拉节点的控制下，向输出端输入处于有效电位的第二时钟信号。该输出阶段为上述的输出阶段的具体示例。
步骤503、复位阶段中，向第二时钟端输入处于无效电位的第二时钟信号，以使得该输出子电路在电位为有效电位的上拉节点的控制下，向输出端输入处于无效电位的第二时钟信号。该复位阶段为上述的复位阶段的具体示例。
步骤504、保持阶段中，向第一时钟端输入处于有效电位的第一时钟信号，向输入信号端输入处于无效电位的输入信号，向电源端输入处于无效电位的电源信号，以使得该输入子电路在第一时钟信号的控制下，向上拉节点输入处于无效电位的输入信号；该下拉控制子电路在第一时钟信号的控制下，向下拉节点输入处于有效电位的第一时钟信号；以及该下拉子电路在下拉节点的控制下，向输出端输入处于无效电位的电源信号。该保持阶段为上述的保持阶段的具体示例。
进一步地，该下拉控制子电路30包括：第一控制子电路301和第二控制子电路302，相应地，方法还包括：
在充电阶段中，第一控制子电路301在处于有效电位的上拉节点Q的控制下，向下拉节点P输入处于无效电位的电源信号，以及，第二控制子电路 302在处于有效电位的第一时钟信号的控制下，向下拉节点P输入处于有效电位的第一时钟信号，以控制下拉节点P的电位为无效电位。
在输出阶段中，第一控制子电路301在处于有效电位的上拉节点Q的控制下向下拉节点P输入处于无效电位的电源信号，以及第二控制子电路302在处于无效电位的第一时钟信号的控制下截止(即不输出信号)。
在复位阶段中，第一控制子电路301在处于有效电位的上拉节点Q的控制下向下拉节点P输入处于无效电位的电源信号，以及第二控制子电路302在处于无效电位的第一时钟信号的控制下截止(即不输出信号)。
在保持阶段中，第一控制子电路301在电位为无效电位的上拉节点Q的控制下截止(即不输入信号)，以及第二控制子电路302在处于有效电位的第一时钟信号的控制下，向下拉节点P输入处于有效电位的第一时钟信号。
综上所述，本公开实施例提供的移位寄存器单元的的驱动方法，在复位阶段中，输出子电路在处于有效电位的上拉节点的控制下，向输出端输入处于无效电位的第二时钟信号，实现对输出端的复位，使得显示区域中的薄膜晶体管保持为截止状态，以及在保持阶段中，输入子电路在第一时钟信号的控制下，向上拉节点输入处于无效电位的输入信号；下拉控制子电路在第一时钟信号的控制下，向下拉节点输入处于有效电位的第一时钟信号；以及下拉子电路在下拉节点的控制下，向输出端输入处于无效电位的电源信号，使输出端的电位保持为无效电位，从而实现对输出端的持续降噪。
示例地，图6是本公开实施例提供的一种移位寄存器单元的驱动过程的时序图，以图4所示的移位寄存器单元，以及移位寄存器单元中的各晶体管为N型晶体管，有效电位相对于无效电位为高电位为例，详细介绍本公开实施例提供的移位寄存器单元的驱动原理。
请参考图6，充电阶段t1中，从第一时钟信号端CLK1输入的第一时钟信号的电位为有效电位，从第二时钟信号端CLK2输入的第二时钟信号的电位为无效电位，从输入信号端IN输入的输入信号的电位为有效电位，从电源端VGL输入的电源信号的电位为无效电位，第一晶体管M1在该第一时钟信号的控制下导通，输入信号端IN通过该第一晶体管M1向上拉节点Q输入处于有效电位的输入信号，为该上拉节点Q充电，使上拉节点Q的电位保持为有效电位。相应的，第二晶体管M2在该处于有效电位的上拉节点Q的 控制下微导通，第二时钟信号端CLK2通过该第二晶体管M2向输出端OUT输入处于无效电位的第二时钟信号。
并且，在该处于有效电位的上拉节点Q的控制下，第三晶体管M3导通，电源端VGL通过该第三晶体管M3向下拉节点P输入处于无效电位的电源信号，同时，在处于有效电位的第一时钟信号的控制下，第四晶体管M4导通，第一时钟信号端CLK1通过该第四晶体管M4向该下拉节点P输入处于有效电位的第一时钟信号，此时，在该电源信号和该第一时钟信号的共同作用下，该下拉节点P的电位保持为无效电位。进一步地，在该处于无效电位的下拉节点P的电位的控制下，第五晶体管M5截止，能够保证输出端OUT的电压稳定性。
在一种可实现方式中，在电源信号和第一时钟信号的共同作用下，使下拉节点P的电位保持为无效电位的可实现方式可以为：预先设计该第三晶体管M3的沟道宽长比小于该第四晶体管M4的沟道宽长比，例如：该第三晶体管M3的沟道宽长比与该第四晶体管M4的沟道宽长比的比值可以为1:5等。
输出阶段t2中，从第一时钟信号端CLK1输入的第一时钟信号的电位为无效电位，从输入信号端IN输入的输入信号的电位为无效电位，从第二时钟信号端CLK2输入的第二时钟信号的电位为有效电位，从电源端VGL输入的电源信号的电位为无效电位，上拉节点Q的电位为有效电位，下拉节点P的电位为无效电位，并且，由于在充电阶段t1中，第二晶体管M2微导通，第二时钟信号端CLK2向输出端OUT输入处于无效电位的第二时钟信号，当第二时钟信号在输出阶段t2跳变至高电平后，由于第一电容器C1的耦合效应，上拉节点Q的电位会随着第二晶体管M2的第二极电位的升高而进一步升高，此时，第二晶体管M2完全导通，第二时钟信号端CLK2通过该第二晶体管M2向输出端OUT输入处于有效电位的第二时钟信号，以驱动显示面板中的像素单元。
同时，在该输出阶段t2中，第三晶体管M3在处于有效电位的上拉节点Q的控制下导通，电源端VGL通过该第三晶体管M3向下拉节点P输入处于无效电位的电源信号，使该下拉节点P的电位保持为无效电位。
复位阶段t3中，从第一时钟信号端CLK1输入的第一时钟信号的电位为 无效电位，从输入信号端IN输入的输入信号的电位为无效电位，从第二时钟信号端CLK2输入的第二时钟信号的电位为无效电位，从电源端VGL输入的电源信号的电位为无效电位，上拉节点Q的电位保持为有效电位，第二晶体管M2在该上拉节点Q的控制下保持导通，第二时钟信号端CLK2通过该第二晶体管M2向输出端OUT输入处于无效电位的第二时钟信号，以实现对输出端OUT的复位，使得显示区域中的薄膜晶体管(Thin Film Transistor，TFT)均保持为截止状态。
保持阶段t4中，从第一时钟信号端CLK1输入的第一时钟信号的电位为有效电位，从输入信号端IN输入的输入信号的电位为无效电位，从第二时钟信号端CLK2输入的第二时钟信号的电位为无效电位，从电源端VGL输入的电源信号的电位为无效电位，第一晶体管M1在该第一时钟信号的控制下导通，输入信号端IN通过该第一晶体管M1向上拉节点Q输入处于无效电位的输入信号，以实现对上拉节点Q的复位。
同时，第四晶体管M4在该第一时钟信号的控制下导通，第一时钟信号端CLK1通过该第四晶体管M4向下拉节点P输入处于有效电位的第一时钟信号，对第二电容器C2充电，使下拉节点P的电位保持为有效电位，第五晶体管M5在该处于有效电位的下拉节点P的控制下导通，电源端VGL通过该第五晶体管M5向输出端OUT输入处于无效电位的电源信号，使该输出端OUT的电位保持为无效电位，即实现对该输出端OUT的持续降噪。
需要说明的是，该各个电源端VGL和信号端输出的信号的具体电平值可以根据实际电路需要进行调整，例如，第一电源信号的电平可以为8伏(V)，第二电源信号的电平可以为-8V，本公开实施例对此不做限定。
综上所述，本公开实施例提供的移位寄存器单元的的驱动方法，在复位阶段中，输出子电路在处于有效电位的上拉节点的控制下，向输出端输入处于无效电位的第二时钟信号，实现对输出端的复位，使得显示区域中的薄膜晶体管保持为截止状态，以及在保持阶段中，输入子电路在第一时钟信号的控制下，向上拉节点输入处于无效电位的输入信号；下拉控制子电路在第一时钟信号的控制下，向下拉节点输入处于有效电位的第一时钟信号；以及下拉子电路在下拉节点的控制下，向输出端输入处于无效电位的电源信号，使输出端的电位保持为无效电位，从而实现对输出端的持续降噪。
本公开实施例提供了一种栅极驱动电路，该栅极驱动电路可以包括多个级联的移位寄存器单元，且每个移位寄存器单元均为图1至图4任一所示的移位寄存器单元。
可选地，该多个级联的移位寄存器单元中，第j个移位寄存器单元的输出端OUT与第j+1个移位寄存器单元的输入信号端IN连接，j为正整数。
示例地，图7是本公开实施例提供的一种栅极驱动电路的局部结构示意图，该图7所示的结构中包括三个级联的移位寄存单元，该三个级联的移位寄存器单元中，每个移位寄存器单元可以为图1至图4任一所示的移位寄存器单元，如图7所示，栅极驱动电路中可以设置有一个启动信号端、三个时钟信号端、有效电位电源信号端VG1和无效电位电源端VG2，每个移位寄存器单元的电源端VGL均与该无效电位电源端VG2连接，且每个移位寄存器单元的供电端VDD均与有效电位电源信号端VG1，该有效电位电源信号端VG1用于为移位寄存器单元供电，启动信号端输出启动信号STV，三个时钟信号端分别输出时钟信号CK1、CK2和CK3，该CK1、CK2和CK3的占空比相同，且CK1、CK2和CK3依次输出处于有效电位的时钟信号，在三个级联的移位寄存单元中，第一级移位寄存器单元GOA1的输入信号端IN输入的输入信号为启动信号STV，第一级移位寄存器单元GOA1的第一时钟信号端CLK1输入的第一时钟信号为时钟信号CK1，第一级移位寄存器单元GOA1的第二时钟信号端CLK2输入的第二时钟信号为时钟信号CK2；第二级移位寄存器单元GOA2的输入信号端IN输入的输入信号为第一级移位寄存器单元GOA1的输出信号，第二级移位寄存器单元GOA2的第一时钟信号端CLK1输入的第一时钟信号为时钟信号CK2，第二级移位寄存器单元GOA2的第二时钟信号端CLK2输入的第二时钟信号为时钟信号CK3；第三级移位寄存器单元GOA3的输入信号端IN输入的输入信号为第二级移位寄存器单元GOA2的的输出信号，第三级移位寄存器单元GOA3的第一时钟信号端CLK1输入的第一时钟信号为时钟信号CK3，第三级移位寄存器单元GOA3的第二时钟信号端CLK2输入的第二时钟信号为时钟信号CK1。本公开实施例提供的栅极驱动电路可以以三个移位寄存器单元为单位，重复以上连接。
综上所述，本公开实施例提供的栅极驱动电路包括多个级联的移位寄存 器单元，每个移位寄存器单元中包括输入子电路、输出子电路、下拉控制子电路和下拉子电路，该移位寄存器单元的电路结构较为简单，且该移位寄存器单元中的输入子电路能够根据输入信号的电位对上拉节点进行充电和复位，无需额外设置对上拉节点进行复位的电路，相较于相关技术，减少了移位寄存器单元中的元件数和信号线占用的空间，进而有效减少了栅极驱动电路在显示装置中所占用的版图面积，有利于窄边框的实现。
本公开实施例提供一种显示装置，该显示装置可以包括本公开实施例提供的栅极驱动电路。该显示装置可以为：液晶面板、电子纸、有机发光二极管(英文：Organic Light-Emitting Diode，简称：OLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供了一种非易失性存储介质，该存储介质内存储有计算机程序，计算机程序被处理器执行时实现本公开实施例提供的移位寄存器单元的驱动方法。
以上所述仅为本公开的较佳实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (15)

  1. 一种移位寄存器单元，包括：
    输入子电路，分别与输入信号端、第一时钟信号端和第一节点连接，所述输入子电路用于在来自所述第一时钟信号端的第一时钟信号的控制下，向所述第一节点输入来自所述输入信号端的输入信号；
    输出子电路，分别与第二时钟信号端、所述第一节点和输出端连接，所述输出子电路用于在所述第一节点的控制下，向所述输出端输入来自所述第二时钟信号端的第二时钟信号；
    控制子电路，分别与所述第一时钟信号端、所述第一节点、电源端和第二节点连接，所述控制子电路用于在所述第一时钟信号的控制下，向所述第二节点输入所述第一时钟信号，以及在所述第一节点的控制下，向所述第二节点输入来自所述电源端的电源信号；以及
    保持子电路，分别与所述电源端、所述第二节点和所述输出端连接，所述保持子电路用于在所述第二节点的控制下，向所述输出端输入所述电源信号。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入子电路包括：第一晶体管；
    所述第一晶体管的栅极与所述第一时钟信号端连接，所述第一晶体管的第一极与所述输入信号端连接，所述第一晶体管的第二极与所述第一节点连接。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述输出子电路包括：第二晶体管；
    所述第二晶体管的栅极与所述第一节点连接，所述第二晶体管的第一极与所述第二时钟信号端连接，所述第二晶体管的第二极与所述输出端连接。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述输出子电路还包括：第一电容器；
    所述第一电容器的一端与所述第一节点连接，所述第一电容器的另一端与所述输出端连接。
  5. 根据权利要求1或2所述的移位寄存器单元，其中，所述控制子电路包括：第一控制子电路和第二控制子电路；
    所述第一控制子电路分别与所述第一节点、所述第二节点和所述电源端连接，所述第一控制子电路用于在所述第一节点的控制下，向所述第二节点输入所述电源信号；
    所述第二控制子电路分别与所述第一时钟信号端和所述第二节点连接，所述第二控制子电路用于在所述第一时钟信号的控制下，向所述第二节点输入所述第一时钟信号。
  6. 根据权利要求5所述的移位寄存器单元，其中，
    所述第一控制子电路包括：第三晶体管；
    所述第三晶体管的栅极与所述第一节点连接，所述第三晶体管的第一极与所述电源端连接，所述第三晶体管的第二极与所述第二节点连接；
    所述第二控制子电路包括：第四晶体管；
    所述第四晶体管的栅极和第一极均与所述第一时钟信号端连接，所述第四晶体管的第二极与所述第二节点连接。
  7. 根据权利要求5所述的移位寄存器单元，其中，所述控制子电路还包括：第二电容器；
    所述第二电容器的一端与所述第二节点连接，所述第二电容器的另一端与所述电源端连接。
  8. 根据权利要求1或2所述的移位寄存器单元，其中，所述保持子电路包括：第五晶体管；
    所述第五晶体管的栅极与所述第二节点连接，所述第五晶体管的第一极与所述电源端连接，所述第五晶体管的第二极与所述输出端连接。
  9. 一种移位寄存器单元的驱动方法，所述方法用于驱动权利要求1至8任一所述的移位寄存器单元，所述方法包括：
    在电位控制阶段中，向第一时钟信号端输入处于有效电位的第一时钟信号，向输入信号端输入处于有效电位的输入信号，以使得所述输入子电路在所述第一时钟信号的控制下，向第一节点输入处于有效电位的输入信号；
    在输出阶段中，向第二时钟信号端输入处于有效电位的第二时钟信号，以使得所述输出子电路在处于有效电位的所述第一节点的控制下，向输出端输入处于有效电位的第二时钟信号；
    在复位阶段中，向第二时钟端输入处于无效电位的所述第二时钟信号， 以使得所述输出子电路在处于有效电位的所述第一节点的控制下，向所述输出端输入处于无效电位的第二时钟信号；
    在保持阶段中，向第一时钟端输入处于有效电位的所述第一时钟信号，向输入信号端输入处于无效电位的所述输入信号，向电源端输入处于无效电位的电源信号，以使得所述输入子电路在所述第一时钟信号的控制下，向所述第一节点输入处于无效电位的输入信号；所述控制子电路在所述第一时钟信号的控制下，向所述第二节点输入处于有效电位的第一时钟信号；以及所述保持子电路在所述第二节点的控制下，向所述输出端输入处于无效电位的电源信号。
  10. 根据权利要求9所述的方法，其中，在所述控制子电路包括第一控制子电路和第二控制子电路的情况下，所述方法还包括：
    在所述电位控制阶段中，所述第一控制子电路在处于有效电位的第一节点的控制下，向所述第二节点输入处于无效电位的电源信号，以及，所述第二控制子电路在处于有效电位的第一时钟信号的控制下，向所述第二节点输入处于有效电位的第一时钟信号，以控制所述第二节点的电位为无效电位。
  11. 根据权利要求9所述的方法，其中，在所述控制子电路包括第一控制子电路和第二控制子电路的情况下，所述方法还包括：在所述输出阶段和所述复位阶段中，所述第一控制子电路在处于有效电位的所述第一节点的控制下向所述第二节点输入处于无效电位的电源信号。
  12. 根据权利要求9所述的方法，其中，在所述控制子电路包括第一控制子电路和第二控制子电路的情况下，所述方法还包括：在所述保持阶段中，所述第二控制子电路在处于有效电位的所述第一时钟信号的控制下，向所述第二节点输入处于有效电位的所述第一时钟信号。
  13. 一种栅极驱动电路，包括：多个级联的权利要求1至8任一所述的移位寄存器单元。
  14. 根据权利要求13所述的栅极驱动电路，其中，所述多个级联的移位寄存器单元中，第j个移位寄存器单元的输出端与第j+1个移位寄存器单元的输入信号端连接，所述j为正整数。
  15. 一种显示装置，包括权利要求13或14所述的栅极驱动电路。
PCT/CN2018/121116 2018-04-25 2018-12-14 移位寄存器单元、驱动方法、栅极驱动电路及显示装置 Ceased WO2019205663A1 (zh)

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CN113113071A (zh) * 2021-04-13 2021-07-13 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108288451B (zh) * 2018-04-25 2021-12-14 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN108831403B (zh) * 2018-08-29 2020-09-04 合肥鑫晟光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN110880285A (zh) * 2018-09-05 2020-03-13 上海和辉光电有限公司 一种移位寄存器、栅极驱动电路及显示面板
CN109658888B (zh) 2019-01-02 2022-01-14 合肥京东方光电科技有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109545152B (zh) * 2019-01-02 2020-09-01 合肥鑫晟光电科技有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN110648638B (zh) 2019-09-25 2022-03-25 合肥京东方卓印科技有限公司 栅极驱动电路、像素电路、显示面板和显示设备
CN210865579U (zh) * 2020-02-24 2020-06-26 北京京东方显示技术有限公司 移位寄存器电路、栅极驱动电路及显示装置
CN111583885B (zh) 2020-06-17 2021-11-30 京东方科技集团股份有限公司 移位寄存器的驱动方法及装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101012972B1 (ko) * 2003-12-30 2011-02-10 엘지디스플레이 주식회사 액티브 매트릭스 표시장치
CN103247255A (zh) * 2012-02-13 2013-08-14 三星显示有限公司 用于显示装置的扫描驱动装置及其驱动方法
CN104282285A (zh) * 2014-10-29 2015-01-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN104992662A (zh) * 2015-08-04 2015-10-21 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、显示装置
CN106548747A (zh) * 2017-02-06 2017-03-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN106782285A (zh) * 2017-03-03 2017-05-31 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108288451A (zh) * 2018-04-25 2018-07-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007317288A (ja) * 2006-05-25 2007-12-06 Mitsubishi Electric Corp シフトレジスタ回路およびそれを備える画像表示装置
JP5419762B2 (ja) * 2010-03-18 2014-02-19 三菱電機株式会社 シフトレジスタ回路
CN102800289B (zh) * 2012-08-10 2015-02-18 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN103151010B (zh) 2013-02-27 2014-12-10 京东方科技集团股份有限公司 一种移位寄存器和显示装置
KR102167138B1 (ko) * 2014-09-05 2020-10-16 엘지디스플레이 주식회사 쉬프트 레지스터 및 그를 이용한 표시 장치
CN104360781B (zh) * 2014-11-12 2017-10-03 京东方科技集团股份有限公司 触控电极的驱动单元、驱动电路、触控面板及驱动方法
CN104616616B (zh) * 2015-02-12 2017-12-15 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、阵列基板、显示装置
JP2018106057A (ja) * 2016-12-27 2018-07-05 株式会社ジャパンディスプレイ 表示装置及び単位レジスタ回路
CN107146568B (zh) * 2017-07-11 2018-12-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
KR102381884B1 (ko) * 2017-10-18 2022-03-31 엘지디스플레이 주식회사 디스플레이 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101012972B1 (ko) * 2003-12-30 2011-02-10 엘지디스플레이 주식회사 액티브 매트릭스 표시장치
CN103247255A (zh) * 2012-02-13 2013-08-14 三星显示有限公司 用于显示装置的扫描驱动装置及其驱动方法
CN104282285A (zh) * 2014-10-29 2015-01-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN104992662A (zh) * 2015-08-04 2015-10-21 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa电路、显示装置
CN106548747A (zh) * 2017-02-06 2017-03-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN106782285A (zh) * 2017-03-03 2017-05-31 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN108288451A (zh) * 2018-04-25 2018-07-17 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113113071A (zh) * 2021-04-13 2021-07-13 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置

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