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WO2018130921A1 - Dispositif de réception d'image, et système de réception d'image le comprenant - Google Patents

Dispositif de réception d'image, et système de réception d'image le comprenant Download PDF

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Publication number
WO2018130921A1
WO2018130921A1 PCT/IB2018/050074 IB2018050074W WO2018130921A1 WO 2018130921 A1 WO2018130921 A1 WO 2018130921A1 IB 2018050074 W IB2018050074 W IB 2018050074W WO 2018130921 A1 WO2018130921 A1 WO 2018130921A1
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WIPO (PCT)
Prior art keywords
image data
decoder
encoder
layer
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/IB2018/050074
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English (en)
Japanese (ja)
Inventor
黒川義元
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of WO2018130921A1 publication Critical patent/WO2018130921A1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display

Definitions

  • the encoder 24 has a function of extracting features from the image data subjected to the image processing and compressing the image data.
  • the decoder 33 restores and outputs image data from the data extracted by the encoder 24 in accordance with the weighting coefficient determined by learning.
  • the restored image data has the same resolution as the image data input to the encoder 24.
  • the decoder 33 may be configured to generate triangular image data from three coordinate data.
  • the learning is performed by inputting learning data to the auto encoder and updating the weighting coefficient so that the output of the auto encoder becomes equal to the learning data.
  • the learning data it is preferable to use a part of the image data cut out.
  • the above learning can be performed by unsupervised learning.
  • a reverse error propagation method or the like can be used as a learning algorithm.
  • the display panel 30 and the reception arithmetic circuit 20 are electrically connected using a cable such as FPC (Flexible Printed Circuits).
  • FPC Flexible Printed Circuits
  • the image receiving apparatus 10 handles a large amount of data, such as 8K (7680 ⁇ 4320) broadcast, an FPC capable of high-speed transmission is required, but transmission is performed due to physical restrictions on the number of FPC wires. May take time.
  • the physical length of the cable connecting the reception arithmetic circuit 20 and the display panel 30 increases, and the transmission loss of image data increases.
  • the image data is transmitted from the reception arithmetic circuit 20 to the display panel 30 in a compressed state (with a small data size). Therefore, the image receiving device 10 can efficiently transmit image data having a high resolution such as 8K to the display panel 30. Also, if the data size is small, the power required for transmission can be small, and the image receiving apparatus 10 can reduce power consumption.
  • the auto encoder may change not only the weighting coefficient but also the configuration of the neural network.
  • configuration data that constitutes an optimal neural network in the learning
  • setting the configuration data in the encoder 24 and the decoder 33 inference reflecting the learning result can be executed by the image receiving apparatus 10.
  • the details of the semiconductor device capable of changing the configuration of the neural network will be described in a second embodiment to be described later.
  • the decoder 33 needs to be used as a set with the encoder 24, the weighting coefficient (or configuration data), the use of a third party can be restricted. Therefore, it is possible to prevent an act of illegally obtaining a driver IC, a display panel, or the like on which the decoder 33 is mounted and manufacturing and selling counterfeit products.
  • FIG. 4 shows a configuration of the semiconductor device 100 capable of realizing various neural networks.
  • the hierarchical structure shown in FIG. 4 can be made to correspond to the hierarchical structure shown in FIG.
  • the product-sum operation element 130 may be referred to as a neuron.
  • FIG. 5 is a block diagram illustrating a configuration example of the product-sum operation element 130.
  • the product-sum operation element 130 includes multiplication elements 131 [1] to 131 [S] corresponding to the input signals IN [1] to IN [S], an addition element 133, an activation function element 134, and CM ( Configuration memory) 132 [1] to 132 [S] and CM 135.
  • S is an integer of 1 or more.
  • the multiplication element 131 has a function of multiplying the data stored in the CM 132 and the input signal IN.
  • the CM 132 stores the weighting factor described with reference to FIG.
  • the adding element 133 has a function of adding all the outputs (multiplication results) of the multiplying elements 131 [1] to 131 [S].
  • the activation function element 134 performs an operation on the output (product-sum operation result) of the addition element 133 according to a function defined by data stored in the CM 135, and sets the output signal OUT.
  • the function can be a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like. These functions are implemented by a table method or a broken line approximation, and the corresponding data is stored in the CM 135 as configuration data.
  • FIG. 6A is a circuit diagram illustrating a configuration of the programmable switch 140.
  • the programmable switch 140 has a switch 160.
  • the programmable switch 140 has a function of transmitting output signals OUT [1] to OUT [S] as input signals IN [1] to IN [S].
  • the programmable switch 140 [S 2 ] includes output signals OUT [1] to OUT [S 1 ] of the operation layer 141 [ 1 ] and a product-sum operation element 130 [ S 2 ] has a function of controlling connection with the input signal IN [1: S 1 ].
  • the programmable switch 140 has a function of controlling connection between the signal “0” and the input signals IN [1] to IN [S] of the product-sum operation element 130.
  • FIG. 6B is a circuit diagram illustrating a configuration example of the switch 160.
  • the switch 160 includes a CM 161 and a switch 162.
  • the switch 162 has a function of controlling electrical continuity between the output signal OUT [i] and the input signal IN [i].
  • the switch 162 has a function of controlling conduction between the signal “0” and the input signal IN [i]. Note that i is an integer of 1 to S.
  • On / off of the switch 162 is controlled by configuration data stored in the CM 161.
  • a transistor can be used as the switch 162.
  • the product-sum operation element 130 When the product-sum operation element 130 does not use the output signal OUT [i] from the immediately preceding operation layer 141 as an input, the product-sum operation element 130 is supplied with the signal “0” as the input signal IN [i]. The At this time, power consumption can be reduced by stopping the supply of power to the multiplier 131 [i] corresponding to the input signal IN [i] (performing power gating). For example, in FIG.
  • the configuration memory can be configured using SRAM and MRAM.
  • the configuration memory can also be configured by a memory using an OS transistor (hereinafter referred to as an OS memory).
  • OS memory By using the OS memory as the configuration memory, the power consumption of the semiconductor device 100 can be significantly reduced.
  • the semiconductor device 100 can configure a low power consumption network with a small number of elements.
  • the semiconductor device 100 can configure a low power consumption network with a small number of elements.
  • the number of wirings included in the network can be reduced.
  • the semiconductor device 100 can be used for the server 50 and the image receiving device 10 shown in FIG.
  • examination and learning of the hierarchical configuration of the neural network can be performed by the server 50 and inference can be performed by the image receiving apparatus 10.
  • an image receiving apparatus capable of efficiently transmitting image data or an image receiving system including the image receiving apparatus.
  • an image receiving apparatus with reduced power consumption or an image receiving system including the same can be provided.
  • FIG. 7A is a block diagram for explaining the structure of the display panel 30.
  • the display panel 30 includes a pixel array 31, a gate driver 34a, a gate driver 34b, and a source driver 32.
  • the gate drivers 34 a and 34 b are respectively provided on the left and right of the pixel array 31.
  • the display panel 30 is arranged substantially in parallel with each other, and the plurality of scanning lines GL whose potentials are controlled by the gate drivers 34 a and 34 b, and each of the display panels 30 are arranged substantially in parallel with each other, and the source driver 32.
  • a plurality of signal lines SL whose potentials are controlled by.
  • the pixel array 31 has a plurality of pixels 36 arranged in a matrix.
  • each scanning line GL is electrically connected to a plurality of pixels 36 arranged in any row.
  • Each signal line SL is electrically connected to a plurality of pixels 36 arranged in any column.
  • the transistors included in the gate drivers 34a and 34b and the source driver 32 (hereinafter collectively referred to as a driver circuit) can be formed at the same time as the transistors included in the pixel 36.
  • part or all of the driver circuit may be formed over another substrate and electrically connected to the display panel 30.
  • part or all of the driver circuit may be formed using an IC chip using a single crystal substrate, and the IC chip may be electrically connected to the display panel 30.
  • the number of IC chips is not limited to one, and a necessary number may be provided according to the number of pixels 36.
  • the IC chip can be provided on the display panel 30 by using a COG (Chip on Glass) method or a COF (Chip on Film) method.
  • the pixel array 31 of FIG. 7A is divided into four pixel arrays 31a, 31b, 31c, and 31d, and the source driver 32 is divided into two source drivers 32a and 32b.
  • An example is shown in which the array is arranged above and below the array.
  • the pixels 36 included in the pixel arrays 31a and 31b are electrically connected to the source driver 32a through the signal line SLa.
  • the pixels 36 included in the pixel arrays 31c and 31d are electrically connected to the source driver 32b through the signal line SLb.
  • the number of divisions of the pixel array 31 is not limited to four, and any number of divisions may be performed.
  • the structure illustrated in FIG. 7B can reduce the number of pixels 36 connected to one signal line. That is, the capacity connected to one signal line can be reduced. As a result, the display panel 30 can shorten the time for writing image data to the signal lines.
  • the structure illustrated in FIG. 7B is particularly preferably applied to a high-definition display panel such as 8K (number of pixels: 7680 ⁇ 4320). For example, by applying a pixel array having 4K pixels (3840 ⁇ 2160) to the pixel arrays 31a to 31d, the display panel 30 having 8K pixels can be realized.
  • FIG. 8A shows an example in which each signal line SL in FIG. 7A is divided into two signal lines SL1 and SL2.
  • the plurality of pixels 36 arranged in the same column are electrically connected alternately with the signal line SL1 or the signal line SL2.
  • the structure illustrated in FIG. 8A can reduce the number of pixels 36 connected to one signal line. As a result, the display panel 30 can shorten the time for writing image data to the signal lines.
  • the display panel 30 can display a seamless smooth image.
  • FIG. 8B illustrates an example in which each signal line SL in FIG. 7A is divided into four signal lines SL1, SL2, SL3, and SL4.
  • the display panel 30 has the structure illustrated in FIG. 8B, the number of pixels 36 connected to one signal line can be further reduced. As a result, the display panel 30 can further reduce the time for writing image data to the signal line. In addition, a smooth image without a joint can be displayed.
  • a pixel 36 illustrated in FIG. 9A includes a transistor 3431, a capacitor 3233, and a liquid crystal element 3432.
  • One of a source electrode and a drain electrode of the transistor 3431 is electrically connected to the signal line SL, and the other is electrically connected to a node 3436.
  • a gate electrode of the transistor 3431 is electrically connected to the scan line GL.
  • the transistor 3431 has a function of controlling writing of a data signal to the node 3436.
  • capacitor line CL a wiring to which a specific potential is supplied
  • the potential of the capacitor line CL is appropriately set according to the specification of the pixel 36.
  • the capacitor 3233 has a function of holding data written to the node 3436.
  • One of the pair of electrodes of the liquid crystal element 3432 is supplied with a common potential (common potential), and the other is electrically connected to the node 3436.
  • the alignment state of the liquid crystal included in the liquid crystal element 3432 is determined by data written to the node 3436.
  • a TN mode for example, a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric ALC).
  • Crystal) mode MVA mode, PVA (Patterned Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, or TBA (Transverse Bend) Or the like may be used lignment) mode.
  • ECB Electrode Controlled Birefringence
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • a pixel 36 illustrated in FIG. 9B includes a transistor 3431, a capacitor 3233, a transistor 3232, and a light-emitting element 3125.
  • One of a source electrode and a drain electrode of the transistor 3431 is electrically connected to a signal line SL to which a data signal is supplied, and the other is electrically connected to a node 3435.
  • a gate electrode of the transistor 3431 is electrically connected to a scan line GL to which a gate signal is supplied.
  • the transistor 3431 has a function of controlling writing of a data signal to the node 3435.
  • One of the pair of electrodes of the capacitor 3233 is electrically connected to the node 3435 and the other is electrically connected to the node 3437.
  • the capacitor 3233 functions as a storage capacitor that stores data written to the node 3435.
  • One of a source electrode and a drain electrode of the transistor 3232 is electrically connected to the potential supply line VL_a, and the other is electrically connected to a node 3437.
  • a gate electrode of the transistor 3232 is electrically connected to the node 3435.
  • the transistor 3232 has a function of controlling current flowing to the light-emitting element 3125.
  • the potential supply line VL_a has a function of supplying V DD .
  • the potential supply line VL_b has a function of supplying a V SS.
  • the 10A and 10B includes an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019.
  • the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.
  • the electrode 4015 is formed from the same conductive layer as the first electrode layer 4030.
  • the pixel 36 provided over the first substrate 4001 includes a transistor.
  • FIG. 10A illustrates a transistor 3431 included in the pixel 36
  • FIG. 10B illustrates the pixel 36.
  • the included transistor 3232 is illustrated.
  • the transistors 3431 and 3232 are provided over the insulating layer 4102.
  • the transistors 3431 and 3232 each include an electrode 517 formed over the insulating layer 4102, and the insulating layer 4103 is formed over the electrode 517.
  • a semiconductor layer 512 is formed over the insulating layer 4103.
  • An electrode 510 and an electrode 511 are formed over the semiconductor layer 512, an insulating layer 4110 and an insulating layer 4111 are formed over the electrode 510 and the electrode 511, and an electrode 516 is formed over the insulating layer 4110 and the insulating layer 4111.
  • the electrode 510 and the electrode 511 are formed using the same conductive layer as the wiring 4014.
  • the electrode 517 functions as a gate electrode
  • the electrode 510 functions as one of a source electrode and a drain electrode
  • the electrode 511 functions as the other of the source electrode and the drain electrode.
  • the electrode 516 functions as a back gate electrode.
  • Each of the transistors 3431 and 3232 has a bottom-gate structure and has a back gate, whereby the on-state current can be increased.
  • the threshold value of the transistor can be controlled. Note that the electrode 516 may be omitted in some cases in order to simplify the manufacturing process.
  • the semiconductor layer 512 functions as a channel formation region.
  • the semiconductor layer 512 crystalline silicon, polycrystalline silicon, amorphous silicon, metal oxide, an organic semiconductor, or the like may be used. Further, an impurity may be introduced into the semiconductor layer 512 as needed in order to increase the conductivity of the semiconductor layer 512 or to control the threshold value of the transistor.
  • the semiconductor layer 512 preferably contains indium (In). In the case where the semiconductor layer 512 is a metal oxide containing indium, the semiconductor layer 512 has high carrier mobility (electron mobility). Further, the semiconductor layer 512 is preferably a metal oxide containing the element M.
  • the element M is preferably aluminum (Al), gallium (Ga), tin (Sn), or the like.
  • the element M may be a combination of a plurality of the aforementioned elements.
  • the element M is an element having a high binding energy with oxygen, for example.
  • the element M is an element whose binding energy with oxygen is higher than that of indium, for example.
  • the semiconductor layer 512 is preferably a metal oxide containing zinc (Zn). A metal oxide containing zinc may be easily crystallized.
  • the semiconductor layer 512 is not limited to a metal oxide containing indium.
  • the semiconductor layer 512 may be a metal oxide that does not contain indium, such as zinc tin oxide and gallium tin oxide, and contains at least one of zinc, gallium, and tin.
  • the 10A and 10B includes a capacitor 3233.
  • the capacitor 3233 has a region where the electrode 511 and the electrode 4021 overlap with each other with the insulating layer 4103 interposed therebetween.
  • the electrode 4021 is formed using the same conductive layer as the electrode 517.
  • FIG. 10A illustrates an example of a liquid crystal display panel using a liquid crystal element as a display element.
  • a liquid crystal element 3432 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008.
  • an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008.
  • the second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 interposed therebetween.
  • the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Yes.
  • a spherical spacer may be used.
  • first substrate 4001 and the second substrate 4006 There is no particular limitation on materials used for the first substrate 4001 and the second substrate 4006. Depending on the purpose, it may be determined in consideration of the presence or absence of translucency and heat resistance enough to withstand heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Further, as the first substrate 4001 and the second substrate 4006, a semiconductor substrate, a flexible substrate (flexible substrate), a bonded film, a base film, or the like may be used, respectively.
  • the semiconductor substrate examples include an elemental semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. is there.
  • the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.
  • Examples of materials such as a flexible substrate, a laminated film, and a base film include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polytetrafluoroethylene (PTFE), and polypropylene.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyethersulfone
  • PTFE polytetrafluoroethylene
  • Polyester polyvinyl fluoride, polyvinyl chloride, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, aramid, epoxy resin, acrylic resin, and the like can be used.
  • a lightweight display panel By using such a material as the substrate, a lightweight display panel can be provided. In addition, by using such a material as the substrate, a display panel that is resistant to impact can be provided. Further, by using such a material for the substrate, a display panel which is not easily damaged can be provided.
  • the flexible substrate used for the first substrate 4001 and the second substrate 4006 is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed.
  • the flexible substrate used for the first substrate 4001 and the second substrate 4006 has a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 / K or less, 5 ⁇ 10 ⁇ 5 / K or less, or 1 ⁇ 10 ⁇ 5 /, for example.
  • a material that is K or less may be used.
  • aramid since aramid has a low coefficient of linear expansion, it is suitable as a flexible substrate.
  • the insulating layers such as the insulating layer 4102, the insulating layer 4103, the insulating layer 4110, and the insulating layer 4111 include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, and oxide
  • a material selected from silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, and the like can be formed as a single layer or stacked layers.
  • a material obtained by mixing a plurality of materials selected from oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.
  • a nitrided oxide refers to a compound having a higher nitrogen content than oxygen.
  • oxynitride refers to a compound having a higher oxygen content than nitrogen.
  • content of each element can be measured using Rutherford backscattering method (RBS: Rutherford Backscattering Spectrometry) etc., for example.
  • the insulating layer 4102 and the insulating layer 4111 are preferably formed using an insulating material which does not easily transmit impurities.
  • an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer, or What is necessary is just to use it by lamination
  • the insulating layer 4102 or the insulating layer 4111 may be formed using indium tin zinc oxide (In—Sn—Zn oxide) with high insulating properties or the like.
  • an insulating material that does not easily transmit impurities for the insulating layer 4102 By using an insulating material that does not easily transmit impurities for the insulating layer 4102, diffusion of impurities from the first substrate 4001 side can be suppressed and the reliability of the transistor can be improved. By using an insulating material that does not easily transmit impurities for the insulating layer 4111, diffusion of impurities from the insulating layer 4112 side can be suppressed, and the reliability of the transistor can be improved.
  • the insulating layer 4112 is an insulating layer having a flat surface.
  • an organic material having heat resistance such as polyimide, acrylic resin, benzocyclobutene-based resin, polyamide, or epoxy resin can be used in addition to the above insulating material.
  • a low dielectric constant material low-k material
  • a siloxane resin PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that a plurality of insulating layers formed using these materials may be stacked.
  • the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material.
  • the siloxane-based resin may have an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent.
  • the organic group may have a fluoro group.
  • CMP chemical mechanical polishing
  • a material for forming a conductive layer such as the first electrode layer 4030, the second electrode layer 4031, the wiring 4014, the electrode 4015, the electrode 4021, the electrode 510, the electrode 511, the electrode 516, and the electrode 517, aluminum
  • a material containing one or more metal elements selected from chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and the like. it can.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus may be used.
  • an oxide semiconductor with high electrical conductivity or a nitride semiconductor with high electrical conductivity may be used.
  • silicide such as nickel silicide may be used. A plurality of conductive layers formed using these materials may be stacked.
  • indium tin oxide ITO: Indium Tin Oxide
  • indium oxide containing tungsten oxide indium zinc oxide containing tungsten oxide
  • indium oxide containing titanium oxide It is also possible to apply a conductive material containing oxygen such as indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, or a conductive material containing nitrogen such as titanium nitride or tantalum nitride. it can.
  • the conductive layer can have a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined.
  • the conductive layer can also have a stacked structure in which the above-described material containing a metal element is combined with a conductive material containing nitrogen.
  • the conductive layer can have a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.
  • At least one of the first electrode layer 4030 and the second electrode layer 4031 is preferably formed using a light-transmitting conductive material.
  • thermotropic liquid crystal a low molecular liquid crystal
  • a polymer liquid crystal a polymer dispersed liquid crystal
  • ferroelectric liquid crystal an antiferroelectric liquid crystal, or the like
  • liquid crystal layer 4008 a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like
  • These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.
  • the specific resistance of the liquid crystal material is 1 ⁇ 10 9 ⁇ ⁇ cm or more, preferably 1 ⁇ 10 11 ⁇ ⁇ cm or more, and more preferably 1 ⁇ 10 12 ⁇ ⁇ cm or more.
  • the value of the specific resistance in this specification shall be the value measured at 20 degreeC.
  • the transistor 3431 can reduce current in an off state (off-state current). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.
  • an optical member such as a black matrix (light shielding layer), a polarizing member, a retardation member, or an antireflection member may be provided as appropriate.
  • a black matrix light shielding layer
  • a polarizing member such as a polarizing member
  • a retardation member such as a retardation member
  • an antireflection member such as a polarizing member, a retardation member, or an antireflection member
  • circularly polarized light using a polarizing substrate and a retardation substrate may be used.
  • a backlight, a sidelight, or the like may be used as the light source.
  • FIG. 10B illustrates an example of a display panel using a light-emitting element such as an EL element as a display element.
  • EL elements are classified into organic EL elements and inorganic EL elements.
  • the organic EL element by applying a voltage, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.
  • the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar layer.
  • Material a material having a high electron transporting property and a high hole transporting property
  • the EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.
  • Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure.
  • the dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level.
  • the thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions.
  • FIG. 10B illustrates an example in which an organic EL element is used as the light-emitting element 3125.
  • the light-emitting element 3125 is electrically connected to a transistor 3232 provided in the pixel 36.
  • the structure of the light-emitting element 3125 is a stacked structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031; however, the structure is not limited to this structure.
  • the structure of the light-emitting element 3125 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 3125, or the like.
  • a partition wall 4510 is formed using an organic insulating material or an inorganic insulating material.
  • a photosensitive resin material is used, an opening is formed on the first electrode layer 4030, and the partition wall 4510 is formed so that a side surface of the opening is an inclined surface formed with a continuous curvature. Is preferred.
  • the light emitting layer 4511 may be composed of a single layer or a plurality of stacked layers.
  • a protective layer may be formed over the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 3125.
  • the protective layer silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be used.
  • a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and sealed.
  • a protective film bonded film, ultraviolet curable resin film, or the like
  • a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.
  • an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon.
  • PVC polyvinyl chloride
  • acrylic resin polyimide
  • epoxy resin epoxy resin
  • silicone resin silicone resin
  • PVB Polyvinyl butyral
  • EVA ethylene vinyl acetate
  • the filler 4514 may contain a desiccant.
  • the sealant 4005 a glass material such as glass frit, or a resin material such as a two-component mixed resin, a curable resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.
  • an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate ( ⁇ / 4 plate, ⁇ / 2 plate), a color filter, or the like is provided on the light emitting surface of the light emitting element. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.
  • the light-emitting element has a microcavity structure
  • light with high color purity can be extracted.
  • the reflection can be reduced and the visibility of the display image can be improved.
  • the first electrode layer 4030 and the second electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. It can be formed using a light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.
  • the first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) and other metals, or alloys thereof, or One or more metal nitrides can be used.
  • the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer).
  • a conductive high molecule also referred to as a conductive polymer.
  • a so-called ⁇ -electron conjugated conductive polymer can be used.
  • polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.
  • the first electrode layer 4030 and the second electrode layer 4031 In order to extract light from the light-emitting element 3125 to the outside, at least one of the first electrode layer 4030 and the second electrode layer 4031 only needs to be transparent. Display panels are classified into a top emission (top emission) structure, a bottom emission (bottom emission) structure, and a double emission (dual emission) structure depending on how light is extracted.
  • the top emission structure refers to a case where light is extracted from the second substrate 4006.
  • the bottom emission structure refers to a case where light is extracted from the first substrate 4001.
  • the dual emission structure refers to a case where light is extracted from both the second substrate 4006 and the first substrate 4001.
  • the second electrode layer 4031 may be transparent.
  • the first electrode layer 4030 In the case of a dual emission structure, the first electrode layer 4030 and the second electrode layer 4031 may be transparent.
  • FIG. 11A illustrates a cross-sectional view in the case where a top-gate transistor is provided in the transistor 3431 illustrated in FIG.
  • FIG. 11B illustrates a cross-sectional view in the case where a top-gate transistor is provided in the transistor 3232 illustrated in FIG.
  • the electrode 517 has a function as a gate electrode
  • the electrode 510 has a function as one of a source electrode and a drain electrode
  • the electrode 511 has It functions as the other of the source electrode and the drain electrode.
  • FIGS. 10A and 10B the description of FIGS. 10A and 10B may be referred to.
  • on-state current refers to drain current when a transistor is in an on state.
  • the ON state (sometimes abbreviated as ON) is a state where the voltage between the gate and the source (V G ) is equal to or higher than the threshold voltage (V th ) in an n-channel transistor, unless otherwise specified, p
  • V G is a state of V th or less.
  • the on-current of the n-channel transistor V G refers to a drain current when the above V th.
  • the on-state current of the transistor may depend on a voltage (V D ) between the drain and the source.
  • off-state current refers to drain current when a transistor is off.
  • the OFF state (sometimes referred to as OFF), unless otherwise specified, the n-channel type transistor, V G is lower than V th state, the p-channel type transistor, V G is higher than V th state Say.
  • the off-current of the n-channel transistor refers to the drain current when V G is lower than V th.
  • Off-state current of the transistor may be dependent on the V G. Accordingly, the off current of the transistor is less than 10 -21 A, and may refer to the value of V G to off-current of the transistor is less than 10 -21 A are present.
  • the off-state current of the transistor may depend on V D.
  • the off-state current is such that the absolute value of V D is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V , 12V, 16V, or 20V may be represented.
  • the off current may represent an off current in V D used in a semiconductor device or the like including the transistor.
  • one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is indicated as “the other of the source and the drain” (or the second electrode or the second terminal).
  • the source and drain of a transistor vary depending on the structure or operating conditions of the transistor.
  • the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • X and Y are connected without passing through an element, a light emitting element, a load, or the like.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • a switch for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • More than one element, light emitting element, load, etc. can be connected between X and Y.
  • the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current.
  • the switch has a function of selecting and switching a path through which a current flows.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.

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  • Multimedia (AREA)
  • Signal Processing (AREA)
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  • Computer Hardware Design (AREA)
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  • Theoretical Computer Science (AREA)
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Abstract

L'invention concerne un dispositif de réception d'image apte à transmettre des données d'image efficacement. Le dispositif de réception d'image comprend un panneau d'affichage, un premier décodeur, et un codeur. Le panneau d'affichage comprend un second décodeur. Le codeur et le second décodeur constituent un autocodeur. Le premier décodeur génère des premières données d'image à partir d'un signal de diffusion. Les premières données d'image sont entrées dans le codeur. Le second décodeur délivre en sortie des secondes données d'image. Le panneau d'affichage affiche les secondes données d'image. Les premières données d'image et les secondes données d'image ont la même résolution.
PCT/IB2018/050074 2017-01-16 2018-01-05 Dispositif de réception d'image, et système de réception d'image le comprenant Ceased WO2018130921A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330194A (ja) * 1996-06-11 1997-12-22 Hitachi Ltd 情報処理装置
JP2005055825A (ja) * 2003-08-07 2005-03-03 Seiko Epson Corp 画像表示装置、画像表示方法及び画像表示プログラム
JP2007181052A (ja) * 2005-12-28 2007-07-12 Seiko Epson Corp 画像出力システム
JP2009065720A (ja) * 2001-04-12 2009-03-26 Sony Corp 画像信号処理装置
JP2010272004A (ja) * 2009-05-22 2010-12-02 Sony Corp 判別装置及び判別方法、並びにコンピューター・プログラム
JP2016082498A (ja) * 2014-10-21 2016-05-16 三菱電機株式会社 デジタル放送受信装置及び方法、並びにプログラム及び記録媒体

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09330194A (ja) * 1996-06-11 1997-12-22 Hitachi Ltd 情報処理装置
JP2009065720A (ja) * 2001-04-12 2009-03-26 Sony Corp 画像信号処理装置
JP2005055825A (ja) * 2003-08-07 2005-03-03 Seiko Epson Corp 画像表示装置、画像表示方法及び画像表示プログラム
JP2007181052A (ja) * 2005-12-28 2007-07-12 Seiko Epson Corp 画像出力システム
JP2010272004A (ja) * 2009-05-22 2010-12-02 Sony Corp 判別装置及び判別方法、並びにコンピューター・プログラム
JP2016082498A (ja) * 2014-10-21 2016-05-16 三菱電機株式会社 デジタル放送受信装置及び方法、並びにプログラム及び記録媒体

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
vol. 115, 22 January 2015 (2015-01-22), pages 129 - 132 *

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