WO2018130921A1 - Image reception device, and image reception system including same - Google Patents

Abstract

Provided is an image reception device capable of transmitting image data efficiently. The image reception device comprises a display panel, a first decoder, and an encoder. The display panel comprises a second decoder. The encoder and the second decoder constitute an autoencoder. The first decoder generates first image data from a broadcast signal. The first image data is input to the encoder. The second decoder outputs second image data. The display panel displays the second image data. The first image data and the second image data have the same resolution.

Description

Image receiving apparatus and image receiving system including the same

One embodiment of the present invention relates to an image receiving apparatus or an image receiving system including the same.

One embodiment of the present invention relates to a semiconductor device. Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a memory device, an electro-optical device, a power storage device, a semiconductor circuit, and an electronic device may include a semiconductor device.

In recent years, 8K UHDTV (8K Ultra High Definition Television) having a number of pixels of 7680 × 4320 has been proposed as a digital video standard, and high definition and an increase in the number of pixels are required.

In digital broadcasting, in order to transmit image data in a limited broadcasting band, how to compress (encode) the image data is important. For example, in 8K digital broadcasting, H.264 is used for compressing broadcast signals. A method called H.265 / HEVC (High Efficiency Video Coding) is employed.

In recent years, it has been proposed that deep learning using a neural network for image recognition and the like is effective, and development has been actively conducted.

An auto encoder is known as one of neural networks. The auto encoder has an encoder and a decoder. The encoder has a function of compressing input data information into low-dimensional data, and the decoder has a function of restoring data corresponding to the input data from the compressed data. Learning by the auto encoder is performed by supplying learning data as input data of the encoder and updating the coupling strength so that the output data of the decoder becomes equal to the input data (that is, learning data). Learning by the auto encoder does not require teacher data corresponding to the learning data, and can be called unsupervised learning.

In recent years, a transistor using an oxide semiconductor or a metal oxide in a channel formation region (Oxide Semiconductor transistor, hereinafter referred to as an OS transistor) has attracted attention. The OS transistor has an extremely small off-state current. An application using an OS transistor has been proposed using the feature.

For example, Patent Document 1 discloses an example in which an OS transistor is used for learning a neural network.

US Patent Publication No. 2016/0343452

In 8K digital broadcasting, a television decompresses (decodes) a received broadcast signal with a receiver, and transmits image data to a display panel. Image data obtained by decompression has a data amount corresponding to 8K. Therefore, the television transmits a huge amount of data from the receiver to the display panel. In particular, when the area of a television display panel is large, it is necessary to connect a physically long distance with a cable or the like. As a result, a long time and high power are required for data transmission.

An object of one embodiment of the present invention is to provide an image receiving device capable of efficiently transmitting image data. Another object of one embodiment of the present invention is to provide an image receiving device with reduced power consumption. Another object of one embodiment of the present invention is to provide an image receiving system capable of efficiently transmitting image data. Another object of one embodiment of the present invention is to provide an image receiving system with reduced power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of a plurality of tasks does not disturb each other's existence. Note that one embodiment of the present invention does not have to solve all of these problems. Problems other than those listed will be apparent from descriptions of the specification, drawings, claims, and the like, and these problems may also be a problem of one embodiment of the present invention.

One embodiment of the present invention is an image receiving device including a display panel, a first decoder, and an encoder. The display panel has a second decoder. The encoder and the second decoder constitute an auto encoder. The first decoder generates first image data from the broadcast signal. The first image data is input to the encoder. The second decoder outputs second image data. The display panel displays the second image data.

In the above embodiment, it is preferable that the first image data and the second image data have the same resolution.

One embodiment of the present invention is an image receiving system including a server, a display panel, a first decoder, and an encoder. The display panel has a second decoder. The encoder and the second decoder constitute an auto encoder. The first decoder generates first image data from the broadcast signal. The first image data is input to the encoder. The second decoder outputs second image data. The display panel displays the second image data. The server determines the autoencoder weighting factor.

One embodiment of the present invention is an image receiving system including a server, a remote controller, a display panel, a first decoder, and an encoder. The display panel has a second decoder. The encoder and the second decoder constitute an auto encoder. The first decoder generates first image data from the broadcast signal. The first image data is input to the encoder. The second decoder outputs second image data. The display panel displays the second image data. The server determines the autoencoder weighting factor. The weighting factor is transmitted from the server to the encoder and the second decoder via the remote controller.

In the said form, it is preferable that a remote controller is a smart phone.

In the above embodiment, it is preferable that the first image data and the second image data have the same resolution.

One embodiment of the present invention can provide an image receiving device capable of efficiently transmitting image data. One embodiment of the present invention can provide an image receiving device with reduced power consumption. One embodiment of the present invention can provide an image receiving system capable of efficiently transmitting image data. One embodiment of the present invention can provide an image receiving system with reduced power consumption. One embodiment of the present invention can provide a novel semiconductor device.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

2 is a diagram illustrating an image receiving apparatus and an image receiving system including the image receiving apparatus. FIG. 1 is a block diagram for explaining an image receiving apparatus and an image receiving system including the image receiving apparatus. The conceptual diagram for demonstrating an auto encoder. FIG. 10 is a circuit diagram illustrating a configuration example of a semiconductor device. The block diagram which shows the structural example of a product-sum operation element. The circuit diagram which shows the structural example of a programmable switch. The block diagram which shows the structural example of a display panel. The block diagram which shows the structural example of a display panel. FIG. 6 is a circuit diagram illustrating a configuration example of a pixel. Sectional drawing which shows the structural example of a display panel. Sectional drawing which shows the structural example of a display panel.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different forms, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and the scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

In the drawings, the size, the thickness of layers, or regions are exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings.

Further, in this specification, the following embodiments can be combined as appropriate. In the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined with each other as appropriate.

In this specification, the term “neural network” refers to all models that imitate the neural network of a living organism, determine the connection strength between neurons by learning, and have problem solving ability. The neural network has an input layer, an intermediate layer (also referred to as a hidden layer), and an output layer. A neural network having two or more intermediate layers is called a deep neural network. Learning with a deep neural network is called deep learning.

In this specification, when describing a neural network, determining the connection strength (also referred to as a weighting factor) between neurons from existing information may be referred to as “learning”.

Further, in this specification, the construction of a neural network using the connection strength obtained by learning and deriving a new conclusion therefrom may be referred to as “inference”.

(Embodiment 1)
In this embodiment, an image receiving device which is one embodiment of the present invention will be described.

FIG. 1 is a diagram illustrating an image receiving apparatus and an image receiving system including the image receiving apparatus according to an embodiment of the present invention. FIG. 1 shows an image receiving device 10, an antenna 60, a remote controller (hereinafter referred to as a remote controller) 40, and a server 50.

The image receiving device 10 is a television and has a function of generating image data from a broadcast signal received by the antenna 60 and displaying an image.

Examples of the antenna 60 include a UHF (Ultra High Frequency) antenna, a BS / 110 ° CS antenna, and a CS antenna.

The remote controller 40 transmits and receives data to and from the image receiving device 10 by means such as infrared communication. FIG. 1 shows an example in which a smartphone is used as the remote controller 40. The remote controller 40 communicates with the server 50 through an internet line or the like.

FIG. 2 is a block diagram showing a configuration example of the image receiving system shown in FIG. The image receiving device 10 includes a display panel 30 and a reception arithmetic circuit 20.

The reception arithmetic circuit 20 includes an analog front end 21, a HEVC decoder 22, an image processing circuit 23, an encoder 24, a control circuit 25, an interface (I / F) 26, and a reception unit 27.

The analog front end 21 has a function of receiving a broadcast signal input from the antenna 60.

The HEVC decoder 22 has a function of expanding the broadcast signal according to the specifications of the broadcast standard and generating image data.

The image processing circuit 23 has a function of performing image processing on the image data obtained by the expansion.

The encoder 24 has a function of extracting features from the image data subjected to the image processing and compressing the image data.

The receiving unit 27 has a function of transmitting / receiving data to / from the remote controller 40.

The control circuit 25 has a function of supplying a control signal to each circuit of the image receiving device 10. For example, the control circuit 25 has a function of supplying control signals to the image processing circuit 23, the encoder 24, and the decoder 33.

The display panel 30 includes a pixel array 31, a source driver 32, a decoder 33, a gate driver 34, and a TCON (timing controller) 35.

The decoder 33 is a decoder corresponding to the encoder 24 and has a function of restoring the above-described compressed image data.

The TCON 35 has a function of generating a timing signal for driving the source driver 32 and the gate driver 34.

In the configuration of FIG. 2, the encoder 24 and the decoder 33 constitute an auto encoder. The encoder 24 has a function of extracting features from image data using a neural network and compressing the image data. The decoder 33 has a function of restoring image data from data compressed using a neural network.

FIG. 3 shows a conceptual diagram of the auto encoder. The image data input from the image processing circuit 23 is output to the source driver 32 via the auto encoder 28 (encoder 24 and decoder 33). The output of the image processing circuit 23 is input to the auto encoder 28, and the output of the auto encoder 28 is input to the source driver 32.

The encoder 24 has a neural network composed of an input layer and a plurality of intermediate layers. The encoder 24 has a neural network in which the number of neurons decreases as the hierarchy progresses. FIG. 3 shows the number of neurons by the number of arrows connecting the respective layers. If the number of outputs of the encoder 24 is smaller than the number of neurons in the input layer, the neural network can be configured such that the number of neurons in the middle layer is larger than the number of neurons in the middle layer in the previous layer.

The decoder 33 has a neural network composed of an output layer and a plurality of intermediate layers. In contrast to the encoder 24, the decoder 33 has a neural network in which the number of neurons increases as the hierarchy progresses. If the number of inputs of the decoder 33 is smaller than the number of neurons in the output layer, the neural network can be configured such that the number of intermediate layer neurons in the middle is smaller than the number of neurons in the previous intermediate layer. .

Arithmetic processing in each layer is executed by a product-sum operation between the output of a neuron included in the previous layer and a weight coefficient. For example, if the output of the i-th neuron in the input layer is x _i and the connection strength (weight coefficient) between the output x _i and the j-th neuron in the first intermediate layer is w _ji , The output is y _j = f (Σw _ji · x _i ). Note that i and j are integers of 1 or more. Here, f (x) is an activation function, and a sigmoid function, a threshold function, or the like can be used. Similarly, the output of the neuron in each layer is a value obtained by applying the activation function to the product-sum operation result of the output of the neuron in the previous layer and the weight coefficient. The connection between layers may be a total connection in which all neurons are connected, or a partial connection in which some neurons are connected.

The number of intermediate layers in the encoder 24 and the decoder 33 is not limited, and the number of intermediate layers may be provided as necessary.

The encoder 24 performs feature extraction from the input image data in accordance with the weighting coefficient determined by learning. To explain with a simple example, in the case of triangular image data, the encoder 24 may be configured to extract the coordinates of three vertices as feature points. That is, the triangular image data is converted into three coordinate data, and the data amount is reduced.

The decoder 33 restores and outputs image data from the data extracted by the encoder 24 in accordance with the weighting coefficient determined by learning. The restored image data has the same resolution as the image data input to the encoder 24. To explain with a simple example, the decoder 33 may be configured to generate triangular image data from three coordinate data.

It is preferable that the learning is performed by a computer having a high processing capacity by installing software corresponding to the auto encoder 28 of FIG. 3 such as a dedicated server or a cloud. For example, in the case of FIG. 2, learning is preferably performed by the server 50. That is, the auto encoder 28 shown in FIG. 3 is preferably mounted on both the image receiving device 10 and the server 50.

The learning is performed by inputting learning data to the auto encoder and updating the weighting coefficient so that the output of the auto encoder becomes equal to the learning data. As the learning data, it is preferable to use a part of the image data cut out. The above learning can be performed by unsupervised learning. In the learning, a reverse error propagation method or the like can be used as a learning algorithm.

In the example of FIG. 2, learning is performed by the server 50, and the optimum weighting coefficient determined by learning is transmitted to the receiving unit 27 via the remote controller 40. The control circuit 25 sets the weight coefficient in the encoder 24 and the decoder 33. The encoder 24 and the decoder 33 can perform inference according to the set weighting factor.

In many cases, the display panel 30 and the reception arithmetic circuit 20 are electrically connected using a cable such as FPC (Flexible Printed Circuits). For example, when the image receiving apparatus 10 handles a large amount of data, such as 8K (7680 × 4320) broadcast, an FPC capable of high-speed transmission is required, but transmission is performed due to physical restrictions on the number of FPC wires. May take time. Further, as the size of the display panel 30 increases, the physical length of the cable connecting the reception arithmetic circuit 20 and the display panel 30 increases, and the transmission loss of image data increases.

With the configuration shown in FIG. 2, the image data is transmitted from the reception arithmetic circuit 20 to the display panel 30 in a compressed state (with a small data size). Therefore, the image receiving device 10 can efficiently transmit image data having a high resolution such as 8K to the display panel 30. Also, if the data size is small, the power required for transmission can be small, and the image receiving apparatus 10 can reduce power consumption.

Note that the auto encoder may change not only the weighting coefficient but also the configuration of the neural network. By acquiring configuration data that constitutes an optimal neural network in the learning, and setting the configuration data in the encoder 24 and the decoder 33, inference reflecting the learning result can be executed by the image receiving apparatus 10. The details of the semiconductor device capable of changing the configuration of the neural network will be described in a second embodiment to be described later.

In the configuration shown in FIG. 2, the weight coefficient (or configuration data) of the encoder 24 and the decoder 33 can be easily updated by the user operating the remote controller 40 even after the image receiving apparatus 10 is shipped. . That is, even after the product is shipped, the user can easily upgrade the product. Moreover, you may give the function of the remote control 40 to a smart phone. By doing so, the user can upgrade the product more easily.

Further, only a specific user may be given a right to update the weighting coefficient (or configuration data) of the image receiving apparatus 10. By doing so, it is possible to provide a service that enables the user to view a high-quality television broadcast.

Further, since the decoder 33 needs to be used as a set with the encoder 24, the weighting coefficient (or configuration data), the use of a third party can be restricted. Therefore, it is possible to prevent an act of illegally obtaining a driver IC, a display panel, or the like on which the decoder 33 is mounted and manufacturing and selling counterfeit products.

The image data input to the encoder 24 and the image data output from the decoder 33 do not necessarily have the same resolution. The image receiving device 10 may change the weighting coefficient (or configuration data) according to the content of the broadcast program. For example, the image receiving device 10 may intentionally reduce the resolution of the image data for a program such as an animation for children or a news program that the viewer does not feel dissatisfied even if the image quality is somewhat low. In that case, the resolution of the image data output from the decoder 33 is lower than that of the image data input to the encoder 24. By doing so, the image receiving apparatus 10 can reduce power consumption.

As described above, by using the configuration described in this embodiment, it is possible to provide an image receiving apparatus capable of efficiently transmitting image data or an image receiving system including the image receiving apparatus. Further, it is possible to provide an image receiving apparatus with reduced power consumption or an image receiving system including the same.

(Embodiment 2)
In this embodiment, a semiconductor device that can change the configuration of the neural network described in the above embodiment will be described.

<Semiconductor device>
FIG. 4 shows a configuration of the semiconductor device 100 capable of realizing various neural networks.

The semiconductor device 100 has a hierarchical structure including operation layers 141 [1] to 141 [N] and switch layers 142 [1] to 142 [N-1]. N is an integer of 2 or more.

The operation layer 141 [1] includes product-sum operation elements 130 [1] to 130 [S ₁ ], and the operation layer 141 [N] includes product-sum operation elements 130 [1] to 130 [S _N ]. The switch layer 142 [1] includes programmable switches 140 [1] to 140 [S ₂ ], and the switch layer 142 [N−1] includes programmable switches 140 [1] to 140 [S _N ]. S _{1 to} S _N are each an integer of 1 or more. The switch layer 142 has a function of controlling the connection between two different calculation layers 141.

The programmable switch 140 has a function of controlling connection between a plurality of product-sum operation elements 130 included in the first operation layer 141 and a product-sum operation element 130 included in the second operation layer 141. For example, in FIG. 4, the programmable switch 140 [S ₂ ] includes a sum-of-products operation 130 [1] to 130 [S ₁ ] included in the operation layer 141 [ ₁ ] and a product-sum operation included in the operation layer 141 [2]. It has a function of controlling connection with the element 130 [S ₂ ].

The hierarchical structure shown in FIG. 4 can be made to correspond to the hierarchical structure shown in FIG. In this specification, the product-sum operation element 130 may be referred to as a neuron.

<Product-sum operation element>
FIG. 5 is a block diagram illustrating a configuration example of the product-sum operation element 130. The product-sum operation element 130 includes multiplication elements 131 [1] to 131 [S] corresponding to the input signals IN [1] to IN [S], an addition element 133, an activation function element 134, and CM ( Configuration memory) 132 [1] to 132 [S] and CM 135. Note that S is an integer of 1 or more.

The multiplication element 131 has a function of multiplying the data stored in the CM 132 and the input signal IN. The CM 132 stores the weighting factor described with reference to FIG.

The adding element 133 has a function of adding all the outputs (multiplication results) of the multiplying elements 131 [1] to 131 [S].

The activation function element 134 performs an operation on the output (product-sum operation result) of the addition element 133 according to a function defined by data stored in the CM 135, and sets the output signal OUT. The function can be a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like. These functions are implemented by a table method or a broken line approximation, and the corresponding data is stored in the CM 135 as configuration data.

Note that each of the CM 132 [1: S] and the CM 135 preferably has a separate writing circuit. As a result, the data update of the CM 132 [1: S] and the data update of the CM 135 can be performed independently. That is, without updating the data of the CM 135, the data update of the CM 132 [1: S] can be repeated many times. In this way, when learning the neural network, only the updating of the weighting coefficient can be repeated many times, and learning can be performed efficiently.

《Programmable switch》
FIG. 6A is a circuit diagram illustrating a configuration of the programmable switch 140. The programmable switch 140 has a switch 160.

The programmable switch 140 has a function of transmitting output signals OUT [1] to OUT [S] as input signals IN [1] to IN [S]. For example, in FIG. 4, the programmable switch 140 [S ₂ ] includes output signals OUT [1] to OUT [S ₁ ] of the operation layer 141 [ ₁ ] and a product-sum operation element 130 [ S ₂ ] has a function of controlling connection with the input signal IN [1: S ₁ ].

The programmable switch 140 has a function of controlling connection between the signal “0” and the input signals IN [1] to IN [S] of the product-sum operation element 130.

"switch"
FIG. 6B is a circuit diagram illustrating a configuration example of the switch 160. The switch 160 includes a CM 161 and a switch 162. The switch 162 has a function of controlling electrical continuity between the output signal OUT [i] and the input signal IN [i]. The switch 162 has a function of controlling conduction between the signal “0” and the input signal IN [i]. Note that i is an integer of 1 to S. On / off of the switch 162 is controlled by configuration data stored in the CM 161. A transistor can be used as the switch 162.

When the product-sum operation element 130 does not use the output signal OUT [i] from the immediately preceding operation layer 141 as an input, the product-sum operation element 130 is supplied with the signal “0” as the input signal IN [i]. The At this time, power consumption can be reduced by stopping the supply of power to the multiplier 131 [i] corresponding to the input signal IN [i] (performing power gating). For example, in FIG. 4, when the product-sum operation element 130 [S ₂ ] included in the operation layer 141 [ ₂ ] does not use the output signal OUT [1] from the operation layer 141 [1] as an input, the product-sum operation element 130 [S ₂ ] is supplied with the signal “0” as its input signal IN [1], and stops supplying power to the multiplier 131 [1].

Further, when the output signal OUT [i] of the product-sum operation element 130 included in a certain operation layer 141 is not supplied to any product-sum operation element 130 included in another operation layer 141, the output signal OUT [i] is output. The power supply of the entire product-sum operation element 130 can be stopped, and the power consumption can be reduced. For example, in FIG. 4, when the product-sum operation element 130 [S ₁ ] included in the operation layer 141 [1] is not connected to any product-sum operation element 130 included in another operation layer 141, the product-sum operation element 130 [S ₁ ] Stop the entire power supply.

In the above configuration, the configuration memory can be configured using SRAM and MRAM. The configuration memory can also be configured by a memory using an OS transistor (hereinafter referred to as an OS memory). By using the OS memory as the configuration memory, the power consumption of the semiconductor device 100 can be significantly reduced.

For example, by configuring the CMs 132 [1] to 132 [S] and the CM 135 illustrated in FIG. 5 with OS memories, the semiconductor device 100 can configure a low power consumption network with a small number of elements.

For example, by configuring the CM 161 illustrated in FIG. 6B with an OS memory, the semiconductor device 100 can configure a low power consumption network with a small number of elements.

Further, when the multiplication element 131 and the addition element 133 are analog circuits, the number of transistors included in the product-sum operation element 130 can be reduced.

Furthermore, by making the input / output signal of the product-sum operation element 130 an analog signal, the number of wirings included in the network can be reduced.

The semiconductor device 100 in FIG. 4 can generate configuration data of the programmable switch 140 having a desired network configuration, and can learn according to the configuration data. When updating the weighting coefficient by learning, a configuration in which only the weighting coefficient configuration data is repeatedly changed without changing the configuration data of the programmable switch 140 is effective. Therefore, it is preferable that the configuration data is written to the CM 132 [1: S] included in the product-sum operation element 130 and the CM 161 included in the programmable switch 140 by different circuits.

The semiconductor device 100 can be used for the server 50 and the image receiving device 10 shown in FIG. For example, examination and learning of the hierarchical configuration of the neural network can be performed by the server 50 and inference can be performed by the image receiving apparatus 10. As a result, it is possible to provide an image receiving apparatus capable of efficiently transmitting image data or an image receiving system including the image receiving apparatus. Further, it is possible to provide an image receiving apparatus with reduced power consumption or an image receiving system including the same.

(Embodiment 3)
In this embodiment, details of the display panel 30 described in the above embodiment will be described.

"Block Diagram"
FIG. 7A is a block diagram for explaining the structure of the display panel 30. The display panel 30 includes a pixel array 31, a gate driver 34a, a gate driver 34b, and a source driver 32. In FIG. 7A, the gate drivers 34 a and 34 b are respectively provided on the left and right of the pixel array 31.

Further, the display panel 30 is arranged substantially in parallel with each other, and the plurality of scanning lines GL whose potentials are controlled by the gate drivers 34 a and 34 b, and each of the display panels 30 are arranged substantially in parallel with each other, and the source driver 32. A plurality of signal lines SL whose potentials are controlled by. Further, the pixel array 31 has a plurality of pixels 36 arranged in a matrix.

In the pixel array 31, each scanning line GL is electrically connected to a plurality of pixels 36 arranged in any row. Each signal line SL is electrically connected to a plurality of pixels 36 arranged in any column.

The transistors included in the gate drivers 34a and 34b and the source driver 32 (hereinafter collectively referred to as a driver circuit) can be formed at the same time as the transistors included in the pixel 36.

Alternatively, part or all of the driver circuit may be formed over another substrate and electrically connected to the display panel 30. For example, part or all of the driver circuit may be formed using an IC chip using a single crystal substrate, and the IC chip may be electrically connected to the display panel 30. The number of IC chips is not limited to one, and a necessary number may be provided according to the number of pixels 36. For example, the IC chip can be provided on the display panel 30 by using a COG (Chip on Glass) method or a COF (Chip on Film) method.

In FIG. 7B, the pixel array 31 of FIG. 7A is divided into four pixel arrays 31a, 31b, 31c, and 31d, and the source driver 32 is divided into two source drivers 32a and 32b. An example is shown in which the array is arranged above and below the array. The pixels 36 included in the pixel arrays 31a and 31b are electrically connected to the source driver 32a through the signal line SLa. The pixels 36 included in the pixel arrays 31c and 31d are electrically connected to the source driver 32b through the signal line SLb. Note that the number of divisions of the pixel array 31 is not limited to four, and any number of divisions may be performed.

The structure illustrated in FIG. 7B can reduce the number of pixels 36 connected to one signal line. That is, the capacity connected to one signal line can be reduced. As a result, the display panel 30 can shorten the time for writing image data to the signal lines. The structure illustrated in FIG. 7B is particularly preferably applied to a high-definition display panel such as 8K (number of pixels: 7680 × 4320). For example, by applying a pixel array having 4K pixels (3840 × 2160) to the pixel arrays 31a to 31d, the display panel 30 having 8K pixels can be realized.

FIG. 8A shows an example in which each signal line SL in FIG. 7A is divided into two signal lines SL1 and SL2. The plurality of pixels 36 arranged in the same column are electrically connected alternately with the signal line SL1 or the signal line SL2.

The structure illustrated in FIG. 8A can reduce the number of pixels 36 connected to one signal line. As a result, the display panel 30 can shorten the time for writing image data to the signal lines.

In the structure shown in FIG. 7B, a joint is generated between the pixel arrays, and the influence appears in the display image. However, the structure shown in FIG. 8A has no joint. Therefore, the above problem can be avoided. As a result, the display panel 30 can display a seamless smooth image.

Note that the number of dividing the signal line SL is not limited to two. FIG. 8B illustrates an example in which each signal line SL in FIG. 7A is divided into four signal lines SL1, SL2, SL3, and SL4.

When the display panel 30 has the structure illustrated in FIG. 8B, the number of pixels 36 connected to one signal line can be further reduced. As a result, the display panel 30 can further reduce the time for writing image data to the signal line. In addition, a smooth image without a joint can be displayed.

<Pixel circuit>
Next, a circuit configuration that can be used for the above-described pixel 36 will be described with reference to FIG.

A pixel 36 illustrated in FIG. 9A includes a transistor 3431, a capacitor 3233, and a liquid crystal element 3432.

One of a source electrode and a drain electrode of the transistor 3431 is electrically connected to the signal line SL, and the other is electrically connected to a node 3436. A gate electrode of the transistor 3431 is electrically connected to the scan line GL. The transistor 3431 has a function of controlling writing of a data signal to the node 3436.

One of the pair of electrodes of the capacitor 3233 is electrically connected to a wiring to which a specific potential is supplied (hereinafter also referred to as “capacitor line CL”), and the other is electrically connected to a node 3436. . The potential of the capacitor line CL is appropriately set according to the specification of the pixel 36. The capacitor 3233 has a function of holding data written to the node 3436.

One of the pair of electrodes of the liquid crystal element 3432 is supplied with a common potential (common potential), and the other is electrically connected to the node 3436. The alignment state of the liquid crystal included in the liquid crystal element 3432 is determined by data written to the node 3436.

As modes of the liquid crystal element 3432, for example, a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric ALC). Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, or TBA (Transverse Bend) Or the like may be used lignment) mode. Other examples include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest host mode. However, the present invention is not limited to this, and various modes can be used.

A pixel 36 illustrated in FIG. 9B includes a transistor 3431, a capacitor 3233, a transistor 3232, and a light-emitting element 3125.

One of a source electrode and a drain electrode of the transistor 3431 is electrically connected to a signal line SL to which a data signal is supplied, and the other is electrically connected to a node 3435. A gate electrode of the transistor 3431 is electrically connected to a scan line GL to which a gate signal is supplied. The transistor 3431 has a function of controlling writing of a data signal to the node 3435.

One of the pair of electrodes of the capacitor 3233 is electrically connected to the node 3435 and the other is electrically connected to the node 3437. The capacitor 3233 functions as a storage capacitor that stores data written to the node 3435.

One of a source electrode and a drain electrode of the transistor 3232 is electrically connected to the potential supply line VL_a, and the other is electrically connected to a node 3437. A gate electrode of the transistor 3232 is electrically connected to the node 3435. The transistor 3232 has a function of controlling current flowing to the light-emitting element 3125.

One of an anode and a cathode of the light-emitting element 3125 is electrically connected to the potential supply line VL_b, and the other is electrically connected to a node 3437.

As the light-emitting element 3125, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 3125 is not limited thereto, and an inorganic EL element made of an inorganic material may be used, for example.

For example, the potential supply line VL_a has a function of supplying V _DD . The potential supply line VL_b has a function of supplying a _{V SS.}

<Cross section>
Next, a configuration example of the display panel 30 will be described using the cross-sectional views of FIGS. 10 and 11.

10A and 10B includes an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019. The display panel 30 illustrated in FIGS. The electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110. The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030.

The pixel 36 provided over the first substrate 4001 includes a transistor. FIG. 10A illustrates a transistor 3431 included in the pixel 36, and FIG. 10B illustrates the pixel 36. The included transistor 3232 is illustrated.

In addition, the transistors 3431 and 3232 are provided over the insulating layer 4102. The transistors 3431 and 3232 each include an electrode 517 formed over the insulating layer 4102, and the insulating layer 4103 is formed over the electrode 517. A semiconductor layer 512 is formed over the insulating layer 4103. An electrode 510 and an electrode 511 are formed over the semiconductor layer 512, an insulating layer 4110 and an insulating layer 4111 are formed over the electrode 510 and the electrode 511, and an electrode 516 is formed over the insulating layer 4110 and the insulating layer 4111. The electrode 510 and the electrode 511 are formed using the same conductive layer as the wiring 4014.

In each of the transistors 3431 and 3232, the electrode 517 functions as a gate electrode, the electrode 510 functions as one of a source electrode and a drain electrode, and the electrode 511 functions as the other of the source electrode and the drain electrode. The electrode 516 functions as a back gate electrode.

Each of the transistors 3431 and 3232 has a bottom-gate structure and has a back gate, whereby the on-state current can be increased. In addition, the threshold value of the transistor can be controlled. Note that the electrode 516 may be omitted in some cases in order to simplify the manufacturing process.

In each of the transistors 3431 and 3232, the semiconductor layer 512 functions as a channel formation region. As the semiconductor layer 512, crystalline silicon, polycrystalline silicon, amorphous silicon, metal oxide, an organic semiconductor, or the like may be used. Further, an impurity may be introduced into the semiconductor layer 512 as needed in order to increase the conductivity of the semiconductor layer 512 or to control the threshold value of the transistor.

In the case where a metal oxide is used for the semiconductor layer 512, the semiconductor layer 512 preferably contains indium (In). In the case where the semiconductor layer 512 is a metal oxide containing indium, the semiconductor layer 512 has high carrier mobility (electron mobility). Further, the semiconductor layer 512 is preferably a metal oxide containing the element M. The element M is preferably aluminum (Al), gallium (Ga), tin (Sn), or the like. Other elements applicable to the element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), yttrium (Y), zirconium (Zr ), Molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), and the like. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. The element M is an element whose binding energy with oxygen is higher than that of indium, for example. Further, the semiconductor layer 512 is preferably a metal oxide containing zinc (Zn). A metal oxide containing zinc may be easily crystallized.

The semiconductor layer 512 is not limited to a metal oxide containing indium. The semiconductor layer 512 may be a metal oxide that does not contain indium, such as zinc tin oxide and gallium tin oxide, and contains at least one of zinc, gallium, and tin.

10A and 10B includes a capacitor 3233. The display panel 30 illustrated in FIGS. The capacitor 3233 has a region where the electrode 511 and the electrode 4021 overlap with each other with the insulating layer 4103 interposed therebetween. The electrode 4021 is formed using the same conductive layer as the electrode 517.

FIG. 10A illustrates an example of a liquid crystal display panel using a liquid crystal element as a display element. 10A, a liquid crystal element 3432 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 interposed therebetween.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Yes. A spherical spacer may be used.

There is no particular limitation on materials used for the first substrate 4001 and the second substrate 4006. Depending on the purpose, it may be determined in consideration of the presence or absence of translucency and heat resistance enough to withstand heat treatment. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Further, as the first substrate 4001 and the second substrate 4006, a semiconductor substrate, a flexible substrate (flexible substrate), a bonded film, a base film, or the like may be used, respectively.

Examples of the semiconductor substrate include an elemental semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. is there. The semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

Examples of materials such as a flexible substrate, a laminated film, and a base film include polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polytetrafluoroethylene (PTFE), and polypropylene. Polyester, polyvinyl fluoride, polyvinyl chloride, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, aramid, epoxy resin, acrylic resin, and the like can be used.

By using such a material as the substrate, a lightweight display panel can be provided. In addition, by using such a material as the substrate, a display panel that is resistant to impact can be provided. Further, by using such a material for the substrate, a display panel which is not easily damaged can be provided.

The flexible substrate used for the first substrate 4001 and the second substrate 4006 is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed. The flexible substrate used for the first substrate 4001 and the second substrate 4006 has a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ /, for example. A material that is K or less may be used. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a flexible substrate.

The insulating layers such as the insulating layer 4102, the insulating layer 4103, the insulating layer 4110, and the insulating layer 4111 include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, and oxide A material selected from silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, and the like can be formed as a single layer or stacked layers. Alternatively, a material obtained by mixing a plurality of materials selected from oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

Note that in this specification, a nitrided oxide refers to a compound having a higher nitrogen content than oxygen. Further, oxynitride refers to a compound having a higher oxygen content than nitrogen. In addition, content of each element can be measured using Rutherford backscattering method (RBS: Rutherford Backscattering Spectrometry) etc., for example.

In particular, the insulating layer 4102 and the insulating layer 4111 are preferably formed using an insulating material which does not easily transmit impurities. For example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer, or What is necessary is just to use it by lamination | stacking. For example, as an insulating material that hardly permeates impurities, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples thereof include silicon nitride. Alternatively, the insulating layer 4102 or the insulating layer 4111 may be formed using indium tin zinc oxide (In—Sn—Zn oxide) with high insulating properties or the like.

By using an insulating material that does not easily transmit impurities for the insulating layer 4102, diffusion of impurities from the first substrate 4001 side can be suppressed and the reliability of the transistor can be improved. By using an insulating material that does not easily transmit impurities for the insulating layer 4111, diffusion of impurities from the insulating layer 4112 side can be suppressed, and the reliability of the transistor can be improved.

The insulating layer 4112 is an insulating layer having a flat surface. As the insulating layer 4112, an organic material having heat resistance such as polyimide, acrylic resin, benzocyclobutene-based resin, polyamide, or epoxy resin can be used in addition to the above insulating material. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that a plurality of insulating layers formed using these materials may be stacked.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may have an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. The organic group may have a fluoro group.

Further, chemical mechanical polishing (CMP) treatment may be performed on the surface of the insulating layer or the like. By performing the CMP treatment, unevenness on the surface of the sample can be reduced, and the coverage of the insulating layer and the conductive layer to be formed thereafter can be improved.

As a material for forming a conductive layer such as the first electrode layer 4030, the second electrode layer 4031, the wiring 4014, the electrode 4015, the electrode 4021, the electrode 510, the electrode 511, the electrode 516, and the electrode 517, aluminum, Use of a material containing one or more metal elements selected from chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and the like. it can. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus may be used. Alternatively, an oxide semiconductor with high electrical conductivity or a nitride semiconductor with high electrical conductivity may be used. Alternatively, silicide such as nickel silicide may be used. A plurality of conductive layers formed using these materials may be stacked.

In addition, as a conductive material for forming a conductive layer, indium tin oxide (ITO: Indium Tin Oxide), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide It is also possible to apply a conductive material containing oxygen such as indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, or a conductive material containing nitrogen such as titanium nitride or tantalum nitride. it can. In addition, the conductive layer can have a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined. The conductive layer can also have a stacked structure in which the above-described material containing a metal element is combined with a conductive material containing nitrogen. In addition, the conductive layer can have a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

In the display panel 30 illustrated in FIG. 10A, at least one of the first electrode layer 4030 and the second electrode layer 4031 is preferably formed using a light-transmitting conductive material.

In the case where a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used as the liquid crystal layer 4008. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

The specific resistance of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. In addition, the value of the specific resistance in this specification shall be the value measured at 20 degreeC.

In the case where an OS transistor is used as the transistor 3431, the transistor 3431 can reduce current in an off state (off-state current). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

In the display panel, an optical member (optical substrate) such as a black matrix (light shielding layer), a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

FIG. 10B illustrates an example of a display panel using a light-emitting element such as an EL element as a display element. EL elements are classified into organic EL elements and inorganic EL elements.

In the organic EL element, by applying a voltage, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element. Note that in addition to the light-emitting compound, the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar layer. Material (a material having a high electron transporting property and a high hole transporting property) may be included. The EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions.

FIG. 10B illustrates an example in which an organic EL element is used as the light-emitting element 3125.

In FIG. 10B, the light-emitting element 3125 is electrically connected to a transistor 3232 provided in the pixel 36. Note that the structure of the light-emitting element 3125 is a stacked structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031; however, the structure is not limited to this structure. The structure of the light-emitting element 3125 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 3125, or the like.

A partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, a photosensitive resin material is used, an opening is formed on the first electrode layer 4030, and the partition wall 4510 is formed so that a side surface of the opening is an inclined surface formed with a continuous curvature. Is preferred.

The light emitting layer 4511 may be composed of a single layer or a plurality of stacked layers.

A protective layer may be formed over the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 3125. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be used. In addition, a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and sealed. As described above, it is preferable to package (seal) with a protective film (bonded film, ultraviolet curable resin film, or the like) or a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.

As the filler 4514, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Further, the filler 4514 may contain a desiccant.

As the sealant 4005, a glass material such as glass frit, or a resin material such as a two-component mixed resin, a curable resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.

If necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting surface of the light emitting element. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, when the light-emitting element has a microcavity structure, light with high color purity can be extracted. Further, by combining the microcavity structure and the color filter, the reflection can be reduced and the visibility of the display image can be improved.

The first electrode layer 4030 and the second electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. It can be formed using a light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.

The first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) and other metals, or alloys thereof, or One or more metal nitrides can be used.

The first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In order to extract light from the light-emitting element 3125 to the outside, at least one of the first electrode layer 4030 and the second electrode layer 4031 only needs to be transparent. Display panels are classified into a top emission (top emission) structure, a bottom emission (bottom emission) structure, and a double emission (dual emission) structure depending on how light is extracted. The top emission structure refers to a case where light is extracted from the second substrate 4006. The bottom emission structure refers to a case where light is extracted from the first substrate 4001. The dual emission structure refers to a case where light is extracted from both the second substrate 4006 and the first substrate 4001. For example, in the case of a top emission structure, the second electrode layer 4031 may be transparent. For example, in the case of a bottom emission structure, the first electrode layer 4030 may be transparent. For example, in the case of a dual emission structure, the first electrode layer 4030 and the second electrode layer 4031 may be transparent.

FIG. 11A illustrates a cross-sectional view in the case where a top-gate transistor is provided in the transistor 3431 illustrated in FIG. Similarly, FIG. 11B illustrates a cross-sectional view in the case where a top-gate transistor is provided in the transistor 3232 illustrated in FIG.

In each of the transistors 3431 and 3232 in FIGS. 11A and 11B, the electrode 517 has a function as a gate electrode, the electrode 510 has a function as one of a source electrode and a drain electrode, and the electrode 511 has It functions as the other of the source electrode and the drain electrode.

11A and 11B, the description of FIGS. 10A and 10B may be referred to.

In this specification, unless otherwise specified, on-state current refers to drain current when a transistor is in an on state. The ON state (sometimes abbreviated as ON) is a state where the voltage between the gate and the source (V _G ) is equal to or higher than the threshold voltage (V _th ) in an n-channel transistor, unless otherwise specified, p In a channel type transistor, V _G is a state of V _th or less. For example, the on-current of the n-channel transistor, V _G refers to a drain current when the above V _th. In addition, the on-state current of the transistor may depend on a voltage (V _D ) between the drain and the source.

In this specification, unless otherwise specified, off-state current refers to drain current when a transistor is off. The OFF state (sometimes referred to as OFF), unless otherwise specified, the n-channel type transistor, V _G is lower than V _th state, the p-channel type transistor, V _G is higher than V _th state Say. For example, the off-current of the n-channel transistor, refers to the drain current when V _G is lower than V _th. Off-state current of the transistor may be dependent on the V _G. Accordingly, the off current of the transistor is less than ^{10 -21} A, and may refer to the value of _{V G} to off-current of the transistor is less than ^{10 -21} A are present.

In addition, the off-state current of the transistor may depend on V _D. In this specification, unless otherwise specified, the off-state current is such that the absolute value of V _D is 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V , 12V, 16V, or 20V may be represented. Alternatively, the off current may represent an off current in V _D used in a semiconductor device or the like including the transistor.

In this specification and the like, when describing the connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is indicated as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode.

In this specification and the like, when X and Y are explicitly described as being connected, X and Y are electrically connected and X and Y are directly connected. It is assumed that this is disclosed in this specification and the like.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) This is a case where X and Y are connected without passing through an element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

GL scanning line SL signal line SL1 signal line SL2 signal line SL3 signal line SL4 signal line SLa signal line SLb signal line 10 image receiving device 20 reception arithmetic circuit 21 analog front end 22 HEVC decoder 23 image processing circuit 24 encoder 25 control circuit 26 interface 27 Receiver 28 Auto encoder 30 Display panel 31 Pixel array 31a Pixel array 31b Pixel array 31c Pixel array 31d Pixel array 32 Source driver 32a Source driver 32b Source driver 33 Decoder 34 Gate driver 34a Gate driver 34b Gate driver 35 TCON
36 pixels 40 remote control 50 server 60 antenna 100 semiconductor device 130 product-sum operation element 131 multiplication element 132 CM
133 Addition element 134 Activation function element 135 CM
140 Programmable switch 141 Operation layer 142 Switch layer 160 Switch 161 CM
162 Switch 510 Electrode 511 Electrode 512 Semiconductor layer 516 Electrode 517 Electrode 3125 Light emitting element 3232 Transistor 3233 Capacitor 3431 Transistor 3432 Liquid crystal element 3435 Node 3436 Node 3437 Node 4001 Substrate 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4014 Wiring 4015 Electrode 4018 FPC
4019 Anisotropic conductive layer 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4102 Insulating layer 4103 Insulating layer 4110 Insulating layer 4111 Insulating layer 4112 Insulating layer 4510 Partition 4511 Light emitting layer 4514 Filler

Claims (7)

A display panel;
A first decoder;
An encoder, and
The display panel includes a second decoder;
The encoder and the second decoder constitute an auto encoder,
The first decoder generates first image data from a broadcast signal;
The first image data is input to the encoder;
The second decoder outputs second image data;
The image receiving apparatus, wherein the display panel displays the second image data. In claim 1,
The image receiving apparatus according to claim 1, wherein the first image data and the second image data have the same resolution. In claim 1,
The encoder has a first neural network;
The first neural network includes an input layer and a first intermediate layer,
The second decoder comprises a second neural network;
The second neural network includes an output layer and a second intermediate layer,
The input layer and the output layer each have N neurons,
The first intermediate layer and the second intermediate layer each have M neurons;
An image receiving apparatus, wherein N is an integer greater than M. Server,
A display panel;
A first decoder;
An encoder, and
The display panel includes a second decoder;
The encoder and the second decoder constitute an auto encoder,
The first decoder generates first image data from a broadcast signal;
The first image data is input to the encoder;
The second decoder outputs second image data;
The display panel displays the second image data;
The image receiving system, wherein the server determines a weighting coefficient of the auto encoder. Server,
A remote controller,
A display panel;
A first decoder;
An encoder, and
The display panel includes a second decoder;
The encoder and the second decoder constitute an auto encoder,
The first decoder generates first image data from a broadcast signal;
The first image data is input to the encoder;
The second decoder outputs second image data;
The display panel displays the second image data;
The image receiving system, wherein the weighting coefficient is transmitted from the server to the encoder and the second decoder via the remote controller. In claim 5,
The image receiving system, wherein the remote controller is a smartphone. In any one of Claims 4 thru | or 6,
The image receiving system, wherein the first image data and the second image data have the same resolution.

Images