WO2018125082A1

WO2018125082A1 - Ge-rich transistors employing si-rich source/drain contact resistance reducing layer

Info

Publication number: WO2018125082A1
Application number: PCT/US2016/068886
Authority: WO
Inventors: Glenn A. Glass; Anand S. Murthy; Karthik JAMBUNATHAN; Scott J. MADDOX; Tahir Ghani
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2016-12-28
Filing date: 2016-12-28
Publication date: 2018-07-05
Anticipated expiration: 2019-06-28

Abstract

Techniques are disclosed for forming transistors for forming Ge-rich transistors employing a Si-rich source/drain (S/D) contact resistance reducing layer. As can be understood based on this disclosure, the Si-rich layer may be utilized at a given S/D-contact interface to improve contact resistance, as Si-rich material (e.g., Si or SiGe with less than 50% Ge concentration by atomic percentage) can be more heavily doped than Ge-rich material (e.g., Ge or SiGe with greater than 50% Ge concentration by atomic percentage). The techniques may include forming the Si-rich layer on {111} faceting of a given Ge-rich S/D region, as such faceting provides enhanced density of states (DOS) overlap between the materials. The techniques may include employing an etch stop layer to either preserve the Si-rich layer during contact trench etch processing or to preserve the S/D {111} faceting to allow formation of the Si-rich layer thereon through the contact trench.

Description

GE- ICH TRANSISTORS EMPLOYING SI-RICH

SOURCE/DRAIN CONTACT RESISTANCE REDUCING LAYER

BACKGROUND

Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, such as silicon, germanium, and gallium arsenide. A field-effect transistor (FET) is a semiconductor device that includes three terminals: a gate, a source, and a drain. A FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. In instances where the charge carriers are electrons, the FET is referred to as an n-channel device, and in instances where the charge carriers are holes, the FET is referred to as a p-channel device. Some FETs have a fourth terminal called the body or substrate, which can be used to bias the transistor. In addition, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric layer between the gate and the channel. MOSFETs may also be known as metal- insulator-semiconductor FETs (MISFETSs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFET (p-MOS) and n-channel MOSFET (n-MOS) to implement logic gates and other digital circuits.

A FinFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin). The conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin). A nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire. BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1A-B illustrate methods of forming an integrated circuit (IC) including one or more germanium (Ge)-rich transistors employing a silicon (Si)-rich source/drain (S/D) contact resistance reducing layer, in accordance with some embodiments of the present disclosure.

Figures 2A-M illustrate example IC structures that are formed when carrying out the method of Figure 1A, in accordance with some embodiments.

Figure 2L' is a blown-out portion of Figure 2L, illustrating a variation that may occur as method 100A is performed, in accordance with some embodiments.

Figures 3A-E illustrate example IC structures, continuing from the example IC structure of Figure 2H, when carrying out the method 100B of Figure IB, in accordance with some embodiments.

Figures 4A-B illustrate example cross-sectional views along the planes A-A and B-B in Figures 2M and 3E, respectively, in accordance with some embodiments.

Figure 5 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.

These and other features of the present embodiments will be understood better by reading the following detailed description, taken together with the figures herein described. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Furthermore, as will be appreciated, the figures are not necessarily drawn to scale or intended to limit the described embodiments to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Further still, some of the features in the drawings may include a patterned and/or shaded fill, which is primarily provided to assist in visually differentiating the different features. In short, the figures are provided merely to show example structures. DETAILED DESCRIPTION

To improve upon state-of-the-art transistor performance (e.g., for MOSFET devices), in some cases, it is desirable to replace silicon (Si) and silicon germanium (SiGe) (including relatively low Ge concentrations, by atomic percentage) channel regions with germanium (Ge)- rich materials (e.g., including greater than 50% Ge concentration by atomic percentage), such as Ge or SiGe (including relatively high Ge concentrations, by atomic percentage). However, such material replacements cause non-trivial issues. One such problem that prevents manufacturing Ge-rich channel transistors is that n-type Ge-rich material has very poor contact properties to all metal materials used for source/drain (S/D) contacts. For instance, the energy barrier between Ge-rich material and contact metal may be on the order of the entire Ge bandgap of approximately 0.66eV. Such high S/D contact resistance causes significant performance degradation and may render the transistor device practically unusable, particularly as transistor devices are being scaled down to include smaller critical dimensions (e.g., devices including sub- 50 nm gate lengths).

Thus, and in accordance with one or more embodiments of the present disclosure, techniques are provided for forming Ge-rich transistors employing a Si-rich source/drain (S/D) contact resistance reducing layer. The Si-rich layer described herein may be referred to as a cladding layer, a cap layer, and/or an intervening layer, as it may be formed on one or more S/D regions (and between the one or more S/D regions and corresponding S/D contacts). As can be understood based on this disclosure, the Si-rich layer may be utilized at one or more S/D-contact interfaces to improve contact resistance, as Si-rich material (e.g., Si or SiGe with less than 50% Ge concentration by atomic percentage) can be more heavily doped relative to Ge-rich material (e.g., Ge or SiGe with greater than 50% Ge concentration by atomic percentage). However, such a Si-rich layer may improve or degrade contact properties depending on the morphology of the Ge-rich S/D. For instance, flat-topped S/D regions (e.g., where the flat-top surface includes (001) faceting) may be degraded by the introduction of a Si-rich layer at the contact location (on that flat-top surface) due to the density of states (DOS) overlap for such a structure being poor for in-plane and out-of-plane current flow directions, thereby causing a relatively large and undesired resistance barrier. However, as will be apparent in light of this disclosure, the techniques described herein can be used to form the Si-rich layer on at least one { 111 } faceted surface of a three-dimensional (e.g., fin-shaped) Ge-rich S/D region to improve contact properties due to the presence of a relatively improved DOS overlap for such a structure (e.g., relatively improved as compared to a flat-top or (001) faceted surface). The relatively improved DOS thereby reduces the resistance barrier between the material features and enables the Si-rich layer to improve contact resistance for the Ge-rich S/D, in accordance with some embodiments. For example, in some such embodiments, use of the Si-rich cladding layer can improve S/D contact resistance by at least two times (or, in other words, the Si-rich cladding layer can lower the contact resistance at that location by at least half). In some embodiments, the Si-rich layer may be formed either before or after S/D contact trench etch processing. For example, in embodiments where the Si-rich layer is formed before S/D contact trench etch processing, the Si-rich layer may be formed on at least one { 111 } faceted surface of a Ge-rich S/D region after the region has been formed. Further, in embodiments where the Si-rich layer is formed after S/D contact trench etch processing, the Si-rich layer may be formed on at least one { 111 } faceted surface of a replacement Ge-rich S/D region through the S/D contact trench. Regardless, in some embodiments, an etch stop layer (e.g., a carbon-based etch stop layer) may be employed to preserve the Si-rich layer and/or the Ge-rich S/D region { 111 } faceting. For example, in embodiments where the Si-rich layer is formed prior to S/D contact trench etch processing, the etch stop layer may be formed over the Si-rich layer (e.g., prior to the formation of overlying interlayer dielectric (ILD) material) to prevent or minimize that Si-rich layer from being consumed or otherwise adversely affected during the S/D contact trench etch processing. Further, in embodiments, where the Si-rich layer is formed after S/D contact trench etch processing (e.g., via through contact trench processing), the etch stop layer may be formed on the Ge-rich S/D region to prevent or minimize the Ge-rich S/D region { 111 } faceting from being consumed or otherwise adversely affected during the S/D contact trench etch processing. In other words, in some embodiments, the etch stop layer may enable the effective formation and/or preservation of a Si-rich layer on { 111 } faceting of a Ge-rich S/D region, as can be understood based on this disclosure.

In embodiments employing an etch stop layer, the etch stop layer may include any suitable material, such as non-carbon semiconductor material (e.g., group IV semiconductor material) alloyed with carbon (C), which may be referred to herein as "Z:C", where Z is the non-carbon semiconductor material. For instance, in some such embodiments, the etch stop layer may include Si alloyed with C, which may be represented as Si:C. In embodiments where the etch stop layer includes C, the included C concentration (by atomic percentage) may be in the range of 1-80% (or in a suitable subrange, such as in the subrange of 1-2, 1-5, 1-10, 1-20, 1-40, 1-60, 2-5, 2-10, 2-20, 2-50, 2-80, 5-10, 5-20, 5-50, 5-80, 10-20, 10-50, 10-80, 20-50, 20-80, or 50- 80%), or some other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the carbon-based etch stop layer may be formed to have a thickness in the range of 1-20 nm (e.g., in the subrange of 1-2, 1-5, 1-10, 2-5, 2-10, 2-20, 5-10, 5-20, or 10-20 nm), or some other suitable thickness as will be apparent in light of this disclosure. In some embodiments, the thickness and C concentration (by atomic percentage) may be inversely related, such that if a relatively thicker carbon-based etch stop layer is employed (e.g., with a thickness of at least 8, 10, 12, or 15 nm, such as having a thickness in the range of 8-20 nm), then relatively lower C concentration may be used to ensure the etch stop layer is adequately robust/resilient enough to effectively function (e.g., C concentration in the range of 1-5%). Further, in some such embodiments, if a relatively thinner carbon-based etch stop layer is employed (e.g., with a thickness less than 5, 3, or 2 nm, such as having a thickness in the range of 1-2 nm), then relatively higher C concentration may be used to ensure that the etch stop layer is robust/resilient enough to effectively function (e.g., C concentration in the range of 20-50%). Numerous variations and configurations for the etch stop layer, where employed, will be apparent in light of this disclosure.

In some embodiments, a given Ge-rich channel or S/D region may include Ge, SiGe, and/or any other suitable material as will be apparent in light of this disclosure. Further, in some embodiments, a given Ge-rich channel or S/D region may include any suitable Ge concentration (by atomic percentage), such as Ge in the range of 50-100%) (or in any suitable subrange, such as in the subrange of 50-60, 50-70, 50-80, 50-90, 60-70, 60-80, 60-90, 60-100, 70-80, 70-90, 70- 100, 80-90, 80-100, or 90-100%>), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, a given Ge-rich channel or S/D region may include a Ge concentration (by atomic percentage) of at least 50, 55, 60, 65, 70, 75, 80, 85, 90, or 95%, for example. In some embodiments, for a given transistor device, the channel region and at least one S/D region may include similar Ge concentrations (by atomic percentage), such that their Ge concentrations are within 1, 2, 3, 4, 5, or 10%>, for example; however, the present disclosure is not intended to be so limited unless otherwise stated. In some embodiments, a given Ge-rich channel region may be intrinsic/undoped (or nominally undoped, with a dopant concentration of less than 1E16 atoms per cubic cm) or include any suitable dopant type (e.g., n-type or p-type) and dopant concentration (e.g., in the range of 1E17-5E22 atoms per cubic cm). In some embodiments, a given Ge-rich S/D region may include any suitable doping type (e.g., n-type or p-type) and dopant concentration (e.g., in the range of 1E17-5E22 atoms per cubic cm), as will be apparent in light of this disclosure. For instance, in some embodiments, the Si-rich layer may be used to improve contact resistance for n-type doped S/D regions of an n-channel MOSFET (n- MOS) device, where the channel includes a p-type doped Ge-rich channel region, to provide an example device. However, the present disclosure is not intended to be so limited unless otherwise stated. For example, the techniques described herein may be used to benefit a multitude of transistor devices including transistors including at least one p-type doped S/D region, an n-type doped channel region, an intrinsic/undoped (or nominally undoped) channel region, and/or any other suitable variations, as will be apparent in light of this disclosure. In some embodiments, the Si-rich layer (formed on at least one Ge-rich S/D region) may include Si, SiGe, and/or any other suitable material as will be apparent in light of this disclosure. Further, in some embodiments, the Si-rich layer may include any suitable Si concentration (by atomic percentage), such as Si in the range of 50-100% (or in any suitable subrange, such as in the subrange of 50-60, 50-70, 50-80, 50-90, 60-70, 60-80, 60-90, 60-100, 70-80, 70-90, 70-100, 80-90, 80-100, or 90-100%), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the Si-rich layer may include a Si concentration (by atomic percentage) of at least 50, 55, 60, 65, 70, 75, 80, 85, 90, or 95%, for example. In some embodiments, the Si-rich layer may include any suitable doping type (e.g., n-type or p-type) and dopant concentration (e.g., in the range of 1E17-5E22 atoms per cubic cm), as will be apparent in light of this disclosure. For instance, in some embodiments, the Si-rich layer may be used to improve contact resistance for n-type doped S/D regions of an n-channel MOSFET (n-MOS) device, where the Si-rich layer is also formed on the n-type doped S/D regions and includes n- type doping, to provide an example device. Further, in some such embodiments, the Si-rich layer may be relatively heavily doped, and in some cases, degenerately doped with a concentration of at least 1E19, 1E20, 1E21, or 1E22 atoms per cubic centimeter (cm), which can help reduce contact resistance, as can be understood based on this disclosure. As previously described, Si-rich material (such as Si or SiGe with greater than 50% Si content) can be effectively doped at relatively higher concentrations compared to Ge-rich material (such as Ge or SiGe with greater than 50% Ge content). Thus, in some embodiments, the Si-rich layer may include a higher dopant concentration relative to an underlying Ge-rich S/D region in the amount of at least 1E17, 5E17, 1E18, 5E18, 1E19, 5E19, 1E20, 5E20, or 1E21 atoms per cubic cm greater dopant concentration, or some other suitable threshold relative value as will be apparent in light of this disclosure.

In some embodiments, the techniques may be used to improve contact resistance for any transistor including at least one Ge-rich S/D region including { 111 } faceting, as will be apparent in light of this disclosure. As is known in the art, the Miller index (111) is a notation in crystallography for planes in crystal lattices. The notation { 111 } denotes the set of all planes that are equivalent to Miller index (111), by the symmetry of the lattice. In some embodiments, a Ge-rich S/D region including { 111 } faceting may be formed by re-growing the S/D region from a finned structure. In some such embodiments, by maintaining relatively high/good quality crystal material during the growth (e.g., keeping the interfaces/surface clean), then such a Ge- rich S/D region including { 111 } faceting can be achieved via any suitable deposition technique (e.g., CVD, MOCVD, PVD, MBE). In some embodiments, a { 111 } faceted surface of a Ge-rich S/D region may be represented by that surface including an angle of approximately 54.7 degrees (plus/minus 5 degrees) relative to the (001) plane, the main plane of the substrate, the top plane of the substrate, and/or the top plane of STI material, for example. As can be understood based on this disclosure, { 111 } faceted Ge-rich material most closely matches the DOS overlap of Si- rich material, such that the intervening Si-rich layer described herein (formed between an S/D region and its corresponding contact) can be used to minimize contact resistance for a S/D region employing such a scheme. Note that in some embodiments, a final S/D region including { 111 } faceting may not include a top surface(s) with 100% { 111 } faceting, such that, in some embodiments, only up to 60, 65, 70, 75, 80, 85, 90, or 95% of the top surface(s) (by contact area) of the final S/D region is { 111 } faceted. The reduction or attenuation in top surface { 111 } faceting of a given S/D region may be due to the shape of the given S/D region as originally formed and/or due to subsequent processing after the given S/D region is formed (e.g., contact trench etch processing). Regardless, even where a Si-rich layer as described herein is only between a given S/D region and its corresponding contact in a small surface area (e.g., only between at most 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, or 80% of the total overlapping surface area of the two features), the Si-rich layer can still provide contact resistance reducing benefits compared to similar structures lacking the Si-rich layer, as can be understood based on this disclosure.

In some embodiments, the techniques can be used to benefit a multitude of transistor devices. For instance, in some embodiments, the techniques may be used to benefit metal-oxide- semiconductor field-effect transistors (MOSFETs), tunnel FETs (TFETs), fermi-filter FETs (FFFETs), and/or any other suitable transistor device, as can be understood based on this disclosure. For example, the techniques may be used to benefit both n-type S/D regions of an n- channel MOSFET (n-MOS) device, the single n-type S/D region of a TFET device, the n-type S/D regions/portions of a FFFET device, and so forth. Although the techniques are primarily described herein in the context of benefitting n-type S/D regions (e.g., due to such n-type S/D regions deriving benefits from the use of Ge-rich material), in accordance with some embodiments, the present disclosure is not intended to be so limited, unless otherwise stated. For example, in some embodiments, the techniques may be used to alternatively or additionally benefit p-type S/D regions. In some embodiments, the techniques described herein can be used to benefit complementary transistor circuits, such as CMOS circuits, where the techniques employing a Si-rich layer for Ge-rich transistors may be used to benefit one or more of the included n-channel and/or p-channel transistors making up a given CMOS circuit. Further still, in some embodiments, the techniques described herein can be used to benefit transistors including a multitude of configurations, such as planar and non-planar configurations, where the non-planar configurations may include finned or FinFET configurations (e.g., dual-gate or tri- gate), gate-all-around (GAA) configurations (e.g., nanowire or nanoribbon), or some combination thereof (e.g., a beaded-fin configurations), to provide a few examples.

Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction ( BD or BED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SFMS); time-of-fiight SFMS (ToF-SFMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools may indicate an integrated circuit (IC) including a transistor that includes Si-rich contact resistance reducing layer between at least one S/D region of the transistor and the at least one corresponding S/D contact, where the Si-rich layer is on { 111 } faceting of the at least one S/D region. In other words, the Si-rich intervening layer as described herein may be between the source region of a given transistor and its corresponding contact and/or the drain region of the given transistor and its corresponding contact. In some embodiments, the S/D region that employs a Si-rich contact resistance reducing layer as described herein may include Ge-rich material, such that it includes a Ge concentration (by atomic percentage) of at least 50%, for example. Further, in some embodiments, the channel region of a given transistor that employs a Si-rich contact resistance reducing layer as described herein may include Ge-rich material, such that it includes a Ge concentration of at least 50%, for example. In some embodiments, the techniques may be used to benefit the n-type S/D regions of a Ge-rich n-MOS device and/or any other suitable transistor device as will be apparent in light of this disclosure.

In some embodiments, an etch stop layer, such as a carbon-based etch stop layer, may be used to enable the formation of the Si-rich layer on { 111 } faceting of a given S/D region. In some such embodiments, use of a carbon-based etch stop layer may be detected, in cases where the etch stop layer is not completely consumed during contact trench etch processing, based on carbon being present at the interface between an S/D region and its corresponding contact, whether it is present as a distinct layer at the interface, or as carbon content that has dissolved into the S/D region, the contact, or both features. For example, the carbon may become a part of the intermetallic (the location where resistance lowering metal of the contact region and semiconductor material from the etch stop layer and S/D region react), with a portion of the carbon potentially remaining in the semiconductor S/D region. In some such cases, the dissolved carbon may be present in the range of 1 to 20 percent, for example. In some such embodiments, carbon would not otherwise be present at or near the S/D-contact interface, as can be understood based on this disclosure. However, in embodiments where the carbon-based etch stop layer is completely consumed during contact trench etch processing, use of an etch stop layer as described herein may be detected based on its presence elsewhere in the structure, such as over at least one portion of a given S/D region (employing an Si-rich contact resistance reducing layer) where the contact trench did not access the given S/D region. In some embodiments, the techniques and structures described herein may be detected based on the benefits derived therefrom, such as the contact resistance reducing benefits gained (e.g., at least 1.25, 1.5, 1.75, 2, 2.25, 2.5, 2.75 or 3 times improved contact resistance compared to a comparable structure lacking a Si-rich contact resistance reducing layer). Numerous configurations and variations will be apparent in light of this disclosure.

Architecture and Methodology

Figures 1A-B illustrate methods 100A-B of forming an integrated circuit (IC) including one or more germanium (Ge)-rich transistors employing a silicon (Si)-rich source/drain (S/D) contact resistance reducing layer, in accordance with some embodiments of the present disclosure. Note that the Si-rich S/D contact resistance reducing layer may be referred to herein as a cap layer, a cladding layer, and/or a Si-rich layer. Figures 2A-M illustrate example IC structures that are formed when carrying out method 100 A of Figure 1A, in accordance with some embodiments. Figures 3A-E illustrate example IC structures, continuing from the example IC structure of Figure 2H, when carrying out method 100B of Figure IB, in accordance with some embodiments. The structures of Figures 2A-M and 3A-E are primarily depicted and described herein in the context of forming finned or FinFET transistor configurations (e.g., tri- gate transistor configurations), for ease of illustration. However, in some embodiments, the techniques can be used to form transistors of any suitable geometry or configuration, as can be understood based on this disclosure. For example, Figures 2K and 3B illustrate example IC structures including transistors with nanowire configurations, as will be described in more detail below.

Note that method 100A of Figure 1A relates to a process flow where an Si-rich layer is formed on one or more Ge-rich S/D regions prior to the formation of overlying insulating material (e.g., interlayer dielectric (ILD) material), and thus, prior to the initiation of the S/D contact loop processing, for example. Further note that method 100B of Figure IB relates to a process flow where an Si-rich layer is formed on one or more Ge-rich S/D regions after the formation of overlying insulating material (e.g., ILD material), and thus, after the initiation of the S/D contact loop processing, whereby the Si-rich layer is formed through one or more S/D contact trenches, for example. Also note that methods 100A-B each include a primary path that illustrates a gate last transistor fabrication process flow, in accordance with some embodiments. However, in other embodiments, a gate first process flow may be used, as will be described herein (and which is illustrated with the alternative gate first flow 100 A' indicator in Figure 1A and the alternative gate first flow 100B' indicator in Figure IB). Numerous variations and configurations will be apparent in light of this disclosure.

A multitude of different transistors can benefit from the techniques described herein, which may include, but are not limited to, field-effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), tunnel FETs (TFETs), and Fermi filter FETs (FFFETs), to name a few examples. For example, the techniques may be used to benefit n-type doped Ge-rich S/D regions of such transistors, in accordance with some embodiments. For example, the techniques may be used to reduce contact resistance for both of the n-type S/D regions of an n-channel MOSFET (n- MOS) device, which may include a source-channel-drain doping scheme of n-p-n or n-i-n, where 'n' indicates n-type doped semiconductor material, 'p' indicates p-type doped semiconductor material, and 'i' indicates intrinsic/undoped semiconductor material (which may also include nominally undoped semiconductor material, including dopant concentrations of less than 1E16 atoms per cubic cm), in accordance with some embodiments. In another example, the techniques may be used to reduce contact resistance for the only included n-type S/D region of a TFET device, which may include a source-channel-drain doping scheme of p-i-n or n-i-p, in accordance with some embodiments. In yet another example, the techniques may be used to reduce contact resistance for one or both of the S/D regions of a FFFET device, which may include a source- channel-drain doping scheme of np-i-p (or np-n-p) or pn-i-n (or pn-p-n), in accordance with some embodiments. For instance, in some such embodiments, a Si-rich contact resistance reducing layer may benefit the upper n-type doped portion of the source region of an np-i-p (or np-n-p) FFFET device or the Si-rich layer may benefit the n-type doped drain region of a pn-i-n (or pn-p-n) FFFET device. Further, the techniques may be used to benefit complementary transistor circuits, such as CMOS circuits, where the techniques employing a Si-rich contact resistance reducing layer may be used to benefit one or more of the included n-channel and/or p- channel transistors making up the CMOS circuit. Other example transistor devices include few to single electron quantum transistor devices, for example. Further still, such devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example. In some embodiments, the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).

Methods 100A-B of Figures 1A-B include patterning 102 hardmask on a substrate, such as patterning hardmask 210 on substrate 200 to form the example structure of Figure 2A, in accordance with some embodiments. In some embodiments, hardmask 210 may be deposited or otherwise formed on substrate 200 using any suitable techniques as will be apparent in light of this disclosure. For example, hardmask 210 may be blanket deposited or otherwise grown on substrate 200 using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin-on processing, and/or any other suitable process to form hardmask 210 on substrate 200. In some instances, the top surface of substrate 200 on which hardmask 210 is to be deposited may be treated (e.g., via chemical treatment, thermal treatment, etc.) prior to deposition of the hardmask 210 material. After being blanket formed on substrate 200, hardmask 210 may then be patterned using any suitable techniques, such as one or more lithography and etch processes, for example. Hardmask 210 may include any suitable material, such as oxide material, nitride material, and/or any other suitable dielectric material, for example. Specific oxide and nitride materials may include silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, and titanium nitride, just to name a few examples. In some cases, the material of hardmask 210 may be selected based on the material of substrate 200, for example.

Substrate 200, in some embodiments, may include: a bulk substrate including group IV semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC), and/or group III-V material and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material). The use of "group IV semiconductor material" (or "group IV material" or generally, "IV") herein includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and so forth. The use of "group III-V semiconductor material" (or "group III-V material" or generally, "III-V") herein includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), and so forth. Note that group III may also be known as the boron group or IUPAC group 13, group IV may also be known as the carbon group or IUPAC group 14, and group V may also be known as the nitrogen family or IUPAC group 15, for example. In some embodiments, substrate 200 may be doped with any suitable n- type and/or p-type dopant. For instance, in the case, of a Si substrate, the Si may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorous, arsenic), to provide some example cases. However, in some embodiments, substrate 200 may be undoped/intrinsic or relatively minimally doped (such as including a dopant concentration of less than 1E16 atoms per cubic centimeter (cm)), for example.

In some embodiments, substrate 200 may include a surface crystalline orientation described by a Miller index of (100), (110), or (111), or its equivalents, as will be apparent in light of this disclosure. Although substrate 200, in this example embodiment, is shown as having a thickness (dimension in the Y-axis direction) similar to other layers shown in subsequent structures for ease of illustration, in some instances, substrate 200 may be much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example, or any other suitable thickness as will be apparent in light of this disclosure. In some embodiments, substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light- emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application. Accordingly, in some embodiments, the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this disclosure.

Methods 100A-B of Figures 1A-B continue performing 104 shallow trench recess (STR) etch to form fins 202 from substrate 200, thereby forming the resulting example structure shown in Figure 2B, in accordance with some embodiments. In some embodiments, the STR etch 104 used to form trenches 215 and fins 202 may include any suitable techniques, such as various masking processes and wet and/or dry etching processes, for example. In some cases, STR etch 104 may be performed in-situ/without air break, while in other cases, STR etch 104 may be performed ex-situ, for example. Trenches 215 may be formed with varying widths (dimension in the X-axis direction) and depths (dimension in the Y-axis direction) as can be understood based on this disclosure. For example, multiple hardmask patterning 102 and STR etching 104 processes may be performed to achieve varying depths in the trenches 215 between fins 202. Fins 202 may be formed to have varying widths Fw (dimension in the X-axis direction) and heights Fh (dimension in the Y-axis direction). For example, in an aspect ratio trapping (ART) integration scheme, the fins may be formed to have particular height to width ratios such that when they are later removed or recessed, the resulting trenches formed allow for defects in the replacement material deposited to terminate on a side surface as the material grows vertically, such as non-crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects, if such an ART scheme is used.

In some embodiments, the fin widths Fw may be in the range of 4-400 nm (or in a subrange of 4-10, 4-20, 4-50, 4-100, 4-200, 10-20, 10-50, 10-100, 10-200, 10-400, 50-100, 50- 200, 50-400, or 100-400 nm), for example, or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the fin heights Fh may be in the range of 4-800 nm (or in a subrange of 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-100, 10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, or 400-800 nm), for example, or any other suitable value or range as will be apparent in light of this disclosure. In embodiments employing an aspect ratio trapping (ART) scheme, the fins may be formed to have particular height to width ratios such that when they are later recessed and/or removed, the resulting fin-shaped trenches formed allow for defects in the replacement material deposited therein to terminate on a side surface as the material grows vertically, such as on non- crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects. In such an example case, the height to width ratio of the fins (Fh:Fw) may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or any other suitable threshold ratio, as will be apparent in light of this disclosure. Note that the trenches 215 and fins 202 are each shown as having essentially the same sizes and shapes in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited. For example, in some embodiments, the fins 202 may be formed to have varying heights Fh, varying widths Fw, varying starting points (or varying starting heights), varying shapes, and/or any other suitable variations as will be apparent in light of this disclosure. Moreover, trenches 215 may be formed to have varying depths, varying widths, varying starting points (or varying starting depths), varying shapes, and/or any other suitable variations as will be apparent in light of this disclosure. Further note that although four fins 202 are shown in the example structure of Figure 2B for ease of illustration, any number of fins may be formed, such as one, two, three, five, ten, hundreds, thousands, millions, billions, and so forth, as can be understood based on this disclosure.

Methods 100A-B of Figures 1A-B continue with depositing 106 shallow trench isolation (STI) material 220 and planarizing/polishing the structure to form the example resulting structure of Figure 2C, in accordance with some embodiments. In some embodiments, deposition 106 of STI material 220 may include any suitable deposition techniques, such as those described herein (e.g., CVD, ALD, PVD), or any other suitable deposition process. In some embodiments, STI material 220 (which may be referred to as an STI layer) may include any suitable insulating material, such as one or more dielectric, oxide (e.g., silicon dioxide), and/or nitride (e.g., silicon nitride) materials. In some embodiments, the material of STI layer 220 may selected based on the material of substrate 200. For instance, in the case of a Si substrate, the STI material may be selected from silicon dioxide or silicon nitride, to provide some examples. In some embodiments, the planarizing and/or polishing process(es) performed after forming STI material 220 may include any suitable techniques, such as chemical-mechanical planarization/polishing (CMP) processes, for example.

Methods 100A-B of Figures 1A-B continue with etching 108 fins 202 to form fin-shaped trenches 225 between the STI material 220 as shown in the resulting example structure of Figure 2D, in accordance with some embodiments. In some embodiments, etching 108 may be performed using any suitable techniques, such as one or more wet and/or dry etch processes that selectively remove the material of fins 202 relative to the STI material 220 to form fin-shaped trenches 225, and/or any other suitable processing as will be apparent in light of this disclosure. As shown in the example embodiment of Figure 2D, a sub-fin portion 203 from fins 202 remains below fin-shaped trenches 225, where the height (dimension in the Y-axis direction) of the sub- fin portion 203 may be based on the etch processing 108 used form fin-shaped trenches 225. For example, in some embodiments, the etch processing 108 may be performed with characteristics (e.g., a longer etch duration) that removes relatively more of fins 202, such that a shorter (by height) sub-fin portion 203 may remain or the fins 202 may be completely removed, such that the fin-shaped trenches 225 extend to the bottom of STI material 220 and possibly beyond. However, in other embodiments, the etch processing 108 may be performed with characteristics (e.g., a shorter etch duration) that removes relatively less of fins 202, such that a taller (by height) sub-fin portion 203 may remain. Regardless, fin-shaped trenches 225 may have similar (or the same) widths (dimension in the X-axis direction) as the width (Fw) of fins 202 that were removed and similar (or the same) depths (dimension in the Y-axis direction) as the height (Fh) of fins 202 that were removed, in accordance with some embodiments. Methods 100A-B of Figures 1A-B continue with depositing 110 replacement material to form replacement material fins 230 in the fin-shaped trenches 225, thereby forming the example resulting structure of Figure 2E, in accordance with some embodiments. In some such embodiments, deposition 110 of the replacement material may include any suitable techniques, such as CVD, metalorganic CVD (MOCVD), PVD, ALD, molecular beam epitaxy (MBE), and/or any other suitable process as can be understood based on this disclosure. As can also be understood based on this disclosure, in some embodiments, deposition processing 110 may be followed by planarization/polish processing (e.g., via CMP) to form the structure of Figure 2E, in accordance with some embodiments. As can further be understood based on this disclosure, replacement material fins 230 may be used in the channel region(s) of one or more transistors, such that the material of fins 230 may also material included in those channel regions.

In some embodiments, replacement material fins 230 may include any suitable semiconductor material as will be apparent in light of this disclosure, such as group IV and/or group III-V semiconductor material. In some such embodiments, replacement material fins 230 may include Ge-rich material, such as Ge or SiGe with at least 50% Ge concentration (by atomic percentage). Thus, in such embodiments where the replacement material fins 230 include Ge- rich material, the Ge concentration may be in the range of 50-100%) (or in any suitable subrange, such as in the subrange of 50-60, 50-70, 50-80, 50-90, 60-70, 60-80, 60-90, 60-100, 70-80, 70- 90, 70-100, 80-90, 80-100, or 90-100%>), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, replacement material fins 230 may include a Ge concentration (by atomic percentage) of at least 50, 55, 60, 65, 70, 75, 80, 85, 90, or 95%, for example. In some embodiments, replacement material fins 230 may include semiconductor material that is intrinsic/undoped (or nominally undoped with a dopant concentration of less than 1E16 atoms per cubic cm), n-type doped, p-type doped, or some combination thereof (e.g., doped in some portions and undoped in other portions). In some embodiments, replacement material fins 230 may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the features, such as the grading of the Ge concentration and/or the grading of the dopant concentration, for example. In some embodiments, replacement material fins 230 may include a multilayer structure that includes at least two distinct layers. For example, in embodiments employed to form a nanowire transistor, a given replacement material fin may include at least one layer to be formed into at least one nanowire in the channel region of the transistor and at least one sacrificial layer (which may alternate with the at least one nanowire layer) to be selectively etched and removed to release the at least one nanowire layer, as can be understood based on this disclosure. Note that the replacement material fins 230 are all shown as including the same material, in the example structure of Figure 2E, for ease of illustration; however, the present disclosure is not intended to be so limited.

Methods 100A-B of Figures 1A-B continue with recessing 112 the STI material 220 to form the example resulting structure of Figure 2F, in accordance with some embodiments. In some embodiments, recessing 112 may be performed using any suitable techniques, such as one or more wet and/or dry etch processes that allow the STI material 220 to be selectively recessed relative to the replacement fin 230 material, and/or any other suitable processing as will be apparent in light of this disclosure. As shown in Figure 2F, the recessing 112 allows replacement material fins 230 to exude from the STI material 220 (and more specifically, from the top plane of STI layer 220), for example. As is also shown, sub-fin portions 203 (that are native to substrate 200, in this example embodiment) are below the top plane of STI layer 220. Note that in this example embodiment, the top plane of STI layer 220 is exactly at the level of the interface between replacement fins 230 and sub-fin portions 203; however, the present disclosure is not intended to be so limited. For example, STI material 220 may have been recessed more or less, in other embodiments.

In this example embodiment, the width (dimension in the X-axis direction) of replacement material fins 230 is the same as the width of fins 202 (i.e., width Fw) previously described. However, the height (dimension in the Y-axis direction) of replacement material fins 230 is less than the height of fins 202 (i.e., height Fh). Instead, the height of the replacement material fins 230 may be referred to as the active fin height Fah, as that height of a given fin 230 may be used in the channel region of a transistor formed therefrom, in accordance with some embodiments. In some embodiments, the height of replacement material fins 230, shown as Fah, may be may be in the range of 4-800 nm (or in a subrange of 4-10, 4-20, 4-50, 4-100, 4-200, 4-400, 10-20, 10-50, 10-100, 10-200, 10-400, 10-800, 50-100, 50-200, 50-400, 50-800, 100-400, 100-800, or 400-800 nm), for example, or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the replacement material fins 230 of the example structure of Figure 2F may be formed using alternative processing (as opposed to the replacement fin scheme described herein with reference to Figures 2A-F). For instance, in some embodiments, replacement material fins 230 may be formed using by blanket-growing/depositing the replacement material on the substrate and then patterning the replacement material into replacement material fins, to provide an example alternative.

Methods 100A-B of Figures 1A-B continue with optionally forming 114 a dummy gate stack to form the example resulting structure of Figure 2G, in accordance with some embodiments. Recall that methods 100A-B are primarily described herein in the context of a gate last transistor fabrication process flow, where the processing includes forming a dummy gate stack, performing the S/D processing, and then forming the final gate stack after the S/D regions have been processed. However, in other embodiments, the techniques may be performed using a gate first process flow. In such an example case, process 114 - forming a dummy gate stack - would not be performed, and thus, process 112 is optional in some embodiments (such as those employing the gate first process flow). This is reflected with the alternative location for performing 122 final gate stack processing, which is shown as the optional gate first flows 100A' and 100B' in Figures 1A and IB, respectively, where performing 122 the final gate stack processing may occur prior to performing S/D processing, for example. However, the description of methods 100A-B will continue using a gate last process flow, to allow for such a flow (which may include additional processes) to be adequately described.

Continuing with forming 114 a dummy gate stack, such a dummy gate stack may include dummy gate dielectric 242 and dummy gate electrode 244, thereby forming the example resulting structure of Figure 2G, in this example embodiment. In this example embodiment, dummy gate dielectric 242 (e.g., dummy oxide material) and dummy gate or dummy gate electrode 244 (e.g., dummy poly-silicon material) may be used for a replacement gate process. Note that side-wall spacers 250, referred to generally as gate spacers (or simply, spacers), on either side of the dummy gate stack were also formed, and such spacers 250 can help determine the channel length and can help with replacement gate processes, for example. As can be understood based on this disclosure, the dummy gate stack (and spacers 250) help define the channel region and source/drain (S/D) regions of each fin, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of and adjacent to the channel region. Note that because the IC structures are being described in the context of forming finned transistors, the final gate stack will also be adjacent to either side of the fin, as the gate stack will reside along three walls of the finned channel regions, in some embodiments. Formation of the dummy gate stack may include depositing the dummy gate dielectric material 242 and dummy gate electrode material 244, patterning the dummy gate stack, depositing gate spacer material 250, and performing a spacer etch to form the structure shown in Figure 2G, for example. Spacers 250 may include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that in some embodiments, the techniques described herein need not include forming a dummy gate stack, such that a final gate stack may be formed in the first instance. Regardless, the end structure will include the final gate stack, as will be apparent in light of this disclosure. Also note that in some embodiments, a hardmask (not shown) may be formed over the dummy gate stack (which may also be formed over spacers 250) to protect the dummy gate stack during subsequent processing, for example.

Methods 100A-B of Figures 1A-B continue with removing and replacing 116 the source/drain (S/D) material to form S/D regions that include { 111 } faceting, thereby forming the example resulting structure of Figure 2H, in accordance with some embodiments. In some embodiments, removing replacement material fins 230 in the S/D regions (the regions not covered by the dummy gate stack, in this example embodiment) may include any suitable techniques, such as one or more wet and/or dry etch processes, for example. Further, in some embodiments, replacing the S/D material with replacement S/D regions 261/262 can be performing using any suitable techniques, such as one or more of the depositions processes described herein (e.g., CVD, MOCVD, ALD, PVD, MBE), and/or any other suitable processes as will be apparent in light of this disclosure. In some such embodiments, the replacement S/D regions 261/262 may be formed using a selective deposition process, e.g., such that the S/D material only or primarily grows (or only grows in a monocrystalline structure) from the exposed semiconductor material sub-fin portions 203, as can be understood based on this disclosure. Note that the S/D regions 261/262 are referred to herein as such, but S/D regions 261 may be either source regions or drain regions, such that the corresponding S/D regions 262 (on the other side of dummy gate stack) are the other of the source regions and drain regions, thereby forming a source and drain region pair. As shown in Figure 2H, the S/D regions 261/262 each include { 111 } faceting, where examples of such { 111 } faceting is indicated by 263, for example. In other words, the upper-most surfaces (e.g., surfaces farthest from substrate 200) include { 111 } faceting, in this example embodiment. Such { 11 1 } faceted surfaces are also the surfaces that would be directly contacted, if an Si-rich layer as described herein were not employed. In some embodiments, a { 111 } faceted surface 263 of a given S/D region 261/262 may be represented by that surface including an angle (illustrated in Figure 2H as angle Q) of approximately 54.7 degrees (plus/minus 5 degrees) relative to the (001) plane, the main plane of substrate 200, the top plane of substrate 200, and/or the top plane of STI layer 220, for example. In other words, the S/D regions 261/262 may be considered to be approximately diamond-shaped, where the { 111 } faceted shape of the S/D regions 261/262 may be considered to be approximately pyramid-shaped, for example. However, a portion of the pyramid top may be removed, in some embodiments, such as is shown in Figure 2L' (described in more detail below).

In some embodiments, S/D regions 261/262 may include any suitable semiconductor material as will be apparent in light of this disclosure, such as group IV and/or group III-V semiconductor material. In some such embodiments, one or both of the S/D regions 261/262 may include Ge-rich material, such as Ge or SiGe with at least 50% Ge concentration (by atomic percentage). Thus, in such embodiments where a given S/D region includes Ge-rich material, the Ge concentration may be in the range of 50-100%) (or in any suitable subrange, such as in the subrange of 50-60, 50-70, 50-80, 50-90, 60-70, 60-80, 60-90, 60-100, 70-80, 70-90, 70-100, 80- 90, 80-100, or 90-100%>), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, a given S/D region may include a Ge concentration (by atomic percentage) of at least 50, 55, 60, 65, 70, 75, 80, 85, 90, or 95%, for example. In some embodiments, S/D regions 261/262 may include semiconductor material that is n-type doped and/or p-type doped. In some embodiments, a given S/D region may include grading (e.g., increasing and/or decreasing) of the concentration of one or more materials within the features, such as the grading of the Ge concentration and/or the grading of the dopant concentration, for example. For instance, in some such embodiments, the dopant concentration (e.g., n-type dopant concentration) included in a given S/D region may be graded such that it is lower near the channel region and higher near the { 111 } faceted surfaces, which may be achieved using any suitable processing, such as tuning the amount of dopant in the reactant flow (e.g., during an in- situ doping scheme). In some embodiments, a given S/D region may include a multilayer structure that includes at least two distinct layers.

Note that the S/D regions 261/262 are shown with different patterning than replacement fins 230 to assist with visual identification of the different features in the figures. However, the patterning/shading of any of the features in the figures is not intended to limit the present disclosure in any manner and is merely provided to assist with visual identification of the different features described herein. Also note that S/D regions 261/262 are all shown as including the same material and sizes/shapes in the example structure of Figure 2H, for ease of illustration; however, the present disclosure is not intended to be so limited. For example, in some embodiments, one of the S/D regions (such as regions 261) may be processed separately than the other S/D regions (such as regions 262), such that a corresponding S/D pair may include different material, dopant type, and/or dopant concentration. For instance, in the case of a TFET device, one of the S/D regions may include n-type doped semiconductor material and the other of the S/D regions may include p-type doped semiconductor material, to provide an example case. In some embodiments, a given S/D region may include the same or similar (e.g., with l -3%>) Ge concentration as the corresponding/adjacent channel region (which may be determined based on the material of replacement fins 230). However, in other embodiments, a given S/D region may include relatively different Ge concentration (e.g., at least 3, 5, or 10% different) compared to a corresponding/adjacent channel region, for example.

At this point in the process flows of methods 100A-B, the methods diverge as previously described. For example, method 100A of Figure 1A includes forming a Si-rich layer on { 111 } faceting of the S/D regions 261/262 prior to initiating S/D contact loop processing, as will be described with reference to Figures 2I-M, in accordance with some embodiments. However, method 100B of Figure IB includes forming the Si-rich layer on { 111 } faceting of the S/D regions 261/262 after initiating contact loop processing, and more specifically, forming the Si- rich layer through the S/D contact trenches, as will be described with reference to Figures 3 A-E, in accordance with some embodiments. Regardless, both methods and the structures formed therefrom continue from the example structure of Figure 2H, as will be apparent in light of this disclosure.

Method 100A of Figure 1 continues with forming 118 a Si-rich layer 264 on the { 111 } faceting of the S/D regions 261/262 of the structure of Figure 2H to form the resulting example structure of Figure 21, in accordance with some embodiments. In some embodiments, the Si-rich layer 264 may be formed on the S/D regions 261/262 using any suitable techniques, such as using one or more deposition processes described herein (e.g., CVD, MOCVD, ALD, PVD, MBE), and/or any other suitable processes as will be apparent in light of this disclosure. In some embodiments, the Si-rich layer 264 may only or primarily be formed on S/D regions 261/262 using, e.g., a selective deposition process. As shown in the example structure of Figure 21, the Si-rich layer 264 was formed over the entirety of each S/D region 261/262, such that the Si-rich layer 264 may be considered a cladding layer, in this example embodiment. However, the present disclosure is not intended to be so limited, unless otherwise stated. As will be apparent in light of this disclosure, the Si-rich layer 264 may be formed to help reduce contact resistance for S/D regions that employ the Si-rich layer 264, for example. In some embodiments, the Si- rich layer 264 may include a thickness in the range of 1-10 nm (or in any suitable subrange, such as 1-2, 1-4, 1-5, 1-6, 1-8, 2-4, 2-6, 2-8, 2-10, 4-6, 4-8, 4-10, 5-10, 6-8, 6-10, or 8-10 nm, for example), or any other suitable value or range as will be apparent in light of this disclosure.

In some embodiments, the Si-rich layer 264 may include Si, SiGe, and/or any other suitable material as will be apparent in light of this disclosure. Further, in some embodiments, the Si-rich layer 264 may include any suitable Si concentration (by atomic percentage), such as Si in the range of 50-100% (or in any suitable subrange, such as in the subrange of 50-60, 50-70, 50-80, 50-90, 60-70, 60-80, 60-90, 60-100, 70-80, 70-90, 70-100, 80-90, 80-100, or 90-100%), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the Si-rich layer may include a Si concentration (by atomic percentage) of at least 50, 55, 60, 65, 70, 75, 80, 85, 90, or 95%, for example. In some embodiments, the Si-rich layer may include any suitable doping type (e.g., n-type or p-type) and dopant concentration (e.g., in the range of 1E17-5E22 atoms per cubic cm), as will be apparent in light of this disclosure. In some such embodiments, the Si-rich layer may be doped the same type (e.g., n-type or p-type) relative to the underlying S/D region semiconductor material dopant (e.g., such that they are both n-type or p-type doped). In some embodiments, the Si-rich layer 264 may be relatively heavily doped, and in some cases, degenerately doped with a concentration of at least 1E19, 1E20, 1E21, or 1E22 atoms per cubic centimeter (cm), which can help reduce S/D contact resistance, as can be understood based on this disclosure. As previously described, Si-rich material (such as Si or SiGe with greater than 50% Si content) can be effectively doped at relatively higher concentrations compared to Ge-rich material (such as Ge or SiGe with greater than 50% Ge content). Thus, in some embodiments, the Si-rich layer 264 may include a higher dopant concentration relative to an underlying Ge-rich S/D region in the amount of at least 1E17, 5E17, 1E18, 5E18, 1E19, 5E19, 1E20, 5E20, or 1E21 atoms per cubic cm greater dopant concentration, or some other suitable threshold relative value as will be apparent in light of this disclosure.

Method 100A of Figure 1A continues with forming 120 etch stop layer 265 on the Si-rich layer 264, thereby forming the example resulting structure of Figure 2J, in accordance with some embodiments. In some embodiments, the etch stop layer 265 may be formed on the Si-rich layer 264 using any suitable techniques, such as using one or more deposition processes described herein (e.g., CVD, MOCVD, ALD, PVD, MBE), and/or any other suitable processes as will be apparent in light of this disclosure. In some embodiments, the etch stop layer 265 may only or primarily be formed on the Si-rich layer 264 using, e.g., a selective deposition process. As shown in the example structure of Figure 2J, the etch stop layer 265 was formed over the entirety of the Si-rich layer 264 for each S/D region 261/262, such that the etch stop layer 265 may be considered a cladding layer, in this example embodiment. However, the present disclosure is not intended to be so limited, unless otherwise stated. As will be apparent in light of this disclosure, the etch stop layer 265 may be formed to help protect the Si-rich layer 264 from being damaged and/or consumed (in part or in total) during subsequent processing, such as during contact trench etch processing, for example.

In some embodiments, the etch stop layer 265 may include any suitable material, such as any suitable group IV and/or group III-V semiconductor material, for example. For instance, in some such embodiments, the etch stop layer 265 may include non-carbon semiconductor material (e.g., group IV semiconductor material) alloyed with carbon (C), which may be referred to herein as "Z:C", where Z is the non-carbon semiconductor material. For instance, in some such embodiments, the etch stop layer may include Si alloyed with C, which may be represented as Si:C, or SiGe alloyed with C (SiGe:C), or Ge alloyed with C (Ge:C). In embodiments where the etch stop layer includes C, the included C concentration (by atomic percentage) may be in the range of 1-80% (or in a suitable subrange, such as in the subrange of 1-2, 1-5, 1-10, 1-20, 1-40, 1-60, 2-5, 2-10, 2-20, 2-50, 2-80, 5-10, 5-20, 5-50, 5-80, 10-20, 10-50, 10-80, 20-50, 20-80, or 50-80%), or some other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the etch stop layer 265 may be formed to have a thickness in the range of 1 - 20 nm (e.g., in the subrange of 1-2, 1-5, 1-10, 2-5, 2-10, 2-20, 5-10, 5-20, or 10-20 nm), or some other suitable thickness as will be apparent in light of this disclosure. In embodiments where the etch stop layer 265 includes C, the thickness and C concentration (by atomic percentage) may be inversely related, such that if a relatively thicker carbon-based etch stop layer is employed (e.g., with a thickness of at least 8, 10, 12, or 15 nm, such as having a thickness in the range of 8-20 nm), then relatively lower C concentration may be used to ensure the etch stop layer is adequately robust/resilient enough to effectively function (e.g., C concentration in the range of 1 - 5%). Further, in some such embodiments, if a relatively thinner carbon-based etch stop layer is employed (e.g., with a thickness less than 5, 3, or 2 nm, such as having a thickness in the range of 1-2 nm), then relatively higher C concentration may be used to ensure that the etch stop layer is robust/resilient enough to effectively function (e.g., C concentration in the range of 20-50%).

Method 100A of Figure 1A continues with performing 122 the final gate stack processing to form the example resulting structure of Figure 2K, in accordance with some embodiments. As shown in Figure 2K, the processing in this example embodiment included depositing interlayer dielectric (ILD) layer 270 on the structure of Figure 2F, followed by optional planarization and/or polishing to reveal the dummy gate stack. Note that ILD layer 270 is shown as transparent in the example structure of Figure 2K to allow for the underlying features to be seen; however, the present disclosure is not intended to be so limited. In some embodiments, the ILD layer 270 may include any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. The gate stack processing, in this example embodiment, continued with removing the dummy gate stack (including dummy gate 244 and dummy gate dielectric 242) to allow for the final gate stack to be formed. Recall that in some embodiments, the formation of the final gate stack, which includes gate dielectric layer 282 and gate (or gate electrode) 284, may be performed using a gate first flow (also called up-front hi-k gate). In such embodiments, the gate processing may have been performed after process 112 and prior to the S/D processing 116. However, in this example embodiment, the gate stack is formed using a gate last flow (also called a replacement gate or replacement metal gate (RMG) process). In such gate last processing, the process may include dummy gate oxide deposition, dummy gate electrode (e.g., poly-Si) deposition, and, optionally, patterning hardmask deposition, as previously described. Regardless of whether gate first or gate last processing is employed, the final gate stack can include gate dielectric layer 282 and gate 284 as shown in Figure 2K and described herein.

Note that when the dummy gate is removed, the channel region of replacement material fins 230 (that were covered by the dummy gate) are exposed to allow for any desired processing of the channel regions of the fins. Such processing of the channel region may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region of the fin as desired, forming the fin into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure. For instance, finned channel region 234 is illustrated (which is the channel region of the right-most of the four original finned structures), which may be a portion of replacement material fin 230 or it may have been processed in any suitable manner. To provide another example, nanowire channel region 236 (which is the channel region of the leftmost of the four original finned structures) may have been formed after the dummy gate was removed and the channel regions of the fins were exposed, by converting the finned structure at that location into the nanowires 236 shown using any suitable techniques, for example. For instance, the original finned channel region may have included a multilayer structure, where one or more of the layers were sacrificial and were selectively etched to remove those sacrificial layers and release the nanowires 236. As shown in Figure 2K, nanowire channel region 236 includes 2 nanowires (or nanoribbons) in this example case. However, a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1, 3, 4, 5, 6, 7, 8, 9, 10, or more, depending on the desired configuration.

As can be understood based on this disclosure, the channel region is at least below the gate stack, in this example embodiment. For instance, in the case of a finned transistor configuration, the channel region may be below and between the gate stack, as the stack is formed on three sides as is known in the art. However, if the transistor device were inverted and bonded to what will be the end substrate, then the channel region may be above the gate. Therefore, in general, the gate and channel relationship may include a proximate relationship (which may or may not include intervening gate dielectric layer and/or other suitable layers), where the gate is near the channel region such that it can exert control over the channel region in some manner (e.g., in an electrical manner), in accordance with some embodiments. Further, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may completely surround each nanowire/nanoribbon in the channel region (or at least substantially surround each nanowire, such as surrounding at least 70, 80, or 90% of each nanowire). Further still, in the case of a planar transistor configuration, the gate stack may simply be above the channel region. In some embodiments, the channel region may include group IV semiconductor material (e.g., Si, SiGe, Ge), group III-V semiconductor material (e.g., GaAs, InGaAs, InAs), and/or any other suitable material as will be apparent in light of this disclosure. In some embodiments, the channel region may be doped (e.g., with any suitable n-type and/or p-type dopant) or intrinsic/undoped (or nominally undoped), depending on the particular configuration. For instance, in some such embodiments, the channel region may include Ge-rich material (e.g., Ge or SiGe with at least 50% Ge concentration) which may or may not be doped as desired (e.g., it may be doped with p- type dopant), to provide some examples.

Note that S/D regions 261/262 are adjacent to either side of a corresponding channel region, as can be seen in Figure 2K, for example. More specifically, the S/D regions 261/262 are directly adjacent to a corresponding channel region, such that there are no intervening layers between either of the S/D regions and the channel region, in this example embodiment. However, the present disclosure is not intended to be so limited. Also note that the configuration/geometry of a transistor formed using the techniques described herein may primarily be described based on the shape/configuration of the respective channel region of that transistor, for example. For instance, a nanowire (or nanoribbon or GAA) transistor may be referred to as such because it includes one or more nanowires (or nanoribbons) in the channel region of that transistor. However, the transistor type (e.g., MOSFET, TFET, HEMT, or other suitable type) may be described based on the doping and/or operating scheme of the source, channel, and drain regions, and thus those respective regions may be used to determine the type or classification of a given transistor, for example. This is especially true for MOSFET versus TFET transistors, as they may structurally be very similar (or the same), but include different doping schemes (e.g., source-drain doping schemes for MOSFET of p-p or n-n versus p-n or n-p for TFET).

Continuing with performing 122 final gate stack processing, after the dummy gate has been removed and any desired channel region processing has been performed, the final gate stack can then be formed, in accordance with some embodiments. In this example embodiment, the final gate stack includes gate dielectric layer 282 and gate 284, as shown in Figure 2K. The gate dielectric layer 282 may include, for example, any suitable oxide (such as silicon dioxide), high- k gate dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, an annealing process may be carried out on the gate dielectric layer 282 to improve its quality when high-k material is used. The gate 284 (or gate electrode) may include a wide range of materials, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example. In some embodiments, gate dielectric layer 282 and/or gate 284 may include a multilayer structure of two or more material layers, for example. In some embodiments, gate dielectric layer 282 and/or gate 284 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s). Additional layers may be present in the final gate stack, in some embodiments, such as one or more work function layers or other suitable layers, for example. Note that although gate dielectric layer 282 is only shown below gate 284 in the example embodiment of Figure 2K, in other embodiments, the gate dielectric layer 282 may also be present on one or both sides of gate 284, such that the gate dielectric layer 282 may also be between gate 284 and one or both of spacers 250, for example. Numerous different gate stack configurations will be apparent in light of this disclosure.

Method 100 A of Figure 1A continues with performing 124 S/D contact processing to form the example resulting structure of Figure 2M, in accordance with some embodiments. In some embodiments, contact processing 124 may first include forming S/D contact trenches 290 above the S/D regions 261/262, as shown in Figure 2L. In some such embodiments, the contact trenches 290 may be formed using any suitable techniques, such as performing one or more wet and/or dry etch processes to remove portions of ILD layer 270 as shown, and/or any other suitable processing as will be apparent in light of this disclosure. Such etch processing may be referred to herein as the S/D contact trench etch processing, or simply, contact trench etch processing. Further, in some such embodiments, the ILD may first be patterned such that areas that are not to be removed via the contact trench etch processing are masked off, for example. As shown in the example structure of Figure 2L, the etch stop layer 265 was completely consumed/removed during the contact trench etch processing, resulting in the Si-rich layer 264 being exposed in the contact trench 290 locations. However, in other embodiments, at least a portion of etch stop layer 265 may remain after contact trench etch processing has been performed, where the remaining portion of the etch stop layer 265 may be kept or removed as desired. Regardless, the etch stop layer 265 can be used to protect and/or preserve the Si-rich layer 264 during the contact trench etch processing, as can be understood based on this disclosure. Also note that regardless of whether at least a portion of etch stop layer 265 remains in the contact trench 290 locations, it is still present elsewhere on the S/D regions where the contact trenches 290 did not access (such as adjacent to the contact trench locations on the other side of the channel region and on the lower portion of the S/D contact regions 261/262, as shown in this example embodiment).

Figure 2L' is a blown-out portion of Figure 2L, illustrating a variation that may occur as method 100A is performed, in accordance with some embodiments. As shown in Figure 2L', the portion reproduced is the top of the right-most S/D region 261 that includes Si-rich layer 264 thereon in contact trench 290. The portion is reproduced to illustrate the variation that, in some cases, the contact trench etch processing (used to form contact trench 290) may consume a portion of the top of the structure such as is shown, thereby removing a portion of the Si-rich layer 264 and, in some cases, removing a portion of the top { 111 } faceting of the S/D region 261, as is also shown. Moreover, the shape of the Si-rich layer 264 and/or the S/D regions 261/262 may be affected by the formation of the metal contacts in the contact trenches 290 and/or by other processing performed after the S/D regions 261/262 have been formed. Regardless, in some embodiments, the top surface(s) of the originally formed S/D regions 261/262 need not include 100% { 111 } faceting to benefit from the Si-rich contact resistance reducing layer 264, such that the top surface(s) of one or more of the S/D regions 261/262 formed may include { 11 1 } faceting for only approximately 60, 65, 70, 75, 80, 85, 90, or 95% of the top surface(s) (by contact area) and not 100%, for example. Such example embodiments can be compared to the S/D regions 261/262 of Figure 2H which all have top surfaces that include 100%) { 111 } faceting. Generally, as can be understood based on this disclosure, even where the Si-rich layer 264 is only between a given S/D region and its corresponding contact in a small surface area (e.g., only between 20, 30, 40, 50, 60, 70, or 80%> of the total overlapping surface area of the two features), the Si-rich layer 264 can still provide contact resistance reducing benefits as described herein.

Continuing from the example structure of Figure 2L to the example structure of Figure 2M, S/D contact processing 124 included forming S/D contacts 291/292 above respective S/D regions 261/262, in accordance with some embodiments. In the example structure of Figure 2M, it can be understood that S/D contacts 291/292 are electrically connected to S/D regions 261/262 but need not be in physical contact with those regions 261/262 as the Si -rich layer 264 may be completely between the S/D contacts 291/292 and the respective S/D regions 261/262, for example. However, in some embodiments, at least a portion of S/D contacts 291/292 may be in physical contact with S/D regions 261/262 (such as where Si-rich layer 264 is not present or where at least a portion of Si-rich layer 264 was consumed during processing, for example). In some embodiments, S/D contacts 291/292 may be formed using any suitable techniques, such as depositing metal or metal alloy (or other suitable electrically conductive material) in contact trenches 290. In some embodiments, S/D contact 291/292 formation may include silicidation, germinidation, and/or annealing processes, for example. In some embodiments, S/D contacts 291/292 may include aluminum or tungsten, although any suitable conductive metal or alloy can be used, such as silver, nickel-platinum, or nickel-aluminum, for example. In some embodiments, one or more of the S/D contacts may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance. Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used. In some embodiments, additional layers may be present in the S/D contact regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired.

Method 100B of Figure IB includes similar processing as method 100A of Figure 1A, with a few variations related to the S/D regions and contact processing, as previously described. More specifically, method 100 A includes forming the Si-rich layer 264 on { 111 } faceting of S/D regions 261/262 prior to the initiation of the S/D contact loop processing (e.g., prior to performing S/D contact processing 124), while method 100B includes forming the Si-rich layer 264' on { 111 } faceting of S/D regions 261/262 after the initiation of the S/D contact loop processing (e.g., during the S/D contact processing 124, through the contact trenches). Variations occur in the finally formed structures as a result of the variations between the methods, however, the structures include similar features such that the previous relevant description with respect to method 100A and the example structures of Figures 2A-M is equally applicable to method 100B and the example structure of Figures 3A-E.

Method 100B of Figure IB continues from box 116 and structure 2H by forming 117 etch stop layer 265 on the S/D regions 261/262, thereby forming the example resulting structure of Figure 3A, in accordance with some embodiments. The previous relevant description with respect to forming 120 the etch stop layer is equally applicable to formation process 117, except that for process 117, the etch stop layer 265 is formed directly on the S/D regions 261/262 as the Si-rich layer has not yet been formed (as compared to formation process 120, for example). Further, the previous relevant description with respect to etch stop layer 265 is equally applicable to the structure of Figure 3A. Method 100B of Figure IB continues with performing 122 final gate stack processing to form the example resulting structure of Figure 3B, in accordance with some embodiments. The previous relevant description with respect to final gate stack processing 122 is equally applicable here.

Method 100B of Figure IB continues with performing S/D contact processing 124 and forming 125 a Si-rich layer on { 111 } faceting of the S/D regions through S/D contact trenches to form the example resulting structure of Figure 3E, in accordance with some embodiments. Note that in Figure IB, boxes 124 and 125 are shown as indicating toward one another because box 125 occurs during the S/D contact loop processing of box 124, as will be apparent in light of this disclosure. In this example embodiment, in Figure 3C, the S/D contact processing 124 included forming contact trenches 290 which expose S/D regions 261/262 as shown. The previous relevant description with respect to forming contact trenches 290 is equally applicable here, except note that the contact trenches 290 do not expose the Si-rich layer (as it has not yet been formed), but instead expose { 111 } faceting of the S/D regions 261/262 as shown. Thus, in this example embodiment, the etch stop layer 265 may have been used to protect and/or preserve the { 111 } faceting of the S/D regions 261/262 during the contact trench etch processing. As was previously the case with the structure of Figure 2L, the contact trench etch processing completely removed etch stop layer 265 in the contact trench 290 locations, as shown in Figure 3C. However, as was also previously stated, the present disclosure is not intended to be so limited, such that at least a portion of etch stop layer 265 may be present at one or more such locations in the final IC structure. Continuing from the example structure of Figure 3C, Si -rich layer 264' was formed through S/D contact trenches 290 and on { 111 } faceting of the S/D regions 261/262 to form the example resulting structure of Figure 3D, in accordance with some embodiments. The previous relevant description with respect to Si-rich layer 264 is equally applicable to Si-rich layer 264', except that Si-rich layer 264' is only formed in the contact trench locations and thus only on the exposed portions of the S/D regions 261/262 (as opposed to the Si-rich layer being formed on additional portions of the S/D regions, such as was the case in method 100A). Continuing from the example structure of Figure 3D, S/D contacts 291/292 were formed in the contact trenches 290, thereby forming the example resulting structure of Figure 3E, in accordance with some embodiments. The previous relevant description with respect to S/D contacts 291/292 is equally applicable here.

Figures 4A-B illustrate example cross-sectional views along the planes A-A and B-B in Figures 2M and 3E, respectively, in accordance with some embodiments. The cross-sectional views of Figures 4A-B are provided to assist in illustrating different features of the structures of Figures 2M and 3E, respectively. Therefore, the previous relevant description with respect to each similarly numbered feature is equally applicable to Figures 4A-B. However, note that the dimensions of the features shown in Figures 4A-B may differ (relative to the features in Figures 2M and 3E, respectively), for ease of illustration. Also note that some variations occur between the structures, such as the shape of spacers 250 and of finned channel region 234, for example. Further note that the portion of the structure where S/D contact trenches 290 were formed is indicated on the left side of Figures 4A-B, as can be understood based on this disclosure. As shown in Figure 4A, the Si-rich layer 264 is on the entirety of the S/D regions 261/262, as that layer 264 was formed prior to the formation of S/D contact trenches 290. Further, the etch stop layer (ESL) 265 is present over areas of the S/D regions 261/262 not exposed by the contact trench 290, as can be understood based on this disclosure. As shown in Figure 4B, the Si-rich layer 264' is only on the S/D regions 261/262 in the portions where the S/D contact trenches 290 were made. Further, the etch stop layer (ESL) 265 is present on the S/D regions 261/262 in areas not exposed by the contact trench 290, as can also be understood based on this disclosure. Further still, the Si-rich layer 264' is shown as adjacent to the ESL 265 in the example structure of Figure 4B, as the Si-rich layer 264' was formed in the location of the removed ESL 265 portion in the contact trench 290 after the ESL 265 was removed during contact trench etch processing. In addition, sacrificial S/D material 260 remains adjacent to both of the S/D regions 262, as shown. In both of the structures of Figures 4A-B, the Si-rich layer is an intervening layer between a given S/D region and the corresponding S/D contact, where the Si -rich layer can be employed to lower the contact resistance at such locations, as can be understood based on this disclosure.

In some embodiments, the length of gate 284 (e.g., the dimension between spacers 250 in the Z-axis direction), which is indicated as Lg, may be any suitable length as will be apparent in light of this disclosure. For instance, in some embodiments, the gate length may be in the range of 3-100 nm (e.g., 3-10, 3-20, 3-30, 3-50, 5-10, 5-20, 5-30, 5-50, 5-100, 10-20, 10-30, 10-50, 10- 100, 20-30, 20-50, 20-100, or 50-100 nm), or any other suitable value or range as will be apparent in light of this disclosure. In some embodiments, the gate length may be less than a given threshold, such as less than 100, 50, 45, 40, 35, 30, 25, 20, 15, 10, 8, or 5 nm, or less than some other suitable threshold as will be apparent in light of this disclosure. In some embodiments, the techniques enable maintaining a desired device performance when scaling to such low thresholds, such as sub-50, sub-40, sub-30, or sub-20 nm thresholds, as can be understood based on this disclosure. Further, the techniques described herein may allow the gate length and the effective channel length (dimension between the S/D regions in the Z-axis direction) to be the same or approximately the same, due to a reduction of dopant diffusion from a given S/D region into the adjacent channel region, as the Si-rich layer can compensate for (from a contact resistance standpoint) the lower dopant content in the given S/D region, in accordance with some embodiments. Thus, the gate length may approximate the effective channel length, in some such embodiments, and the techniques described herein can prevent that effective channel length from undesirably shortening due to undesirable S/D dopant diffusion that may otherwise occur. Numerous other benefits of the techniques and structures described herein will be apparent in light of this disclosure.

Methods 100A-B of Figures 1A-B continue with completing 126 integrated circuit (IC) processing as desired, in accordance with some embodiments. Such additional processing to complete the IC may include back-end or back-end-of-line (BEOL) processing to form one or more metallization layers and/or to interconnect the transistor devices formed during front-end or front-end-of-line (FEOL) processing, for example. Any other suitable processing may be performed, as will be apparent in light of this disclosure. Note that the processes 102-126 of methods 100 A and 100B are shown in a particular order for ease of description. However, one or more of the processes 102-126 may be performed in a different order or may not be performed at all. For example, box 114 is an optional process that need not be performed in embodiments employing a gate first process flow, for example. Numerous variations on methods 100A-B and the techniques described herein will be apparent in light of this disclosure. Recall that the techniques may be used to form a multitude of different transistor types and configurations. Although the techniques are primarily depicted and described herein in the context of employing an Si-rich S/D contact resistance reducing layer for both of the S/D regions of a given transistor (such as for both of the n-type S/D regions of an n-MOS device), the present disclosure is not intended to be so limited, as the techniques may be used to benefit only one S/D region of a given transistor, and not the other. Numerous variations and configurations will be apparent in light of the present disclosure.

Example System

Figure 5 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.

Depending on its applications, computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment. In some embodiments, multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing system 1000 may include a plurality of communication chips 1006. For instance, a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006. In accordance with some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. As will be appreciated in light of this disclosure, note that multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips). Further note that processor 1004 may be a chip set having such wireless capability. In short, any number of processor 1004 and/or communication chips 1006 can be used. Likewise, any one chip or chip set can have multiple functions integrated therein.

In various implementations, the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. Note that reference to a computing system is intended to include computing devices, apparatuses, and other structures configured for computing or processing information.

Further Example Embodiments

The following examples pertain to further embodiments, from which numerous permutations and configurations will be apparent.

Example 1 is an integrated circuit (IC) including: a substrate; and a transistor at least one of above and in the substrate, the transistor including a gate, a channel region below the gate and including a first semiconductor material, source and drain (S/D) regions adjacent the channel region, one of the S/D regions including a second semiconductor material and { 111 } faceting, wherein the second semiconductor material includes at least 50% germanium (Ge) by atomic percentage, a contact above the one of the S/D regions, and an intervening layer between the contact and the one of the S/D regions, wherein the intervening layer is on the { 111 } faceting of the one of the S/D regions and wherein the intervening layer includes at least 50% silicon (Si) by atomic percentage.

Example 2 includes the subject matter of Example 1, wherein the first semiconductor material includes at least 50% Ge by atomic percentage.

Example 3 includes the subject matter of Example 1 or 2, wherein the first semiconductor material is Ge that is p-type doped.

Example 4 includes the subject matter of any of Examples 1-3, wherein the second semiconductor material is n-type doped.

Example 5 includes the subject matter of any of Examples 1-4, wherein the second semiconductor material is Ge that is n-type doped.

Example 6 includes the subject matter of any of Examples 1-5, wherein the contact includes at least one metal material.

Example 7 includes the subject matter of any of Examples 1-6, wherein the third semiconductor material is Si.

Example 8 includes the subject matter of any of Examples 1-7, wherein the intervening layer is n-type doped.

Example 9 includes the subject matter of Example 8, wherein the intervening layer n-type dopant includes a concentration that is at least 1E18 atoms per cubic centimeter (cm) greater than a concentration of n-type dopant included in the one of the S/D regions.

Example 10 includes the subject matter of any of Examples 1-9, further including an etch stop layer present on a portion of the one of the S/D regions and not present between the contact and the one of the S/D regions, wherein the etch stop layer includes carbon (C).

Example 11 includes the subject matter of any of Examples 1-10, wherein the intervening layer is present on the one of the S/D regions in areas other than between the contact and the one of the S/D regions.

Example 12 includes the subject matter of any of Examples 1-10, wherein the intervening layer is only between the contact and the one of the S/D regions, such that it is not present elsewhere on the one of the S/D regions. Example 13 includes the subject matter of any of Examples 1-12, wherein the transistor includes at least one of a finned, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA) configuration.

Example 14 includes the subject matter of any of Examples 1-13, wherein the transistor is at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET), tunnel field-effect transistor (TFET), and fermi-filter field-effect transistor (FFFET).

Example 15 includes the subject matter of any of Examples 1-14, wherein the transistor is an n-channel metal-oxide-semiconductor field-effect transistor (n-MOS) device.

Example 16 includes the subject matter of any of Examples 1-15, further including a complementary metal-oxide-semiconductor (CMOS) circuit formed at least one of above and in the substrate, wherein the CMOS circuit includes the transistor.

Example 17 is a computing system including the subject matter of any of Examples 1-16.

Example 18 is an integrated circuit (IC) including a substrate; and a transistor at least one of above and in the substrate, the transistor including a gate, a channel region below the gate and including a first semiconductor material, source and drain (S/D) regions adjacent the channel region, one of the S/D regions including a second semiconductor material and { 111 } faceting, wherein the second semiconductor material is n-type doped, a contact above the one of the S/D regions, and an intervening layer between the contact and the one of the S/D regions, wherein the intervening layer is on the { 111 } faceting of the one of the S/D regions and the intervening layer includes at least 50% silicon (Si) by atomic percentage, wherein the first and second semiconductor materials each include at least 50% germanium (Ge) by atomic percentage.

Example 19 includes the subject matter of Example 18, wherein the first semiconductor material is Ge that is p-type doped.

Example 20 includes the subject matter of Example 18 or 19, wherein the second semiconductor material is Ge that is n-type doped.

Example 21 includes the subject matter of any of Examples 18-20, wherein the contact includes at least one metal material.

Example 22 includes the subject matter of any of Examples 18-21, wherein the third semiconductor material is Si.

Example 23 includes the subject matter of any of Examples 18-22, wherein the intervening layer is n-type doped. Example 24 includes the subject matter of Example 23, wherein the intervening layer n- type dopant includes a concentration that is at least 1E18 atoms per cubic centimeter (cm) greater than a concentration of n-type dopant included in the one of the S/D regions.

Example 25 includes the subject matter of any of Examples 18-24, further including an etch stop layer present on a portion of the one of the S/D regions and not present between the contact and the one of the S/D regions, wherein the etch stop layer includes carbon (C).

Example 26 includes the subject matter of any of Examples 18-25, wherein the intervening layer is present on the one of the S/D regions in areas other than between the contact and the one of the S/D regions.

Example 27 includes the subject matter of any of Examples 18-26, wherein the intervening layer is only between the contact and the one of the S/D regions, such that it is not present elsewhere on the one of the S/D regions.

Example 28 includes the subject matter of any of Examples 18-27, wherein the transistor includes at least one of a finned, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA) configuration.

Example 29 includes the subject matter of any of Examples 18-28, wherein the transistor is at least one of a metal-oxide-semiconductor field-effect transistor (MOSFET), tunnel field-effect transistor (TFET), and fermi-filter field-effect transistor (FFFET).

Example 30 includes the subject matter of any of Examples 18-29, wherein the transistor is an n-channel metal-oxide-semiconductor field-effect transistor (n-MOS) device.

Example 31 includes the subject matter of any of Examples 18-30, further including a complementary metal-oxide-semiconductor (CMOS) circuit formed at least one of above and in the substrate, wherein the CMOS circuit includes the transistor.

Example 32 is a computing system including the subject matter of any of Examples 18-31. Example 33 is a method of forming an integrated circuit (IC), the method including: forming source and drain (S/D) regions of a transistor adjacent a channel region, one of the S/D regions including a second semiconductor material and { 111 } faceting, wherein the second semiconductor material includes at least 50% germanium (Ge) by atomic percentage; forming an intervening layer on the { 111 } faceting of the one of the S/D regions, wherein the intervening layer includes at least 50% silicon (Si) by atomic percentage; and forming a contact above the intervening layer, such that the intervening layer is between the contact and the one of the S/D regions. Example 34 includes the subject matter of Example 33, wherein the intervening layer is formed prior to forming a contact trench in which the contact is formed.

Example 35 includes the subject matter of Example 33, wherein the intervening layer is formed after forming a contact trench in which the contact is formed.

Example 36 includes the subject matter of any of Examples 33-35, further including forming an etch stop layer over the one of the S/D regions, wherein the etch stop layer includes carbon (C).

Example 37 includes the subject matter of Example 36, wherein the etch stop layer is formed after forming the intervening layer.

Example 38 includes the subject matter of Example 36, wherein the etch stop layer is formed prior to forming the intervening layer.

Example 39 includes the subject matter of any of Examples 33-38, wherein the transistor is formed using a gate last process flow.

Example 40 includes the subject matter of any of Examples 33-38, wherein the transistor is formed using a gate first process flow.

Example 41 includes the subject matter of any of Examples 33-40, wherein the transistor is an n-channel metal-oxide-semiconductor field-effect transistor (n-MOS) device.

Example 42 includes the subject matter of any of Examples 33-41, further including forming a complementary metal-oxide-semiconductor (CMOS) circuit, wherein the CMOS circuit includes the transistor.

The foregoing description of example embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to this application may claim the disclosed subject matter in a different manner, and may generally include any set of one or more limitations as variously disclosed or otherwise demonstrated herein.

Claims

CLAIMS What is claimed is:

1. An integrated circuit (IC) comprising:

a substrate; and

a transistor at least one of above and in the substrate, the transistor including

a gate,

a channel region below the gate and including a first semiconductor material, source and drain (S/D) regions adjacent the channel region, one of the S/D regions including a second semiconductor material and { 111 } faceting, wherein the second semiconductor material includes at least 50% germanium (Ge) by atomic percentage,

a contact above the one of the S/D regions, and

an intervening layer between the contact and the one of the S/D regions, wherein the intervening layer is on the { 111 } faceting of the one of the S/D regions and wherein the intervening layer includes at least 50% silicon (Si) by atomic percentage.

2. The IC of claim 1, wherein the first semiconductor material includes at least 50% Ge by atomic percentage.

3. The IC of claim 1, wherein the first semiconductor material is Ge that is p-type doped.

4. The IC of claim 1, wherein the second semiconductor material is n-type doped.

5. The IC of claim 1, wherein the second semiconductor material is Ge that is n-type doped.

6. The IC of claim 1, wherein the contact includes at least one metal material.

7. The IC of claim 1, wherein the third semiconductor material is Si.

8. The IC of claim 1, wherein the intervening layer is n-type doped.

9. The IC of claim 8, wherein the intervening layer n-type dopant includes a concentration that is at least 1E18 atoms per cubic centimeter (cm) greater than a concentration of n-type dopant included in the one of the S/D regions.

10. The IC of claim 1, further comprising an etch stop layer present on a portion of the one of the S/D regions and not present between the contact and the one of the S/D regions, wherein the etch stop layer includes carbon (C).

11. The IC of claim 1, wherein the intervening layer is present on the one of the S/D regions in areas other than between the contact and the one of the S/D regions.

12. The IC of claim 1, wherein the intervening layer is only between the contact and the one of the S/D regions, such that it is not present elsewhere on the one of the S/D regions.

13. The IC of claim 1, wherein the transistor includes at least one of a finned, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA) configuration.

14. The IC of claim 1, wherein the transistor is at least one of a metal-oxide- semiconductor field-effect transistor (MOSFET), tunnel field-effect transistor (TFET), and fermi-filter field-effect transistor (FFFET).

15. The IC of claim 1, wherein the transistor is an n-channel metal -oxide- semi conductor field-effect transistor (n-MOS) device.

16. The IC of claim 1, further comprising a complementary metal-oxide- semiconductor (CMOS) circuit formed at least one of above and in the substrate, wherein the

CMOS circuit includes the transistor.

17. A computing system comprising the IC of any of claims 1-16.

18. An integrated circuit (IC) compri

a substrate; and

a gate,

a channel region below the gate and including a first semiconductor material, source and drain (S/D) regions adjacent the channel region, one of the S/D regions including a second semiconductor material and { 111 } faceting, wherein the second semiconductor material is n-type doped, a contact above the one of the S/D regions, and

an intervening layer between the contact and the one of the S/D regions, wherein the intervening layer is on the { 111 } faceting of the one of the S/D regions and the intervening layer includes at least 50% silicon (Si) by atomic percentage,

wherein the first and second semiconductor materials each include at least 50% germanium (Ge) by atomic percentage.

19. The IC of claim 18, wherein the intervening layer n-type dopant includes a concentration that is at least 1E18 atoms per cubic centimeter (cm) greater than a concentration of n-type dopant included in the one of the S/D regions.

20. The IC of claim 18, further comprising an etch stop layer present on a portion of the one of the S/D regions and not present between the contact and the one of the S/D regions, wherein the etch stop layer includes carbon (C).

21. The IC of any of claims 18-20, wherein the transistor is an n-channel metal-oxide- semiconductor field-effect transistor (n-MOS) device.

22. A method of forming an integrated circuit (IC), the method comprising:

forming source and drain (S/D) regions of a transistor adjacent a channel region, one of the S/D regions including a second semiconductor material and { 111 } faceting, wherein the second semiconductor material includes at least 50% germanium (Ge) by atomic percentage;

forming an intervening layer on the { 111 } faceting of the one of the S/D regions, wherein the intervening layer includes at least 50% silicon (Si) by atomic percentage; and forming a contact above the intervening layer, such that the intervening layer is between the contact and the one of the S/D regions.

23. The method of claim 22, wherein the intervening layer is formed prior to forming a contact trench in which the contact is formed.

24. The method of claim 22, wherein the intervening layer is formed after forming a contact trench in which the contact is formed.

25. The method of any of claims 22-24, further comprising forming an etch stop layer over the one of the S/D regions, wherein the etch stop layer includes carbon (C).