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WO2018198600A1 - Composant électronique - Google Patents

Composant électronique Download PDF

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Publication number
WO2018198600A1
WO2018198600A1 PCT/JP2018/010973 JP2018010973W WO2018198600A1 WO 2018198600 A1 WO2018198600 A1 WO 2018198600A1 JP 2018010973 W JP2018010973 W JP 2018010973W WO 2018198600 A1 WO2018198600 A1 WO 2018198600A1
Authority
WO
WIPO (PCT)
Prior art keywords
outer peripheral
peripheral surface
terminals
electronic component
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/010973
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English (en)
Japanese (ja)
Inventor
智史 浅田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to TW107113730A priority Critical patent/TWI675386B/zh
Publication of WO2018198600A1 publication Critical patent/WO2018198600A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

Definitions

  • This disclosure relates to a rectangular parallelepiped electronic component.
  • Patent document 1 discloses a rectangular parallelepiped electronic component.
  • This electronic component includes first and second external electrodes disposed on first and second outer peripheral surfaces facing each other.
  • the first and second external electrodes are respectively disposed in regions facing each other on the first and second outer peripheral surfaces.
  • the opposing area between the electrodes increases, so the first and second external electrodes They may be capacitively coupled to each other, leading to isolation degradation (increase in signal leakage).
  • the degree of capacitive coupling between the electrodes is proportional to the opposing area between the electrodes and inversely proportional to the distance between the electrodes.
  • the present disclosure has been made in view of the above problems, and an object of the present disclosure is to provide isolation in an electronic component including first and second external electrodes disposed on first and second outer peripheral surfaces facing each other. It is to suppress the deterioration.
  • An electronic component is a rectangular parallelepiped electronic component having a first outer peripheral surface and a second outer peripheral surface facing each other, and each includes a first portion disposed on the first outer peripheral surface. And a plurality of first external electrodes that do not have a second portion disposed on the second outer peripheral surface, and at least one second external electrode that has the second portion and does not have the first portion. At least a part of the first portion of each first external electrode is disposed in a region outside the region facing the second portion of the second external electrode on the first outer peripheral surface. At least a part of the second portion of the second external electrode is disposed in a region on the second outer peripheral surface that is out of any of the plurality of regions that respectively face the first portions of the plurality of first external electrodes.
  • each of the plurality of first external electrodes and the second external electrode are compared with the case where all of the first portions of the first external electrodes and all of the second portions of the second external electrodes are disposed in regions facing each other. Since the area facing the electrode is reduced, the degree of capacitive coupling between the first and second external electrodes can be reduced. As a result, it is possible to suppress deterioration of isolation in the electronic component including the first and second external electrodes disposed on the first and second outer peripheral surfaces facing each other.
  • the electronic component includes a plurality of second external electrodes. At least a part of the first portion of each first external electrode is arranged in a region on the first outer peripheral surface that is out of any of the plurality of regions that respectively face the second portions of the plurality of second external electrodes. At least a part of the second portion of each second external electrode is arranged in a region on the second outer peripheral surface that is out of any of the plurality of regions that respectively face the first portions of the plurality of first external electrodes.
  • the electronic component includes a plurality of first external electrodes and a plurality of second external electrodes, capacitive coupling between each of the plurality of first external electrodes and each of the plurality of second external electrodes is performed. Can be suppressed.
  • each first external electrode is from any of the plurality of regions respectively facing the second portions of the plurality of second external electrodes on the first outer peripheral surface. Arranged in the deviated area. All of the second portions of the respective second external electrodes are arranged in a region outside the plurality of regions respectively opposed to the first portions of the plurality of first external electrodes on the second outer peripheral surface.
  • each of the plurality of first external electrodes is compared with a case in which a part of the first part of each first external electrode and a part of the second part of each second external electrode are arranged in regions that do not face each other. Since the facing area with each of the plurality of second external electrodes is further reduced (becomes 0), the degree of capacitive coupling between the first and second external electrodes can be further reduced.
  • the electronic component is connected to a third outer peripheral surface connected to the first outer peripheral surface and the second outer peripheral surface, to the first outer peripheral surface and the second outer peripheral surface, and And a third outer peripheral surface opposite to the third outer peripheral surface.
  • the distance between the first outer peripheral surface and the second outer peripheral surface is shorter than the distance between the third outer peripheral surface and the fourth outer peripheral surface.
  • the distance between the first and second outer peripheral surfaces is shorter than the distance between the third and fourth outer peripheral surfaces, and the degree of capacitive coupling between the first and second external electrodes increases accordingly.
  • at least a part of the first part of each first external electrode and at least a part of the second part of the second external electrode are arranged in regions that do not face each other.
  • the electronic component includes a third external electrode having a third portion arranged on the third outer peripheral surface and a fourth external electrode having a fourth portion arranged on the fourth outer peripheral surface.
  • a third external electrode having a third portion arranged on the third outer peripheral surface and a fourth external electrode having a fourth portion arranged on the fourth outer peripheral surface.
  • At least a portion of the third portion of the third external electrode is disposed in a region outside the region facing the fourth portion of the fourth external electrode on the third outer peripheral surface.
  • At least a portion of the fourth portion of the fourth external electrode is disposed in a region outside the region facing the third portion of the third external electrode on the fourth outer peripheral surface.
  • At least a part of the third part of the third external electrode and at least a part of the fourth part of the fourth external electrode are also arranged in regions that do not face each other. Therefore, in addition to capacitive coupling between the first and second external electrodes, capacitive coupling between the third and fourth external electrodes can be suppressed.
  • the electronic component includes a third external electrode having a third portion disposed on the third outer peripheral surface, and a fourth external electrode having a fourth portion disposed on the fourth outer peripheral surface.
  • the third portion of the third external electrode is disposed in a region closer to the electrode having the greater distance from the third outer peripheral surface of the first external electrode and the second external electrode than the center of the third outer peripheral surface.
  • the fourth portion of the fourth external electrode is disposed in a region closer to the electrode having the greater distance from the fourth outer peripheral surface of the first external electrode and the second external electrode than the center of the fourth outer peripheral surface. .
  • the third portion of the third external electrode is closer to the electrode having the greater distance from the third outer peripheral surface of the first and second external electrodes than the center of the third outer peripheral surface. Placed in the area. Accordingly, the distance between the third external electrode and the electrode having the smaller distance between the third outer peripheral surface and the third external electrode is ensured as compared with the case where the third external electrode is arranged at the center of the third outer peripheral surface. Therefore, it is possible to suppress the deterioration of isolation between the electrode having the smaller distance between the third external electrode and the third outer peripheral surface.
  • the fourth portion of the fourth external electrode is disposed in a region closer to the electrode having the greater distance from the fourth outer peripheral surface of the first and second external electrodes than the center of the fourth outer peripheral surface.
  • FIG. 1 is an external perspective view of an electronic component 1 according to the present embodiment.
  • the electronic component 1 is formed in a rectangular parallelepiped shape by stacking a plurality of rectangular dielectrics.
  • the stacking direction of the dielectric (the height direction of the electronic component 1) is the Z-axis direction.
  • the long side (width) direction of the electronic component 1 is defined as the X-axis direction.
  • the short side (depth) direction of the electronic component 1 is defined as the Y-axis direction.
  • the X axis, the Y axis, and the Z axis are orthogonal to each other.
  • the electronic component 1 has a rectangular parallelepiped shape, and has six outer peripheral surfaces, that is, a top surface UF and a bottom surface BF that are parallel to the XY plane and face each other, and a first that is parallel to the ZX plane and faces each other. It has a side surface SA and a second side surface SB, and a third side surface SC and a fourth side surface SD that are parallel to the YZ plane and face each other.
  • the electronic component 1 includes terminals (external electrodes) P1 to P8 configured to be connectable to external devices.
  • Terminals P1 to P8 are an input port for inputting a high-frequency signal from an external device, an output port for outputting a high-frequency signal to an external device, a ground port terminated with a predetermined resistance value, and a ground port connected to a ground potential Used as such.
  • Each of the terminals P1 to P3 (first external electrode) is provided across the top surface UF, the first side surface SA, and the bottom surface BF.
  • Each of the terminals P4 to P6 (second external electrode) is provided across the top surface UF, the second side surface SB, and the bottom surface BF.
  • the terminal P7 (third external electrode) is provided across the top surface UF, the third side surface SC, and the bottom surface BF.
  • the terminal P8 (fourth external electrode) is provided across the top surface UF, the fourth side surface SD, and the bottom surface BF.
  • the shapes of the terminals P1 to P8 are substantially the same will be described, but the shapes of the terminals P1 to P8 are not necessarily the same.
  • some of the terminals P1 to P8 may have different X-axis widths than the remaining X-axis widths.
  • each of the terminals P1 to P8 may not have a portion arranged on at least one of the upper surface UF and the bottom surface BF. That is, each of the terminals P1 to P3 (first external electrode) has at least a portion disposed on the first side surface SA (more specifically, a portion extending from the upper side to the lower side of the first side surface SA). What is necessary is just to have no part arrange
  • the terminal P7 has at least a portion (more specifically, a portion extending from the upper side to the lower side in the third side surface SC) disposed on the third side surface SC, and is provided on the fourth side surface SD. What is necessary is just to have no part to be arranged.
  • the terminal P8 has at least a portion (more specifically, a portion extending from the upper side to the lower side in the fourth side surface SD) arranged on the fourth side surface SD, and is on the third side surface SC. What is necessary is just to have no part to be arranged.
  • a portion disposed on the first side surface SA of the terminal P1 “a portion disposed on the first side surface SA of the terminal P2”, and “a first side surface SA of the terminal P3”
  • the “placed portion” is also simply referred to as “terminal P1”, “terminal P2”, and “terminal P3”, respectively.
  • “Parts disposed on the second side surface SB of the terminal P4”, “parts disposed on the second side surface SB of the terminal P5”, and “portions disposed on the second side surface SB of the terminal P6” are simply referred to as “terminals”. Also referred to as “P4”, “terminal P5”, and “terminal P6”.
  • the “portion disposed on the third side surface SC of the terminal P7” and the “portion disposed on the fourth side surface SD of the terminal P8” are also simply referred to as “terminal P7” and “terminal P8”, respectively.
  • FIG. 2 is a cross-sectional view of the electronic component 1 cut along a plane parallel to the XY plane.
  • the distance between the first side surface SA and the second side surface SB facing each other is a length LY in the short side direction (Y-axis direction) of the electronic component 1.
  • the distance between the third side surface SC and the fourth side surface SD facing each other is the length LX in the long side direction (X-axis direction) of the electronic component 1.
  • regions where the terminals P1 to P3 are respectively projected onto the second side surface SB along the Y-axis direction are shown as facing regions 11 to 13 facing the terminals P1 to P3 on the second side surface SB, respectively.
  • regions where the terminals P4 to P6 are respectively projected on the first side surface SA along the Y-axis direction are shown as regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA.
  • a region where the terminal P8 is projected on the third side surface SC along the X-axis direction is shown as a region 18 facing the terminal P8 on the third side surface SC.
  • a region where the terminal P7 is projected on the fourth side surface SD along the X-axis direction is shown as a region 17 facing the terminal P7 on the fourth side surface SD.
  • the terminals P1 to P3 are arranged on the first side surface SA.
  • the terminals P4 to P6 are disposed on the second side surface SB that faces the first side surface SA.
  • the terminal P7 is disposed on the third side surface SC.
  • the terminal P8 is disposed on the fourth side surface SD facing the third side surface SC.
  • the terminals P1 to P3 are respectively disposed in the facing regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA, the facing area between each of the terminals P1 to P3 and each of the terminals P4 to P6 increases. For this reason, capacitive coupling occurs between the terminals facing each other, which may lead to deterioration of isolation.
  • the terminal P7 is disposed in the region 18 facing the terminal P8 on the third side surface SC, the opposing terminals P7 and P8 are capacitively coupled to each other, which may lead to deterioration of isolation.
  • the degree of capacitive coupling between the opposing terminals is proportional to the opposing area between the terminals and inversely proportional to the distance between the terminals.
  • the distance between the terminals (the length LY in the short side direction, or Since the length LX) in the long side direction is shortened and the capacitive coupling between the terminals is further increased, there is a concern that the isolation is further deteriorated.
  • the distance LY between the first side surface SA and the second side surface SB is shorter than the distance LX between the third side surface SC and the fourth side surface SD, and accordingly, the degree of capacitive coupling between the terminals P1 to P3 and the terminals P4 to P6. There is a concern that it will become larger.
  • the terminals P1 to P3 are arranged in a region that is out of any of the regions 14 to 16 facing the terminals P4 to P6 on the first side surface SA.
  • the terminals P4 to P6 are arranged in a region outside any of the regions 11 to 13 facing the terminals P1 to P3 on the second side surface SB.
  • terminals P1 to P3 first external electrodes
  • terminals P4 to P6 second external electrodes
  • the facing area between the terminals P1 to P3 and the terminals P4 to P6 becomes 0, the degree of capacitive coupling between each of the terminals P1 to P3 and each of the terminals P4 to P6 can be suppressed to a very small value.
  • the terminal P7 is arranged in a region outside the region 18 facing the terminal P8 on the third side surface SC.
  • the terminal P8 is disposed in a region outside the region 17 facing the terminal P7 on the fourth side surface SD. Therefore, in addition to the capacitive coupling degree between each of the terminals P1 to P3 and each of the terminals P4 to P6, capacitive coupling between the terminals P7 and P8 can be suppressed.
  • the terminal P7 is disposed in a region closer to the terminal P1 than the center CL3 on the third side surface SC.
  • the terminals P1 to P3 (first external electrode) and the terminals P4 to P6 (second external electrode) are arranged in regions that do not face each other, so that the third side surface SC and the terminal P4 (second external electrode) are arranged.
  • the distance to the electrode) is smaller than the distance between the third side surface SC and the terminal P1 (first external electrode).
  • the terminal P7 is disposed at the center CL3 on the third side surface SC, the distance between the terminal P7 and the terminal P4 cannot be secured, and there is a concern that the isolation between the terminal P7 and the terminal P4 deteriorates. . Therefore, in the present embodiment, the terminal P7 is disposed in a region closer to the terminal P1 having a larger distance from the third side SC of the terminals P1 and P4 than the center CL3 of the third side SC. The Thereby, the distance between the terminal P7 and the terminal P4 is ensured as compared with the case where the terminal P7 is arranged at the center CL3 on the third side surface SC. Therefore, it is possible to suppress the deterioration of isolation between the terminal P7 and the terminal P4.
  • the terminal P8 is connected to the terminal P6 having a larger distance from the terminal P3 and the fourth side surface SD among the terminals P6 than the center CL4 in the fourth side surface SD. Arranged in the near area. Thereby, the distance between the terminal P8 and the terminal P3 is ensured as compared with the case where the terminal P8 is arranged at the center CL4 in the fourth side surface SD. Therefore, it is possible to suppress the deterioration of isolation between the terminal P8 and the terminal P3.
  • the terminals P1 to P3 disposed on the first side surface SA and the terminals P4 to P6 disposed on the second side surface SB facing the first side surface SA are both. These are arranged so as not to face each other (the facing area becomes 0). Thereby, the capacitive coupling degree between each of the terminals P1 to P3 and each of the terminals P4 to P6 can be suppressed to a very small value.
  • the terminal P7 disposed on the third side surface SC and the terminal P8 disposed on the fourth side surface SD do not face each other (the facing area becomes 0). Placed in. Thereby, the capacitive coupling degree of the terminal P7 and the terminal P8 can also be suppressed to a very small value.
  • the terminals P7 and P8 are disposed on the third side surface SC and the fourth side surface SD, respectively, but may not include at least one of the terminals P7 and P8.
  • FIG. 3 is an example of a cross-sectional view when the electronic component 1A according to the first modification is cut along a plane parallel to the XY plane.
  • An electronic component 1A according to Modification 1 is obtained by removing the terminals P7 and P8 from the electronic component 1 according to the above-described embodiment.
  • terminals P1 to P3 and the terminals P4 to P6 are arranged so as not to face each other as in the electronic component 1 according to the present embodiment described above, each of the terminals P1 to P3 and the terminal The degree of capacitive coupling with each of P4 to P6 can be suppressed to a very small value.
  • each of the terminals P1 to P3 is disposed in a region that is out of any of the opposing regions 14 to 16, and only a part of each of the terminals P4 to P6 is from any of the opposing regions 11 to 13. May be arranged in a region outside.
  • FIG. 4 is an example of a cross-sectional view when the electronic component 1B according to Modification 2 is cut along a plane parallel to the XY plane.
  • the electronic component 1B according to the second modification differs from the electronic component 1 according to the above-described embodiment only in the arrangement of the terminals P1 to P6.
  • the terminals P1 are arranged in areas outside the opposing areas 14 to 16, but the remaining part is included in the opposing area 14 and the terminals P4 Is facing. Most of the terminal P4 is disposed in a region outside the facing regions 11 to 13, but the remaining part is included in the facing region 11 and faces the terminal P1.
  • the arrangement relationship between the terminals P2 and P5 and the arrangement relationship between the terminals P3 and P6 are the same as the arrangement relationship between the terminals P1 and P4.
  • all of the terminals P1 to P3 are all included in any of the opposing regions 14 to 16, and all of the terminals P4 to P6 are all included in any of the opposing regions 11 to 13.
  • the capacity of the capacitive coupling between the terminals P1 to P3 and the terminals P4 to P6 can be reduced.
  • the example in which the three terminals P1 to P3 are arranged on the first side surface SA and the three terminals P4 to P6 are arranged on the second side surface SB has been described.
  • the number of terminals arranged on the first side surface SA and the number of terminals arranged on the second side surface SB are not limited to three, and may be one or two. There may be four or more.
  • the terminals P1 to P3 disposed on the first side surface SA and the terminals P4 to P6 disposed on the second side surface SB are merely disposed so as not to face each other.
  • the terminal P7 arranged on the third side surface SC and the terminal P8 arranged on the fourth side surface SD are arranged so as not to face each other.
  • the terminal P7 disposed on the third side surface SC and the terminal P8 disposed on the fourth side surface SD may be disposed to face each other.
  • FIG. 5 is an example of a cross-sectional view when the electronic component 1C according to the third modification is cut along a plane parallel to the XY plane.
  • the electronic component 1C according to the third modification is obtained by removing the terminals P3, P5, and P6 from the electronic component 1 according to the above-described embodiment, and further changing the arrangement of the terminals P1, P2, P4, P7, and P8. is there.
  • the distance LY between the first side surface SA and the second side surface SB is shorter than the distance LX between the third side surface SC and the fourth side surface SD, and accordingly, the degree of capacitive coupling between the terminals P1, P2 and the terminal P4 is increased. Is concerned. Therefore, in the electronic component 1C according to the third modification, as shown in FIG. 5, the terminals P1 and P2 arranged on the first side surface SA are arranged in a region away from the facing region 14 and arranged on the second side surface SB.
  • the terminal P4 to be connected is disposed in a region outside the opposing regions 11 and 12. Thereby, the capacitive coupling degree between the terminals P1, P2 and the terminal P4 can be suppressed to a very small value.
  • the distance LX between the third side surface SC and the fourth side surface SD is longer than the distance LY between the first side surface SA and the second side surface SB, and even if the terminal P7 and the terminal P8 face each other, It is assumed that the capacitive coupling degree is a small value. Further, the third side surface SC and the fourth side surface SD are smaller in width than the first side surface SA and the second side surface SB, and the area where the terminals can be arranged is narrow.
  • the terminal P7 disposed on the third side surface SC is disposed in the facing region 18, and the terminal P8 disposed on the fourth side surface SD is opposed.
  • region 17 Arranged in region 17.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

Un composant électronique (1) comporte : une pluralité de bornes (P1-P3) disposées sur une première surface latérale (SA) ; et une pluralité de bornes (P4-P6) disposées sur une seconde surface latérale (SB) opposée à la première surface latérale (SA). La pluralité de bornes (P1-P3) disposées sur la première surface latérale (SA) sont situées dans une région de la première surface latérale (SA) autre que toutes les régions (14-16) opposées à la pluralité de bornes (P4-P6) disposées sur la seconde surface latérale (SB). La pluralité de bornes (P4-P6) disposées sur la seconde surface latérale (SB) sont situées dans une région de la seconde surface latérale (SB) autre que toutes les régions (11-13) opposées à la pluralité de bornes (P1-P3) disposées sur la première surface latérale (SA).
PCT/JP2018/010973 2017-04-28 2018-03-20 Composant électronique Ceased WO2018198600A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW107113730A TWI675386B (zh) 2017-04-28 2018-04-23 電子零件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017090373 2017-04-28
JP2017-090373 2017-04-28

Publications (1)

Publication Number Publication Date
WO2018198600A1 true WO2018198600A1 (fr) 2018-11-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/010973 Ceased WO2018198600A1 (fr) 2017-04-28 2018-03-20 Composant électronique

Country Status (2)

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TW (1) TWI675386B (fr)
WO (1) WO2018198600A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02117933U (fr) * 1989-03-13 1990-09-21
WO2008015899A1 (fr) * 2006-08-02 2008-02-07 Murata Manufacturing Co., Ltd. Élément de filtre et procédé de fabrication d'un élément de filtre
JP2008078664A (ja) * 2006-09-22 2008-04-03 Samsung Electro-Mechanics Co Ltd 積層型チップキャパシタ
US20110090665A1 (en) * 2009-10-16 2011-04-21 Avx Corporation Thin film surface mount components

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006286731A (ja) * 2005-03-31 2006-10-19 Tdk Corp 積層コンデンサ
JP5652542B2 (ja) * 2011-03-14 2015-01-14 株式会社村田製作所 方向性結合器
TWM527148U (zh) * 2016-03-29 2016-08-11 Yageo Corp 具有多個端電極的積層電容器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02117933U (fr) * 1989-03-13 1990-09-21
WO2008015899A1 (fr) * 2006-08-02 2008-02-07 Murata Manufacturing Co., Ltd. Élément de filtre et procédé de fabrication d'un élément de filtre
JP2008078664A (ja) * 2006-09-22 2008-04-03 Samsung Electro-Mechanics Co Ltd 積層型チップキャパシタ
US20110090665A1 (en) * 2009-10-16 2011-04-21 Avx Corporation Thin film surface mount components

Also Published As

Publication number Publication date
TW201905947A (zh) 2019-02-01
TWI675386B (zh) 2019-10-21

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