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WO2018193760A1 - Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur Download PDF

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Publication number
WO2018193760A1
WO2018193760A1 PCT/JP2018/010087 JP2018010087W WO2018193760A1 WO 2018193760 A1 WO2018193760 A1 WO 2018193760A1 JP 2018010087 W JP2018010087 W JP 2018010087W WO 2018193760 A1 WO2018193760 A1 WO 2018193760A1
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WO
WIPO (PCT)
Prior art keywords
solder
semiconductor device
copper
solder material
copper fiber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2018/010087
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English (en)
Japanese (ja)
Inventor
隆 齊藤
谷口　克己
英司 望月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2019513270A priority Critical patent/JP7006686B2/ja
Publication of WO2018193760A1 publication Critical patent/WO2018193760A1/fr
Anticipated expiration legal-status Critical
Priority to JP2021182888A priority patent/JP7509358B2/ja
Ceased legal-status Critical Current

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C12/00—Alloys based on antimony or bismuth
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • the power semiconductor module includes one or a plurality of power semiconductor chips to constitute part or all of the conversion connection, and the power semiconductor chip and the laminated substrate or the metal substrate are electrically insulated. It is a power semiconductor device with Power semiconductor modules are used in motor drive control inverters such as elevators for industrial purposes. Further, in recent years, it has been widely used for in-vehicle motor drive control inverters. In-vehicle inverters are required to have long-term reliability in high-temperature operation because they are reduced in size and weight to improve fuel efficiency and are disposed near the drive motor in the engine room.
  • the structure of a conventional power semiconductor module will be described by taking a general IGBT (Insulated Gate Bipolar Transistor) power semiconductor module structure as an example.
  • IGBT Insulated Gate Bipolar Transistor
  • FIG. 9 is a cross-sectional view showing a configuration of a power semiconductor module having a conventional structure.
  • the power semiconductor module includes a power semiconductor chip 1, an insulating substrate 2, an electrode pattern 3, a conductive plate 9 disposed on the back surface of the insulating substrate 2, a solder material 14, and a heat sink 5. And a cooling body 7, a metal wire 10, an external terminal 11, a terminal case 12, and a sealing material 13.
  • the power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip.
  • An electrode pattern 3 and a conductive plate 9 are provided on both surfaces of the insulating substrate 2.
  • the power semiconductor chip 1 is bonded by a solder material 14 that is a bonding material.
  • the heat radiating plate 5 is joined with a solder material 14.
  • the heat radiating plate 5 is joined via a heat radiating grease 6 to a cooling body 7 provided with heat radiating fins.
  • a substrate provided with the electrode pattern 3 on at least one surface of the insulating substrate 2 is called a laminated substrate.
  • a metal wire 10 is connected to the electrode pattern 3 on the upper surface of the power semiconductor chip 1 as a wiring for electrical connection.
  • a metal external terminal 11 for external connection is provided on the upper surface of the electrode pattern 3. Further, in order to protect the power semiconductor chip 1 from insulation, the terminal case 12 is filled with a sealing material 13 such as silicon gel having a low elastic modulus and packaged with a lid (not shown).
  • a sealing material 13 such as silicon gel having a low elastic modulus
  • the in-vehicle power semiconductor module is required to be smaller and lighter than the industrial power semiconductor module due to restrictions on the installation space. Further, since the output power density for driving the motor is increased, the temperature of the semiconductor chip during operation is increased, and the demand for long-term reliability during high-temperature operation is increasing. For this reason, a power semiconductor module structure having high temperature operation and long-term reliability has been demanded.
  • the power semiconductor module having the above configuration is provided with a cooling body 7 provided with heat radiating fins, and heat generated by the power semiconductor chip 1 due to energization is transferred to the heat radiating fins to dissipate heat outside the system. If the surface of the cooling body 7 and the surface of the heat radiating plate 5 are not in close contact with each other, the contact thermal resistance between them increases and the heat dissipation performance decreases.
  • the heat sink 5 and the cooling body 7 are finished so that the surface flatness and the surface roughness are as small as possible.
  • the thermal contact resistance between the heat sink 5 and the cooling body 7 is kept low by applying a thermal compound.
  • the power semiconductor chip 1 and the electrode pattern 3 and the conductive plate 9 and the heat radiating plate 5 are joined using a solder material 14.
  • a solder material 14 For example, Pb (lead) -free solder is bonded to the lower portion of the power semiconductor chip 1 by a paste solder or flux solder containing flux.
  • solder As a Pb-free solder used in a semiconductor module, there is a composite solder having a configuration in which a metal net made of Cu (copper) is sandwiched between two solder foils and used for temperature layer connection such as die bonding of a semiconductor chip. (For example, refer to Patent Document 1).
  • the thermal conductivity of the solder material 14 used for bonding under the power semiconductor chip 1 is 40 to 60 W / m ⁇ K. This value is lower than the thermal conductivity of copper, 390 W / m ⁇ K. For this reason, since the generated heat of the power semiconductor chip 1 due to energization cannot be sufficiently transferred to the electrode pattern 3 and the generated heat cannot reach the radiation fin, there is a problem that the power semiconductor chip 1 cannot be sufficiently cooled. . Moreover, since the thermal conductivity of the solder material 14 is low, the temperature of the solder material 14 itself increases, cracks are generated in the solder material 14, the thermal resistance increases, and the heat dissipation performance further decreases.
  • the present invention can efficiently dissipate heat generated from a power semiconductor chip, and can suppress the occurrence of cracks in solder and increase in thermal resistance.
  • An object is to provide a manufacturing method.
  • a semiconductor device has the following characteristics.
  • a semiconductor device has an assembly structure in which a semiconductor element is mounted on a laminated substrate.
  • a bonding layer for bonding the semiconductor element and the electrode pattern on the laminated substrate includes a metal fiber, and a solder material in which a space between the metal fibers is filled with solder is used.
  • the solder material is used as the bonding layer for bonding the semiconductor element and the wiring for electrical connection between the semiconductor element and the electrode pattern on the multilayer substrate. It is used.
  • the assembly structure further includes a heat sink on which the multilayer substrate is mounted, and a bonding layer that joins the multilayer substrate and the heat sink is the solder. Material is used.
  • the metal fiber included in the solder material is disposed in a central portion, and a predetermined distance from an end portion of the bonding layer.
  • the metal fiber is not arranged.
  • the predetermined distance is not less than 0.1 mm and not more than 1 mm.
  • the metal fiber included in the solder material is disposed on the semiconductor element, the laminated substrate, and the heat dissipation plate side, and the metal fiber A solder having a predetermined thickness is disposed therebetween.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the predetermined thickness is not less than 5 ⁇ m and not more than 20 ⁇ m.
  • the predetermined thickness is 5% to 20% of the thickness of the solder material.
  • the diameter of the metal fiber is equal to or less than the thickness of the solder material.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is a copper fiber.
  • the metal fiber has a diameter of 20 ⁇ m or less in the above-described invention.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fibers have contacts with each other.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder does not contain copper.
  • the solder is a Sn—Sb solder containing Ni or Co, a Sn—Bi solder containing Ni or Co, or Sn. -Ag-based solder containing Ni or Co.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is Ni-plated.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal fiber is Co-plated.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the space between the metal fibers is filled with a sintered material of Ag or Cu.
  • the semiconductor device according to the present invention is characterized in that, in the above-described invention, the solder material is formed by folding the metal fibers in two or more layers.
  • a semiconductor device manufacturing method has the following characteristics. First, a step of mounting the semiconductor element on the multilayer substrate by joining the electrode pattern on the multilayer substrate and the semiconductor element using a solder material containing metal fibers and filled with solder between the metal fibers I do. A step of assembling the laminated substrate into a laminated assembly is performed. Next, a step of electrically connecting the semiconductor element and the electrode pattern on the laminated substrate is performed. Next, a process of combining the laminated assembly with a resin case is performed.
  • the solder element in the electrically connecting step, is used to electrically connect the semiconductor element and the electrode pattern on the multilayer substrate. It is characterized by being connected.
  • the multilayer substrate in the above-described invention, is joined to a heat radiating plate of the multilayer assembly using the solder material. .
  • the joining portion that joins the power semiconductor element and the electrode pattern is a copper fiber-containing solder material that includes copper fibers and is filled with solder between the copper fibers.
  • the copper fibers have contact points with each other to form a heat path, an increase in thermal resistance can be suppressed even if cracks occur in the solder.
  • the same handling as the conventional one can be performed, and the solder thickness can be controlled more uniformly than the conventional one.
  • the semiconductor device and the method for manufacturing the semiconductor device of the present invention it is possible to efficiently dissipate the heat generated by the power semiconductor chip, and to suppress the occurrence of cracks in the solder and an increase in thermal resistance.
  • FIG. 1 is a cross-sectional view illustrating a configuration of a power semiconductor module according to an embodiment.
  • FIG. 2 is a sectional view showing details of a solder material for joining the power semiconductor chip and the electrode pattern (part 1).
  • FIG. 3 is a sectional view showing details of a solder material for joining the power semiconductor chip and the electrode pattern (part 2).
  • FIG. 4 is a table showing the results of the solder power cycle test according to the embodiment.
  • FIG. 5 is a graph showing the relationship between solder thickness and equivalent thermal conductivity.
  • FIG. 6 is a graph showing the relationship between copper occupancy and equivalent thermal conductivity.
  • FIG. 7 is a cross-sectional view showing an example of a copper fiber-containing solder material.
  • FIG. 8 is a cross-sectional view of a joint portion of an example of a copper fiber-containing solder material.
  • FIG. 9 is a cross-sectional view showing a configuration of a power semiconductor module having a conventional structure.
  • FIG. 1 is a cross-sectional view illustrating a configuration of a power semiconductor module according to an embodiment.
  • the power semiconductor module has a power semiconductor chip 1, an insulating substrate 2, an electrode pattern 3, a joint 4, a heat sink 5, a lead frame wiring 8, and a back surface of the insulating substrate 2.
  • a conductive plate 9 is provided.
  • the power semiconductor chip 1 and the electrode pattern 3 are connected using the lead frame wiring 8, but may be connected using a metal wire 10 as in the conventional structure.
  • the power semiconductor chip 1 is a semiconductor element such as an IGBT or a diode chip.
  • an insulating substrate 2 such as a ceramic substrate that ensures insulation.
  • an electrode pattern made of a conductive plate such as copper (Cu) 3 etc. are provided on the front surface (power semiconductor chip 1 side) and back surface (heat sink 5 side) of an insulating substrate 2 such as a ceramic substrate that ensures insulation.
  • surface of the insulated substrate 2 is set as a laminated substrate.
  • the power semiconductor chip 1 is bonded at the bonding portion 4.
  • a heat radiating plate 5 is joined at the joint 4.
  • the heatsink 5 is joined to a cooling body (not shown) provided with heatsink fins.
  • a conductive plate such as copper on the front surface of the multilayer substrate is referred to as an electrode pattern
  • a conductive plate such as copper on the back surface is referred to as a conductive plate.
  • one end of a lead frame wiring 8 is bonded to the upper surface of the power semiconductor chip 1 (the surface opposite to the surface in contact with the bonding portion 4) at the bonding portion 4 as a wiring for electrical connection.
  • the other end of the lead frame wiring 8 is joined to the electrode pattern 3.
  • the joint portion of the present invention is used in places where a solder material is used in a conventional semiconductor module.
  • the joint 4 is formed of a metal fiber-containing solder material including a metal fiber member.
  • the metal fiber-containing solder material includes a fibrous metal (hereinafter referred to as metal fiber), the metal fibers have contact points with each other to form a heat path, and the metal fibers are filled with solder.
  • the metal is preferably a metal having high thermal conductivity, such as copper.
  • the fibrous copper is referred to as a copper fiber
  • the joint portion 4 is referred to as a copper fiber-containing solder material 4.
  • copper fibers will be described.
  • the fibrous shape means an elongated shape, that is, a length that is extremely large with respect to the diameter. In the embodiment, the diameter of one copper fiber is preferably 20 ⁇ m or less.
  • the length of the copper fiber is preferably 50 ⁇ m or more, more preferably 1 mm or more. This is because the contact length between the copper fibers is increased and the three-dimensional structure is easily obtained when the length is set. Moreover, it is preferable that length is 10 mm or less which is the length of a copper fiber member.
  • the contact point is a point where the copper fiber of the copper fiber-containing solder material 4 is in contact with another copper fiber.
  • the copper fiber member is formed of a plurality of copper fibers.
  • the copper fiber member may have a cloth shape in which copper fibers are woven like a woven fabric, or may be formed in a net shape or a mesh shape. A plurality of these cloth-like or net-like copper fibers may be laminated. Further, a plurality of fibers may be randomly accumulated and laminated to form a sheet. Furthermore, you may pressurize the laminated sheet form and pressure-bond copper fibers. Moreover, it is preferable that these are shape
  • the thickness of the sheet-like copper fiber member is preferably 50 ⁇ m to 200 ⁇ m.
  • the space between the copper fibers may be filled with a sintered material of silver (Ag) or Cu instead of filling with solder.
  • the copper fiber-containing solder material 4 includes copper fibers having contact points and forming a heat path, and is different from a solder material including spherical copper.
  • the heat path is a path for transferring heat generated by the power semiconductor chip or the like.
  • a solder material containing spherical copper has fewer heat paths than copper fibers, has a large thermal resistance, and does not differ in bonding strength from the solder itself.
  • positions metals, such as plate-shaped or foil-shaped copper, in a solder joining strength and heat conductivity like a copper fiber member containing solder are not obtained.
  • the thickness of the solder layer itself does not change in order to obtain a predetermined bonding strength even if a copper plate or the like is arranged in the solder. That is, the thermal resistance does not change.
  • the thermal resistance is lowered and the bonding strength can be improved.
  • the copper fiber-containing solder material 4 is formed by weaving and sintering copper fibers to form a copper fiber member that is folded so that the fibers have contact with each other, and soldering the copper fiber member with solder. Wood may be used. It can be handled as sheet solder by soaking solder in advance. Specifically, a copper fiber-containing solder in which a copper fiber member is impregnated with solder is formed in advance, and the solder can be placed between the materials to be joined and heated to be joined. Further, when assembling the semiconductor module, the solder and the copper fiber member may be disposed between the materials to be joined and heated to be joined. Here, it is preferable that two or more copper fibers are folded.
  • That two or more layers are folded means that there are two or more copper fibers having contacts in the thickness direction (the direction from the power semiconductor chip 1 to the heat sink 5).
  • the copper fiber is folded into three layers.
  • the copper occupancy is higher than that processed into a mesh shape.
  • the copper and the copper fiber member have a total copper content.
  • the copper occupation ratio of the fiber member is 22 to 30% by weight. The higher the copper occupancy ratio of the copper fiber member, the better the thermal conductivity. Accordingly, the copper occupation ratio of the copper fiber members of various forms is preferably 5 to 50% by weight, and more preferably 20 to 30% by weight.
  • the thermal conductivity of the copper fiber-containing solder material 4 is improved, and the generated heat can be efficiently radiated.
  • the copper fiber is contained in the solder, even if a crack is generated in the solder, the crack is detoured and progresses, so that the bonding strength is improved.
  • copper fiber itself has intensity
  • the thickness of the copper fiber containing solder material 4 can be made uniform by using said sheet-like copper fiber member.
  • the power semiconductor chip 1 is displaced when placed on the solder material, or the solder material flows at the time of heat joining, and the thickness of the copper fiber-containing solder material 4 It was difficult to make uniform.
  • the above-described problems can be solved, and the thickness of the copper fiber-containing solder material 4 can be made uniform.
  • the copper fiber-containing solder material 4 is used under the power semiconductor chip 1, that is, in the bonding layer between the power semiconductor chip 1 and the electrode pattern 3 in order to efficiently diffuse the heat generated by the power semiconductor chip 1. Is preferred. Further, the copper fiber-containing solder material 4 may be used for a bonding layer between the conductive plate 9 and the heat sink 5 and a bonding layer between the power semiconductor chip 1 and the lead frame wiring 8.
  • the power semiconductor chip 1 is mounted on the multilayer substrate by bonding the power semiconductor chip 1 to the multilayer substrate using the copper fiber-containing solder material 4.
  • the copper fiber-containing solder material 4 may be prepared by impregnating a copper fiber member with solder before the manufacture of the power semiconductor module.
  • the copper fiber member and the solder may be overlapped, and for example, the copper fiber member may be sandwiched by the solder to produce the copper fiber-containing solder material 4.
  • the power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 are electrically connected by the lead frame wiring 8.
  • these are joined to the heat sink 5 to assemble a laminated assembly including the power semiconductor chip 1, the laminated substrate, and the heat sink 5.
  • a resin case is bonded to the laminated assembly with an adhesive such as silicon.
  • the power semiconductor chip 1 and the electrode pattern 3 provided on the insulating substrate 2 may be electrically connected with a metal wire.
  • the electrode pattern 3 and the metal external terminal 11 are connected with a metal wire, and a sealing material such as a hard resin such as epoxy is filled in the resin case.
  • a sealing material such as a hard resin such as epoxy
  • the power semiconductor module according to the embodiment shown in FIG. 1 is completed.
  • the sealing material is not a sealing material such as an epoxy resin, a lid is attached to prevent the sealing material from leaking outside.
  • Copper fiber-containing solder material 4 is disposed on substantially the entire back surface of the power semiconductor chip.
  • 2 and 3 are cross-sectional views showing details of the solder material for joining the power semiconductor chip and the electrode pattern.
  • the copper fiber member 20 is arrange
  • the solder 23 which does not contain copper fiber in the power semiconductor chip 1 or the electrode pattern 3 side.
  • the thickness of each solder 23 is preferably 25 ⁇ m to 100 ⁇ m. This is because, within this range, both joint strength and void reduction can be achieved.
  • the copper fiber member 20 has a structure in which copper fibers are bent in a complicated manner and intersect each other, and depletion exists. At the time of heat bonding, the solder is impregnated in the copper fiber member 20, but it tends to become a void in the vicinity of the depletion. However, it is presumed that the void is easily discharged by separating the predetermined distance d, and as a result, the void is reduced.
  • the distance d is preferably 0.1 mm or more and 1 mm or less regardless of the size of the power semiconductor chip 1. More preferably. It is 0.2 mm or more. This is because if it is shorter than 0.1 mm, a void is generated, the bonding property with the electrode pattern 3 is deteriorated, and the control becomes difficult.
  • the copper fiber member 20 may sandwich the solder 23 inside the copper fiber-containing solder material 4. In this case, there is a layer of solder 23 having a predetermined thickness t between the copper fiber member layers.
  • thermal conductivity improves.
  • the form of FIG. 3 is more thermally conductive than the form of FIG. 2 in which the solder 23 is present on the power semiconductor chip 1 or electrode pattern 3 side.
  • the thickness t of the central part is preferably 5 ⁇ m or more and 20 ⁇ m or less.
  • the thickness t is preferably 5% to 20% in proportion to the thickness of the copper fiber-containing solder material 4.
  • a solder having a specific composition in the solder of the copper fiber-containing solder material effects of joint strength and thermophysical properties can be produced.
  • a Cu-free solder that suppresses diffusion of copper and copper alloy of the copper fiber is preferable.
  • the portion that conducts heat decreases and the thermal conductivity decreases, so that the diffusion of copper and copper alloy can be suppressed.
  • Nickel (Ni), cobalt (Co) Is preferably put into the solder. Note that Cu-free means that Cu is not included except for the degree of impurities.
  • Sn— (5-10) Sb— (0.1-1) Ni, Co solder in which Ni and Co are added to Sn—Sb (antimony) solder (Example 1) Is preferably used.
  • the unit here is% by weight (wt%).
  • Sb is contained in the solder.
  • Ni and Co have the same effect, only Ni or Co may be included.
  • Ni and Co are more preferably contained in the solder in an amount of 0.2 to 0.5% by weight.
  • Sn- (40-70) Bi- (0.1-1) Ni, Co solder (Example 2) in which Ni and Co are added to Sn-Bi (bismuth) solder. Since the solder having this composition is brittle, it cannot normally be used for joining the power semiconductor chip 1. However, it has sufficient strength when used together with the copper fiber member as in the embodiment, so that the power semiconductor chip 1 can be joined. Can be used. Ni and Co are the same as the Sn—Sb solder.
  • Sn— (1-6) Ag— (0.1-1) Ni, Co solder (Example 3) in which Ni and Co are added to Sn—Ag (silver) solder. Ni and Co are the same as the Sn—Sb solder.
  • FIG. 4 is a table showing the results of the power cycle test of the solder according to the embodiment.
  • Sn—Sb—Cu—Ni based solder was also tested as a comparative example.
  • Ni and Co were contained by 0.4 weight% in solder.
  • the number of times the thermal resistance increased by 20% or more from the initial stage was measured by repeatedly turning on / off the power source.
  • Example 1 to Example 3 the thermal resistance did not increase by 20% or more from the initial stage even when the power was turned on / off 100,000 times or more.
  • the thermal resistance did not increase by 20% or more from the initial stage even after repeating 200,000 times or more.
  • the thermal resistance increased by 20% or more from the initial stage after repeating 50,000 times or less.
  • FIG. 5 is a graph showing the relationship between solder thickness and equivalent thermal conductivity.
  • the horizontal axis represents the total thickness of the upper and lower solders, the unit is ⁇ m, the vertical axis is the equivalent thermal conductivity, and the unit is W / m ⁇ K.
  • the equivalent thermal conductivity is a thermal conductivity that is given by considering a component composed of a plurality of materials as one block.
  • the distance d from the edge part of the copper fiber containing solder material 4 to the edge of a copper fiber member was 0.5 mm.
  • the thermal conductivity of solder is 40 W / m ⁇ K
  • the thermal conductivity of copper is 390 W / m ⁇ K
  • the copper occupation ratio of the copper fiber member is 22%
  • the thickness of the copper fiber member is 100 ⁇ m. It is a calculation result in the case.
  • FIG. 6 is a graph showing the relationship between copper occupancy and equivalent thermal conductivity.
  • the horizontal axis represents the copper occupancy, the unit is weight%, the vertical axis is the equivalent thermal conductivity, and the unit is W / m ⁇ K.
  • the copper occupation ratio is the weight% of copper contained in the copper fiber member, and the remainder is the weight of solder.
  • the straight line ⁇ represents the copper occupancy x and the equivalent heat conduction when the upper solder thickness, the copper fiber member thickness, and the lower solder thickness are 10 ⁇ m, 100 ⁇ m, and 10 ⁇ m, respectively.
  • y 3.25x + 6.6667 It is represented by
  • FIG. 7 is a cross-sectional view showing an example of the copper fiber-containing solder material 4.
  • the copper fiber-containing solder material 4 includes a copper fiber portion 22 that is folded so that the copper fibers have contact with each other, and a solder immersion portion 21 in which solder has soaked between the copper fiber members 20. It consists of.
  • FIG. 8 is a cross-sectional view of a joint portion of an example of a copper fiber-containing solder material.
  • the right figure is an enlargement of the center of the left figure.
  • the copper fibers 20 have contact points with each other and the space between the copper fibers 20 is filled with the solder 23.
  • the thermal conductivity of the copper fiber-containing solder material thus prepared is 72.2 W / m ⁇ K in calculation.
  • the thermal conductivity is about 40 W / m ⁇ K only with the Sn—Sb solder, but the thermal conductivity is up to 75.8 W / m ⁇ K with the copper fiber-containing solder material.
  • the laser flash method is to obtain a thermal diffusivity by uniformly heating the surface of a flat sample placed in an adiabatic vacuum and observing a one-dimensional thermal diffusion phenomenon from the front surface to the back surface. Is the method.
  • the joining portion that joins the power semiconductor element and the electrode pattern includes the copper fiber, and the copper fiber-containing portion is filled with the solder between the copper fibers.
  • It is a solder material.
  • the copper fibers have contact points with each other to form a heat path, an increase in thermal resistance can be suppressed even if cracks occur in the solder.
  • the same handling as the conventional one can be performed, and the solder thickness can be controlled more uniformly than the conventional one.
  • the copper fiber-containing solder material has an internal copper fiber arranged in the center, the internal copper fiber is arranged away from the power semiconductor element and the electrode pattern, and the copper fiber-containing solder material has an copper fiber at the end. Is not placed. Thereby, the generated heat of the power semiconductor chip can be dissipated from the central portion where the copper fibers are arranged, the voids can be reduced, and the bondability can be improved.
  • the copper fiber-containing solder material is joined by sandwiching the solder between the copper fibers, and the copper fibers are arranged on the power semiconductor chip or electrode pattern side.
  • thermal conductivity further improves.
  • the thermal conductivity is improved by about 5% as compared with the above result where the copper fiber member is sandwiched between the solder.
  • the copper fiber member and the solder had the same thickness.
  • voids are less likely to occur in the vicinity of the copper fiber.
  • the composition of the solder contained in the copper fiber-containing solder material is Sn- (5-10) Sb- (0.1-1) Ni, Co, Sn- (40-70) Sb- (0.1-1). ) Ni, Co, or Sn- (1-6) Sb- (0.1-1) Ni, Co. Ni and Co can suppress the diffusion of copper and copper alloy of the copper fiber, and can suppress a decrease in thermal conductivity. Furthermore, by using these solders, effects of bonding strength and thermophysical properties can be produced.
  • Ni plating or Co plating may be applied to the copper fiber.
  • Ni and Co can suppress the diffusion of copper and copper alloy of the copper fiber, and can suppress a decrease in thermal conductivity.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for power conversion devices such as inverters, power supply devices such as various industrial machines, and power semiconductor devices used for automobile igniters. is there.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Air Conditioning Control Device (AREA)
PCT/JP2018/010087 2017-04-18 2018-03-14 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur Ceased WO2018193760A1 (fr)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021111633A (ja) * 2020-01-06 2021-08-02 日立Astemo株式会社 半導体装置
CN114222638A (zh) * 2019-08-05 2022-03-22 日本斯倍利亚社股份有限公司 焊料－金属网格复合材料及其制造方法
JP7133739B1 (ja) 2021-11-30 2022-09-08 株式会社タムラ製作所 接合部、電子回路基板及び半導体パッケージ
DE102021119288A1 (de) 2021-07-26 2023-01-26 Infineon Technologies Ag Elektronisches System, welches eine intermetallische Verbindungsstruktur mit einer zentralen intermetallischen Netzstruktur und netzfreie äußere Strukturen hat
WO2023248302A1 (fr) * 2022-06-20 2023-12-28 三菱電機株式会社 Élément de liaison de brasure, dispositif semi-conducteur, procédé de liaison de brasure et procédé de production de dispositif semi-conducteur
WO2025037640A1 (fr) * 2023-08-17 2025-02-20 株式会社巴川コーポレーション Couche de liaison, dispositif de transfert de chaleur et procédé de production de couche de liaison
DE102021119288B4 (de) 2021-07-26 2025-09-25 Infineon Technologies Ag Elektronisches System, welches eine intermetallische Verbindungsstruktur mit einer zentralen intermetallischen Netzstruktur und netzfreie äußere Strukturen hat sowie Verfahren zum Herstellen eines elektronischen Systems

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002301588A (ja) * 2000-12-21 2002-10-15 Hitachi Ltd はんだ箔および半導体装置および電子装置
JP2004174522A (ja) * 2002-11-25 2004-06-24 Hitachi Ltd 複合はんだ、その製造方法および電子機器
JP2008004651A (ja) * 2006-06-21 2008-01-10 Hitachi Ltd 異方性微粒子を用いた接合材料
JP2008153470A (ja) * 2006-12-18 2008-07-03 Renesas Technology Corp 半導体装置および半導体装置の製造方法
JP2010179336A (ja) * 2009-02-05 2010-08-19 Toyota Central R&D Labs Inc 接合体、半導体モジュール、及び接合体の製造方法
JP2014086607A (ja) * 2012-10-25 2014-05-12 Nissan Motor Co Ltd Ａｕ系はんだダイアタッチメント半導体装置及びその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6093170B2 (ja) 2012-12-19 2017-03-08 富士紡ホールディングス株式会社 ダイヤモンドラッピング用樹脂定盤及びそれを用いたラッピング方法
JP2014175454A (ja) 2013-03-08 2014-09-22 Mitsubishi Electric Corp 電力用半導体装置および電力用半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002301588A (ja) * 2000-12-21 2002-10-15 Hitachi Ltd はんだ箔および半導体装置および電子装置
JP2004174522A (ja) * 2002-11-25 2004-06-24 Hitachi Ltd 複合はんだ、その製造方法および電子機器
JP2008004651A (ja) * 2006-06-21 2008-01-10 Hitachi Ltd 異方性微粒子を用いた接合材料
JP2008153470A (ja) * 2006-12-18 2008-07-03 Renesas Technology Corp 半導体装置および半導体装置の製造方法
JP2010179336A (ja) * 2009-02-05 2010-08-19 Toyota Central R&D Labs Inc 接合体、半導体モジュール、及び接合体の製造方法
JP2014086607A (ja) * 2012-10-25 2014-05-12 Nissan Motor Co Ltd Ａｕ系はんだダイアタッチメント半導体装置及びその製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114222638A (zh) * 2019-08-05 2022-03-22 日本斯倍利亚社股份有限公司 焊料－金属网格复合材料及其制造方法
CN114222638B (zh) * 2019-08-05 2024-03-12 日本斯倍利亚社股份有限公司 焊料－金属网格复合材料及其制造方法
JP2021111633A (ja) * 2020-01-06 2021-08-02 日立Astemo株式会社 半導体装置
JP7421935B2 (ja) 2020-01-06 2024-01-25 日立Astemo株式会社 半導体装置
DE102021119288A1 (de) 2021-07-26 2023-01-26 Infineon Technologies Ag Elektronisches System, welches eine intermetallische Verbindungsstruktur mit einer zentralen intermetallischen Netzstruktur und netzfreie äußere Strukturen hat
DE102021119288B4 (de) 2021-07-26 2025-09-25 Infineon Technologies Ag Elektronisches System, welches eine intermetallische Verbindungsstruktur mit einer zentralen intermetallischen Netzstruktur und netzfreie äußere Strukturen hat sowie Verfahren zum Herstellen eines elektronischen Systems
JP7133739B1 (ja) 2021-11-30 2022-09-08 株式会社タムラ製作所 接合部、電子回路基板及び半導体パッケージ
JP2023081268A (ja) * 2021-11-30 2023-06-09 株式会社タムラ製作所 接合部、電子回路基板及び半導体パッケージ
WO2023248302A1 (fr) * 2022-06-20 2023-12-28 三菱電機株式会社 Élément de liaison de brasure, dispositif semi-conducteur, procédé de liaison de brasure et procédé de production de dispositif semi-conducteur
WO2025037640A1 (fr) * 2023-08-17 2025-02-20 株式会社巴川コーポレーション Couche de liaison, dispositif de transfert de chaleur et procédé de production de couche de liaison

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