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WO2018193554A1 - Semiconductor device production method - Google Patents

Semiconductor device production method Download PDF

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Publication number
WO2018193554A1
WO2018193554A1 PCT/JP2017/015723 JP2017015723W WO2018193554A1 WO 2018193554 A1 WO2018193554 A1 WO 2018193554A1 JP 2017015723 W JP2017015723 W JP 2017015723W WO 2018193554 A1 WO2018193554 A1 WO 2018193554A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
semiconductor wafer
manufacturing
range
mesa groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2017/015723
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French (fr)
Japanese (ja)
Inventor
小笠原 淳
浩二 伊東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to PCT/JP2017/015723 priority Critical patent/WO2018193554A1/en
Priority to CN201780000855.6A priority patent/CN109121423B/en
Priority to JP2017540673A priority patent/JP6396598B1/en
Priority to TW106126889A priority patent/TWI657512B/en
Publication of WO2018193554A1 publication Critical patent/WO2018193554A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D13/00Electrophoretic coating characterised by the process
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D13/00Electrophoretic coating characterised by the process
    • C25D13/02Electrophoretic coating characterised by the process with inorganic material
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D13/00Electrophoretic coating characterised by the process
    • C25D13/10Electrophoretic coating characterised by the process characterised by the additives used
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D13/00Electrophoretic coating characterised by the process
    • C25D13/12Electrophoretic coating characterised by the process characterised by the article coated

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • lead-free glass fine particles not containing lead are deposited on a mesa groove of a semiconductor wafer by electrophoretic deposition (EPD), and then the lead deposited in the mesa groove.
  • the passivation film of the semiconductor device is formed by baking the free glass fine particles to vitrify.
  • lead-free glass fine particles are deposited on the bottom of the mesa groove of the semiconductor wafer in the glass film forming step by electrophoretic deposition.
  • a passivation film obtained by firing a deposit of lead-free glass fine particles and vitrifying it is also formed at the bottom of the mesa groove.
  • the silicon of the semiconductor wafer and the glass that is a passivation film, that is, a plurality of different materials are used. Need to be cut.
  • the lead-free glass fine particles that cause cracks at the time of cutting of the semiconductor wafer are formed at the bottom of the mesa groove of the semiconductor wafer. There is also a problem of being deposited.
  • the present invention by controlling the characteristics of the suspension used in the glass film forming step, at least a part of the bottom of the mesa groove is exposed (the lead-free glass fine particles are partially formed on at least a part of the bottom of the mesa groove.
  • the glass film of the lead-free glass fine particle deposit can be accurately formed to a predetermined thickness so as to cover the periphery of the opening end of the mesa groove and the side wall of the mesa groove.
  • a method for manufacturing a semiconductor device includes: A semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass coating formation surface, and a suspension in which lead-free glass fine particles are suspended in a solvent, the first electrode plate and the second electrode plate are A state in which the semiconductor wafer is placed between the first electrode plate and the second electrode plate while facing each other while being immersed in the suspension, and the glass film forming surface faces the first electrode plate side A glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition, and a method for manufacturing a semiconductor device, In the glass film forming step, at least a part of the bottom of the mesa groove is exposed, the glass film that is a deposit of the lead-free glass fine particles is formed around the opening end of the mesa groove and the side wall of the mesa groove.
  • the suspension used in the glass film forming step is After controlling the dielectric constant of the solvent containing the lead-free glass fine particles to the first range, a mixed liquid containing an organic solvent and nitric acid as an electrolyte is added to the solvent, and the electric conductivity is set to a second value. Suspension controlled to range The first range of the dielectric constant of the solvent is in the range of 5-7; The second range of the electric conductivity of the suspension is 20 nS / cm to 100 nS / cm.
  • the electrical conductivity of the suspension is controlled in the second range by adjusting the mixed solution.
  • the mixture Before being added to the solvent, the mixture is controlled in electrical conductivity to a third range, and the third range of electrical conductivity of the mixture is 90 ⁇ S / cm to 130 ⁇ S / cm. It is a range.
  • the organic solvent is isopropyl alcohol or ethyl acetate.
  • the electrical conductivity of the mixed liquid is controlled to the third range by adjusting a ratio of the nitric acid in the mixed liquid.
  • the solvent is a mixed solvent containing isopropyl alcohol and ethyl acetate.
  • the dielectric constant of the solvent is controlled to the first range by adjusting a ratio of the ethyl acetate in the mixed solvent.
  • the lead-free glass fine particles are lead-free glass fine particles containing at least one of SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , and BaO.
  • the semiconductor wafer preparation step Preparing a semiconductor wafer having a pn junction parallel to the main surface; Forming an exposed portion of the pn junction on the inner surface of the mesa groove by forming a mesa groove having a depth exceeding the pn junction from one surface of the semiconductor wafer; And a step of forming a base insulating film 121 on the inner surface of the mesa groove so as to cover the exposed portion of the pn junction.
  • the suspension is characterized by not containing a surfactant.
  • the semiconductor wafer preparation step includes a step of forming an exposed portion of a pn junction of a side wall of the mesa groove on the surface of the semiconductor wafer, and forming a base insulating film on the surface of the semiconductor wafer so as to cover the exposed portion of the pn junction And a step of performing.
  • the glass coating forming step is characterized in that the glass coating is formed on the surface of the base insulating film around the opening end of the mesa groove and on the side wall of the mesa groove.
  • the method further comprises forming an anode electrode between two adjacent mesa grooves on the one surface of the semiconductor wafer and forming a cathode electrode on the other surface of the semiconductor wafer.
  • the glass coating covers an exposed portion of the pn junction through the base insulating film.
  • the method further includes a semiconductor wafer cutting step of cutting the semiconductor wafer along the vicinity of the center of the bottom portion of the mesa groove where the glass coating is not formed to form the semiconductor wafer into chips.
  • a method of manufacturing a semiconductor device includes a semiconductor wafer preparation step of preparing a semiconductor wafer W having mesa grooves formed on a glass film forming surface, and a suspension in which lead-free glass fine particles are suspended in a solvent.
  • the first electrode plate and the second electrode plate are placed facing each other in a state of being immersed in the suspension, and the glass film forming surface is disposed between the first electrode plate and the second electrode plate.
  • the glass film forming step at least a part of the bottom of the mesa groove is exposed so that the glass film, which is a deposit of lead-free glass fine particles, covers the periphery of the opening end of the mesa groove and the side wall of the mesa groove.
  • the suspension used in the glass coating formation step is a mixed solution containing an organic solvent and nitric acid as an electrolyte in the solvent after controlling the dielectric constant of the solvent containing lead-free glass fine particles to the first range. (Electrolyte solution) is added and the electric conductivity is controlled to be in the second range. Furthermore, the first range of the dielectric constant of the solvent is in the range of 5-7. Furthermore, the second range of electrical conductivity of the suspension is in the range of 20 nS / cm to 100 nS / cm.
  • the glass film of the lead-free glass fine particle deposit is accurately coated to a predetermined thickness so as to cover the periphery of the opening end of the mesa groove and the side wall of the mesa groove. Can be formed.
  • FIG. 1 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to the first embodiment.
  • FIG. 2 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 1.
  • FIG. 3 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 2.
  • FIG. 4 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 3.
  • FIG. 5 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 4.
  • FIG. 6 is a diagram illustrating steps in the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 5.
  • FIG. 5 is a diagram illustrating steps in the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 5.
  • FIG. 7 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 6.
  • FIG. 8 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 7.
  • FIG. 9 is a cross-sectional view of the glass film forming apparatus 1 as seen from the lateral direction.
  • FIG. 10 is a diagram illustrating an example of the composition of the suspension 12 used in the electrophoretic deposition method of the semiconductor device manufacturing method according to the first embodiment.
  • FIG. 11 is a diagram showing an example of the relationship between the dielectric constant and the ratio of isopropyl alcohol to ethyl acetate in the solvent (1) which is a mixed solvent containing isopropyl alcohol and ethyl acetate.
  • FIG. 12 is a diagram illustrating an example of the relationship between the electrical conductivity of the suspension 12 and the adhesion state of the deposit on the bottom 120 a of the mesa groove 120.
  • FIG. 13 is a photograph of the upper surface of the semiconductor wafer in a state where the glass coating 124 before firing is formed in the glass coating formation step.
  • FIG. 14 is a photograph of a cross section of the mesa groove 120 including the glass coating 124 after firing in the glass coating forming step.
  • the method of manufacturing a semiconductor device according to the first embodiment includes a “semiconductor wafer preparation step”, a “glass film formation step”, an “oxide film removal step”, and a “roughened region”.
  • the “forming process”, “electrode forming process”, and “semiconductor wafer cutting process” are performed in this order.
  • the semiconductor device manufacturing method according to the embodiment will be described below in the order of steps.
  • a p + type diffusion layer 112 is formed by diffusion of p type impurities from one surface of an n ⁇ type semiconductor wafer (for example, an n ⁇ type silicon wafer having a diameter of 4 inches) 110,
  • An n + -type diffusion layer 114 is formed by diffusion of n-type impurities from the other surface to prepare a semiconductor wafer W in which a pn junction parallel to the main surface is formed (FIG. 1).
  • oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (FIG. 1).
  • a predetermined opening is formed in a predetermined portion of the oxide film 116 by a photoetching method.
  • the semiconductor wafer is subsequently etched to form a groove (mesa groove) 120 having a depth exceeding the pn junction from one surface of the semiconductor wafer (FIG. 2).
  • the exposed portion A of the pn junction is formed on the inner surface (side wall) of the groove 120. That is, the exposed portion A of the pn junction of the side wall of the mesa groove 120 is formed on the surface of the semiconductor wafer.
  • a base insulating film 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (FIG. 3). That is, the base insulating film 121 is formed on the surface of the semiconductor wafer (the inner surface of the groove 120) so as to cover the exposed portion A of the pn junction.
  • DryO 2 dry oxygen
  • the mesa groove 120 has a bottom portion 120a, an opening end 120b, and a side wall 120c.
  • the bottom 120 a, the opening end 120 b, and the sidewall 120 c indicate the surface of the base insulating film 121.
  • a part of the bottom 120a, the opening end 120b, and the side wall 120c of the mesa groove 120 are simply defined as a part of the glass film forming surface.
  • the inner surface of the mesa groove 120 indicates the surface of the p + type diffusion layer 112 and the n ⁇ type diffusion layer 114.
  • the thickness of the base insulating film 121 is, for example, in the range of 5 nm to 60 nm (for example, 20 nm).
  • the base insulating film 121 is formed by placing the semiconductor wafer in a diffusion furnace and then treating it at a temperature of 900 ° C. for 10 minutes while flowing an oxygen gas. If the thickness of the base insulating film 121 is less than 5 nm, the effect of reducing the BT resistance may not be obtained. On the other hand, if the thickness of the base insulating film 121 exceeds 60 nm, it may not be possible to form a glass film by electrophoretic deposition in the next glass film forming process.
  • the semiconductor wafer W having the mesa groove 120 formed on the glass film forming surface is prepared.
  • the glass film 124 which is a deposit of lead-free glass fine particles, is opened in the mesa groove 120 by electrophoretic deposition with at least a part of the bottom 120a of the mesa groove 120 exposed.
  • the glass coating 124 is densified by forming it so as to cover the periphery of the end 120b and the side wall 120c (the surface of the base insulating film 121) of the mesa groove 120 and baking the glass coating 124 (FIG. 4).
  • the fired glass film is also denoted by the same reference numeral 124 as that of the glass film before firing.
  • the glass coating 124 covers the periphery of the opening end 120 b of the mesa groove 120 and the side wall 120 c (surface of the base insulating film 121) of the mesa groove 120 and is adjacent to the side wall 120 c of the mesa groove 120.
  • a part of the bottom 120a of the mesa groove 120 (for example, near the center of the bottom 120a) is also covered (at least a part of the bottom 120a of the mesa groove 120 is exposed).
  • the glass film 124 is formed on the surface of the base insulating film 121 around the opening end 120b of the mesa groove 120 and the side wall 120c of the mesa groove 120.
  • the glass coating 124 covers the exposed portion A of the pn junction via the base insulating film 121.
  • a glass film forming apparatus having the following configuration, that is, a tank 10 for storing a suspension 12 in which lead-free glass fine particles are suspended in a solvent, is opposed to each other.
  • the first and second electrode plates 14 and 16 installed in the tank 10 in a state and the first and second electrode plates 14 and 16 are disposed between the first electrode plate 14 and the second electrode plate 16, and the semiconductor wafer W is disposed at a predetermined position.
  • a glass film forming apparatus provided with a semiconductor wafer placement jig (not shown) for powering and a power supply device 20 for applying a potential to the first electrode plate 14 and the second electrode plate 16 is used (FIG. 9).
  • the first electrode plate 14 connected to the plus terminal and the minus terminal are connected to the inside of the tank 10 storing the suspension 12 in which the lead-free glass fine particles are suspended in the solvent.
  • the second electrode plate 16 is placed oppositely in a state of being immersed in the suspension 12, and the semiconductor wafer W is placed between the first electrode plate 14 and the second electrode plate 16 on the surface on which the glass film is to be formed (
  • the glass coating 124 is formed on the glass coating formation planned surface by the electrophoretic deposition method in a state where the inner surface of the groove) is arranged in a posture facing the first electrode plate 14 side.
  • a voltage of 10 V to 800 V (for example, 400 V) is applied as a voltage applied between the first electrode plate 14 and the second electrode plate 16.
  • this glass film forming step is a glass film that is a deposit of lead-free glass fine particles with at least a part of the bottom 120a of the mesa groove 120 (the surface of the base oxide film 121 in the bottom 120a) exposed. Is formed so as to cover the periphery of the opening end 120b of the mesa groove and the side wall 120c of the mesa groove.
  • the suspension 12 used in this glass film forming step is controlled in the first range of the dielectric constant of the solvent (1) containing the lead-free glass fine particles, and then the organic solvent and the solvent (1).
  • This is a suspension obtained by adding a mixed solution (electrolyte solution (2)) containing nitric acid as an electrolyte and controlling the electric conductivity (EC: Electro Conductivity) within the second range (see FIG. 10).
  • this suspension 12 does not contain surface activity.
  • the lead-free glass particles made of lead-free glass include, for example, at least one of the following glass particles, that is, SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , BaO. And lead-free glass particles prepared from a melt obtained by melting a raw material containing substantially no Pb.
  • the solvent (1) is a mixed solvent of isopropyl alcohol and ethyl acetate.
  • the dielectric constant of the solvent (1) is controlled to the first range described above by adjusting the ratio of ethyl acetate in the mixed solvent.
  • the first range of the dielectric constant of the solvent (1) is in the range of 5-7.
  • FIG. 11 is a diagram showing an example of the relationship between the dielectric constant and the ratio of isopropyl alcohol to ethyl acetate in the solvent (1) which is a mixed solvent containing isopropyl alcohol and ethyl acetate.
  • the dielectric constant of the solvent (1) can be adjusted to the first range described above by adjusting the ratio of ethyl acetate in the mixed solvent.
  • the electrolyte (2) is a mixed solution of an organic solvent (isopropyl alcohol (IPA)) and nitric acid (HNO 3 ).
  • the volume ratio of the organic solvent and nitric acid in this mixed solution is, for example, 1000: 1 to 5.
  • IPA isopropyl alcohol
  • HNO 3 nitric acid
  • the organic solvent ethyl acetate, acetone, ethanol, and other organic solvents can be selected as long as desired characteristics can be obtained.
  • the electric conductivity of the suspension 12 is controlled to the second range described above by adjusting the above-described mixed solution (electrolyte solution (2)).
  • the second range of the electrical conductivity of the suspension 12 is in the range of 20 nS / cm to 100 nS / cm.
  • the electrical conductivity (conductivity) of the suspension in which the lead glass powder is suspended is 150. ⁇ 50 ⁇ S / cm (refer to the above-mentioned JP-A-57-143832).
  • the lead glass powder is commercially available under the trade name IP760 from Innotech, USA (see the lower right column on page 1 of JP-A-57-143832).
  • the electrical conductivity condition (150 ⁇ 50 ⁇ S / cm) of this conventional suspension is compared with the second range (20 nS / cm to 100 nS / cm) of the electrical conductivity of the suspension 12 of the present application described above. Differ greatly (in the range of high electrical conductivity).
  • Japanese Patent Application Laid-Open No. 57-143832 discloses that when the conductivity of the suspension is 100 ⁇ S / cm or less, not only the surface where the PN junction end of the mesa semiconductor element is exposed, but also other It is described that a glass film is also formed on this portion, for example, a SiO 2 film, and this has an adverse effect in the subsequent manufacturing process.
  • the conventional electrophoretic deposition method for depositing lead glass powder containing lead described in JP-A-57-143832 is used by setting the conductivity of the suspension to 100 ⁇ S / cm or less. Not supposed to do.
  • the second range of the electric conductivity of the suspension 12 is the mesa groove with high accuracy in a state where at least a part of the bottom 120a of the mesa groove 120 is exposed to the lead-free glass fine particles.
  • the condition for depositing on 120 is set to a very low range of 20 nS / cm to 100 nS / cm, which is not used in the above-mentioned conventional technique, and is 100 ⁇ S / cm or less.
  • the lead-free glass applied in the present embodiment cannot be deposited in the mesa groove of the semiconductor element by the electrophoretic deposition method under the above-described conventional electrical conductivity condition of the suspension (150 ⁇ 50 ⁇ S / cm). Has been confirmed.
  • the electrical conductivity of the mixed solution is controlled in the third range before being added to the solvent (1) described above.
  • the electrical conductivity of the mixed solution is controlled to the third range described above by adjusting the ratio of nitric acid in the mixed solution.
  • the third range of the electric conductivity of this mixed solution is in the range of 90 ⁇ S / cm to 130 ⁇ S / cm.
  • the electrolyte solution (2) is about 30 to 40 cc.
  • the dielectric constant of the solvent containing the lead-free glass fine particles is controlled within the first range (5 to 11), and then the dielectric constant is changed to the first dielectric constant.
  • Electrolytic solution (2) was added to the solvent controlled to the range (mixed solvent of isopropyl alcohol (IPA) and ethyl acetate) to control the electric conductivity to the second range (20 nS / cm to 100 nS / cm).
  • the lead-free glass particles in the suspension are deposited on the mesa grooves of the semiconductor wafer by electrophoretic deposition using the suspension.
  • the electric conductivity of the electrolyte (2) is controlled within the third range (90 ⁇ S / cm to 130 ⁇ S / cm).
  • the thickness of the lead-free glass fine particles deposited in the mesa groove formed in the semiconductor wafer can be controlled to a predetermined thickness with high accuracy.
  • the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness
  • the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.
  • Electrode formation step Ni plating is performed on the semiconductor wafer W to form the anode electrode 134 on the roughened region 132 (between two adjacent mesa grooves 120 on one surface of the semiconductor wafer W). Then, the cathode electrode 136 is formed on the other surface of the semiconductor wafer W (FIG. 7).
  • (F) Semiconductor wafer cutting step Next, the semiconductor wafer is cut into chips by cutting the semiconductor wafer along the vicinity of the center of the bottom 120a of the mesa groove 120 where the glass coating 124 is not formed by dicing, laser, or the like.
  • a semiconductor device (mesa type pn diode) 100 is manufactured (FIG. 8).
  • the glass coating 124 of the lead-free glass fine particle deposit is formed so as to cover the periphery of the opening end 120b of the mesa groove 120 and the side wall 120c of the mesa groove 120. It is formed to a predetermined thickness with high accuracy.
  • the glass (glass coating 124) as the passivation film is cut. There is no need.
  • the semiconductor device (mesa type pn diode) 100 can be manufactured.
  • FIG. 12 is a diagram showing an example of the relationship between the electrical conductivity of the suspension 12 and the adhesion state of the deposit on the bottom 120a of the mesa groove 120.
  • FIG. 13 is a photograph of the upper surface of the semiconductor wafer in a state where the glass coating 124 before firing is formed in the glass coating formation step.
  • FIG. 14 is a photograph of a cross section of the mesa groove 120 including the fired glass coating 124 in the glass coating formation step.
  • the second range of the electrical conductivity of the suspension 12 is set to a range of 20 nS / cm to 100 nS / cm, so that the lead-free glass fine particles can be removed at least from the bottom 120a of the mesa groove 120. It can be deposited in the mesa groove 120 accurately with a part (for example, near the center of the bottom 120a) exposed.
  • the glass film forming step before firing, at least a part of the bottom 120a of the mesa groove 120 (for example, near the center of the bottom 120a) is exposed, It has been confirmed that the glass coating 124 is formed so as to cover the periphery of the opening end 120 b of the mesa groove 120 and the side wall 120 c of the mesa groove 120.
  • the glass coating 124 is opened in the mesa groove 120 in a state where at least a part of the bottom 120 a of the mesa groove 120 is exposed after firing in the glass film forming step according to the embodiment. It can be confirmed that it is formed so as to cover the periphery of the end 120 b and the side wall 120 c of the mesa groove 120.
  • the adherence of lead-free glass particles to the semiconductor wafer is not stable, and the thickness of the lead-free glass particles deposited in the mesa groove is accurately adjusted. It cannot be controlled to a predetermined thickness.
  • the glass film of the lead-free glass fine particle deposit is opened in the mesa groove with at least a part of the bottom of the mesa groove exposed. It can be accurately formed to a predetermined thickness so as to cover the periphery of the end and the side wall of the mesa groove.
  • the adherence of lead-free glass particles to the semiconductor wafer is stable, and the thickness of the deposit of lead-free glass particles deposited in the mesa groove can be accurately controlled to a predetermined thickness.
  • a method for manufacturing a semiconductor device includes a semiconductor wafer preparation step of preparing a semiconductor wafer W having a mesa groove formed on a glass film formation surface, and a lead-free glass fine particle suspended in a solvent.
  • the first electrode plate and the second electrode plate are placed opposite to each other in the suspended suspension and the semiconductor wafer is placed between the first electrode plate and the second electrode plate.
  • a glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition with the glass film forming surface facing the first electrode plate.
  • the glass film which is a deposit of lead-free glass fine particles, is covered with the periphery of the opening end 120b of the mesa groove and the side wall of the mesa groove with at least a part of the bottom of the mesa groove exposed.
  • the suspension used in the glass film forming step is prepared by controlling the dielectric constant of the solvent containing lead-free glass fine particles in the first range, and then adding the organic solvent and the nitric acid that is an electrolyte to the solvent.
  • a mixed liquid (electrolyte solution) containing and a suspension whose electric conductivity is controlled in the second range the first range of the dielectric constant of the solvent is in the range of 5-7,
  • the second range of electrical conductivity of the suspension is in the range of 20 nS / cm to 100 nS / cm.
  • the glass film of the lead-free glass fine particle deposit is accurately coated to a predetermined thickness so as to cover the periphery of the opening end of the mesa groove and the side wall of the mesa groove. Can be formed.
  • a semiconductor wafer plate made of silicon is used as the semiconductor wafer, but the present invention is not limited to this.
  • a semiconductor wafer made of SiC, GaN, GaO or the like can be used.

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Abstract

A semiconductor device production method comprises: a semiconductor wafer preparation step for preparing a semiconductor wafer W, on the glass film-forming surface of which mesa grooves 120 are formed; and a glass film-forming step in which a glass film 124 is formed on the glass film-forming surface by electrophoretic deposition with a first electrode plate 14 and a second electrode plate 16 set facing each other immersed in a suspension 12 in which lead-free glass microparticles are suspended in a solvent, the semiconductor wafer between the first electrode plate and the second electrode plate, and the glass film-forming surface facing toward the first electrode plate.

Description

半導体装置の製造方法Manufacturing method of semiconductor device

 本発明は、半導体装置の製造方法に関する発明である。 The present invention relates to a method for manufacturing a semiconductor device.

 従来、半導体ウェーハの表面にガラス被膜を形成するガラス被膜形成工程を含む半導体装置の製造方法が知られている(例えば、特開平8-64557号公報、特開2014-187144号公報、特開昭2005-243893号公報、特開昭57-143832号公報参照)。 Conventionally, a method of manufacturing a semiconductor device including a glass film forming step of forming a glass film on the surface of a semiconductor wafer is known (for example, Japanese Patent Application Laid-Open Nos. 8-64557, 2014-187144, and Sho-A). 2005-243893, JP-A-57-143832).

 この従来の半導体装置の製造方法においては、電気泳動堆積法(EPD:Electrophoretic Deposition)により、鉛を含まない鉛フリーガラス微粒子を半導体ウェーハのメサ溝に堆積させ、その後、当該メサ溝に堆積した鉛フリーガラス微粒子を焼成して、ガラス化することで、半導体装置のパッシベーション膜を形成する。 In this conventional method of manufacturing a semiconductor device, lead-free glass fine particles not containing lead are deposited on a mesa groove of a semiconductor wafer by electrophoretic deposition (EPD), and then the lead deposited in the mesa groove. The passivation film of the semiconductor device is formed by baking the free glass fine particles to vitrify.

 特に、上述の従来の半導体装置の製造方法では、電気泳動堆積法によるガラス被膜形成工程において、鉛フリーガラス微粒子が半導体ウェーハのメサ溝の底部にも堆積される。 In particular, in the above-described conventional method for manufacturing a semiconductor device, lead-free glass fine particles are deposited on the bottom of the mesa groove of the semiconductor wafer in the glass film forming step by electrophoretic deposition.

 これにより、鉛フリーガラス微粒子の堆積物を焼成してガラス化したパッシベーション膜がメサ溝の底部にも形成されることとなる。 Thus, a passivation film obtained by firing a deposit of lead-free glass fine particles and vitrifying it is also formed at the bottom of the mesa groove.

 したがって、例えば、半導体ウェーハをチップ化するために、ダイシング又はレーザー等で半導体ウェーハをメサ溝に沿って切断する際に、半導体ウェーハのシリコンとパシベーション膜であるガラスを、すなわち材質が異なる複数の材料を、切断する必要がある。 Therefore, for example, when a semiconductor wafer is cut along a mesa groove by dicing or laser to form a semiconductor wafer into a chip, the silicon of the semiconductor wafer and the glass that is a passivation film, that is, a plurality of different materials are used. Need to be cut.

 そして、この材質が異なる複数の材料の切断の応力によりクラック等が発生してしまう。このクラック発生防止策として、半導体ウェーハの切断スピードを落としたり、特殊な切断装置などを使ったりする必要がある。 And a crack etc. will generate | occur | produce by the stress of the cutting | disconnection of several materials from which this material differs. In order to prevent the occurrence of cracks, it is necessary to reduce the cutting speed of the semiconductor wafer or use a special cutting device.

 また、効率よく切断するために、メサ溝部のガラスを写真工程後、選択的にエッチングし、シリコン面を露出させる方法もある。 Also, in order to cut efficiently, there is a method in which the glass of the mesa groove is selectively etched after the photographic process to expose the silicon surface.

 しかしながら、上記いずれの対策においても工程追加や処理時間の増加なり、コストの増加につながる。 However, in any of the above measures, the process is added and the processing time is increased, leading to an increase in cost.

 上述のように、従来の半導体装置の製造方法では、電気泳動堆積法によるガラス被膜形成工程において、半導体ウェーハの切断時のクラックやの原因になる、鉛フリーガラス微粒子が半導体ウェーハのメサ溝の底部にも堆積される問題がある。 As described above, in the conventional semiconductor device manufacturing method, in the glass film forming process by the electrophoretic deposition method, the lead-free glass fine particles that cause cracks at the time of cutting of the semiconductor wafer are formed at the bottom of the mesa groove of the semiconductor wafer. There is also a problem of being deposited.

 そこで、本発明では、ガラス被膜形成工程で用いられる懸濁液の特性を制御して、メサ溝の底部の少なくとも一部が露出した(メサ溝の底部の少なくともに一部に鉛フリーガラス微粒子の堆積物のガラス被膜が形成されない)状態で、鉛フリーガラス微粒子の堆積物のガラス被膜をメサ溝の開口端周辺とメサ溝の側壁を被覆するように精度良く所定の厚さに形成することが可能な半導体装置の製造方法を提供することを目的とする。 Therefore, in the present invention, by controlling the characteristics of the suspension used in the glass film forming step, at least a part of the bottom of the mesa groove is exposed (the lead-free glass fine particles are partially formed on at least a part of the bottom of the mesa groove. In a state in which the glass film of the deposit is not formed), the glass film of the lead-free glass fine particle deposit can be accurately formed to a predetermined thickness so as to cover the periphery of the opening end of the mesa groove and the side wall of the mesa groove. An object of the present invention is to provide a method for manufacturing a possible semiconductor device.

 本発明の一態様に係る実施形態に従った半導体装置の製造方法は、
 ガラス被膜形成面にメサ溝が形成された半導体ウェーハを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第1電極板と第2電極板とを前記懸濁液に浸漬した状態で対向して設置するとともに、前記第1電極板と前記第2電極板との間に前記半導体ウェーハを前記ガラス被膜形成面が前記第1電極板側に向いた状態で、電気泳動堆積法により前記ガラス被膜形成面にガラス被膜を形成するガラス被膜形成工程と、を含む半導体装置の製造方法であって、
 前記ガラス被膜形成工程は、前記メサ溝の底部の少なくとも一部が露出した状態で、前記鉛フリーガラス微粒子の堆積物である前記ガラス被膜を前記メサ溝の開口端周辺と前記メサ溝の側壁を被覆するように形成するものであり、
 前記ガラス被膜形成工程で用いられる前記懸濁液は、
 前記鉛フリーガラス微粒子を含む前記溶媒の誘電率を第1の範囲に制御した後、当該溶媒に、有機溶剤と電解質である硝酸とを含む混合液を加えて、その電気伝導度を第2の範囲に制御した懸濁液であり、
 前記溶媒の誘電率の前記第1の範囲は、5~7の範囲であり、
 前記懸濁液の電気伝導度の前記第2の範囲は、20nS/cm~100nS/cmの範囲である
 ことを特徴とする。
A method for manufacturing a semiconductor device according to an embodiment of one aspect of the present invention includes:
A semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass coating formation surface, and a suspension in which lead-free glass fine particles are suspended in a solvent, the first electrode plate and the second electrode plate are A state in which the semiconductor wafer is placed between the first electrode plate and the second electrode plate while facing each other while being immersed in the suspension, and the glass film forming surface faces the first electrode plate side A glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition, and a method for manufacturing a semiconductor device,
In the glass film forming step, at least a part of the bottom of the mesa groove is exposed, the glass film that is a deposit of the lead-free glass fine particles is formed around the opening end of the mesa groove and the side wall of the mesa groove. It is formed to cover,
The suspension used in the glass film forming step is
After controlling the dielectric constant of the solvent containing the lead-free glass fine particles to the first range, a mixed liquid containing an organic solvent and nitric acid as an electrolyte is added to the solvent, and the electric conductivity is set to a second value. Suspension controlled to range
The first range of the dielectric constant of the solvent is in the range of 5-7;
The second range of the electric conductivity of the suspension is 20 nS / cm to 100 nS / cm.

 前記半導体装置の製造方法において、
 前記混合液を調整することで、前記懸濁液の前記電気伝導度を前記第2の範囲に制御することを特徴とする。
In the method for manufacturing the semiconductor device,
The electrical conductivity of the suspension is controlled in the second range by adjusting the mixed solution.

 前記半導体装置の製造方法において、
 前記溶媒に加えられる前に、前記混合液は、電気伝導度が第3の範囲に制御されており、前記混合液の電気伝導度の前記第3の範囲は、90μS/cm~130μS/cmの範囲であることを特徴とする。
In the method for manufacturing the semiconductor device,
Before being added to the solvent, the mixture is controlled in electrical conductivity to a third range, and the third range of electrical conductivity of the mixture is 90 μS / cm to 130 μS / cm. It is a range.

 前記半導体装置の製造方法において、
 前記有機溶剤は、イソプロピルアルコール又は酢酸エチルであることを特徴とする。
In the method for manufacturing the semiconductor device,
The organic solvent is isopropyl alcohol or ethyl acetate.

 前記半導体装置の製造方法において、
 前記混合液の前記電気伝導度を、前記混合液における前記硝酸の割合を調整することにより、前記第3の範囲に制御することを特徴とする。
In the method for manufacturing the semiconductor device,
The electrical conductivity of the mixed liquid is controlled to the third range by adjusting a ratio of the nitric acid in the mixed liquid.

 前記半導体装置の製造方法において、
 前記溶媒は、イソプロピルアルコールと酢酸エチルとを含む混合溶媒であることを特徴とする。
In the method for manufacturing the semiconductor device,
The solvent is a mixed solvent containing isopropyl alcohol and ethyl acetate.

 前記半導体装置の製造方法において、
 前記溶媒の誘電率を、前記混合溶媒における前記酢酸エチルの割合を調整することにより、前記第1の範囲に制御する
 ことを特徴とする。
In the method for manufacturing the semiconductor device,
The dielectric constant of the solvent is controlled to the first range by adjusting a ratio of the ethyl acetate in the mixed solvent.

 前記半導体装置の製造方法において、
 前記鉛フリーガラス微粒子は、SiO、Al、CaO、MgO、ZnO、B、BaOの少なくとも何れか1つを含む鉛フリーガラス微粒子である
 ことを特徴とする。
In the method for manufacturing the semiconductor device,
The lead-free glass fine particles are lead-free glass fine particles containing at least one of SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , and BaO.

 前記半導体装置の製造方法において、
 前記半導体ウェーハ準備工程は、
 主面に平行なpn接合を備える半導体ウェーハを準備する工程と、
 前記半導体ウェーハの一方の表面から前記pn接合を超える深さのメサ溝を形成することにより、前記メサ溝の内面に前記pn接合の露出部を形成する工程と、
 前記pn接合の露出部を覆うように前記メサ溝の内面に下地絶縁膜121を形成する工程と、を含む
 ことを特徴とする。
In the method for manufacturing the semiconductor device,
The semiconductor wafer preparation step
Preparing a semiconductor wafer having a pn junction parallel to the main surface;
Forming an exposed portion of the pn junction on the inner surface of the mesa groove by forming a mesa groove having a depth exceeding the pn junction from one surface of the semiconductor wafer;
And a step of forming a base insulating film 121 on the inner surface of the mesa groove so as to cover the exposed portion of the pn junction.

 前記半導体装置の製造方法において、
 前記懸濁液は、界面活性剤を含まないことを特徴とする。
In the method for manufacturing the semiconductor device,
The suspension is characterized by not containing a surfactant.

 前記半導体装置の製造方法において、
 前記半導体ウェーハ準備工程は、半導体ウェーハの表面に前記メサ溝の側壁のpn接合の露出部を形成する工程と、前記pn接合の露出部を覆うように前記半導体ウェーハの表面に下地絶縁膜を形成する工程と、を含む
 ことを特徴とする。
In the method for manufacturing the semiconductor device,
The semiconductor wafer preparation step includes a step of forming an exposed portion of a pn junction of a side wall of the mesa groove on the surface of the semiconductor wafer, and forming a base insulating film on the surface of the semiconductor wafer so as to cover the exposed portion of the pn junction And a step of performing.

 前記半導体装置の製造方法において、
 前記ガラス被膜形成工程は、前記ガラス被膜を、前記メサ溝の開口端周辺及び前記メサ溝の側壁の前記下地絶縁膜の表面に形成する
 ことを特徴とする。
In the method for manufacturing the semiconductor device,
The glass coating forming step is characterized in that the glass coating is formed on the surface of the base insulating film around the opening end of the mesa groove and on the side wall of the mesa groove.

 前記半導体装置の製造方法において、
 前記半導体ウェーハの前記一方の表面の隣接する2つの前記メサ溝間にアノード電極を形成するとともに、前記半導体ウェーハの他方の表面にカソード電極を形成する電極形成工程をさらに備える
 ことを特徴とする。
In the method for manufacturing the semiconductor device,
The method further comprises forming an anode electrode between two adjacent mesa grooves on the one surface of the semiconductor wafer and forming a cathode electrode on the other surface of the semiconductor wafer.

 前記半導体装置の製造方法において、
 前記ガラス被膜は、前記下地絶縁膜を介して、前記pn接合の露出部を覆っていることを特徴とする。
In the method for manufacturing the semiconductor device,
The glass coating covers an exposed portion of the pn junction through the base insulating film.

 前記半導体装置の製造方法において、
 前記ガラス被膜が形成されていない前記メサ溝の前記底部の中央近傍に沿って前記半導体ウェーハを切断して前記半導体ウェーハをチップ化する半導体ウェーハ切断工程をさらに含む
 ことを特徴とする。
In the method for manufacturing the semiconductor device,
The method further includes a semiconductor wafer cutting step of cutting the semiconductor wafer along the vicinity of the center of the bottom portion of the mesa groove where the glass coating is not formed to form the semiconductor wafer into chips.

 本発明の一態様に係る半導体装置の製造方法は、ガラス被膜形成面にメサ溝が形成された半導体ウェーハWを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第1電極板と第2電極板とを懸濁液に浸漬した状態で対向して設置するとともに、第1電極板と第2電極板との間に半導体ウェーハをガラス被膜形成面が第1電極板側に向いた状態で、電気泳動堆積法によりガラス被膜形成面にガラス被膜を形成するガラス被膜形成工程と、を含む。 A method of manufacturing a semiconductor device according to an aspect of the present invention includes a semiconductor wafer preparation step of preparing a semiconductor wafer W having mesa grooves formed on a glass film forming surface, and a suspension in which lead-free glass fine particles are suspended in a solvent. In the liquid, the first electrode plate and the second electrode plate are placed facing each other in a state of being immersed in the suspension, and the glass film forming surface is disposed between the first electrode plate and the second electrode plate. And a glass film forming step of forming a glass film on the glass film forming surface by an electrophoretic deposition method in a state facing the first electrode plate side.

 そして、ガラス被膜形成工程は、メサ溝の底部の少なくとも一部が露出した状態で、鉛フリーガラス微粒子の堆積物であるガラス被膜をメサ溝の開口端周辺とメサ溝の側壁を被覆するように形成するものである。 In the glass film forming step, at least a part of the bottom of the mesa groove is exposed so that the glass film, which is a deposit of lead-free glass fine particles, covers the periphery of the opening end of the mesa groove and the side wall of the mesa groove. To form.

 そして、ガラス被膜形成工程で用いられる懸濁液は、鉛フリーガラス微粒子を含む溶媒の誘電率を第1の範囲に制御した後、当該溶媒に、有機溶剤と電解質である硝酸とを含む混合液(電解質溶液)を加えて、その電気伝導度を第2の範囲に制御した懸濁液である。さらに、溶媒の誘電率の第1の範囲は、5~7の範囲である。さらに、懸濁液の電気伝導度の第2の範囲は、20nS/cm~100nS/cmの範囲である。 The suspension used in the glass coating formation step is a mixed solution containing an organic solvent and nitric acid as an electrolyte in the solvent after controlling the dielectric constant of the solvent containing lead-free glass fine particles to the first range. (Electrolyte solution) is added and the electric conductivity is controlled to be in the second range. Furthermore, the first range of the dielectric constant of the solvent is in the range of 5-7. Furthermore, the second range of electrical conductivity of the suspension is in the range of 20 nS / cm to 100 nS / cm.

 これにより、メサ溝の底部の少なくとも一部が露出した状態で、鉛フリーガラス微粒子の堆積物のガラス被膜をメサ溝の開口端周辺とメサ溝の側壁を被覆するように精度良く所定の厚さに形成することができる。 As a result, with the at least part of the bottom of the mesa groove exposed, the glass film of the lead-free glass fine particle deposit is accurately coated to a predetermined thickness so as to cover the periphery of the opening end of the mesa groove and the side wall of the mesa groove. Can be formed.

図1は、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 1 is a diagram illustrating a process of a method for manufacturing a semiconductor device according to the first embodiment. 図2は、図1に続く、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 2 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 1. 図3は、図2に続く、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 3 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 2. 図4は、図3に続く、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 4 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 3. 図5は、図4に続く、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 5 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 4. 図6は、図5に続く、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 6 is a diagram illustrating steps in the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 5. 図7は、図6に続く、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 7 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 6. 図8は、図7に続く、第1の実施形態に係る半導体装置の製造方法の工程を示す図である。FIG. 8 is a diagram illustrating steps of the method for manufacturing the semiconductor device according to the first embodiment, which are subsequent to FIG. 7. 図9は、ガラス被膜形成装置1を横方向から見た断面図である。FIG. 9 is a cross-sectional view of the glass film forming apparatus 1 as seen from the lateral direction. 図10は、第1の実施形態に係る半導体装置の製造方法の電気泳動堆積法で用いられる懸濁液12の組成の一例を示す図である。FIG. 10 is a diagram illustrating an example of the composition of the suspension 12 used in the electrophoretic deposition method of the semiconductor device manufacturing method according to the first embodiment. 図11は、イソプロピルアルコールと酢酸エチルとを含む混合溶媒である溶媒(1)の、イソプロピルアルコールと酢酸エチルの比率と、誘電率との関係の一例を示す図である。FIG. 11 is a diagram showing an example of the relationship between the dielectric constant and the ratio of isopropyl alcohol to ethyl acetate in the solvent (1) which is a mixed solvent containing isopropyl alcohol and ethyl acetate. 図12は、懸濁液12の電気伝導度とメサ溝120の底部120aの堆積物の付着状態との関係の一例を示す図である。FIG. 12 is a diagram illustrating an example of the relationship between the electrical conductivity of the suspension 12 and the adhesion state of the deposit on the bottom 120 a of the mesa groove 120. 図13は、ガラス被膜形成工程における、焼成前のガラス被膜124が成膜された状態の半導体ウェーハの上面の写真である。FIG. 13 is a photograph of the upper surface of the semiconductor wafer in a state where the glass coating 124 before firing is formed in the glass coating formation step. 図14は、ガラス被膜形成工程における、焼成後のガラス被膜124を含むメサ溝120の断面の写真である。FIG. 14 is a photograph of a cross section of the mesa groove 120 including the glass coating 124 after firing in the glass coating forming step.

以下、本発明に係る実施形態について図面に基づいて説明する。 Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

第1の実施形態First embodiment

 第1の実施形態に係る半導体装置の製造方法は、図1ないし図8に示すように、「半導体ウェーハ準備工程」、「ガラス被膜形成工程」、「酸化膜除去工程」、「粗面化領域形成工程」、「電極形成工程」及び「半導体ウェーハ切断工程」をこの順序で実施する。以下、実施形態に係る半導体装置の製造方法を工程順に説明する。 As shown in FIGS. 1 to 8, the method of manufacturing a semiconductor device according to the first embodiment includes a “semiconductor wafer preparation step”, a “glass film formation step”, an “oxide film removal step”, and a “roughened region”. The “forming process”, “electrode forming process”, and “semiconductor wafer cutting process” are performed in this order. The semiconductor device manufacturing method according to the embodiment will be described below in the order of steps.

(a)半導体ウェーハ準備工程
 まず、n-型半導体ウェーハ(例えば、直径4インチのn-型シリコンウェーハ)110の一方の表面からのp型不純物の拡散によりp+型拡散層112を形成するとともに、他方の表面からのn型不純物の拡散によりn+型拡散層114を形成して、主面に平行なpn接合が形成された半導体ウェーハWを準備する(図1)。
(A) Semiconductor wafer preparation step First, a p + type diffusion layer 112 is formed by diffusion of p type impurities from one surface of an n− type semiconductor wafer (for example, an n− type silicon wafer having a diameter of 4 inches) 110, An n + -type diffusion layer 114 is formed by diffusion of n-type impurities from the other surface to prepare a semiconductor wafer W in which a pn junction parallel to the main surface is formed (FIG. 1).

 その後、熱酸化によりp+型拡散層112及びn+型拡散層114の表面に酸化膜116、118を形成する(図1)。 Thereafter, oxide films 116 and 118 are formed on the surfaces of the p + type diffusion layer 112 and the n + type diffusion layer 114 by thermal oxidation (FIG. 1).

 次に、フォトエッチング法によって、酸化膜116の所定部位に所定の開口部を形成する。酸化膜のエッチング後、引き続いて半導体ウェーハのエッチングを行い、半導体ウェーハの一方の表面からpn接合を超える深さの溝(メサ溝)120を形成する(図2)。このとき、溝120の内面(側壁)にpn接合の露出部Aが形成される。すなわち、半導体ウェーハの表面にメサ溝120の側壁のpn接合の露出部Aを形成する。 Next, a predetermined opening is formed in a predetermined portion of the oxide film 116 by a photoetching method. After etching the oxide film, the semiconductor wafer is subsequently etched to form a groove (mesa groove) 120 having a depth exceeding the pn junction from one surface of the semiconductor wafer (FIG. 2). At this time, the exposed portion A of the pn junction is formed on the inner surface (side wall) of the groove 120. That is, the exposed portion A of the pn junction of the side wall of the mesa groove 120 is formed on the surface of the semiconductor wafer.

 次に、ドライ酸素(DryO)を用いた熱酸化法によって、溝120の内面にシリコン酸化膜からなる下地絶縁膜121を形成する(図3)。すなわち、pn接合の露出部Aを覆うように半導体ウェーハの表面(溝120の内面)に下地絶縁膜121を形成する。 Next, a base insulating film 121 made of a silicon oxide film is formed on the inner surface of the groove 120 by a thermal oxidation method using dry oxygen (DryO 2 ) (FIG. 3). That is, the base insulating film 121 is formed on the surface of the semiconductor wafer (the inner surface of the groove 120) so as to cover the exposed portion A of the pn junction.

 ここでは、図3に示すように、メサ溝120は、底部120aと、開口端120bと、側壁120cと、を有する。この図3の例では、底部120a、開口端120b、及び、側壁120cは、下地絶縁膜121の表面を示している。なお、下地絶縁膜121を省略して考える場合には、メサ溝120の底部120aの一部、開口端120b、及び側壁120cは、単に、ガラス被膜形成面の一部として定義される。また、この下地酸化膜121が形成される前の工程(図2)では、メサ溝120の内面は、p+型拡散層112とn-型拡散層114との表面を示す。 Here, as shown in FIG. 3, the mesa groove 120 has a bottom portion 120a, an opening end 120b, and a side wall 120c. In the example of FIG. 3, the bottom 120 a, the opening end 120 b, and the sidewall 120 c indicate the surface of the base insulating film 121. When the base insulating film 121 is omitted, a part of the bottom 120a, the opening end 120b, and the side wall 120c of the mesa groove 120 are simply defined as a part of the glass film forming surface. Further, in the step (FIG. 2) before the base oxide film 121 is formed, the inner surface of the mesa groove 120 indicates the surface of the p + type diffusion layer 112 and the n− type diffusion layer 114.

 なお、下地絶縁膜121の厚さは、例えば、5nm~60nmの範囲内(例えば20nm)とする。下地絶縁膜121の形成は、半導体ウェーハを拡散炉に入れた後、酸素ガスを流しながら900℃の温度で10分処理することにより行う。下地絶縁膜121の厚さが5nm未満であるとBT耐量低減の効果が得られなくなる場合がある。一方、下地絶縁膜121の厚さが60nmを超えると次のガラス被膜形成工程で電気泳動堆積法によりガラス被膜を形成することができなくなる場合がある。 Note that the thickness of the base insulating film 121 is, for example, in the range of 5 nm to 60 nm (for example, 20 nm). The base insulating film 121 is formed by placing the semiconductor wafer in a diffusion furnace and then treating it at a temperature of 900 ° C. for 10 minutes while flowing an oxygen gas. If the thickness of the base insulating film 121 is less than 5 nm, the effect of reducing the BT resistance may not be obtained. On the other hand, if the thickness of the base insulating film 121 exceeds 60 nm, it may not be possible to form a glass film by electrophoretic deposition in the next glass film forming process.

 以上のようにして、ガラス被膜形成面にメサ溝120が形成された半導体ウェーハWが準備される。 As described above, the semiconductor wafer W having the mesa groove 120 formed on the glass film forming surface is prepared.

 (b)ガラス被膜形成工程
 次に、電気泳動堆積法により、メサ溝120の底部120aの少なくとも一部が露出した状態で、鉛フリーガラス微粒子の堆積物であるガラス被膜124をメサ溝120の開口端120b周辺とメサ溝120の側壁120c(下地絶縁膜121の表面)を被覆するように形成するとともに、当該ガラス被膜124を焼成することにより、当該ガラス被膜124を緻密化する(図4)。なお、以下の図5から図8に示す工程でも、焼成された当該ガラス被膜についても焼成前のガラス被膜と同じ符号124を用いて表記するものとする。
(B) Glass Film Formation Step Next, the glass film 124, which is a deposit of lead-free glass fine particles, is opened in the mesa groove 120 by electrophoretic deposition with at least a part of the bottom 120a of the mesa groove 120 exposed. The glass coating 124 is densified by forming it so as to cover the periphery of the end 120b and the side wall 120c (the surface of the base insulating film 121) of the mesa groove 120 and baking the glass coating 124 (FIG. 4). In the steps shown in FIGS. 5 to 8 below, the fired glass film is also denoted by the same reference numeral 124 as that of the glass film before firing.

 この図4に示す例では、ガラス被膜124は、メサ溝120の開口端120b周辺とメサ溝120の側壁120c(下地絶縁膜121の表面)を被覆するとともに、メサ溝120の側壁120cに隣接するメサ溝120の底部120aの一部(例えば、底部120aの中央近傍)も被覆している(メサ溝120の底部120aの少なくとも一部が露出した状態である)。 In the example shown in FIG. 4, the glass coating 124 covers the periphery of the opening end 120 b of the mesa groove 120 and the side wall 120 c (surface of the base insulating film 121) of the mesa groove 120 and is adjacent to the side wall 120 c of the mesa groove 120. A part of the bottom 120a of the mesa groove 120 (for example, near the center of the bottom 120a) is also covered (at least a part of the bottom 120a of the mesa groove 120 is exposed).

 すなわち、このガラス被膜形成工程は、ガラス被膜124を、メサ溝120の開口端120b周辺及びメサ溝120の側壁120cの下地絶縁膜121の表面に形成する。換言すれば、このガラス被膜124は、下地絶縁膜121を介して、pn接合の露出部Aを覆っている。 That is, in this glass film forming step, the glass film 124 is formed on the surface of the base insulating film 121 around the opening end 120b of the mesa groove 120 and the side wall 120c of the mesa groove 120. In other words, the glass coating 124 covers the exposed portion A of the pn junction via the base insulating film 121.

 このガラス被膜形成工程を実施するにあたっては、以下の構成を備えるガラス被膜形成装置、すなわち、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液12を貯留するための槽10と、互いに対向した状態で槽10の中に設置された第1電極板14及び第2電極板16と、第1電極板14と第2電極板16との間に設置され、所定位置に半導体ウェーハWを配設するための半導体ウェーハ配設治具(図示せず。)と、第1電極板14および第2電極板16に電位を与える電源装置20と、を備えるガラス被膜形成装置を用いる(図9)。 In carrying out this glass film forming step, a glass film forming apparatus having the following configuration, that is, a tank 10 for storing a suspension 12 in which lead-free glass fine particles are suspended in a solvent, is opposed to each other. The first and second electrode plates 14 and 16 installed in the tank 10 in a state and the first and second electrode plates 14 and 16 are disposed between the first electrode plate 14 and the second electrode plate 16, and the semiconductor wafer W is disposed at a predetermined position. A glass film forming apparatus provided with a semiconductor wafer placement jig (not shown) for powering and a power supply device 20 for applying a potential to the first electrode plate 14 and the second electrode plate 16 is used (FIG. 9).

 そして、図9に示すように、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液12を貯留した槽10の内部に、プラス端子に接続された第1電極板14とマイナス端子に接続された第2電極板16とを懸濁液12に浸漬した状態で対向して設置するとともに、これら第1電極板14と第2電極板16との間に半導体ウェーハWをガラス被膜形成予定面(図9では溝の内面)が第1電極板14側に向いた姿勢で配置した状態で、電気泳動堆積法によりガラス被膜形成予定面にガラス被膜124を形成する。 Then, as shown in FIG. 9, the first electrode plate 14 connected to the plus terminal and the minus terminal are connected to the inside of the tank 10 storing the suspension 12 in which the lead-free glass fine particles are suspended in the solvent. The second electrode plate 16 is placed oppositely in a state of being immersed in the suspension 12, and the semiconductor wafer W is placed between the first electrode plate 14 and the second electrode plate 16 on the surface on which the glass film is to be formed ( In FIG. 9, the glass coating 124 is formed on the glass coating formation planned surface by the electrophoretic deposition method in a state where the inner surface of the groove) is arranged in a posture facing the first electrode plate 14 side.

 なお、第1電極板14と第2電極板16との間に印加する電圧としては、10V~800V(例えば400V)の電圧を与える。 Note that a voltage of 10 V to 800 V (for example, 400 V) is applied as a voltage applied between the first electrode plate 14 and the second electrode plate 16.

 以上のように、このガラス被膜形成工程は、メサ溝120の底部120a(底部120aにおける下地酸化膜121の表面)の少なくとも一部が露出した状態で、鉛フリーガラス微粒子の堆積物であるガラス被膜をメサ溝の開口端120b周辺とメサ溝の側壁120cを被覆するように形成するものである。 As described above, this glass film forming step is a glass film that is a deposit of lead-free glass fine particles with at least a part of the bottom 120a of the mesa groove 120 (the surface of the base oxide film 121 in the bottom 120a) exposed. Is formed so as to cover the periphery of the opening end 120b of the mesa groove and the side wall 120c of the mesa groove.

 ここで、このガラス被膜形成工程で用いられる懸濁液12は、鉛フリーガラス微粒子を含む溶媒(1)の誘電率を第1の範囲に制御した後、当該溶媒(1)に、有機溶剤と電解質である硝酸とを含む混合液(電解質溶液(2))を加えて、その電気伝導度(EC:Electro Conductivity)を第2の範囲に制御した懸濁液である(図10参照)。特に、この懸濁液12は、界面活性を含まない。 Here, the suspension 12 used in this glass film forming step is controlled in the first range of the dielectric constant of the solvent (1) containing the lead-free glass fine particles, and then the organic solvent and the solvent (1). This is a suspension obtained by adding a mixed solution (electrolyte solution (2)) containing nitric acid as an electrolyte and controlling the electric conductivity (EC: Electro Conductivity) within the second range (see FIG. 10). In particular, this suspension 12 does not contain surface activity.

 なお、鉛フリーガラスからなる鉛フリーガラス微粒子として、例えば、次のようなガラス微粒子、すなわち、SiO、Al、CaO、MgO、ZnO、B、BaOの少なくとも何れか1つを含有し、かつ、Pbを実質的に含有しない原料を溶融させて得られる融液から作製された鉛フリーガラス微粒子を用いる。 The lead-free glass particles made of lead-free glass include, for example, at least one of the following glass particles, that is, SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , BaO. And lead-free glass particles prepared from a melt obtained by melting a raw material containing substantially no Pb.

 そして、溶媒(1)は、イソプロピルアルコールと酢酸エチルとの混合溶媒である。この溶媒(1)の誘電率を、混合溶媒における酢酸エチルの割合を調整することにより、既述の第1の範囲に制御する。例えば、溶媒(1)の誘電率の第1の範囲は、5~7の範囲である。 The solvent (1) is a mixed solvent of isopropyl alcohol and ethyl acetate. The dielectric constant of the solvent (1) is controlled to the first range described above by adjusting the ratio of ethyl acetate in the mixed solvent. For example, the first range of the dielectric constant of the solvent (1) is in the range of 5-7.

 ここで、図11は、イソプロピルアルコールと酢酸エチルとを含む混合溶媒である溶媒(1)の、イソプロピルアルコールと酢酸エチルの比率と、誘電率との関係の一例を示す図である。 Here, FIG. 11 is a diagram showing an example of the relationship between the dielectric constant and the ratio of isopropyl alcohol to ethyl acetate in the solvent (1) which is a mixed solvent containing isopropyl alcohol and ethyl acetate.

 この図11に示すように、この溶媒(1)の誘電率を、混合溶媒における酢酸エチルの割合を調整することにより、既述の第1の範囲に調整可能である。 As shown in FIG. 11, the dielectric constant of the solvent (1) can be adjusted to the first range described above by adjusting the ratio of ethyl acetate in the mixed solvent.

 また、電解質(2)は、有機溶剤(イソプロピルアルコール(IPA))と硝酸(HNO)との混合液である。この混合液の有機溶剤と硝酸との体積比は、例えば、1000:1~5である。なお、有機溶剤は、所望の特性が得られるものであれば、酢酸エチル、アセトン、エタノール、その他の有機溶剤も選択され得る。 The electrolyte (2) is a mixed solution of an organic solvent (isopropyl alcohol (IPA)) and nitric acid (HNO 3 ). The volume ratio of the organic solvent and nitric acid in this mixed solution is, for example, 1000: 1 to 5. As the organic solvent, ethyl acetate, acetone, ethanol, and other organic solvents can be selected as long as desired characteristics can be obtained.

 ここで、本実施形態では、既述の混合液(電解質溶液(2))を調整することで、懸濁液12の電気伝導度を既述の第2の範囲に制御する。この懸濁液12の電気伝導度の第2の範囲は、20nS/cm~100nS/cmの範囲である。 Here, in this embodiment, the electric conductivity of the suspension 12 is controlled to the second range described above by adjusting the above-described mixed solution (electrolyte solution (2)). The second range of the electrical conductivity of the suspension 12 is in the range of 20 nS / cm to 100 nS / cm.

 なお、従来の鉛を含有させた鉛ガラス粉末を電気泳動堆積法により半導体素子のメサ溝に堆積させる場合、鉛ガラス粉末を懸濁させた懸濁液の電気伝導度(導電率)は、150±50μS/cmである(既述の特開昭57-143832号公報参照)。なお、当該鉛ガラス粉末はアメリカ合衆国イノテック社から商品名IP760として市販されている(特開昭57-143832号公報の1ページ右下欄参照)。 When the conventional lead glass powder containing lead is deposited on the mesa groove of the semiconductor element by electrophoretic deposition, the electrical conductivity (conductivity) of the suspension in which the lead glass powder is suspended is 150. ± 50 μS / cm (refer to the above-mentioned JP-A-57-143832). The lead glass powder is commercially available under the trade name IP760 from Innotech, USA (see the lower right column on page 1 of JP-A-57-143832).

 この従来の懸濁液の電気伝導度の条件(150±50μS/cm)は、上述の本願の懸濁液12の電気伝導度の第2の範囲(20nS/cm~100nS/cm)と比較して大きく異なる(電気伝導度が高い範囲である)。 The electrical conductivity condition (150 ± 50 μS / cm) of this conventional suspension is compared with the second range (20 nS / cm to 100 nS / cm) of the electrical conductivity of the suspension 12 of the present application described above. Differ greatly (in the range of high electrical conductivity).

Figure JPOXMLDOC01-appb-I000001
Figure JPOXMLDOC01-appb-I000001

 このように、特開昭57-143832号公報には、懸濁液の導電率が100μS/cm以下である場合には、メサ型半導体素子のPN接合端部が露出する面のみならず、他の部分、例えば、SiO膜上にもガラス被膜が形成され、この後の製造工程において悪影響がもたらされることが記載されている。 As described above, Japanese Patent Application Laid-Open No. 57-143832 discloses that when the conductivity of the suspension is 100 μS / cm or less, not only the surface where the PN junction end of the mesa semiconductor element is exposed, but also other It is described that a glass film is also formed on this portion, for example, a SiO 2 film, and this has an adverse effect in the subsequent manufacturing process.

 すなわち、特開昭57-143832号公報に記載された、従来の鉛を含有させた鉛ガラス粉末を堆積させる電気泳動堆積法は、懸濁液の導電率を100μS/cm以下に設定して使用することを想定していない。 That is, the conventional electrophoretic deposition method for depositing lead glass powder containing lead described in JP-A-57-143832 is used by setting the conductivity of the suspension to 100 μS / cm or less. Not supposed to do.

 これに対し、本願の実施形態においては、懸濁液12の電気伝導度の第2の範囲は、鉛フリーガラス微粒子をメサ溝120の底部120aの少なくとも一部が露出した状態で精度よくメサ溝120に堆積させる条件として、上記の従来技術では使用しない100μS/cm以下の非常に低い、20nS/cm~100nS/cmの範囲に設定するものである。 On the other hand, in the embodiment of the present application, the second range of the electric conductivity of the suspension 12 is the mesa groove with high accuracy in a state where at least a part of the bottom 120a of the mesa groove 120 is exposed to the lead-free glass fine particles. The condition for depositing on 120 is set to a very low range of 20 nS / cm to 100 nS / cm, which is not used in the above-mentioned conventional technique, and is 100 μS / cm or less.

 なお、上記従来の懸濁液の電気伝導度の条件(150±50μS/cm)では、本実施形態で適用する鉛フリーガラスを電気泳動堆積法により半導体素子のメサ溝に堆積させることができないことが確認されている。 Note that the lead-free glass applied in the present embodiment cannot be deposited in the mesa groove of the semiconductor element by the electrophoretic deposition method under the above-described conventional electrical conductivity condition of the suspension (150 ± 50 μS / cm). Has been confirmed.

 一方、本実施形態では、既述の溶媒(1)に加えられる前に、混合液(電解質溶液(2))は、電気伝導度が第3の範囲に制御される。例えば、混合液(電解質溶液(2))の電気伝導度を、混合液における硝酸の割合を調整することにより、既述の第3の範囲に制御する。この混合液(電解質溶液(2))の電気伝導度の第3の範囲は、90μS/cm~130μS/cmの範囲である。 On the other hand, in the present embodiment, the electrical conductivity of the mixed solution (electrolyte solution (2)) is controlled in the third range before being added to the solvent (1) described above. For example, the electrical conductivity of the mixed solution (electrolyte solution (2)) is controlled to the third range described above by adjusting the ratio of nitric acid in the mixed solution. The third range of the electric conductivity of this mixed solution (electrolyte solution (2)) is in the range of 90 μS / cm to 130 μS / cm.

 なお、溶媒(1)の体積を、例えば、7l程度とした場合、電解質溶液(2)は30~40cc程度である。 When the volume of the solvent (1) is about 7 l, for example, the electrolyte solution (2) is about 30 to 40 cc.

 このように、本実施形態に係る半導体装置の製造方法においては、先ず鉛フリーガラス微粒子を含む溶媒の誘電率を第1の範囲(5~11)に制御し、次に誘電率を第1の範囲に制御した溶媒(イソプロピルアルコール(IPA)と酢酸エチルとの混合溶媒)に、電解質溶液(2)を加えて、電気伝導度を第2の範囲(20nS/cm~100nS/cm)に制御した懸濁液を用いる電気泳動堆積法により、当該懸濁液中の鉛フリーガラス微粒子を半導体ウェーハのメサ溝に堆積させる。特に、本実施形態では、既述の溶媒(1)に加えられる前に、電解質(2)は、電気伝導度が第3の範囲(90μS/cm~130μS/cm)に制御される。 As described above, in the method of manufacturing a semiconductor device according to the present embodiment, first, the dielectric constant of the solvent containing the lead-free glass fine particles is controlled within the first range (5 to 11), and then the dielectric constant is changed to the first dielectric constant. Electrolytic solution (2) was added to the solvent controlled to the range (mixed solvent of isopropyl alcohol (IPA) and ethyl acetate) to control the electric conductivity to the second range (20 nS / cm to 100 nS / cm). The lead-free glass particles in the suspension are deposited on the mesa grooves of the semiconductor wafer by electrophoretic deposition using the suspension. In particular, in this embodiment, before the electrolyte (2) is added to the solvent (1) described above, the electric conductivity of the electrolyte (2) is controlled within the third range (90 μS / cm to 130 μS / cm).

 さらに、既述のように、半導体ウェーハに形成されたメサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができる。 Furthermore, as described above, the thickness of the lead-free glass fine particles deposited in the mesa groove formed in the semiconductor wafer can be controlled to a predetermined thickness with high accuracy.

 特に、鉛フリーガラス微粒子の堆積物の厚さが所定の厚さに制御されるため、この堆積物を焼成してガラス化したパッシベーション膜の膜厚も所定の膜厚に制御されることとなり、半導体ウェーハから切断分離された半導体装置のパッシベーション膜の絶縁性(逆方向特性)のばらつきを低減して当該半導体装置の信頼性を向上ことが可能となる。 In particular, since the thickness of the lead-free glass particulate deposit is controlled to a predetermined thickness, the thickness of the passivation film obtained by firing and depositing the deposit is also controlled to a predetermined thickness. It is possible to improve the reliability of the semiconductor device by reducing variations in the insulating properties (reverse characteristics) of the passivation film of the semiconductor device cut and separated from the semiconductor wafer.

 (c)酸化膜除去工程
 次に、ガラス被膜124の表面を覆うようにフォトレジスト126を形成した後、当該フォトレジスト126をマスクとして酸化膜116のエッチングを行い、Niめっき電極膜を形成する部位130における酸化膜116を除去する(図5)。
(C) Oxide Film Removal Step Next, a photoresist 126 is formed so as to cover the surface of the glass coating 124, and then the oxide film 116 is etched using the photoresist 126 as a mask to form a Ni plating electrode film. The oxide film 116 in 130 is removed (FIG. 5).

 (d)粗面化領域形成工程
 次に、Niめっき電極膜を形成する部位130における半導体ウェーハ表面の粗面化処理を行い、Niめっき電極と半導体ウェーハとの密着性を高くするための粗面化領域132を形成する(図6)。
(D) Roughened region forming step Next, a roughened surface for increasing the adhesion between the Ni plated electrode and the semiconductor wafer by performing a roughening process on the surface of the semiconductor wafer in the portion 130 where the Ni plated electrode film is to be formed. The formation region 132 is formed (FIG. 6).

 (e)電極形成工程
 次に、半導体ウェーハWにNiめっきを行い、粗面化領域132上(半導体ウェーハWの一方の表面の隣接する2つのメサ溝120間)にアノード電極134を形成するとともに、半導体ウェーハWの他方の表面にカソード電極136を形成する(図7)。
(E) Electrode formation step Next, Ni plating is performed on the semiconductor wafer W to form the anode electrode 134 on the roughened region 132 (between two adjacent mesa grooves 120 on one surface of the semiconductor wafer W). Then, the cathode electrode 136 is formed on the other surface of the semiconductor wafer W (FIG. 7).

 (f)半導体ウェーハ切断工程
 次に、ダイシング又はレーザー等により、ガラス被膜124が形成されていないメサ溝120の底部120aの中央近傍に沿って、半導体ウェーハを切断して半導体ウェーハをチップ化して、半導体装置(メサ型のpnダイオード)100を製造する(図8)。
(F) Semiconductor wafer cutting step Next, the semiconductor wafer is cut into chips by cutting the semiconductor wafer along the vicinity of the center of the bottom 120a of the mesa groove 120 where the glass coating 124 is not formed by dicing, laser, or the like. A semiconductor device (mesa type pn diode) 100 is manufactured (FIG. 8).

 ここで、既述のガラス被膜形成工程で用いられる懸濁液12の特性を制御して、メサ溝120の底部120aの少なくとも一部(底部120aの中央近傍)が露出した(メサ溝120の底部に鉛フリーガラス微粒子の堆積物のガラス被膜124が形成されない)状態で、鉛フリーガラス微粒子の堆積物のガラス被膜124をメサ溝120の開口端120b周辺とメサ溝120の側壁120cを被覆するように精度良く所定の厚さに形成されている。 Here, by controlling the characteristics of the suspension 12 used in the glass coating forming process described above, at least a part of the bottom 120a of the mesa groove 120 (near the center of the bottom 120a) is exposed (the bottom of the mesa groove 120). In this state, the glass coating 124 of the lead-free glass fine particle deposit is formed so as to cover the periphery of the opening end 120b of the mesa groove 120 and the side wall 120c of the mesa groove 120. It is formed to a predetermined thickness with high accuracy.

 したがって、半導体ウェーハをチップ化するために、ダイシング又はレーザー等で半導体ウェーハをメサ溝120(底部120aの中央近傍)に沿って切断する際に、パシベーション膜であるガラス(ガラス被膜124)を切断する必要がなくなる。 Therefore, when the semiconductor wafer is cut along the mesa groove 120 (near the center of the bottom portion 120a) by dicing or laser to cut the semiconductor wafer into chips, the glass (glass coating 124) as the passivation film is cut. There is no need.

 すなわち、この半導体ウェーハ切断工程では、半導体ウェーハのシリコンを主として切断することとなる。これにより、切断の応力が低減され、半導体ウェーハのクラック等の発生が抑制され、半導体ウェーハの切断が容易になる。 That is, in this semiconductor wafer cutting step, silicon of the semiconductor wafer is mainly cut. Thereby, the stress of cutting | disconnection is reduced, generation | occurrence | production of the crack etc. of a semiconductor wafer is suppressed, and the cutting | disconnection of a semiconductor wafer becomes easy.

 以上のようにして、半導体装置(メサ型のpnダイオード)100を製造することができる。 As described above, the semiconductor device (mesa type pn diode) 100 can be manufactured.

 ここで、上述の第1の実施形態に係る半導体装置の製造方法の効果を説明する。 Here, the effect of the semiconductor device manufacturing method according to the first embodiment will be described.

 図12は、懸濁液12の電気伝導度とメサ溝120の底部120aの堆積物の付着状態との関係の一例を示す図である。また、図13は、ガラス被膜形成工程における、焼成前のガラス被膜124が成膜された状態の半導体ウェーハの上面の写真である。また、図14は、ガラス被膜形成工程における、焼成後のガラス被膜124を含むメサ溝120の断面の写真である。 FIG. 12 is a diagram showing an example of the relationship between the electrical conductivity of the suspension 12 and the adhesion state of the deposit on the bottom 120a of the mesa groove 120. FIG. 13 is a photograph of the upper surface of the semiconductor wafer in a state where the glass coating 124 before firing is formed in the glass coating formation step. FIG. 14 is a photograph of a cross section of the mesa groove 120 including the fired glass coating 124 in the glass coating formation step.

 図12に示すように、懸濁液12の電気伝導度の第2の範囲を、20nS/cm~100nS/cmの範囲に設定することで、鉛フリーガラス微粒子をメサ溝120の底部120aの少なくとも一部(例えば、底部120aの中央近傍)が露出した状態で精度よくメサ溝120に堆積させることができる。 As shown in FIG. 12, the second range of the electrical conductivity of the suspension 12 is set to a range of 20 nS / cm to 100 nS / cm, so that the lead-free glass fine particles can be removed at least from the bottom 120a of the mesa groove 120. It can be deposited in the mesa groove 120 accurately with a part (for example, near the center of the bottom 120a) exposed.

 そして、例えば、図13に示すように、実施形態に係るガラス被膜形成工程における、焼成前において、メサ溝120の底部120aの少なくとも一部(例えば、底部120aの中央近傍)が露出した状態で、ガラス被膜124がメサ溝120の開口端120b周辺とメサ溝120の側壁120cを被覆するように形成されているのが確認されている。 And, for example, as shown in FIG. 13, in the glass film forming step according to the embodiment, before firing, at least a part of the bottom 120a of the mesa groove 120 (for example, near the center of the bottom 120a) is exposed, It has been confirmed that the glass coating 124 is formed so as to cover the periphery of the opening end 120 b of the mesa groove 120 and the side wall 120 c of the mesa groove 120.

 さらに、例えば、図14に示すように、実施形態に係るガラス被膜形成工程における、焼成後において、メサ溝120の底部120aの少なくとも一部が露出した状態で、ガラス被膜124がメサ溝120の開口端120b周辺とメサ溝120の側壁120cを被覆するように形成されているのが確認できている。 Further, for example, as shown in FIG. 14, the glass coating 124 is opened in the mesa groove 120 in a state where at least a part of the bottom 120 a of the mesa groove 120 is exposed after firing in the glass film forming step according to the embodiment. It can be confirmed that it is formed so as to cover the periphery of the end 120 b and the side wall 120 c of the mesa groove 120.

 なお、既述のように、従来の電気泳動堆積法では、鉛フリーガラス微粒子の半導体ウェーハに対する付着性が安定せず、メサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができない。 As described above, in the conventional electrophoretic deposition method, the adherence of lead-free glass particles to the semiconductor wafer is not stable, and the thickness of the lead-free glass particles deposited in the mesa groove is accurately adjusted. It cannot be controlled to a predetermined thickness.

 一方、既述の条件を適用した実施形態に係る半導体装置の製造方法においては、メサ溝の底部の少なくとも一部が露出した状態で、鉛フリーガラス微粒子の堆積物のガラス被膜をメサ溝の開口端周辺とメサ溝の側壁を被覆するように精度良く所定の厚さに形成することができる。特に、鉛フリーガラス微粒子の半導体ウェーハに対する付着性が安定して、メサ溝に堆積される鉛フリーガラス微粒子の堆積物の厚さを精度良く所定の厚さに制御することができる。 On the other hand, in the method of manufacturing a semiconductor device according to the embodiment to which the above-described conditions are applied, the glass film of the lead-free glass fine particle deposit is opened in the mesa groove with at least a part of the bottom of the mesa groove exposed. It can be accurately formed to a predetermined thickness so as to cover the periphery of the end and the side wall of the mesa groove. In particular, the adherence of lead-free glass particles to the semiconductor wafer is stable, and the thickness of the deposit of lead-free glass particles deposited in the mesa groove can be accurately controlled to a predetermined thickness.

 以上のように、本発明の一態様に係る半導体装置の製造方法は、ガラス被膜形成面にメサ溝が形成された半導体ウェーハWを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第1電極板と第2電極板とを懸濁液に浸漬した状態で対向して設置するとともに、第1電極板と第2電極板との間に半導体ウェーハをガラス被膜形成面が第1電極板側に向いた状態で、電気泳動堆積法によりガラス被膜形成面にガラス被膜124を形成するガラス被膜形成工程と、を含む。 As described above, a method for manufacturing a semiconductor device according to an aspect of the present invention includes a semiconductor wafer preparation step of preparing a semiconductor wafer W having a mesa groove formed on a glass film formation surface, and a lead-free glass fine particle suspended in a solvent. The first electrode plate and the second electrode plate are placed opposite to each other in the suspended suspension and the semiconductor wafer is placed between the first electrode plate and the second electrode plate. And a glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition with the glass film forming surface facing the first electrode plate.

 そして、ガラス被膜形成工程は、メサ溝の底部の少なくとも一部が露出した状態で、鉛フリーガラス微粒子の堆積物であるガラス被膜をメサ溝の開口端120b周辺とメサ溝の側壁を被覆するように形成するものであり、ガラス被膜形成工程で用いられる懸濁液は、鉛フリーガラス微粒子を含む溶媒の誘電率を第1の範囲に制御した後、当該溶媒に、有機溶剤と電解質である硝酸とを含む混合液(電解質溶液)を加えて、その電気伝導度を第2の範囲に制御した懸濁液であり、溶媒の誘電率の第1の範囲は、5~7の範囲であり、懸濁液の電気伝導度の第2の範囲は、20nS/cm~100nS/cmの範囲である。 In the glass film forming step, the glass film, which is a deposit of lead-free glass fine particles, is covered with the periphery of the opening end 120b of the mesa groove and the side wall of the mesa groove with at least a part of the bottom of the mesa groove exposed. The suspension used in the glass film forming step is prepared by controlling the dielectric constant of the solvent containing lead-free glass fine particles in the first range, and then adding the organic solvent and the nitric acid that is an electrolyte to the solvent. And a mixed liquid (electrolyte solution) containing and a suspension whose electric conductivity is controlled in the second range, the first range of the dielectric constant of the solvent is in the range of 5-7, The second range of electrical conductivity of the suspension is in the range of 20 nS / cm to 100 nS / cm.

 これにより、メサ溝の底部の少なくとも一部が露出した状態で、鉛フリーガラス微粒子の堆積物のガラス被膜をメサ溝の開口端周辺とメサ溝の側壁を被覆するように精度良く所定の厚さに形成することができる。 As a result, with the at least part of the bottom of the mesa groove exposed, the glass film of the lead-free glass fine particle deposit is accurately coated to a predetermined thickness so as to cover the periphery of the opening end of the mesa groove and the side wall of the mesa groove. Can be formed.

 なお、上記実施形態においては、半導体ウェーハとしてシリコンからなる半導体ウェーハ板を用いたが、本発明はこれに限定されるものではない。例えば、SiC、GaN、GaOなどからなる半導体ウェーハを用いることもできる。 In the above embodiment, a semiconductor wafer plate made of silicon is used as the semiconductor wafer, but the present invention is not limited to this. For example, a semiconductor wafer made of SiC, GaN, GaO or the like can be used.

 本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。 Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

1 ガラス被膜形成装置 
10 槽 
12 懸濁液 
14 第1電極板 
16 第2電極板 
20 電源装置 
100 半導体装置
110 n-型半導体基板
112 p+型拡散層
114 n-型拡散層
116,118 酸化膜
120 溝(メサ溝)
120a メサ溝の底部
120b メサ溝の開口端
120c メサ溝の側壁
121 下地絶縁膜
124 ガラス被膜
126 フォトレジスト
130 Niめっき電極膜を形成する部位
132 粗面化領域
134 アノード電極
136 カソード電極
V1 第1電極板の電位
V2 第2電極板の電位
A 露出部
1 Glass film forming equipment
10 tanks
12 Suspension
14 First electrode plate
16 Second electrode plate
20 Power supply
100 Semiconductor device 110 n− type semiconductor substrate 112 p + type diffusion layer 114 n− type diffusion layers 116 and 118 Oxide film 120 groove (mesa groove)
120a Mesa groove bottom 120b Mesa groove opening edge 120c Mesa groove sidewall 121 Base insulating film 124 Glass coating 126 Photoresist 130 Ni plating electrode film forming portion 132 Roughened region 134 Anode electrode 136 Cathode electrode V1 First electrode Plate potential V2 Potential A of second electrode plate Exposed part

Claims (15)

 ガラス被膜形成面にメサ溝が形成された半導体ウェーハを準備する半導体ウェーハ準備工程と、鉛フリーガラス微粒子を溶媒に懸濁させた懸濁液に、第1電極板と第2電極板とを前記懸濁液に浸漬した状態で対向して設置するとともに、前記第1電極板と前記第2電極板との間に前記半導体ウェーハを前記ガラス被膜形成面が前記第1電極板側に向いた状態で、電気泳動堆積法により前記ガラス被膜形成面にガラス被膜を形成するガラス被膜形成工程と、を含む半導体装置の製造方法であって、
 前記ガラス被膜形成工程は、前記メサ溝の底部の少なくとも一部が露出した状態で、前記鉛フリーガラス微粒子の堆積物である前記ガラス被膜を前記メサ溝の開口端周辺と前記メサ溝の側壁を被覆するように形成するものであり、
 前記ガラス被膜形成工程で用いられる前記懸濁液は、
 前記鉛フリーガラス微粒子を含む前記溶媒の誘電率を第1の範囲に制御した後、当該溶媒に、有機溶剤と電解質である硝酸とを含む混合液を加えて、その電気伝導度を第2の範囲に制御した懸濁液であり、
 前記溶媒の誘電率の前記第1の範囲は、5~7の範囲であり、
 前記懸濁液の電気伝導度の前記第2の範囲は、20nS/cm~100nS/cmの範囲である
 ことを特徴とする半導体装置の製造方法。
A semiconductor wafer preparation step of preparing a semiconductor wafer having mesa grooves formed on a glass coating formation surface, and a suspension in which lead-free glass fine particles are suspended in a solvent, the first electrode plate and the second electrode plate are A state in which the semiconductor wafer is placed between the first electrode plate and the second electrode plate while facing each other while being immersed in the suspension, and the glass film forming surface faces the first electrode plate side A glass film forming step of forming a glass film on the glass film forming surface by electrophoretic deposition, and a method for manufacturing a semiconductor device,
In the glass film forming step, at least a part of the bottom of the mesa groove is exposed, the glass film that is a deposit of the lead-free glass fine particles is formed around the opening end of the mesa groove and the side wall of the mesa groove. It is formed to cover,
The suspension used in the glass film forming step is
After controlling the dielectric constant of the solvent containing the lead-free glass fine particles to the first range, a mixed liquid containing an organic solvent and nitric acid as an electrolyte is added to the solvent, and the electric conductivity is set to a second value. Suspension controlled to range
The first range of the dielectric constant of the solvent is in the range of 5-7;
The method of manufacturing a semiconductor device, wherein the second range of electric conductivity of the suspension is in a range of 20 nS / cm to 100 nS / cm.
 前記混合液を調整することで、前記懸濁液の前記電気伝導度を前記第2の範囲に制御することを特徴とする請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the electric conductivity of the suspension is controlled to the second range by adjusting the mixed solution.  前記溶媒に加えられる前に、前記混合液は、電気伝導度が第3の範囲に制御されており、前記混合液の電気伝導度の前記第3の範囲は、90μS/cm~130μS/cmの範囲であることを特徴とする請求項2に記載の半導体装置の製造方法。 Before being added to the solvent, the mixture is controlled in electrical conductivity to a third range, and the third range of electrical conductivity of the mixture is 90 μS / cm to 130 μS / cm. The method of manufacturing a semiconductor device according to claim 2, wherein the method is a range.  前記有機溶剤は、イソプロピルアルコール又は酢酸エチルであることを特徴とする請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the organic solvent is isopropyl alcohol or ethyl acetate.  前記混合液の前記電気伝導度を、前記混合液における前記硝酸の割合を調整することにより、前記第3の範囲に制御する
 ことを特徴とする請求項4に記載の半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 4, wherein the electrical conductivity of the mixed solution is controlled to the third range by adjusting a ratio of the nitric acid in the mixed solution.
 前記溶媒は、イソプロピルアルコールと酢酸エチルとを含む混合溶媒であることを特徴とする請求項5に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein the solvent is a mixed solvent containing isopropyl alcohol and ethyl acetate.  前記溶媒の誘電率を、前記混合溶媒における前記酢酸エチルの割合を調整することにより、前記第1の範囲に制御する
 ことを特徴とする請求項6に記載の半導体装置の製造方法。
The method of manufacturing a semiconductor device according to claim 6, wherein the dielectric constant of the solvent is controlled to the first range by adjusting a ratio of the ethyl acetate in the mixed solvent.
 前記鉛フリーガラス微粒子は、SiO、Al、CaO、MgO、ZnO、B、BaOの少なくとも何れか1つを含む鉛フリーガラス微粒子である
 ことを特徴とする請求項1に記載の半導体装置の製造方法。
The lead-free glass fine particles are lead-free glass fine particles containing at least one of SiO 2 , Al 2 O 3 , CaO, MgO, ZnO, B 2 O 3 , and BaO. The manufacturing method of the semiconductor device of description.
 前記半導体ウェーハ準備工程は、
 主面に平行なpn接合を備える半導体ウェーハを準備する工程と、
 前記半導体ウェーハの一方の表面から前記pn接合を超える深さのメサ溝を形成することにより、前記メサ溝の内面に前記pn接合の露出部を形成する工程と、
 前記pn接合の露出部を覆うように前記メサ溝の内面に下地絶縁膜を形成する工程と、を含む
 ことを特徴とする請求項3に記載の半導体装置の製造方法。
The semiconductor wafer preparation step
Preparing a semiconductor wafer having a pn junction parallel to the main surface;
Forming an exposed portion of the pn junction on the inner surface of the mesa groove by forming a mesa groove having a depth exceeding the pn junction from one surface of the semiconductor wafer;
Forming a base insulating film on the inner surface of the mesa groove so as to cover the exposed portion of the pn junction. The method for manufacturing a semiconductor device according to claim 3, wherein:
 前記懸濁液は、界面活性剤を含まないことを特徴とする請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the suspension does not contain a surfactant.  前記半導体ウェーハ準備工程は、半導体ウェーハの表面に前記メサ溝の側壁のpn接合の露出部を形成する工程と、前記pn接合の露出部を覆うように前記半導体ウェーハの表面に下地絶縁膜を形成する工程と、を含む
 ことを特徴とする請求項3に記載の半導体装置の製造方法。
The semiconductor wafer preparation step includes a step of forming an exposed portion of a pn junction of a side wall of the mesa groove on the surface of the semiconductor wafer, and forming a base insulating film on the surface of the semiconductor wafer so as to cover the exposed portion of the pn junction The method for manufacturing a semiconductor device according to claim 3, further comprising:
 前記ガラス被膜形成工程は、前記ガラス被膜を、前記メサ溝の開口端周辺及び前記メサ溝の側壁の前記下地絶縁膜の表面に形成する
 ことを特徴とする請求項9に記載の半導体装置の製造方法。
10. The semiconductor device manufacturing method according to claim 9, wherein in the glass coating forming step, the glass coating is formed on the surface of the base insulating film on the periphery of the opening end of the mesa groove and on the side wall of the mesa groove. Method.
 前記半導体ウェーハの前記一方の表面の隣接する2つの前記メサ溝間にアノード電極を形成するとともに、前記半導体ウェーハの他方の表面にカソード電極を形成する電極形成工程をさらに備える
 ことを特徴とする請求項12に記載の半導体装置の製造方法。
The method further comprises forming an anode electrode between two adjacent mesa grooves on the one surface of the semiconductor wafer, and forming a cathode electrode on the other surface of the semiconductor wafer. Item 13. A method for manufacturing a semiconductor device according to Item 12.
 前記ガラス被膜は、前記下地絶縁膜を介して、前記pn接合の露出部を覆っていることを特徴とする請求項12に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 12, wherein the glass coating covers an exposed portion of the pn junction through the base insulating film.  前記ガラス被膜が形成されていない前記メサ溝の前記底部の中央近傍に沿って前記半導体ウェーハを切断して前記半導体ウェーハをチップ化する半導体ウェーハ切断工程をさらに含む
 ことを特徴とする請求項14に記載の半導体装置の製造方法。
The semiconductor wafer cutting step of cutting the semiconductor wafer along the vicinity of the center of the bottom of the mesa groove where the glass film is not formed to form the semiconductor wafer into chips. The manufacturing method of the semiconductor device of description.
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