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WO2018176769A1 - 叠层结构及其制备方法 - Google Patents

叠层结构及其制备方法 Download PDF

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Publication number
WO2018176769A1
WO2018176769A1 PCT/CN2017/103979 CN2017103979W WO2018176769A1 WO 2018176769 A1 WO2018176769 A1 WO 2018176769A1 CN 2017103979 W CN2017103979 W CN 2017103979W WO 2018176769 A1 WO2018176769 A1 WO 2018176769A1
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material layer
layer
thickness
forming
width
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French (fr)
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元淼
赵娜
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a stacked structure and a method of fabricating the same.
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a laminated structure and a method of fabricating the same.
  • a laminated structure comprising: a substrate; at least one material layer on the substrate; a via hole passing through at least a portion of the at least one material layer, wherein The via has a stepped side surface; and another layer of material conforming to cover the side surface of the via.
  • the ratio of the thickness of the at least one material layer to the thickness of the other material layer is greater than 10.
  • the stacked structure further includes a thin film transistor; the at least one material layer covers at least the thin film transistor; the via exposes a source/drain of the thin film transistor or a gate; and the other material layer comprises a conductive layer.
  • the at least one material layer comprises an organic film layer.
  • the organic film layer has a thickness of about 20,000 angstroms and the conductive layer has a thickness of less than about 1000 angstroms.
  • the stacked structure further includes: a passivation layer on the conductive layer; and another conductive layer on the passivation layer.
  • a method of preparing a laminate structure comprising: forming at least one material layer on a substrate; forming at least one of the at least one material layer in the at least one material layer a portion of the via, wherein the via has a stepped side surface; and conforming another layer of material on the at least one material layer to cover a side surface of the via.
  • the ratio of the thickness of the at least one material layer to the thickness of the other material layer is greater than 10.
  • a method of forming the via includes: forming a first via having a first width through the at least one material layer, wherein a depth of the first via is less than the at least one a thickness of the material layer; and a second via having a second width through the at least one material layer at a bottom of the first via,
  • first width is greater than the second width, and a side surface of the second via is discontinuous from a side surface of the first via.
  • a method of forming the via includes: forming a third via having a third width through the at least one material layer; and forming a pass through the top of the third via a fourth via having a fourth width of at least one material layer,
  • the third width is smaller than the fourth width, and a side surface of the third via hole is discontinuous from a side surface of the fourth via hole.
  • the at least one material layer comprises an organic film layer.
  • the method of forming the via includes: forming the via having a stepped side surface once by using a halftone mask, wherein the halftone mask comprises a full transmissive zone, a semi-permeable zone on either side of the full transmissive zone, and a full obscuration zone on either side of the semi-permeable zone.
  • the method further includes forming a thin film transistor on the substrate before forming the at least one material layer, wherein the via exposes a source/drain or a gate of the thin film transistor,
  • the other material layer includes a conductive layer;
  • the method further includes: forming a passivation layer on the another material layer; and forming a further conductive layer on the passivation layer.
  • the organic film layer has a thickness of about 20,000 angstroms and the conductive layer has a thickness of less than about 1000 angstroms.
  • FIG. 1 is a cross-sectional view schematically showing a laminated structure according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view schematically showing a stacked structure including a thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 is a schematic view schematically showing formation of at least one material layer of a method of preparing a laminated structure according to an embodiment of the present disclosure
  • FIG. 4 is a schematic view schematically showing formation of via holes in a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 5 is a schematic view schematically showing another material layer forming a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 6 is a schematic view schematically showing formation of a first via hole in a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 7 is a schematic view schematically showing formation of a second via hole in a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 8 is a schematic view schematically showing formation of a third via hole in a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 9 is a schematic view schematically showing formation of a fourth via hole in a method of fabricating a stacked structure according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic view schematically showing formation of via holes in a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 11 is a schematic view schematically showing a laminated structure including a thin film transistor, in a method of fabricating a stacked structure, according to an embodiment of the present disclosure.
  • a laminated structure which includes a via having a stepped side surface, which can reduce the breakage of the layer above the via when the via is difficult due to difficulty in climbing the material. The risk of the line, thereby increasing product yield.
  • the term "stack" may include one or more layers.
  • FIG. 1 is a cross-sectional view schematically showing a laminated structure 10 in accordance with an embodiment of the present disclosure.
  • the laminated structure 10 includes a substrate 1, at least one material layer 6 on the substrate 1, a via hole passing through at least a portion of the at least one material layer 6, and a side surface conformally covering the via hole.
  • the substrate 1 may be a glass substrate.
  • the via hole has a stepped side surface, and the number of steps of the side surface of the via hole is greater than or equal to 1. In an exemplary embodiment, the number of steps of the side surface of the via is equal to one.
  • the thickness of the at least one material layer 6 is greater than the thickness of the other material layer 7.
  • the ratio of the thickness of the at least one material layer 6 to the thickness of the other material layer 7 is greater than 10.
  • the thin film transistor includes: a gate electrode 2 on the substrate 1, a gate insulating layer 3 on the substrate 1 and the gate electrode 2; an active layer 5 on a portion of the gate insulating layer 3; Source/drain electrode layers 4 on the active layer 5 and the gate insulating layer 3.
  • at least one material layer 6 covers at least the thin film transistor; the via exposes the source/drain; and the other material layer 7 includes the conductive layer 7.
  • the embodiment of the present invention is described by taking a bottom gate type thin film transistor as an example, the embodiment of the present invention is also applicable to the case of a top gate type thin film transistor, in which case the thin film transistor includes the substrate sequentially.
  • the laminated structure 20 further includes: being electrically conductive A passivation layer 8 on layer 7; and a further conductive layer 9 on passivation layer 8.
  • the passivation layer 8 serves as an insulation protection function to prevent interference of thin film transistors such as water vapor and impurities in the external environment.
  • At least one material layer 6 comprises an organic film layer 6.
  • the thickness of the organic film layer 6 is greater than the thickness of the conductive layer 7.
  • the organic film layer 6 has a thickness of about 20,000 angstroms and the conductive layer has a thickness of less than about 1000 angstroms.
  • the conductive layer 7 may be the pixel electrode layer 7; the further conductive layer 9 may be the common electrode layer 9.
  • the organic film layer 6 includes a binder, a photoinitiator, a crosslinking monomer, and the like; the pixel electrode layer 7 includes indium tin oxide; and the common electrode layer 9 includes indium tin oxide.
  • the pixel electrode layer 7 and the common electrode layer 9 may also include other conductive materials such as a transparent conductive oxide including indium zinc oxide or the like.
  • the prepared laminated structure includes a via having a stepped side surface, which can reduce the risk of disconnection when the via is over the via in the case where the via depth is deep, thereby improving the yield of the product.
  • FIG. 3 is a schematic view schematically showing formation of at least one material layer 6 of a method of preparing a laminated structure according to an embodiment of the present disclosure. As shown in FIG. 3, at least one material layer 6 is formed on the substrate 1.
  • the substrate 1 may be a glass substrate.
  • FIG. 4 is a schematic view schematically showing formation of vias 60 of a method of fabricating a stacked structure in accordance with an embodiment of the present disclosure.
  • a via 60 is formed in at least one of the material layers 6 through at least a portion of the at least one material layer 6.
  • the via 60 has a stepped side surface.
  • the number of steps of the side surface of the via 60 is equal to or greater than one. In an exemplary embodiment, the number of steps of the side surface of the via 60 is equal to one.
  • FIG. 5 is a schematic view schematically showing formation of another material layer 7 of a method of preparing a laminated structure according to an embodiment of the present disclosure. As shown in FIG. 5, another material layer 7 is conformally formed on at least one material layer 6 by deposition or sputtering or the like to cover the side surface of the via 60.
  • At least one material layer 6 has a greater thickness than the other material layer 7.
  • the ratio of the thickness of the at least one material layer 6 to the thickness of the other material layer 7 is greater than 10.
  • FIG. 6 and 7 illustrate a first method of forming vias 60.
  • 6 is a schematic view schematically showing formation of a first via hole 601 of a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 7 is a view schematically showing formation of a method of fabricating a stacked structure according to an embodiment of the present disclosure.
  • a first via 601 having a first width passing through at least one material layer 6 is formed by patterning.
  • the depth of the first via 601 is less than the thickness of the at least one material layer 6.
  • a second via 602 having a second width through at least one material layer 6 is then patterned at the bottom of the first via 601.
  • the first width is greater than the second width
  • the side surface of the second via 602 is discontinuous from the side surface of the first via 601.
  • the first via 601 and the second via 602 constitute a via 60 having a stepped side surface.
  • FIG. 8 is a schematic view schematically showing formation of a third via hole 603 of a method of fabricating a stacked structure according to an embodiment of the present disclosure
  • FIG. 9 is a view schematically showing formation of a method of fabricating a stacked structure according to an embodiment of the present disclosure.
  • a third via 603 having a third width passing through at least one material layer 6 is formed by patterning.
  • the third via 603 passes through the entire at least one material layer 6.
  • a fourth via 604 having a fourth width through at least one material layer 6 is then patterned on top of the third via 603.
  • the third width is smaller than the fourth width
  • the side surface of the third via 603 is discontinuous from the side surface of the fourth via 604.
  • the third via 603 and the fourth via 604 constitute a via 60 having a stepped side surface.
  • At least one material layer 6 comprises an organic film layer 6.
  • FIG. 10 is a schematic view schematically showing the formation of the via 60 in the case where the at least one material layer 6 includes the organic film layer 6.
  • a via hole 60 having a stepped side surface is formed in the organic film layer 6 by one half pattern using the halftone mask 100.
  • the halftone mask 10 includes a full transmissive region 101, a semi-transparent region 102 on either side of the full transmissive region 101, and a full obscuration region 103 on either side of the semipermeable region 102.
  • the region of the organic film layer 6 corresponding to the full-transmissive region 101 is completely exposed, and the region of the organic film layer 6 corresponding to the semi-transmissive region 102 is partially exposed, and the region of the organic film layer 6 corresponding to the full-shielding region 103 is exposed. No exposure.
  • the exposed portion of the organic film layer 6 is developed to form a via 60.
  • FIG 11 is a schematic view schematically showing the formation of a stacked structure 30 including a thin film transistor in a method of fabricating a stacked structure in accordance with an embodiment of the present disclosure.
  • a gate electrode 2, a gate insulating layer 3, an active layer 5, and a source/drain electrode layer 4 are sequentially formed on the substrate 1, wherein the gate electrode 2, the gate insulating layer 3, and the active layer 5 are formed.
  • the source-drain electrode layer 4 constitutes a thin film transistor; an organic film layer 6 is formed on the thin film transistor; and a via hole penetrating through the organic film layer 6 is formed once in the organic film layer 6, wherein the via hole has a stepped side surface, The via is exposed to the source/drain; another material layer 7 is conformally formed on the organic film layer 6, wherein the other material layer 7 comprises a conductive layer 7; the passivation layer 8 is conformally formed on the conductive layer 7; A further conductive layer 9 is formed on the passivation layer 8.
  • the embodiment of the present invention is described by taking a bottom gate type thin film transistor as an example, the embodiment of the present invention is also applicable to the case of a top gate type thin film transistor, in which case the thin film transistor includes the substrate sequentially.
  • the thickness of the organic film layer 6 is greater than the thickness of the conductive layer 7.
  • the organic film layer 6 has a thickness of about 20,000 angstroms and the conductive layer has a thickness of less than about 1000 angstroms.
  • conductive layer 7 includes a pixel electrode layer and yet another conductive layer 9 includes a common electrode layer.
  • the organic film layer 6 includes a binder, a photoinitiator, a crosslinking monomer, and the like; the pixel electrode layer 7 includes indium tin oxide; and the common electrode layer 9 includes indium tin oxide.
  • the pixel electrode layer 7 and the common electrode layer 9 further include other conductive materials such as a transparent conductive oxide including indium zinc oxide or the like.
  • the laminated structure includes a via having a stepped side surface capable of reducing the thickness of the layer including the via than the thickness of the layer above the via, reducing the layer over the via covering the via due to material creep The risk of disconnection occurs when the slope is difficult, thereby increasing product yield.

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Abstract

一种叠层结构（10）及其制备方法。所述叠层结构（10）包括：基板（1）；位于所述基板（1）上的至少一个材料层（6）；穿过所述至少一个材料层（6）的至少一部分的过孔，其中，所述过孔具有台阶状的侧表面；以及保形覆盖所述过孔的侧表面的另一材料层（7）。所述至少一个材料层（6）的厚度与所述另一材料层（7）的厚度的比率大于10。

Description

叠层结构及其制备方法
相关申请的交叉引用
本申请要求于2017年3月27日递交的中国专利申请第201710188507.8号优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及半导体技术领域，尤其涉及一种叠层结构及其制备方法。
背景技术
随着平板显示技术的不断推广，薄膜晶体管(Thin Film Transistor，TFT)的技术也得到迅速发展。掩模层数的不断增加致使TFT制备过程中的过孔现象更为普遍。当过孔深度过大，尤其是对于目前的有机膜过孔，其深度是上方导电层厚度的数十倍，如此高的厚度差很容易使得导电层过孔时由于爬坡困难而存在断线风险。
发明内容
本公开实施例提供了一种叠层结构及其制备方法。
在本公开的第一方面中，提供一种叠层结构，包括：基板；位于所述基板上的至少一个材料层；穿过所述至少一个材料层的至少一部分的过孔，其中，所述过孔具有台阶状的侧表面；以及保形覆盖所述过孔的侧表面的另一材料层。
在一个实施例中，所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。
在一个实施例中，所述叠层结构还包括薄膜晶体管；所述至少一个材料层至少覆盖所述薄膜晶体管；所述过孔暴露所述薄膜晶体管的源/漏极或 栅极；以及所述另一材料层包括导电层。
在一个实施例中，所述至少一个材料层包括有机膜层。
在一个实施例中，所述有机膜层的厚度为约20000埃，所述导电层的厚度小于约1000埃。
在一个实施例中，所述叠层结构还包括：位于所述导电层上的钝化层；以及位于所述钝化层上的又一导电层。
在本公开的第二方面中，还提供一种制备叠层结构的方法，包括：在基板上形成至少一个材料层；在所述至少一个材料层中形成穿过所述至少一个材料层的至少一部分的过孔，其中，所述过孔具有台阶状的侧表面；以及在所述至少一个材料层上保形形成另一材料层以覆盖所述过孔的侧表面。
在一个实施例中，所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。
在一个实施例中，形成所述过孔的方法包括：形成穿过所述至少一个材料层的具有第一宽度的第一过孔，其中，所述第一过孔的深度小于所述至少一个材料层的厚度；以及在所述第一过孔的底部形成穿过所述至少一个材料层的具有第二宽度的第二过孔，
其中，所述第一宽度大于所述第二宽度，所述第二过孔的侧表面与所述第一过孔的侧表面不连续。
在一个实施例中，形成所述过孔的方法包括：形成穿过所述至少一个材料层的具有第三宽度的第三过孔；以及在所述第三过孔的顶部形成穿过所述至少一个材料层的具有第四宽度的第四过孔，
其中，所述第三宽度小于所述第四宽度，所述第三过孔的侧表面与所述第四过孔的侧表面不连续。
在一个实施例中，所述至少一个材料层包括有机膜层。
在一个实施例中，形成所述过孔的方法包括：采用半色调掩模板一次构图形成具有台阶状的侧表面的所述过孔，其中，所述半色调掩膜板包括 全透区、位于所述全透区两侧的半透区和位于所述半透区两侧的全遮区。
在一个实施例中，所述方法还包括：在形成所述至少一个材料层之前在所述基板上形成薄膜晶体管，其中，所述过孔暴露所述薄膜晶体管的源/漏极或栅极，所述另一材料层包括导电层；
以及所述方法进一步包括：在所述另一材料层上形成钝化层；以及在所述钝化层上形成又一导电层。
在一个实施例中，所述有机膜层的厚度为约20000埃，所述导电层的厚度小于约1000埃。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所有可能的实施方式，并且不旨在限制本申请的范围，其中：
图1是示意性示出根据本公开实施例的一种叠层结构的截面图；
图2是示意性示出根据本公开实施例的包括薄膜晶体管的叠层结构的截面图；
图3是示意性示出根据本公开实施例的制备叠层结构的方法的形成至少一个材料层的示意图；
图4是示意性示出根据本公开实施例的制备叠层结构的方法的形成过孔的示意图；
图5是示意性示出根据本公开实施例的制备叠层结构的方法的形成另一材料层的示意图；
图6是示意性示出根据本公开实施例的制备叠层结构的方法的形成第一过孔的示意图；
图7是示意性示出根据本公开实施例的制备叠层结构的方法的形成第二过孔的示意图；
图8是示意性示出根据本公开实施例的制备叠层结构的方法的形成第三过孔的示意图；
图9是示意性示出根据本公开实施例的制备叠层结构的方法的形成第四过孔的示意图；
图10是示意性示出根据本公开实施例的制备叠层结构的方法的形成过孔的示意图；以及
图11是示意性示出根据本公开实施例的制备叠层结构的方法的形成包括薄膜晶体管的叠层结构的示意图。
贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征。
具体实施方式
首先需要说明的是，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
此外，在附图中，为了清楚起见夸大了各层的厚度及区域。应当理解的是，当提到层、区域、或组件在别的部分“上”时，指其直接位于别的部分上，或者也可能有别的组件介于其间。相反，当某个组件被提到“直接”位于别的组件上时，指并无别的组件介于其间。
另外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在 包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
现将参照附图更全面地描述示例性的实施例。
在本文描述的实施例中，提供一种叠层结构，该叠层结构中包括具有台阶状的侧表面的过孔，能够降低过孔上方的层覆盖过孔时由于材料爬坡困难而发生断线的风险，从而提高产品良率。可以理解的是，除非另外声明，在本发明中，术语“叠层”可以包括一个层或多个层。
图1是示意性示出根据本公开实施例的一种叠层结构10的截面图。如图1所示，叠层结构10包括基板1、位于基板1上的至少一个材料层6、穿过至少一个材料层6的至少一部分的过孔、以及保形覆盖该过孔的侧表面的另一材料层7。基板1可以为玻璃基板。在该实施例中，过孔具有台阶状的侧表面，过孔的侧表面的台阶数大于等于1。在一个示例性实施例中，过孔的侧表面的台阶数等于1。
在一个示例性实施例中，至少一个材料层6的厚度大于另一材料层7的厚度。可选地，至少一个材料层6的厚度与另一材料层7的厚度的比率大于10。
图2是示意性示出根据本公开实施例的包括薄膜晶体管的叠层结构20的截面图。如图2所示，薄膜晶体管包括：位于基板1上的栅极2；位于基板1和栅极2上的栅极绝缘层3；位于栅极绝缘层3的部分上的有源层5；以及位于有源层5和栅极绝缘层3上的源/漏电极层4。在该实施例中，至少一个材料层6至少覆盖薄膜晶体管；过孔暴露源/漏极；另一材料层7包括导电层7。可以理解的是，虽然以底栅型薄膜晶体管为例描述了本发明的实施例，但本发明实施例也同样适应于顶栅型薄膜晶体管的情况，在该情况下，薄膜晶体管包括依次位于基板上的有源层、栅极绝缘层、栅极或源/漏极，其中，过孔暴露栅极或源/漏极。
在一个示例性实施例中，如图2所示，叠层结构20还包括：位于导电 层7上的钝化层8；以及位于钝化层8上的又一导电层9。钝化层8起绝缘保护作用，可以防止外界环境的水汽、杂质等对薄膜晶体管的干扰。
在一个示例性实施例中，至少一个材料层6包括有机膜层6。在一个示例性实施例中，有机膜层6的厚度大于导电层7的厚度。可选地，有机膜层6的厚度为约20000埃，导电层的厚度小于约1000埃。
在一个示例性实施例中，导电层7可以为像素电极层7；又一导电层9可以为公共电极层9。
在一个示例性实施例中，有机膜层6包括粘合剂、光引发剂、交联单体等；像素电极层7包括氧化铟锡；公共电极层9包括氧化铟锡。
可以理解，像素电极层7和公共电极层9还可以包括其他导电材料，诸如包括氧化铟锌等的透明导电氧化物。
在本文描述的实施例中，还提供一种制备叠层结构的方法。制备出的叠层结构包括具有台阶状的侧表面的过孔，能够降低在过孔深度较深的情况下过孔上方的层过孔时发生断线的风险，从而提高产品良率。
现将参照图3至图11详细地描述本公开实施例提供的制备叠层结构的方法。
图3是示意性示出根据本公开实施例的制备叠层结构的方法的形成至少一个材料层6的示意图。如图3所示，在基板1上形成至少一个材料层6。基板1可以为玻璃基板。
图4是示意性示出根据本公开实施例的制备叠层结构的方法的形成过孔60的示意图。如图4所示，在至少一个材料层6中形成穿过至少一个材料层6的至少一部分的过孔60。在该实施例中，过孔60具有台阶状的侧表面。过孔60的侧表面的台阶数大于等于1。在一个示例性实施例中，过孔60的侧表面的台阶数等于1。
图5是示意性示出根据本公开实施例的制备叠层结构的方法的形成另一材料层7的示意图。如图5所示，通过沉积或溅射等方法在至少一个材料层6上保形形成另一材料层7以覆盖过孔60的侧表面。
在该实施例中，至少一个材料层6的厚度大于另一材料层7。可选地，至少一个材料层6的厚度与另一材料层7的厚度的比率大于10。
接下来，参照图6至图10描述形成过孔60的方法。
图6和图7示出形成过孔60的第一种方法。图6是示意性示出根据本公开实施例的制备叠层结构的方法的形成第一过孔601的示意图；图7是示意性示出根据本公开实施例的制备叠层结构的方法的形成第二过孔602的示意图。
如图6所示，首先，通过构图形成穿过至少一个材料层6的具有第一宽度的第一过孔601。第一过孔601的深度小于至少一个材料层6的厚度。
如图7所示，然后，在第一过孔601的底部构图形成穿过至少一个材料层6的具有第二宽度的第二过孔602。在该实施例中，第一宽度大于第二宽度，第二过孔602的侧表面与第一过孔601的侧表面不连续。第一过孔601和第二过孔602构成具有台阶状的侧表面的过孔60。
图8和图9示出形成过孔60的第二种方法。
图8是示意性示出根据本公开实施例的制备叠层结构的方法的形成第三过孔603的示意图；图9是示意性示出根据本公开实施例的制备叠层结构的方法的形成第四过孔604的示意图。
如图8所示，首先，通过构图形成穿过至少一个材料层6的具有第三宽度的第三过孔603。在一个示例性实施例中，第三过孔603穿过整个至少一个材料层6。
如图9所示，然后，在第三过孔603的顶部构图形成穿过至少一个材料层6的具有第四宽度的第四过孔604。在该实施例中，第三宽度小于第四宽度，第三过孔603的侧表面与第四过孔604的侧表面不连续。第三过孔603和第四过孔604构成具有台阶状的侧表面的过孔60。
在一个示例性实施例中，至少一个材料层6包括有机膜层6。图10是示意性示出在至少一个材料层6包括有机膜层6的情况下形成过孔60的示意图。
如图10所示，采用半色调掩模板100通过一次构图在有机膜层6中形成具有台阶状的侧表面的过孔60。在该实施例中，半色调掩模板10包括全透区101、位于全透区101两侧的半透区102和位于半透区102两侧的全遮区103。在曝光过程中，有机膜层6的与全透区101对应的区域完全曝光，有机膜层6的与半透区102对应的区域部分曝光，有机膜层6的与全遮区103对应的区域不曝光。然后，对有机膜层6的被曝光的部分进行显影以形成过孔60。
图11是示意性示出根据本公开实施例的制备叠层结构的方法的形成包括薄膜晶体管的叠层结构30的示意图。
如图11所示，在基板1上依次形成栅极2、栅极绝缘层3、有源层5、以及源漏电极层4，其中，栅极2、栅极绝缘层3、有源层5和源漏电极层4构成薄膜晶体管；在薄膜晶体管上形成有机膜层6；在有机膜层6中一次构图形成穿过有机膜层6的过孔，其中，过孔具有台阶状的侧表面，过孔暴露源/漏极；在有机膜层6上保形形成另一材料层7，其中，另一材料层7包括导电层7；在导电层7上保形形成钝化层8；以及在钝化层8上形成又一导电层9。可以理解的是，虽然以底栅型薄膜晶体管为例描述了本发明的实施例，但本发明实施例也同样适应于顶栅型薄膜晶体管的情况，在该情况下，薄膜晶体管包括依次位于基板上的有源层、栅极绝缘层、栅极或源/漏极，其中，过孔暴露栅极或源/漏极。
在一个示例性实施例中，有机膜层6的厚度大于导电层7的厚度。可选地，有机膜层6的厚度为约20000埃，导电层的厚度小于约1000埃。
在一个示例性实施例中，导电层7包括像素电极层，又一导电层9包括公共电极层。
在一个示例性实施例中，有机膜层6包括粘合剂、光引发剂、交联单体等；像素电极层7包括氧化铟锡；公共电极层9包括氧化铟锡。
可以理解，像素电极层7和公共电极层9还包括其他导电材料，诸如包括氧化铟锌等的透明导电氧化物。
在本公开的实施例中，描述了一种叠层结构及其制备方法。该叠层结构包括具有台阶状的侧表面的过孔，能够在包括该过孔的层的厚度大于过孔上方的层的厚度的情况下，降低过孔上方的层覆盖过孔时由于材料爬坡困难而发生断线的风险，从而提高产品良率。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (14)

  1. 一种叠层结构，包括：
    基板；
    位于所述基板上的至少一个材料层；
    穿过所述至少一个材料层的至少一部分的过孔，
    其中，所述过孔具有台阶状的侧表面；以及
    保形覆盖所述过孔的侧表面的另一材料层。
  2. 根据权利要求1所述的叠层结构，其中，所述至少一个材料层的厚度与所述另一材料层的厚度的比率大于10。
  3. 根据权利要求2所述的叠层结构，其中，所述叠层结构还包括薄膜晶体管；
    所述至少一个材料层至少覆盖所述薄膜晶体管；
    所述过孔暴露所述薄膜晶体管的源/漏极或栅极；以及
    所述另一材料层包括导电层。
  4. 根据权利要求3所述的叠层结构，其中，所述至少一个材料层包括有机膜层。
  5. 根据权利要求4所述的叠层结构，其中，所述有机膜层的厚度为约20000埃，所述导电层的厚度小于约1000埃。
  6. 根据权利要求4所述的叠层结构，其中，还包括：位于所述导电层上的钝化层；以及
    位于所述钝化层上的又一导电层。
  7. 一种制备叠层结构的方法，其中，包括：
    在基板上形成至少一个材料层；
    在所述至少一个材料层中形成穿过所述至少一个材料层的至少一部分的过孔，其中，所述过孔具有台阶状的侧表面；以及
    在所述至少一个材料层上保形形成另一材料层以覆盖所述过孔的侧表面。
  8. 根据权利要求7所述的方法，其中，所述至少一个材料层的厚度与 所述另一材料层的厚度的比率大于10。
  9. 根据权利要求7所述的方法，其中，形成所述过孔的方法包括：形成穿过所述至少一个材料层的具有第一宽度的第一过孔，其中，所述第一过孔的深度小于所述至少一个材料层的厚度；以及在所述第一过孔的底部形成穿过所述至少一个材料层的具有第二宽度的第二过孔，
    其中，所述第一宽度大于所述第二宽度，所述第二过孔的侧表面与所述第一过孔的侧表面不连续。
  10. 根据权利要求7所述的方法，其中，形成所述过孔的方法包括：形成穿过所述至少一个材料层的具有第三宽度的第三过孔；以及在所述第三过孔的顶部形成穿过所述至少一个材料层的具有第四宽度的第四过孔，
    其中，所述第三宽度小于所述第四宽度，所述第三过孔的侧表面与所述第四过孔的侧表面不连续。
  11. 根据权利要求7所述的方法，其中，所述至少一个材料层包括有机膜层。
  12. 根据权利要求11所述的方法，其中，形成所述过孔的方法包括：采用半色调掩模板一次构图形成具有台阶状的侧表面的所述过孔，其中，所述半色调掩模板包括全透区、位于所述全透区两侧的半透区和位于所述半透区两侧的全遮区。
  13. 根据权利要求11所述的方法，其中，所述方法还包括：在形成所述至少一个材料层之前在所述基板上形成薄膜晶体管，其中，所述过孔暴露所述薄膜晶体管的源/漏极或栅极，所述另一材料层包括导电层；
    以及所述方法进一步包括：
    在所述另一材料层上形成钝化层；以及
    在所述钝化层上形成又一导电层。
  14. 根据权利要求13所述的叠层结构的制备方法，其中，所述有机膜层的厚度为约20000埃，所述导电层的厚度小于约1000埃。
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