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WO2018157572A1 - 移位寄存器及其驱动方法、栅极驱动装置以及显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动装置以及显示装置 Download PDF

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Publication number
WO2018157572A1
WO2018157572A1 PCT/CN2017/100381 CN2017100381W WO2018157572A1 WO 2018157572 A1 WO2018157572 A1 WO 2018157572A1 CN 2017100381 W CN2017100381 W CN 2017100381W WO 2018157572 A1 WO2018157572 A1 WO 2018157572A1
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Prior art keywords
transistor
output
node
coupled
clock signal
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PCT/CN2017/100381
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English (en)
French (fr)
Inventor
马占洁
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US15/759,420 priority Critical patent/US10490150B2/en
Priority to EP17847706.3A priority patent/EP3591644B1/en
Publication of WO2018157572A1 publication Critical patent/WO2018157572A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0221—Addressing of scan or signal lines with use of split matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0294—Details of sampling or holding circuits arranged for use in a driver for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/022—Power management, e.g. power saving in absence of operation, e.g. no data being entered during a predetermined time

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register suitable for a folded display and a method of driving the same, a gate driving device, an array substrate, and a display device.
  • the liquid crystal display panel is composed of a vertical and horizontal array pixel matrix.
  • the gate scan signal is outputted by the gate driving device during the display process, and each pixel unit is scanned line by line.
  • Gate driver on Array is a technology that integrates a shift register on an array substrate. Each GOA unit as a shift register unit sequentially transfers the scan signal to the next GOA unit, thereby turning on the switching transistors in the pixel unit row by row to input the data signals of the pixel units.
  • the embodiments described herein provide a shift register suitable for folding display and a driving method thereof, a gate driving device, an array substrate, and a display device, which are capable of better controlling the delay of an output signal, and are more advantageous for driving. Fold the display.
  • a shift register includes an input circuit, a hold circuit, a select output circuit, a first output circuit, a second output circuit, and a third output circuit.
  • the input circuit is configured to control the first node according to a start signal from the input, a first clock signal from the first clock signal terminal, and a first voltage from the first voltage terminal And the voltage of the second node.
  • the hold circuit is configured to maintain voltages of the first and second nodes, and output signals of the first and second output circuits.
  • the selection output circuit is configured to select the first output circuit and/or the second output circuit to output a scan signal and control the voltage of the third node and/or the fourth node according to the voltage of the second node.
  • the first output circuit is configured to output the first output signal from the first output according to the voltages of the first node and the third node.
  • the second output circuit is configured to output a second output signal from the second output based on the voltages of the first node and the fourth node.
  • the third output circuit is configured to output a third output signal from the third output based on the second clock signal and the voltage of the second node.
  • the input circuit includes a first transistor, a second transistor, and a third transistor.
  • the control electrode of the first transistor is coupled to the first clock signal terminal, the first electrode of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the second node.
  • the control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the first voltage terminal, and the second electrode of the second transistor is coupled to the first node.
  • the control electrode of the third transistor is coupled to the second node, the first electrode of the third transistor is coupled to the first clock signal terminal, and the second electrode of the third transistor is coupled to the first node.
  • the holding circuit includes a first capacitor, a second capacitor, a third capacitor, a fourth transistor, and a fifth transistor.
  • the first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the second voltage end.
  • the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the first output end.
  • the first end of the third capacitor is coupled to the second node, and the second end of the third capacitor is coupled to the second output end.
  • the control electrode of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the second voltage terminal, and the second electrode of the fourth transistor is coupled to the first electrode of the fifth transistor.
  • the control electrode of the fifth transistor is coupled to the second clock signal terminal, and the second electrode of the fifth transistor is coupled to the second node.
  • the selection output circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor.
  • the control electrode of the sixth transistor is coupled to the first selection signal, the first electrode of the sixth transistor is coupled to the second node, and the second electrode of the sixth transistor is coupled to the third node.
  • the control electrode of the seventh transistor is coupled to the second selection signal, the first electrode of the seventh transistor is coupled to the second voltage terminal, and the second electrode of the seventh transistor is coupled to the third node.
  • the control electrode of the eighth transistor is coupled to the third selection signal, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the fourth node point.
  • the control electrode of the ninth transistor is coupled to the fourth selection signal, the first electrode of the ninth transistor is coupled to the second voltage terminal, and the second electrode of the ninth transistor is coupled to the fourth node.
  • the first output circuit includes a tenth transistor and an eleventh transistor.
  • the control electrode of the tenth transistor is coupled to the first node, the first electrode of the tenth transistor is coupled to the second voltage terminal, and the second electrode of the tenth transistor is coupled to the first output terminal.
  • the control electrode of the eleventh transistor is coupled to the third node, the first electrode of the eleventh transistor is coupled to the second clock signal terminal, and the second electrode of the eleventh transistor is coupled to the first output terminal.
  • the second output circuit includes a twelfth transistor and a thirteenth transistor.
  • the control electrode of the twelfth transistor is coupled to the first node, the first electrode of the twelfth transistor is coupled to the second voltage terminal, and the second electrode of the twelfth transistor is coupled to the second output terminal.
  • the control electrode of the thirteenth transistor is coupled to the fourth node, the first pole of the thirteenth transistor is coupled to the second clock signal terminal, and the second pole of the thirteenth transistor is coupled to the second output terminal.
  • the third output circuit includes a fourteenth transistor and a fifteenth transistor.
  • the control electrode of the fourteenth transistor is coupled to the second clock signal terminal, the first electrode of the fourteenth transistor is coupled to the second node, and the second electrode of the fourteenth transistor is coupled to the third output terminal.
  • the control electrode of the fifteenth transistor is coupled to the second node, the first pole of the fifteenth transistor is coupled to the second clock signal end, and the second pole of the fifteenth transistor is coupled to the third output end.
  • the duty ratio of the first clock signal is greater than 1/2, and the second clock signal is different from the first clock signal by half a cycle.
  • a driving method of driving a shift register as described above.
  • the voltages of the first node and the second node are controlled by the input circuit to control the outputs of the first and second output circuits, and the voltage according to the second node and the second clock signal in the first period of time Controlling the output of the third output circuit.
  • the voltage of the first node is inverted by the holding circuit, the voltage of the first node is inverted under the control of the input circuit, and the voltages of the third node and the fourth node are controlled by selecting the output circuit to respectively control the first An output circuit and an output of the second output circuit.
  • the voltages of the first node and the second node are controlled by an input circuit to control the outputs of the first and second output circuits. Holding the voltages of the first and second nodes during the fourth time period, controlling the first and second output circuits by the voltage of the first node Output.
  • the second clock signal in a second period of time, in a case where the second clock signal is turned on to the path of the first output circuit by controlling the voltage of the third node, the second clock signal is output from the first output circuit. In the case where the second clock signal is turned off to the path of the first output circuit by controlling the voltage of the third node, the output of the first output circuit is held by the hold circuit.
  • the second clock signal in a second period of time, in a case where the second clock signal is turned on to the path of the second output circuit by controlling the voltage of the fourth node, the second clock signal is output from the second output circuit. In the case where the second clock signal is turned off to the path of the second output circuit by controlling the voltage of the fourth node, the output of the second output circuit is held by the hold circuit.
  • a gate driving device includes a plurality of cascaded shift registers as described above.
  • a scan enable signal is input to the input of the first stage shift register.
  • the input end of the other stage shift register is coupled to the third output end of the shift register of the first stage, the first clock signal end is coupled to the second clock signal end of the shift register of the first stage, and the second clock signal end is coupled The first clock signal terminal of the primary shift register.
  • an array substrate comprising the gate driving device as described above.
  • a display device comprising the array substrate as described above.
  • the shift register structure is modified to be suitable for folding display, and the delay of the output signal can be better controlled, and the array for folding display is more facilitated.
  • Substrate and display device are included in the shift register structure.
  • FIG. 1 is a diagram showing an example of a conventional drive circuit suitable for a folded display
  • FIG. 2 is an exemplary block diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 3 is an exemplary circuit diagram of a shift register in accordance with an embodiment of the present disclosure.
  • Figure 4 is a timing diagram of signals of the shift register shown in Figure 3;
  • FIG. 5 is an exemplary block diagram of a gate driving device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a driving method of driving a shift register as shown in FIG. 2 according to an embodiment of the present disclosure
  • FIG. 7 illustrates a schematic structural view of a display device according to an embodiment of the present disclosure.
  • the source and drain (emitter and collector) of the transistor are symmetrical, and the source and drain (emitter and collector) of the N-type transistor and the P-type transistor
  • the conduction currents are opposite in direction, so in the embodiments of the present disclosure, the controlled intermediate end of the transistor is referred to as the control pole, the signal input terminal is referred to as the first pole, and the signal output terminal is referred to as the second pole.
  • the transistors employed in the embodiments of the present disclosure are primarily switching transistors.
  • terms such as "first" and "second” are used to distinguish one component (or a portion of the component) from another component (or another portion of the component).
  • the structure of the existing driving circuit for driving the foldable display screen is, for example, as shown in FIG. structure.
  • the driving circuit synchronously transmits the same scanning signal to the display areas on the left and right sides by using a plurality of cascaded conventional shift registers, and controls the left and right display areas by a control circuit disposed between the shift register and the left and right display areas. Turn it on and off.
  • the display of the left display area is controlled by the control signals S1 and S2
  • the display of the right display area is controlled by the control signals S3 and S4.
  • this approach can make it more difficult to control the delay of the output signal.
  • FIG. 2 shows an exemplary block diagram of a shift register 100 in accordance with an embodiment of the present disclosure.
  • the shift register 100 includes an input circuit 110, a hold circuit 120, a selection output circuit 130, a first output circuit 140, a second output circuit 150, and a third output circuit 160.
  • the input circuit 110 is connected to the holding circuit 120, the selection output circuit 130, the first output circuit 140, the second output circuit 150, and the third output circuit 160, and is configured to be derived from the first clock signal according to a start signal from the input terminal STV.
  • the first clock signal CLK1 of the terminal CLK1 and the first voltage VGL from the first voltage terminal control the voltages of the first node P and the second node Q between the terminal CLK1 and the holding circuit 120.
  • the holding circuit 120 is connected to the selection output circuit 130, the first output circuit 140, the second output circuit 150, and the third output circuit 160, and is configured to maintain voltages of the first node P and the second node Q, and the first output The output voltage of circuit 140 and second output circuit 150.
  • the selection output circuit 130 is connected to the first output circuit 140 and the second output circuit 150 and configured to be based on the first selection signal SW1, the second selection signal SW2, the voltage of the second node Q, and the second voltage VGH from the second voltage terminal.
  • the voltage of the third node X is controlled, and the voltage of the fourth node Y is controlled according to the third selection signal SW3, the fourth selection signal SW4, the voltage of the second node Q, and the second voltage VGH.
  • the first output circuit 140 is configured to selectively output the second clock signal CLK2 or the second voltage VGH from the second clock signal terminal CLK2 from the first output terminal OUTPUT_L according to the voltages of the first node P and the third node X.
  • the second output circuit 150 is configured to selectively output the second clock signal CLK2 or the second voltage VGH from the second output terminal OUTPUT_R according to the voltages of the first node P and the fourth node Y.
  • the third output circuit 160 is configured to be based on the second clock signal CLK2 and the second node Q The voltage selectively outputs the voltage of the second clock signal CLK2 or the second node Q from the third output terminal OUTPUT_N.
  • the shift register 100 Since the selection output circuit 130 is disposed between the input circuit 110 and the first output circuit 140 and the second output circuit 150, it is possible to make an output of the scan signal before the first output circuit 140 and the second output circuit 150 output signals. The selection, therefore, the shift register 100 according to the present embodiment can better control the delay of the output signal. Further, the shift register 100 according to the present embodiment has the third output circuit 160 which is not controlled by the selection output circuit 130, and the third output circuit 160 can be shifted to the next stage regardless of whether or not the scan signal is output to the left and right display areas. The bit register provides the start signal.
  • FIG. 3 shows an exemplary circuit diagram of a shift register 100 in accordance with an embodiment of the present disclosure.
  • the input circuit 110 includes a first transistor MT1, a second transistor MT2, and a third transistor MT3.
  • the control electrode of the first transistor MT1 is coupled to the first clock signal terminal CLK1, the first electrode of the first transistor MT1 is coupled to the input terminal STV, and the second electrode of the first transistor MT1 is coupled to the second node Q.
  • the control electrode of the second transistor MT2 is coupled to the first clock signal terminal CLK1, the first electrode of the second transistor MT2 is coupled to the first voltage terminal, and the second electrode of the second transistor MT2 is coupled to the first node P.
  • the control electrode of the third transistor MT3 is coupled to the second node Q.
  • the first electrode of the third transistor MT3 is coupled to the first clock signal terminal CLK1, and the second electrode of the third transistor MT3 is coupled to the first node P.
  • the holding circuit 120 includes a first capacitor CS1, a second capacitor CS2, a third capacitor CS3, a fourth transistor MT4, and a fifth transistor MT5.
  • the first end of the first capacitor CS1 is coupled to the first node P, and the second end of the first capacitor CS1 is coupled to the second voltage end.
  • the first end of the second capacitor CS2 is coupled to the second node Q, and the second end of the second capacitor CS2 is coupled to the first output terminal OUTPUT_L.
  • the first end of the third capacitor CS3 is coupled to the second node Q, and the second end of the third capacitor CS3 is coupled to the second output terminal OUTPUT_R.
  • the control electrode of the fourth transistor MT4 is coupled to the first node P, the first electrode of the fourth transistor MT4 is coupled to the second voltage terminal, and the second electrode of the fourth transistor MT4 is coupled to the first electrode of the fifth transistor MT5.
  • the control electrode of the fifth transistor MT5 is coupled to the second clock signal terminal CLK2, and the second electrode of the fifth transistor MT5 is coupled to the second node Q.
  • the selection output circuit 130 includes a sixth transistor MT6, a seventh transistor MT7, an eighth transistor MT8, and a ninth transistor MT9.
  • the control electrode of the sixth transistor MT6 is coupled to the first selection signal
  • the first pole of the sixth transistor MT6 is coupled to the second node Q
  • the second pole of the sixth transistor MT6 is coupled to the third node X.
  • the control electrode of the seventh transistor MT7 is coupled to the second selection signal SW2, the first electrode of the seventh transistor MT7 is coupled to the second voltage terminal, and the second electrode of the seventh transistor MT7 is coupled to the third node X.
  • the control electrode of the eighth transistor MT8 is coupled to the third selection signal SW3, the first electrode of the eighth transistor MT8 is coupled to the second node Q, and the second electrode of the eighth transistor MT8 is coupled to the fourth node Y.
  • the control electrode of the ninth transistor MT9 is coupled to the fourth selection signal SW4, the first electrode of the ninth transistor MT9 is coupled to the second voltage terminal, and the second electrode of the ninth transistor MT9 is coupled to the fourth node Y.
  • the first output circuit 140 includes a tenth transistor MT10 and an eleventh transistor MT11.
  • the first pole of the tenth transistor MT10 is coupled to the first node P
  • the first pole of the tenth transistor MT10 is coupled to the second voltage terminal
  • the second pole of the tenth transistor MT10 is coupled to the first output terminal OUTPUT_L.
  • the control electrode of the eleventh transistor MT11 is coupled to the third node X.
  • the first electrode of the eleventh transistor MT11 is coupled to the second clock signal terminal CLK2, and the second electrode of the eleventh transistor MT11 is coupled to the first output terminal OUTPUT_L.
  • the second output circuit 150 includes a twelfth transistor MT12 and a thirteenth transistor MT13.
  • the first pole of the twelfth transistor MT12 is coupled to the first node P
  • the first pole of the twelfth transistor MT12 is coupled to the second voltage terminal
  • the second pole of the twelfth transistor MT12 is coupled to the second output terminal OUTPUT_R.
  • the control electrode of the thirteenth transistor MT13 is coupled to the fourth node Y.
  • the first electrode of the thirteenth transistor MT13 is coupled to the second clock signal terminal CLK2, and the second electrode of the thirteenth transistor MT13 is coupled to the second output terminal OUTPUT_R.
  • the third output circuit 160 includes a fourteenth transistor MT14 and a fifteenth transistor MT15.
  • the control electrode of the fourteenth transistor MT14 is coupled to the second clock signal terminal CLK2, the first electrode of the fourteenth transistor MT14 is coupled to the second node Q, and the second electrode of the fourteenth transistor MT14 is coupled to the third output terminal OUTPUT_N.
  • the first pole of the fifteenth transistor MT15 is coupled to the second clock terminal CLK2, and the second pole of the fifteenth transistor MT15 is coupled to the third output terminal OUTPUT_N.
  • Fig. 4 is a timing chart showing signals of the shift register shown in Fig. 3.
  • the operation of the shift register unit 100 according to an embodiment of the present disclosure will be described below by taking a P-type transistor as an example with reference to FIG. process.
  • the first voltage VGL "0”, indicating a low voltage
  • the second voltage VGH "1”, indicating a high voltage.
  • the first clock signal CLK1 is a low voltage
  • the first transistor MT1 and the second transistor MT2 are turned on.
  • the low voltage from the first voltage VGL is input to the first node P through the second transistor MT2, so that the tenth transistor MT10 and the twelfth transistor MT12 are turned on, thereby outputting at both the first output terminal OUTPUT_L and the second output terminal OUTPUT_R A high voltage will be taken from the second voltage VGH.
  • the low voltage from the input terminal STV is input to the second node Q through the first transistor MT1, thereby charging the first ends of the second capacitor CS2 and the third capacitor CS3 with a low voltage.
  • the low voltage from the second node Q causes the third node X and the fourth node Y to be low voltages through the sixth transistor MT6 and the eighth transistor MT8, respectively. Therefore, the eleventh transistor MT11 and the thirteenth transistor MT13 are turned on, so that the high voltage from the second clock signal CLK2 is outputted at both the first output terminal OUTPUT_L and the second output terminal OUTPUT_R.
  • the third output circuit 160 since the second node Q is a low voltage, the fifteenth transistor MT15 is turned on, and the high voltage from the second clock signal CLK2 is output from the third output terminal OUTPUT_N. Further, the high voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned off, so the voltage of the second node Q does not affect the output of the third output terminal OUTPUT_N.
  • the first clock signal CLK1 is a high voltage
  • the first transistor MT1 and the second transistor MT2 are turned off.
  • the voltage of the second node Q is held at a low voltage by the second capacitor CS2 and the third capacitor CS3, so that the third node X and the fourth node Y are at a low voltage. Therefore, the eleventh transistor MT11 and the thirteenth transistor MT13 are turned on, thereby being at the first output terminal OUTPUT_L And the second output terminal OUTPUT_R outputs a low voltage to be derived from the second clock signal CLK2. Further, the low voltage from the second node Q turns on the third transistor MT3.
  • the high voltage from the first clock signal CLK1 is input to the first node P through the third transistor MT3, thereby turning off the tenth transistor MT10 and the twelfth transistor MT12. Therefore, the high voltage from the second voltage VGH does not affect the signals of the first output terminal OUTPUT_L and the second output terminal OUTPUT_R at this stage.
  • the third output circuit 160 since the second node Q is a low voltage, the fifteenth transistor MT15 is turned on, and the low voltage from the second clock signal CLK2 is output from the third output terminal OUTPUT_N. Further, the low voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned on, and also causes the third output terminal OUTPUT_N to output a low voltage from the second node Q.
  • the first transistor MT1 and the second transistor MT2 are turned on.
  • the low voltage from the first voltage VGL is input to the first node P through the second transistor MT2 such that the first end of the first capacitor CS1 is charged with a low voltage and the tenth transistor MT10 and the twelfth transistor MT12 are turned on, Thereby, a high voltage from the second voltage VGH is outputted at both the first output terminal OUTPUT_L and the second output terminal OUTPUT_R.
  • the high voltage from the input terminal STV is input to the second node Q through the first transistor MT1, thereby charging the first ends of the second capacitor CS2 and the third capacitor CS3 with a high voltage.
  • the high voltage from the second node Q causes the third node X and the fourth node Y to be high voltages through the sixth transistor MT6 and the eighth transistor MT8, respectively. Therefore, the eleventh transistor MT11 and the thirteenth transistor MT13 are turned off, and at this stage, the first output terminal OUTPUT_L and the second output terminal OUTPUT_R are not affected by the second clock signal CLK2.
  • the third output circuit 160 since the second node Q is a high voltage, the fifteenth transistor MT15 is turned off. And the high voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned off, so the voltage of the third output terminal OUTPUT_N is not controlled by the shift register of this stage at this stage.
  • the first clock signal CLK1 is a high voltage
  • the first transistor MT1 and the second transistor MT2 are turned off.
  • the voltage of the first node P is maintained at a low voltage by the first capacitor CS1
  • the tenth transistor MT10 and the twelfth transistor MT12 are turned on, so that a high voltage from the second voltage VGH is outputted at both the first output terminal OUTPUT_L and the second output terminal OUTPUT_R.
  • the low voltage from the first node P turns on the fourth transistor MT4, and the low voltage from the second clock signal CLK2 turns on the fifth transistor MT5, so the high voltage from the second voltage VGH passes through the fourth transistor MT4 and the fifth Transistor MT5 causes second node Q to be at a high voltage.
  • the high voltage from the second node Q causes the third node X and the fourth node Y to be high voltages through the sixth transistor MT6 and the eighth transistor MT8, respectively. Therefore, the eleventh transistor MT11 and the thirteenth transistor MT13 are turned off, and at this stage, the first output terminal OUTPUT_L and the second output terminal OUTPUT_R are not affected by the second clock signal CLK2.
  • the fifteenth transistor MT15 is turned off.
  • the low voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned on, thereby outputting a high voltage from the second node Q at the third output terminal OUTPUT_N.
  • the duty ratio of the first clock signal CLK1 is greater than 1/2, and the second clock signal CLK2 is different from the first clock signal CLK1 by half a cycle. Since the first clock signal CLK1 and the second clock signal CLK2 are both at a high voltage when transitioning from one phase to the next, the output voltage of the shift register 100 can be prevented from being unstable.
  • the second clock signal CLK2 is also The high voltage prevents the instability of the output voltage of the first output terminal OUTPUT_L and the second output terminal OUTPUT_R.
  • the selection output circuit for the first output terminal OUTPUT_L and the second output terminal OUTPUT_R is configured to control the control terminals of the eleventh transistor MT11 and the thirteenth transistor MT13 such that the first output terminal OUTPUT_L and the second output terminal OUTPUT_R The delay of the output signal can be better controlled.
  • the first clock signal CLK1 is a low voltage
  • the first transistor MT1 and the second transistor MT2 are turned on.
  • the low voltage from the first voltage VGL is input to the first node P through the second transistor MT2, so that the tenth transistor MT10 and the twelfth transistor MT12 are turned on, thereby outputting at both the first output terminal OUTPUT_L and the second output terminal OUTPUT_R A high voltage will be taken from the second voltage VGH.
  • the high voltage from the second voltage VGH charges the second end of the second capacitor CS2 with a high voltage.
  • the low voltage from the input terminal STV is input to the second node Q through the first transistor MT1, thereby charging the first ends of the second capacitor CS2 and the third capacitor CS3 with a low voltage.
  • the low voltage from the second node Q causes the fourth node Y to be a low voltage through the eighth transistor MT8. Therefore, the thirteenth transistor MT13 is turned on, thereby outputting a high voltage from the second clock signal CLK2 at the second output terminal OUTPUT_R.
  • the third output circuit 160 since the second node Q is a low voltage, the fifteenth transistor MT15 is turned on, and the high voltage from the second clock signal CLK2 is output from the third output terminal OUTPUT_N. Further, the high voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned off, so the voltage of the second node Q does not affect the output of the third output terminal OUTPUT_N.
  • the first clock signal CLK1 is a high voltage
  • the first transistor MT1 and the second transistor MT2 are turned off.
  • the voltage of the second node Q is held at a low voltage by the second capacitor CS2 and the third capacitor CS3, so that the fourth node Y is at a low voltage. Therefore, the thirteenth transistor MT13 leads
  • the second output terminal OUTPUT_R outputs a low voltage from the second clock signal CLK2. Further, the low voltage from the second node Q turns on the third transistor MT3.
  • the high voltage from the first clock signal CLK1 is input to the first node P through the third transistor MT3, thereby turning off the tenth transistor MT10 and the twelfth transistor MT12.
  • the high voltage from the second voltage VGH does not affect the signals of the first output terminal OUTPUT_L and the second output terminal OUTPUT_R at this stage. Since the second end of the second capacitor CS2 is maintained at a high voltage, the first output terminal OUTPUT_L outputs a high voltage.
  • the third output circuit 160 since the second node Q is a low voltage, the fifteenth transistor MT15 is turned on, and the low voltage from the second clock signal CLK2 is output from the third output terminal OUTPUT_N. Further, the low voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned on, and also causes the third output terminal OUTPUT_N to output a low voltage from the second node Q.
  • the first transistor MT1 and the second transistor MT2 are turned on.
  • the low voltage from the first voltage VGL is input to the first node P through the second transistor MT2 such that the first end of the first capacitor CS1 is charged with a low voltage and the tenth transistor MT10 and the twelfth transistor MT12 are turned on, Thereby, a high voltage from the second voltage VGH is outputted at both the first output terminal OUTPUT_L and the second output terminal OUTPUT_R.
  • the high voltage from the input terminal STV is input to the second node Q through the first transistor MT1, thereby charging the first ends of the second capacitor CS2 and the third capacitor CS3 with a high voltage.
  • the high voltage from the second node Q causes the fourth node Y to be a high voltage through the eighth transistor MT8. Therefore, the thirteenth transistor MT13 is turned off, and at this stage, the second output terminal OUTPUT_R is not affected by the second clock signal CLK2.
  • the third output circuit 160 since the second node Q is a high voltage, the fifteenth transistor MT15 is turned off. And the high voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned off, so the voltage of the third output terminal OUTPUT_N is not controlled by the shift register of this stage at this stage.
  • the first clock signal CLK1 is a high voltage
  • the first transistor MT1 and the second transistor MT2 are turned off.
  • the voltage of the first node P is maintained at a low voltage by the first capacitor CS1
  • the tenth transistor MT10 and the twelfth transistor MT12 are turned on, so that a high voltage from the second voltage VGH is outputted at both the first output terminal OUTPUT_L and the second output terminal OUTPUT_R.
  • the low voltage from the first node P turns on the fourth transistor MT4, and the low voltage from the second clock signal CLK2 turns on the fifth transistor MT5, so the high voltage from the second voltage VGH passes through the fourth transistor MT4 and the fifth Transistor MT5 causes second node Q to be at a high voltage.
  • the high voltage from the second node Q causes the fourth node Y to be a high voltage through the eighth transistor MT8. Therefore, the thirteenth transistor MT13 is turned off, and at this stage, the second output terminal OUTPUT_R is not affected by the second clock signal CLK2.
  • the fifteenth transistor MT15 is turned off.
  • the low voltage from the second clock signal CLK2 causes the fourteenth transistor MT14 to be turned on, thereby outputting a high voltage from the second node Q at the third output terminal OUTPUT_N.
  • the start signal for the next stage shift register can still be output at the third output terminal OUTPUT_N without the first output terminal OUTPUT_L outputting the scan signal. Therefore, turning off the first display area does not affect the display of the second display area (corresponding to the display area of the second output terminal OUTPUT_R).
  • the third selection signal SW3 may be set to a high voltage before the start of scanning, and the fourth selection signal SW4 is set to low voltage.
  • the above settings can also be made only in the second phase or in several phases including the second phase.
  • the circuit of the shift register unit 100 may be implemented by using an N-type transistor, or may be partially P-type transistors are used, partially implemented with N-type transistors.
  • FIG. 5 shows an exemplary block diagram of a gate driving device 500 in accordance with an embodiment of the present disclosure.
  • the gate driving device 500 includes a plurality of cascaded shift registers 100 as described above.
  • First level shift The scan enable signal is input to the input terminal STV of the bit register.
  • the input terminal STV of the other stage shift register is coupled to the third output terminal OUTPUT_N of the previous stage shift register, and the first clock signal terminal CLK1 is coupled to the second clock signal terminal CLK2 of the previous stage shift register, and the second clock signal is
  • the terminal CLK2 is coupled to the first clock signal terminal CLK1 of the previous stage shift register.
  • the input terminal STV is input with a scan enable signal.
  • the first clock signal terminal CLK1 is coupled to the first clock signal Clock1.
  • the second clock signal terminal CLK2 is coupled to the second clock signal Clock2.
  • the first output terminal OUTPUT_L outputs a first output signal OUTPUT_L_1.
  • the second output terminal OUTPUT_R outputs a second output signal OUTPUT_R_1.
  • the third output terminal OUTPUT_N outputs a third output signal OUTPUT_N_1.
  • the input terminal STV is input with the third output signal OUTPUT_N_1 from the first stage shift register.
  • the first clock signal terminal CLK1 is coupled to the second clock signal Clock2.
  • the second clock signal terminal CLK2 is coupled to the first clock signal Clock1.
  • the first output terminal OUTPUT_L outputs a first output signal OUTPUT_L_2.
  • the second output terminal OUTPUT_R outputs a second output signal OUTPUT_R_2.
  • the third output terminal OUTPUT_N outputs a third output signal OUTPUT_N_2.
  • the input terminal STV is input with the third output signal OUTPUT_N_2 from the second stage shift register.
  • the first clock signal terminal CLK1 is coupled to the first clock signal Clock1.
  • the second clock signal terminal CLK2 is coupled to the second clock signal Clock2.
  • the first output terminal OUTPUT_L outputs a first output signal OUTPUT_L_3.
  • the second output terminal OUTPUT_R outputs a second output signal OUTPUT_R_3.
  • the third output terminal OUTPUT_N outputs a third output signal OUTPUT_N_3.
  • the input terminal STV is input with the third output signal OUTPUT_N_3 from the third stage shift register.
  • the first clock signal terminal CLK1 is coupled to the second clock signal Clock2.
  • the second clock signal terminal CLK2 is coupled to the first clock signal Clock1.
  • the first output terminal OUTPUT_L outputs a first output signal OUTPUT_L_4.
  • the second output terminal OUTPUT_R outputs a second output signal OUTPUT_R_4.
  • the third output terminal OUTPUT_N outputs a third output signal OUTPUT_N_4.
  • FIG. 6 shows a schematic flow chart of a driving method of driving the shift register 100 shown in FIG. 2 according to an embodiment of the present disclosure.
  • step S602 Under the control of the first clock signal CLK1, the voltage of the first node P is set by the first voltage terminal and the voltage of the second node Q is set by the input terminal STV, thereby controlling the first The outputs of the output circuit 140 and the second output circuit 150.
  • the output of the third output circuit 160 is controlled by the voltage of the second node Q and the second clock signal CLK2.
  • step S604 the voltage of the second node Q is maintained.
  • the first clock signal CLK1 is input to the first node P under the control of the voltage of the second node Q.
  • the voltage of the third node X is controlled according to the first selection signal SW1 and the second selection signal SW2, thereby controlling the output of the first output circuit 140.
  • the voltage of the fourth node Y is controlled according to the third selection signal SW3 and the fourth selection signal SW4, thereby controlling the output of the second output circuit 150.
  • the output of the third output circuit 160 is controlled by the voltage of the second node Q and the second clock signal CLK2.
  • step S606 Under the control of the first clock signal CLK1, the voltage of the first node P is set by the first voltage terminal and the voltage of the second node Q is set by the input terminal STV, thereby controlling the first The outputs of the output circuit 140 and the second output circuit 150.
  • step S608 the voltages of the first node P and the second node Q are maintained.
  • the outputs of the first output circuit 140 and the second output circuit 150 are controlled by the voltage of the first node P.
  • the output of the third output circuit 160 is controlled by the voltage of the second node Q and the second clock signal CLK2.
  • the second clock signal CLK2 in a second time period, in a case where the second clock signal CLK2 is turned on to the path of the first output circuit 140 by controlling the voltage of the third node X, the second clock signal is output from the first output circuit 140. CLK2. In the case where the second clock signal CLK2 is turned off to the path of the first output circuit 140 by controlling the voltage of the third node X, the output of the first output circuit 140 is held by the hold circuit 120.
  • the second clock signal in a second period of time, in a case where the path of the second clock signal CLK2 to the second output circuit 150 is turned on by controlling the voltage of the fourth node Y, the second clock signal is output from the second output circuit 150. CLK2. In the case where the path of the second clock signal CLK2 to the second output circuit 150 is turned off by controlling the voltage of the fourth node Y, the output of the second output circuit 150 is held by the holding circuit 120.
  • FIG. 7 shows a schematic structural view of a display device 700 according to an embodiment of the present disclosure.
  • Display device 700 can include an array substrate 710.
  • Array substrate 710 can include gate drive device 500 as shown in FIG.
  • the shift register structure is improved to be suitable for folding display, and the delay of the output signal can be better controlled, and It is advantageous to drive an array substrate and a display device for folding display.
  • the display device provided by the embodiment of the present disclosure can be applied to any product having a display function, such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, or a navigator.

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Abstract

一种移位寄存器（100），其包括输入电路（110）、保持电路（120）、选择输出电路（130）、第一、第二以及第三输出电路（140、150、160）。输入电路（110）被配置为控制第一和第二节点（P、Q）的电压。保持电路（120）被配置为用于保持第一和第二节点（P、Q）的电压，以及第一和第二输出电路（140、150）的输出电压。选择输出电路（130）被配置为选择第一输出电路（140）和/或第二输出电路（150）来输出扫描信号，并根据第二节点（Q）的电压来控制第三节点（X）和/或第四节点（Y）的电压。第一输出电路（140）被配置为根据第一节点（P）和第三节点（X）的电压，从第一输出端（OUTPUT_L）输出第一输出信号。第二输出电路（150）被配置为根据第一节点（P）和第四节点（Y）的电压从第二输出端（OUTPUT_R）输出第二输出信号。第三输出电路（160）被配置为根据第二时钟信号（CLK2）和第二节点（Q）的电压从第三输出端（OUTPUT_N）输出第三输出信号。

Description

移位寄存器及其驱动方法、栅极驱动装置以及显示装置
相关申请的交叉引用
本申请要求于2017年03月02日递交的中国专利申请第201710119688.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及适用于折叠显示器的移位寄存器及其驱动方法、栅极驱动装置、阵列基板以及显示装置。
背景技术
液晶显示面板由垂直和水平阵列式像素矩阵组成。在显示过程中通过栅极驱动装置输出栅极扫描信号，逐行扫描各像素单元。阵列基板栅极驱动(Gate driver on Array，简称GOA)是一种将移位寄存器集成于阵列基板上的技术。每个GOA单元作为一个移位寄存器单元将扫描信号依次传递给下一个GOA单元，从而逐行开启像素单元中的开关晶体管，以便输入像素单元的数据信号。随着显示技术的发展，可折叠显示屏越来越流行。适用于折叠显示器的移位寄存器及其驱动方法也得到发展。
发明内容
本文中描述的实施例提供了一种适用于折叠显示的移位寄存器及其驱动方法、栅极驱动装置、阵列基板以及显示装置，其能够更好地控制输出信号的延迟，更有利于驱动可折叠显示屏。
根据本公开的第一方面，提供了一种移位寄存器。该移位寄存器包括输入电路、保持电路、选择输出电路、第一输出电路、第二输出电路以及第三输出电路。输入电路被配置为根据来自输入端的起始信号、来自第一时钟信号端的第一时钟信号和来自第一电压端的第一电压来控制第一节点 和第二节点的电压。保持电路被配置为用于保持第一和第二节点的电压，以及第一和第二输出电路的输出信号。选择输出电路被配置为选择第一输出电路和/或第二输出电路来输出扫描信号，并根据第二节点的电压来控制第三节点和/或第四节点的电压。第一输出电路被配置为根据第一节点和第三节点的电压，从第一输出端输出第一输出信号。第二输出电路被配置为根据第一节点和第四节点的电压从第二输出端输出第二输出信号。第三输出电路被配置为根据第二时钟信号和第二节点的电压从第三输出端输出第三输出信号。
在本公开的实施例中，输入电路包括第一晶体管、第二晶体管和第三晶体管。第一晶体管的控制极耦接第一时钟信号端，第一晶体管的第一极耦接输入端，第一晶体管的第二极耦接第二节点。第二晶体管的控制极耦接第一时钟信号端，第二晶体管的第一极耦接第一电压端，第二晶体管的第二极耦接第一节点。第三晶体管的控制极耦接第二节点，第三晶体管的第一极耦接第一时钟信号端，第三晶体管的第二极耦接第一节点。
在本公开的实施例中，保持电路包括第一电容器、第二电容器、第三电容器、第四晶体管和第五晶体管。第一电容器的第一端耦接第一节点，第一电容器的第二端耦接第二电压端。第二电容器的第一端耦接第二节点，第二电容器的第二端耦接第一输出端。第三电容器的第一端耦接第二节点，第三电容器的第二端耦接第二输出端。第四晶体管的控制极耦接第一节点，第四晶体管的第一极耦接第二电压端，第四晶体管的第二极耦接第五晶体管的第一极。第五晶体管的控制极耦接第二时钟信号端，第五晶体管的第二极耦接第二节点。
在本公开的实施例中，选择输出电路包括第六晶体管、第七晶体管、第八晶体管和第九晶体管。第六晶体管的控制极耦接第一选择信号，第六晶体管的第一极耦接第二节点，第六晶体管的第二极耦接第三节点。第七晶体管的控制极耦接第二选择信号，第七晶体管的第一极耦接第二电压端，第七晶体管的第二极耦接第三节点。第八晶体管的控制极耦接第三选择信号，第八晶体管的第一极耦接第二节点，第八晶体管的第二极耦接第四节 点。第九晶体管的控制极耦接第四选择信号，第九晶体管的第一极耦接第二电压端，第九晶体管的第二极耦接第四节点。
在本公开的实施例中，第一输出电路包括第十晶体管和第十一晶体管。第十晶体管的控制极耦接第一节点，第十晶体管的第一极耦接第二电压端，第十晶体管的第二极耦接第一输出端。第十一晶体管的控制极耦接第三节点，第十一晶体管的第一极耦接第二时钟信号端，第十一晶体管的第二极耦接第一输出端。
在本公开的实施例中，第二输出电路包括第十二晶体管和第十三晶体管。第十二晶体管的控制极耦接第一节点，第十二晶体管的第一极耦接第二电压端，第十二晶体管的第二极耦接第二输出端。第十三晶体管的控制极耦接第四节点，第十三晶体管的第一极耦接第二时钟信号端，第十三晶体管的第二极耦接第二输出端。
在本公开的实施例中，第三输出电路包括第十四晶体管和第十五晶体管。第十四晶体管的控制极耦接第二时钟信号端，第十四晶体管的第一极耦接第二节点，第十四晶体管的第二极耦接第三输出端。第十五晶体管的控制极耦接第二节点，第十五晶体管的第一极耦接第二时钟信号端，第十五晶体管的第二极耦接第三输出端。
在本公开的实施例中，第一时钟信号的占空比大于1/2，第二时钟信号与第一时钟信号相差半个周期。
根据本公开的第二方面，提供了一种驱动如上所述的移位寄存器的驱动方法。在该驱动方法中，在第一时间段，通过输入电路控制第一节点和第二节点的电压，以控制第一和第二输出电路的输出，以及根据第二节点的电压和第二时钟信号控制第三输出电路的输出。在第二时间段，通过保持电路保持第二节点的电压，在输入电路的控制下反相第一节点的电压，通过选择输出电路来控制第三节点和第四节点的电压，以分别控制第一输出电路和第二输出电路的输出。在第三时间段，通过输入电路控制第一节点和第二节点的电压，以控制第一和第二输出电路的输出。在第四时间段，保持第一和第二节点的电压，由第一节点的电压控制第一和第二输出电路 的输出。
在本公开的实施例中，在第二时间段，在通过控制第三节点的电压而打开第二时钟信号到第一输出电路的通路的情况下，从第一输出电路输出第二时钟信号。在通过控制第三节点的电压而关闭第二时钟信号到第一输出电路的通路的情况下，通过保持电路保持第一输出电路的输出。
在本公开的实施例中，在第二时间段，在通过控制第四节点的电压而打开第二时钟信号到第二输出电路的通路的情况下，从第二输出电路输出第二时钟信号。在通过控制第四节点的电压而关闭第二时钟信号到第二输出电路的通路的情况下，通过保持电路保持第二输出电路的输出。
根据本公开的第三方面，提供了一种栅极驱动装置。该栅极驱动装置包括多个级联的如上所述的移位寄存器。第一级移位寄存器的输入端被输入扫描启动信号。其它级移位寄存器的输入端耦接上一级移位寄存器的第三输出端，第一时钟信号端耦接上一级移位寄存器的第二时钟信号端，第二时钟信号端耦接上一级移位寄存器的第一时钟信号端。
根据本公开的第四方面，提供了一种阵列基板，其包括如上所述的栅极驱动装置。
根据本公开的第五方面，提供了一种显示装置，其包括如上所述的阵列基板。
根据本公开实施例的移位寄存器及栅极驱动装置，对移位寄存器结构做出改进以适用于折叠显示，并能够更好地控制输出信号的延迟，更有利于驱动用于折叠显示的阵列基板和显示装置。
附图说明
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：
图1是现有的适用于折叠显示的驱动电路的示例图；
图2是根据本公开的实施例的移位寄存器的示例性框图；
图3是根据本公开的实施例的移位寄存器的示例性电路图；
图4是如图3所示的移位寄存器的各信号的时序图；
图5是根据本公开的实施例的栅极驱动装置的示例性框图；
图6是根据本公开的实施例的驱动如图2所示的移位寄存器的驱动方法的示意性流程图；
图7示出根据本公开的实施例的显示装置的结构示意图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开保护的范围。
除非另外定义，否则在此使用的所有术语(包括技术和科学术语)具有与本公开主题所属的领域的技术人员所通常理解的相同含义。进一步将理解的是，诸如在通常使用的词典中定义的那些的术语应解释为具有与说明书上下文和相关技术中它们的含义一致的含义，并且将不以理想化或过于正式的形式来解释，除非在此另外明确定义。如在此所使用的，将两个或更多部分“连接”或“耦接”到一起的陈述应指该部分直接结合到一起或通过一个或多个中间部件结合。
在本公开的所有实施例中，由于晶体管的源极和漏极(发射极和集电极)是对称的，并且N型晶体管和P型晶体管的源极和漏极(发射极和集电极)之间的导通电流方向相反，因此在本公开的实施例中，统一将晶体管的受控中间端称为控制极，信号输入端称为第一极，信号输出端称为第二极。本公开的实施例中所采用的晶体管主要是开关晶体管。另外，诸如“第一”和“第二”的术语仅用于将一个部件(或部件的一部分)与另一个部件(或部件的另一部分)区分开。
现有的用于驱动可折叠显示屏的驱动电路的结构例如为如图1所示的 结构。该驱动电路采用多个级联的传统移位寄存器向左右两侧的显示区同步发送同一扫描信号，并通过设置在移位寄存器与左右侧显示区之间的控制电路来控制左右侧显示区的开启和关闭。如图1所示，通过控制信号S1和S2来控制左侧显示区的显示，通过控制信号S3和S4来控制右侧显示区的显示。然而这种方式会造成较难控制输出信号的延迟。
图2示出根据本公开的实施例的移位寄存器100的示例性框图。移位寄存器100包括输入电路110、保持电路120、选择输出电路130、第一输出电路140、第二输出电路150以及第三输出电路160。
输入电路110连接保持电路120、选择输出电路130、第一输出电路140、第二输出电路150以及第三输出电路160，并被配置为根据来自输入端STV的起始信号、来自第一时钟信号端CLK1的第一时钟信号CLK1和来自第一电压端的第一电压VGL来控制其与保持电路120之间的第一节点P和第二节点Q的电压。
保持电路120连接选择输出电路130、第一输出电路140、第二输出电路150以及第三输出电路160，并被配置为用于保持第一节点P和第二节点Q的电压，以及第一输出电路140和第二输出电路150的输出电压。
选择输出电路130连接第一输出电路140和第二输出电路150，并被配置为根据第一选择信号SW1、第二选择信号SW2、第二节点Q的电压和来自第二电压端的第二电压VGH来控制第三节点X的电压，以及根据第三选择信号SW3、第四选择信号SW4、第二节点Q的电压和第二电压VGH来控制第四节点Y的电压。
第一输出电路140被配置为根据第一节点P和第三节点X的电压从第一输出端OUTPUT_L选择性地输出来自第二时钟信号端CLK2的第二时钟信号CLK2或者第二电压VGH。
第二输出电路150被配置为根据第一节点P和第四节点Y的电压从第二输出端OUTPUT_R选择性地输出第二时钟信号CLK2或者第二电压VGH。
第三输出电路160被配置为根据第二时钟信号CLK2和第二节点Q的 电压从第三输出端OUTPUT_N选择性地输出第二时钟信号CLK2或者第二节点Q的电压。
由于选择输出电路130设置在输入电路110与第一输出电路140和第二输出电路150之间，其能够在第一输出电路140和第二输出电路150输出信号之前就做出是否允许输出扫描信号的选择，因此根据本实施例的移位寄存器100可以更好地控制输出信号的延迟。并且根据本实施例的移位寄存器100具有第三输出电路160，其不受到选择输出电路130的控制，无论是否向左右侧显示区输出扫描信号，第三输出电路160都能够向下一级移位寄存器提供起始信号。
图3示出根据本公开的实施例的移位寄存器100的示例性电路图。
输入电路110包括第一晶体管MT1、第二晶体管MT2和第三晶体管MT3。第一晶体管MT1的控制极耦接第一时钟信号端CLK1，第一晶体管MT1的第一极耦接输入端STV，第一晶体管MT1的第二极耦接第二节点Q。第二晶体管MT2的控制极耦接第一时钟信号端CLK1，第二晶体管MT2的第一极耦接第一电压端，第二晶体管MT2的第二极耦接第一节点P。第三晶体管MT3的控制极耦接第二节点Q，第三晶体管MT3的第一极耦接第一时钟信号端CLK1，第三晶体管MT3的第二极耦接第一节点P。
保持电路120包括第一电容器CS1、第二电容器CS2、第三电容器CS3、第四晶体管MT4和第五晶体管MT5。第一电容器CS1的第一端耦接第一节点P，第一电容器CS1的第二端耦接第二电压端。第二电容器CS2的第一端耦接第二节点Q，第二电容器CS2的第二端耦接第一输出端OUTPUT_L。第三电容器CS3的第一端耦接第二节点Q，第三电容器CS3的第二端耦接第二输出端OUTPUT_R。第四晶体管MT4的控制极耦接第一节点P，第四晶体管MT4的第一极耦接第二电压端，第四晶体管MT4的第二极耦接第五晶体管MT5的第一极。第五晶体管MT5的控制极耦接第二时钟信号端CLK2，第五晶体管MT5的第二极耦接第二节点Q。
选择输出电路130包括第六晶体管MT6、第七晶体管MT7、第八晶体管MT8和第九晶体管MT9。第六晶体管MT6的控制极耦接第一选择信号 SW1，第六晶体管MT6的第一极耦接第二节点Q，第六晶体管MT6的第二极耦接第三节点X。第七晶体管MT7的控制极耦接第二选择信号SW2，第七晶体管MT7的第一极耦接第二电压端，第七晶体管MT7的第二极耦接第三节点X。第八晶体管MT8的控制极耦接第三选择信号SW3，第八晶体管MT8的第一极耦接第二节点Q，第八晶体管MT8的第二极耦接第四节点Y。第九晶体管MT9的控制极耦接第四选择信号SW4，第九晶体管MT9的第一极耦接第二电压端，第九晶体管MT9的第二极耦接第四节点Y。
第一输出电路140包括第十晶体管MT10和第十一晶体管MT11。第十晶体管MT10的控制极耦接第一节点P，第十晶体管MT10的第一极耦接第二电压端，第十晶体管MT10的第二极耦接第一输出端OUTPUT_L。第十一晶体管MT11的控制极耦接第三节点X，第十一晶体管MT11的第一极耦接第二时钟信号端CLK2，第十一晶体管MT11的第二极耦接第一输出端OUTPUT_L。
第二输出电路150包括第十二晶体管MT12和第十三晶体管MT13。第十二晶体管MT12的控制极耦接第一节点P，第十二晶体管MT12的第一极耦接第二电压端，第十二晶体管MT12的第二极耦接第二输出端OUTPUT_R。第十三晶体管MT13的控制极耦接第四节点Y，第十三晶体管MT13的第一极耦接第二时钟信号端CLK2，第十三晶体管MT13的第二极耦接第二输出端OUTPUT_R。
第三输出电路160包括第十四晶体管MT14和第十五晶体管MT15。第十四晶体管MT14的控制极耦接第二时钟信号端CLK2，第十四晶体管MT14的第一极耦接第二节点Q，第十四晶体管MT14的第二极耦接第三输出端OUTPUT_N。第十五晶体管MT15的控制极耦接第二节点Q，第十五晶体管MT15的第一极耦接第二时钟信号端CLK2，第十五晶体管MT15的第二极耦接第三输出端OUTPUT_N。
图4示出如图3所示的移位寄存器的各信号的时序图。下面参考图3以P型晶体管为例来描述根据本公开实施例的移位寄存器单元100的工作 过程。在下面的实施例中，第一电压VGL＝“0”，表示低电压；第二电压VGH＝“1”，表示高电压。
首先以全屏显示为例进行说明。可以在扫描开始之前设置第一选择信号SW1＝0，第二选择信号SW2＝1，第三选择信号SW3＝0，第四选择信号SW4＝1。由于第一选择信号SW1为低电压，所以第六晶体管MT6导通。由于第二选择信号SW2为高电压，所以第七晶体管MT7截止。由于第三选择信号SW3为低电压，所以第八晶体管MT8导通。由于第四选择信号SW4为高电压，所以第九晶体管MT9截止。
在第一阶段，STV＝0，CLK1＝0，CLK2＝1。
由于第一时钟信号CLK1为低电压，所以第一晶体管MT1和第二晶体管MT2导通。来自第一电压VGL的低电压通过第二晶体管MT2被输入到第一节点P，使得第十晶体管MT10和第十二晶体管MT12导通，从而在第一输出端OUTPUT_L和第二输出端OUTPUT_R都输出将来自第二电压VGH的高电压。来自输入端STV的低电压通过第一晶体管MT1被输入到第二节点Q，从而向第二电容器CS2和第三电容器CS3的第一端充入低电压。来自第二节点Q的低电压分别通过第六晶体管MT6和第八晶体管MT8使第三节点X和第四节点Y为低电压。因此，第十一晶体管MT11和第十三晶体管MT13导通，从而在第一输出端OUTPUT_L和第二输出端OUTPUT_R都输出将来自第二时钟信号CLK2的高电压。对于第三输出电路160，由于第二节点Q为低电压，所以第十五晶体管MT15导通，从第三输出端OUTPUT_N输出来自第二时钟信号CLK2的高电压。此外，来自第二时钟信号CLK2的高电压使得第十四晶体管MT14截止，所以第二节点Q的电压不影响第三输出端OUTPUT_N的输出。
在第二阶段，STV＝1，CLK1＝1，CLK2＝0。
由于第一时钟信号CLK1为高电压，所以第一晶体管MT1和第二晶体管MT2截止。第二节点Q的电压通过第二电容器CS2和第三电容器CS3被保持为低电压，使第三节点X和第四节点Y为低电压。因此，第十一晶体管MT11和第十三晶体管MT13导通，从而在第一输出端OUTPUT_L 和第二输出端OUTPUT_R都输出将来自第二时钟信号CLK2的低电压。此外，来自第二节点Q的低电压使第三晶体管MT3导通。来自第一时钟信号CLK1的高电压通过第三晶体管MT3输入到第一节点P，从而使第十晶体管MT10和第十二晶体管MT12截止。因此在本阶段来自第二电压VGH的高电压不影响第一输出端OUTPUT_L和第二输出端OUTPUT_R的信号。对于第三输出电路160，由于第二节点Q为低电压，所以第十五晶体管MT15导通，从第三输出端OUTPUT_N输出来自第二时钟信号CLK2的低电压。此外，来自第二时钟信号CLK2的低电压使得第十四晶体管MT14导通，也使得第三输出端OUTPUT_N输出来自第二节点Q的低电压。
在第三阶段，STV＝1，CLK1＝0，CLK2＝1。
由于第一时钟信号CLK1为低电压，所以第一晶体管MT1和第二晶体管MT2导通。来自第一电压VGL的低电压通过第二晶体管MT2被输入到第一节点P，使得第一电容器CS1的第一端被充入低电压以及使得第十晶体管MT10和第十二晶体管MT12导通，从而在第一输出端OUTPUT_L和第二输出端OUTPUT_R都输出将来自第二电压VGH的高电压。来自输入端STV的高电压通过第一晶体管MT1被输入到第二节点Q，从而向第二电容器CS2和第三电容器CS3的第一端充入高电压。来自第二节点Q的高电压分别通过第六晶体管MT6和第八晶体管MT8使第三节点X和第四节点Y为高电压。因此，第十一晶体管MT11和第十三晶体管MT13截止，在本阶段第一输出端OUTPUT_L和第二输出端OUTPUT_R都不受第二时钟信号CLK2的影响。对于第三输出电路160，由于第二节点Q为高电压，所以第十五晶体管MT15截止。并且来自第二时钟信号CLK2的高电压使得第十四晶体管MT14截止，所以第三输出端OUTPUT_N的电压在本阶段不受本级移位寄存器的控制。
在第四阶段，STV＝1，CLK1＝1，CLK2＝0。
由于第一时钟信号CLK1为高电压，所以第一晶体管MT1和第二晶体管MT2截止。第一节点P的电压通过第一电容器CS1被保持为低电压， 使第十晶体管MT10和第十二晶体管MT12导通，从而在第一输出端OUTPUT_L和第二输出端OUTPUT_R都输出将来自第二电压VGH的高电压。来自第一节点P的低电压使第四晶体管MT4导通，来自第二时钟信号CLK2的低电压使第五晶体管MT5导通，因此来自第二电压VGH的高电压通过第四晶体管MT4和第五晶体管MT5使第二节点Q为高电压。来自第二节点Q的高电压分别通过第六晶体管MT6和第八晶体管MT8使第三节点X和第四节点Y为高电压。因此，第十一晶体管MT11和第十三晶体管MT13截止，在本阶段第一输出端OUTPUT_L和第二输出端OUTPUT_R都不受第二时钟信号CLK2的影响。对于第三输出电路160，由于第二节点Q为高电压，所以第十五晶体管MT15截止。来自第二时钟信号CLK2的低电压使得第十四晶体管MT14导通，从而在第三输出端OUTPUT_N输出来自第二节点Q的高电压。
在本实施例中，如图4所示，第一时钟信号CLK1的占空比大于1/2，第二时钟信号CLK2与第一时钟信号CLK1相差半个周期。因为在从一个阶段过渡到下一个阶段的时候，第一时钟信号CLK1和第二时钟信号CLK2都处于高电压，所以可以避免移位寄存器100的输出电压不稳定。例如在第二阶段，在来自第一时钟信号CLK1的高电压通过第三晶体管MT3输入到第一节点P，从而使第十晶体管MT10和第十二晶体管MT12截止之前，第二时钟信号CLK2也为高电压，这样可以避免第一输出端OUTPUT_L和第二输出端OUTPUT_R的输出电压的不稳定。
而且用于第一输出端OUTPUT_L和第二输出端OUTPUT_R的选择输出电路被配置为控制第十一晶体管MT11和第十三晶体管MT13的控制端，使得第一输出端OUTPUT_L和第二输出端OUTPUT_R的输出信号的延迟能够得到较好的控制。
在替代实施例中，可以仅在第二阶段将第一至第四选择信号设置为SW1＝0，SW2＝1，SW3＝0，SW4＝1。还可以在包括第二阶段的若干个阶段将第一至第四选择信号设置为SW1＝0，SW2＝1，SW3＝0，SW4＝1。
下面再以关闭第一显示区(对应于第一输出端OUTPUT_L的显示区) 为例，对扫描过程进行说明。可以在扫描开始之前设置第一选择信号SW1＝1，第二选择信号SW2＝0，第三选择信号SW3＝0，第四选择信号SW4＝1。由于第一选择信号SW1为高电压，所以第六晶体管MT6截止。由于第二选择信号SW2为低电压，所以第七晶体管MT7导通，第三节点X的电压为来自第二电压VGH的高电压，从而使得第十一晶体管MT11截止。因此在本示例中，在各个阶段，第一输出端OUTPUT_L都不受第二时钟信号CLK2的影响。由于第三选择信号SW3为低电压，所以第八晶体管MT8导通。由于第四选择信号SW4为高电压，所以第九晶体管MT9截止。
在第一阶段，STV＝0，CLK1＝0，CLK2＝1。
由于第一时钟信号CLK1为低电压，所以第一晶体管MT1和第二晶体管MT2导通。来自第一电压VGL的低电压通过第二晶体管MT2被输入到第一节点P，使得第十晶体管MT10和第十二晶体管MT12导通，从而在第一输出端OUTPUT_L和第二输出端OUTPUT_R都输出将来自第二电压VGH的高电压。并且来自第二电压VGH的高电压对第二电容器CS2的第二端充入高电压。来自输入端STV的低电压通过第一晶体管MT1被输入到第二节点Q，从而向第二电容器CS2和第三电容器CS3的第一端充入低电压。来自第二节点Q的低电压通过第八晶体管MT8使第四节点Y为低电压。因此，第十三晶体管MT13导通，从而在第二输出端OUTPUT_R输出将来自第二时钟信号CLK2的高电压。对于第三输出电路160，由于第二节点Q为低电压，所以第十五晶体管MT15导通，从第三输出端OUTPUT_N输出来自第二时钟信号CLK2的高电压。此外，来自第二时钟信号CLK2的高电压使得第十四晶体管MT14截止，所以第二节点Q的电压不影响第三输出端OUTPUT_N的输出。
在第二阶段，STV＝1，CLK1＝1，CLK2＝0。
由于第一时钟信号CLK1为高电压，所以第一晶体管MT1和第二晶体管MT2截止。第二节点Q的电压通过第二电容器CS2和第三电容器CS3被保持为低电压，使第四节点Y为低电压。因此，第十三晶体管MT13导 通，从而第二输出端OUTPUT_R输出将来自第二时钟信号CLK2的低电压。此外，来自第二节点Q的低电压使第三晶体管MT3导通。来自第一时钟信号CLK1的高电压通过第三晶体管MT3输入到第一节点P，从而使第十晶体管MT10和第十二晶体管MT12截止。因此在本阶段来自第二电压VGH的高电压不影响第一输出端OUTPUT_L和第二输出端OUTPUT_R的信号。由于第二电容器CS2的第二端被保持为高电压，所以第一输出端OUTPUT_L输出高电压。对于第三输出电路160，由于第二节点Q为低电压，所以第十五晶体管MT15导通，从第三输出端OUTPUT_N输出来自第二时钟信号CLK2的低电压。此外，来自第二时钟信号CLK2的低电压使得第十四晶体管MT14导通，也使得第三输出端OUTPUT_N输出来自第二节点Q的低电压。
在第三阶段，STV＝1，CLK1＝0，CLK2＝1。
由于第一时钟信号CLK1为低电压，所以第一晶体管MT1和第二晶体管MT2导通。来自第一电压VGL的低电压通过第二晶体管MT2被输入到第一节点P，使得第一电容器CS1的第一端被充入低电压以及使得第十晶体管MT10和第十二晶体管MT12导通，从而在第一输出端OUTPUT_L和第二输出端OUTPUT_R都输出将来自第二电压VGH的高电压。来自输入端STV的高电压通过第一晶体管MT1被输入到第二节点Q，从而向第二电容器CS2和第三电容器CS3的第一端充入高电压。来自第二节点Q的高电压通过第八晶体管MT8使第四节点Y为高电压。因此，第十三晶体管MT13截止，在本阶段第二输出端OUTPUT_R不受第二时钟信号CLK2的影响。对于第三输出电路160，由于第二节点Q为高电压，所以第十五晶体管MT15截止。并且来自第二时钟信号CLK2的高电压使得第十四晶体管MT14截止，所以第三输出端OUTPUT_N的电压在本阶段不受本级移位寄存器的控制。
在第四阶段，STV＝1，CLK1＝1，CLK2＝0。
由于第一时钟信号CLK1为高电压，所以第一晶体管MT1和第二晶体管MT2截止。第一节点P的电压通过第一电容器CS1被保持为低电压， 使第十晶体管MT10和第十二晶体管MT12导通，从而在第一输出端OUTPUT_L和第二输出端OUTPUT_R都输出将来自第二电压VGH的高电压。来自第一节点P的低电压使第四晶体管MT4导通，来自第二时钟信号CLK2的低电压使第五晶体管MT5导通，因此来自第二电压VGH的高电压通过第四晶体管MT4和第五晶体管MT5使第二节点Q为高电压。来自第二节点Q的高电压通过第八晶体管MT8使第四节点Y为高电压。因此，第十三晶体管MT13截止，在本阶段第二输出端OUTPUT_R不受第二时钟信号CLK2的影响。对于第三输出电路160，由于第二节点Q为高电压，所以第十五晶体管MT15截止。来自第二时钟信号CLK2的低电压使得第十四晶体管MT14导通，从而在第三输出端OUTPUT_N输出来自第二节点Q的高电压。
在本示例中，能够在第一输出端OUTPUT_L不输出扫描信号的情况下，仍然在第三输出端OUTPUT_N输出用于下一级移位寄存器的起始信号。因此关闭第一显示区不会影响第二显示区(对应于第二输出端OUTPUT_R的显示区)的显示。
在替代实施例中，可以仅在第二阶段将第一至第四选择信号设置为SW1＝1，SW2＝0，SW3＝0，SW4＝1。还可以在包括第二阶段的若干个阶段将第一至第四选择信号设置为SW1＝1，SW2＝0，SW3＝0，SW4＝1。
本领域的技术人员应理解的是，与上述示例相似地，在关闭第二显示区的实施例中，可以在扫描开始之前将第三选择信号SW3设置为高电压，第四选择信号SW4设置为低电压。也可以仅在第二阶段或者在包括第二阶段的若干个阶段做出上述设置。
同样地，本领域的技术人员应理解的是，通过改变移位寄存器100中各信号的电压，根据本公开实施例的移位寄存器单元100的电路可以采用N型晶体管来实现，也可以部分地采用P型晶体管，部分地采用N型晶体管来实现。
图5示出根据本公开的实施例的栅极驱动装置500的示例性框图。该栅极驱动装置500包括多个级联的如上所述的移位寄存器100。第一级移 位寄存器的输入端STV被输入扫描启动信号。其它级移位寄存器的输入端STV耦接上一级移位寄存器的第三输出端OUTPUT_N，第一时钟信号端CLK1耦接上一级移位寄存器的第二时钟信号端CLK2，第二时钟信号端CLK2耦接上一级移位寄存器的第一时钟信号端CLK1。
如图5所示，在第一级移位寄存器中，输入端STV被输入扫描启动信号。第一时钟信号端CLK1耦接第一时钟信号Clock1。第二时钟信号端CLK2耦接第二时钟信号Clock2。第一输出端OUTPUT_L输出第一输出信号OUTPUT_L_1。第二输出端OUTPUT_R输出第二输出信号OUTPUT_R_1。第三输出端OUTPUT_N输出第三输出信号OUTPUT_N_1。
在第二级移位寄存器中，输入端STV被输入来自第一级移位寄存器的第三输出信号OUTPUT_N_1。第一时钟信号端CLK1耦接第二时钟信号Clock2。第二时钟信号端CLK2耦接第一时钟信号Clock1。第一输出端OUTPUT_L输出第一输出信号OUTPUT_L_2。第二输出端OUTPUT_R输出第二输出信号OUTPUT_R_2。第三输出端OUTPUT_N输出第三输出信号OUTPUT_N_2。
在第三级移位寄存器中，输入端STV被输入来自第二级移位寄存器的第三输出信号OUTPUT_N_2。第一时钟信号端CLK1耦接第一时钟信号Clock1。第二时钟信号端CLK2耦接第二时钟信号Clock2。第一输出端OUTPUT_L输出第一输出信号OUTPUT_L_3。第二输出端OUTPUT_R输出第二输出信号OUTPUT_R_3。第三输出端OUTPUT_N输出第三输出信号OUTPUT_N_3。
在第四级移位寄存器中，输入端STV被输入来自第三级移位寄存器的第三输出信号OUTPUT_N_3。第一时钟信号端CLK1耦接第二时钟信号Clock2。第二时钟信号端CLK2耦接第一时钟信号Clock1。第一输出端OUTPUT_L输出第一输出信号OUTPUT_L_4。第二输出端OUTPUT_R输出第二输出信号OUTPUT_R_4。第三输出端OUTPUT_N输出第三输出信号OUTPUT_N_4。
随后的移位寄存器的连接方式以此类推，不再赘述。
图6示出根据本公开的实施例的驱动如图2所示的移位寄存器100的驱动方法的示意性流程图。
在第一时间段(即步骤S602)，在第一时钟信号CLK1的控制下，通过第一电压端设置第一节点P的电压并且通过输入端STV设置第二节点Q的电压，从而控制第一输出电路140和第二输出电路150的输出。由第二节点Q的电压和第二时钟信号CLK2控制第三输出电路160的输出。
在第二时间段(即步骤S604)，保持第二节点Q的电压。在第二节点Q的电压的控制下将第一时钟信号CLK1输入第一节点P。根据第一选择信号SW1和第二选择信号SW2来控制第三节点X的电压，从而控制第一输出电路140的输出。根据第三选择信号SW3和第四选择信号SW4来控制第四节点Y的电压，从而控制第二输出电路150的输出。由第二节点Q的电压和第二时钟信号CLK2控制第三输出电路160的输出。
在第三时间段(即步骤S606)，在第一时钟信号CLK1的控制下，通过第一电压端设置第一节点P的电压并且通过输入端STV设置第二节点Q的电压，从而控制第一输出电路140和第二输出电路150的输出。
在第四时间段(即步骤S608)，保持第一节点P和第二节点Q的电压。由第一节点P的电压控制第一输出电路140和第二输出电路150的输出。由第二节点Q的电压和第二时钟信号CLK2控制第三输出电路160的输出。
在一个示例中，在第二时间段，在通过控制第三节点X的电压而打开第二时钟信号CLK2到第一输出电路140的通路的情况下，从第一输出电路140输出第二时钟信号CLK2。在通过控制第三节点X的电压而关闭第二时钟信号CLK2到第一输出电路140的通路的情况下，通过保持电路120保持第一输出电路140的输出。
在一个示例中，在第二时间段，在通过控制第四节点Y的电压而打开第二时钟信号CLK2到第二输出电路150的通路的情况下，从第二输出电路150输出第二时钟信号CLK2。在通过控制第四节点Y的电压而关闭第二时钟信号CLK2到第二输出电路150的通路的情况下，通过保持电路120保持第二输出电路150的输出。
图7示出根据本公开的实施例的显示装置700的结构示意图。显示装置700可包括阵列基板710。阵列基板710可包括如图5所示的栅极驱动装置500。
如前所述，根据本公开实施例的移位寄存器及其驱动方法、栅极驱动装置，对移位寄存器结构做出改进以适用于折叠显示，并能够更好地控制输出信号的延迟，更有利于驱动用于折叠显示的阵列基板和显示装置。
本公开实施例提供的显示装置可以应用于任何具有显示功能的产品，例如，电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框或导航仪等。
除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中明确禁止这样的解释。在本文中使用术语“示例”之处，特别是当其位于一组术语之后时，所述“示例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其它方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
以上对本公开的若干实施例进行了详细描述，但显然，本领域技术人员可以在不脱离本公开的精神和范围的情况下对本公开的实施例进行各种修改和变型。本公开的保护范围由所附的权利要求限定。

Claims (14)

  1. 一种移位寄存器，包括输入电路、保持电路、选择输出电路、第一输出电路、第二输出电路以及第三输出电路，
    其中，所述输入电路被配置为根据来自输入端的起始信号、来自第一时钟信号端的第一时钟信号和来自第一电压端的第一电压来控制第一节点和第二节点的电压；
    所述保持电路被配置为用于保持所述第一和第二节点的电压，以及所述第一和第二输出电路的输出信号；
    所述选择输出电路被配置为选择所述第一输出电路和/或所述第二输出电路来输出扫描信号，并根据所述第二节点的电压来控制第三节点和/或第四节点的电压；
    所述第一输出电路被配置为根据所述第一节点和第三节点的电压，从第一输出端输出第一输出信号；
    所述第二输出电路被配置为根据所述第一节点和第四节点的电压从第二输出端输出第二输出信号；
    所述第三输出电路被配置为根据所述第二时钟信号和所述第二节点的电压从第三输出端输出第三输出信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述输入电路包括第一晶体管、第二晶体管和第三晶体管，
    其中，所述第一晶体管的控制极耦接所述第一时钟信号端，所述第一晶体管的第一极耦接输入端，所述第一晶体管的第二极耦接所述第二节点；
    所述第二晶体管的控制极耦接所述第一时钟信号端，所述第二晶体管的第一极耦接第一电压端，所述第二晶体管的第二极耦接所述第一节点；
    所述第三晶体管的控制极耦接所述第二节点，所述第三晶体管的第一极耦接所述第一时钟信号端，所述第三晶体管的第二极耦接所述第一节点。
  3. 根据权利要求1所述的移位寄存器，其中，所述保持电路包括第一电容器、第二电容器、第三电容器、第四晶体管和第五晶体管，
    其中，所述第一电容器的第一端耦接所述第一节点，所述第一电容器 的第二端耦接所述第二电压端；
    所述第二电容器的第一端耦接所述第二节点，所述第二电容器的第二端耦接所述第一输出端；
    所述第三电容器的第一端耦接所述第二节点，所述第三电容器的第二端耦接所述第二输出端；
    所述第四晶体管的控制极耦接所述第一节点，所述第四晶体管的第一极耦接所述第二电压端，所述第四晶体管的第二极耦接所述第五晶体管的第一极；
    所述第五晶体管的控制极耦接所述第二时钟信号端，所述第五晶体管的第二极耦接所述第二节点。
  4. 根据权利要求1所述的移位寄存器，其中，所述选择输出电路包括第六晶体管、第七晶体管、第八晶体管和第九晶体管，
    其中，所述第六晶体管的控制极耦接所述第一选择信号，所述第六晶体管的第一极耦接所述第二节点，所述第六晶体管的第二极耦接所述第三节点；
    所述第七晶体管的控制极耦接所述第二选择信号，所述第七晶体管的第一极耦接所述第二电压端，所述第七晶体管的第二极耦接所述第三节点；
    所述第八晶体管的控制极耦接所述第三选择信号，所述第八晶体管的第一极耦接所述第二节点，所述第八晶体管的第二极耦接所述第四节点；
    所述第九晶体管的控制极耦接所述第四选择信号，所述第九晶体管的第一极耦接所述第二电压端，所述第九晶体管的第二极耦接所述第四节点。
  5. 根据权利要求1所述的移位寄存器，其中，所述第一输出电路包括第十晶体管和第十一晶体管，
    其中，所述第十晶体管的控制极耦接所述第一节点，所述第十晶体管的第一极耦接所述第二电压端，所述第十晶体管的第二极耦接所述第一输出端；
    所述第十一晶体管的控制极耦接所述第三节点，所述第十一晶体管的第一极耦接所述第二时钟信号端，所述第十一晶体管的第二极耦接所述第 一输出端。
  6. 根据权利要求1所述的移位寄存器，其中，所述第二输出电路包括第十二晶体管和第十三晶体管，
    其中，所述第十二晶体管的控制极耦接所述第一节点，所述第十二晶体管的第一极耦接所述第二电压端，所述第十二晶体管的第二极耦接所述第二输出端；
    所述第十三晶体管的控制极耦接所述第四节点，所述第十三晶体管的第一极耦接所述第二时钟信号端，所述第十三晶体管的第二极耦接所述第二输出端。
  7. 根据权利要求1所述的移位寄存器，其中，所述第三输出电路包括第十四晶体管和第十五晶体管，
    其中，所述第十四晶体管的控制极耦接所述第二时钟信号端，所述第十四晶体管的第一极耦接所述第二节点，所述第十四晶体管的第二极耦接所述第三输出端；
    所述第十五晶体管的控制极耦接所述第二节点，所述第十五晶体管的第一极耦接所述第二时钟信号端，所述第十五晶体管的第二极耦接所述第三输出端。
  8. 根据权利要求1所述的移位寄存器，其中，所述第一时钟信号的占空比大于1/2，所述第二时钟信号与所述第一时钟信号相差半个周期。
  9. 一种驱动如权利要求1所述的移位寄存器的驱动方法，包括：
    在第一时间段，通过输入电路控制第一节点和第二节点的电压，以控制第一和第二输出电路的输出，以及根据所述第二节点的电压和第二时钟信号控制第三输出电路的输出；
    在第二时间段，通过保持电路保持所述第二节点的电压，在所述输入电路的控制下反相所述第一节点的电压，通过选择输出电路来控制第三节点和第四节点的电压，以分别控制第一输出电路和第二输出电路的输出；
    在第三时间段，通过输入电路控制第一节点和第二节点的电压，以控制第一和第二输出电路的输出；
    在第四时间段，保持所述第一和第二节点的电压，由所述第一节点的电压控制第一和第二输出电路的输出。
  10. 根据权利要求9所述的驱动方法，其中，在第二时间段，在通过控制所述第三节点的电压而打开所述第二时钟信号到所述第一输出电路的通路的情况下，从所述第一输出电路输出所述第二时钟信号；在通过控制所述第三节点的电压而关闭所述第二时钟信号到所述第一输出电路的通路的情况下，通过所述保持电路保持所述第一输出电路的输出。
  11. 根据权利要求9所述的驱动方法，其中，在第二时间段，在通过控制所述第四节点的电压而打开所述第二时钟信号到所述第二输出电路的通路的情况下，从所述第二输出电路输出所述第二时钟信号；在通过控制所述第四节点的电压而关闭所述第二时钟信号到所述第二输出电路的通路的情况下，通过所述保持电路保持所述第二输出电路的输出。
  12. 一种栅极驱动装置，包括多个级联的如1-8中任一项所述的移位寄存器，
    其中，第一级移位寄存器的输入端被输入扫描启动信号；
    其它级移位寄存器的输入端耦接上一级移位寄存器的第三输出端，第一时钟信号端耦接上一级移位寄存器的第二时钟信号端，第二时钟信号端耦接上一级移位寄存器的第一时钟信号端。
  13. 一种阵列基板，包括如权利要求12所述的栅极驱动装置。
  14. 一种显示装置，包括如权利要求13所述的阵列基板。
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