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WO2018010067A1 - Transistor à effet de champ et son procédé de fabrication - Google Patents

Transistor à effet de champ et son procédé de fabrication Download PDF

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Publication number
WO2018010067A1
WO2018010067A1 PCT/CN2016/089644 CN2016089644W WO2018010067A1 WO 2018010067 A1 WO2018010067 A1 WO 2018010067A1 CN 2016089644 W CN2016089644 W CN 2016089644W WO 2018010067 A1 WO2018010067 A1 WO 2018010067A1
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Prior art keywords
layer
thin film
film layer
conductive thin
gate
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PCT/CN2016/089644
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English (en)
Chinese (zh)
Inventor
梁晨
秦旭东
张臣雄
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2016/089644 priority Critical patent/WO2018010067A1/fr
Priority to CN201680064400.6A priority patent/CN108352326A/zh
Publication of WO2018010067A1 publication Critical patent/WO2018010067A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Definitions

  • the invention relates to the technical field of electronic components, in particular to a field effect transistor and a manufacturing method thereof.
  • FETs Field Effect Transistors
  • main structure includes a substrate, a channel layer disposed on the substrate, and disposed on both sides of the channel layer.
  • the FET is usually fabricated by photolithography.
  • a large gap (usually a few microns) is usually left between the gate and the source electrode (drain electrode).
  • the uncovered channel layer between the gate and the source electrode (drain electrode) cannot be gate-modulated, and a parasitic resistance is formed on the unmodulated channel layer, so when the gap is large, the channel layer is formed.
  • the parasitic resistance is also large, resulting in a decrease in the transconductance of the field effect transistor, a slower switching speed, and a reduced gain, which is extremely disadvantageous for the radio frequency application of the field effect transistor.
  • a gap is usually left between the gate and the source electrode (drain electrode) in the existing field effect transistor, and the present invention provides the problem that the parasitic resistance is formed.
  • a field effect transistor comprising: a substrate, a channel layer disposed on the substrate, and source electrodes disposed on the channel layer and respectively located on both sides of the channel layer And a drain electrode, an insulating layer disposed on the source electrode, the drain electrode, and the channel layer, and a gate disposed on the insulating layer, the gate being disposed at the source electrode and the drain Between the poles, the field effect transistor further includes a conductive thin film layer, the conductive thin film layer being located between the source electrode and the drain electrode, and the conductive thin film layer covering the gate electrode and at the source electrode and The insulating layer between the drain electrodes extends.
  • a conductive thin film layer is formed on the insulating layer of the top surface of the gate, the side of the gate, and the source electrode and the drain electrode, and the conductive film is connected to the gate and at the source. Electrode and Extending on the insulating layer between the drain electrodes corresponds to increasing the gate length, reducing the gap between the gate and the source electrode (drain electrode), making it easier for the gate to modulate the channel layer, thereby reducing The parasitic resistance increases the transconductance of the device and improves the switching speed and gain of the field effect transistor.
  • the channel layer is a two-dimensional crystalline material layer.
  • the channel layer is implemented using a two-dimensional crystalline material layer, which improves the performance of the field effect transistor.
  • the two-dimensional crystalline material layer is a transition metal sulfide layer, a graphene layer, or a black phosphorus layer.
  • the conductive thin film layer is a graphene conductive thin film layer or a transition metal sulfide Conductive film layer.
  • a gap exists between the conductive thin film layer and the source electrode, There is a gap between the conductive film layer and the drain electrode.
  • a method of fabricating a field effect transistor comprising:
  • a source electrode and a drain electrode on the channel layer, the source electrode and the drain electrode being respectively located on both sides of the channel layer;
  • the conductive thin film layer is located between the source electrode and the drain electrode, and the conductive thin film layer covers the gate electrode and is between the source electrode and the drain electrode Extending on the insulating layer.
  • a conductive thin film layer is formed on the insulating layer of the top surface of the gate, the side of the gate, and the source electrode and the drain electrode, and the conductive film is connected to the gate and at the source. Extending on the insulating layer between the electrode and the drain electrode, corresponding to increasing the gate length, reducing the gap between the gate and the source electrode (drain electrode), making it easier for the gate to modulate the channel layer, thereby The parasitic resistance is reduced, the transconductance of the device is increased, and the switching speed and gain of the field effect transistor are improved.
  • the channel layer is a two-dimensional crystal material Material layer.
  • the two-dimensional crystalline material layer is a transition metal sulfide layer, a graphene layer, or a black phosphorus layer.
  • the substrate includes, but is not limited to, silicon, silicon oxide, boron nitride, etc., which can withstand high temperatures.
  • the insulating layer includes, but is not limited to, a layer of a gate dielectric material that can withstand high temperatures, such as aluminum oxide or tantalum oxide.
  • the source electrode, the drain electrode, and the gate electrode are electrodes formed of any one of the following metal materials or an alloy of any two or more kinds of metal materials: Pt, Ni, Au, and Cu.
  • the forming the conductive thin film layer on the gate includes:
  • a source gas is introduced during annealing, and the source gas is used to react under the catalytic action of the gate electrode to form the conductive thin film layer.
  • the conductive thin film layer is a graphene conductive thin film layer or a transition metal sulfide conductive thin film layer.
  • the annealing temperature is 900-1100 ° C, and the annealing time is 5-60 minutes.
  • the source gas is argon gas, hydrogen gas, and methane, or argon gas, hydrogen gas, and Acetylene.
  • the annealing temperature is 800-1050 ° C
  • the annealing time is 10- 90 minutes.
  • the source gas is argon gas, hydrogen sulfide, and transition group Metal oxides, or argon, hydrogen sulfide, and transition metal chlorides.
  • forming a channel layer on the substrate comprises:
  • a two-dimensional crystalline material layer is formed on the substrate using a micromechanical lift-off method.
  • the forming the source electrode and the drain electrode on the channel layer comprises:
  • the source electrode Forming the source electrode on the channel layer by an electron beam evaporation process and a lift-off Lift-off process And a drain electrode; or, the source electrode and the drain electrode are formed on the channel layer by a sputtering process and a Lift-off process.
  • forming an insulating layer on the channel layer on which the source electrode and the drain electrode are formed comprises:
  • the insulating layer is deposited on the channel layer on which the source and drain electrodes are formed using an atomic layer deposition ALD process.
  • forming a gate on the insulating layer comprises:
  • the gate is formed on the channel layer by an electron beam evaporation process and a lift-off Lift-off process; or the gate is formed on the channel layer by a sputtering process and a Lift-off process.
  • FIG. 1 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
  • FIG. 2 is a flow chart of a method for fabricating a field effect transistor according to an embodiment of the present invention
  • 2a is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
  • 2b is a schematic structural view of a field effect transistor according to an embodiment of the present invention.
  • 2c is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
  • 2d is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention.
  • 2e is a transfer characteristic diagram of a graphene field effect transistor according to an embodiment of the present invention.
  • 2f is a transfer characteristic diagram of a graphene field effect transistor according to an embodiment of the present invention.
  • FIG. 3 is a flow chart of another method for fabricating a field effect transistor according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of another method for fabricating a field effect transistor according to an embodiment of the present invention.
  • the field effect transistor includes a substrate 101, a channel layer 102 disposed on the substrate 101, and is disposed in the trench.
  • the source electrode 103 and the drain electrode 104 on the track layer 102 and on both sides of the channel layer 102, the insulating layer 105 disposed on the source electrode 103, the drain electrode 104, and the channel layer 102, and the insulating layer 105 are disposed on the insulating layer 105.
  • the gate electrode 106 is disposed between the source electrode 103 and the drain electrode 104.
  • the field effect transistor further includes a conductive thin film layer 107 between the source electrode 103 and the drain electrode 104, and the conductive thin film layer 107 simultaneously covers the gate electrode 106 and the insulating layer 105 between the source electrode 103 and the drain electrode 104. Extend.
  • a conductive thin film layer 107 is formed on the top surface of the gate electrode 106, the side surface of the gate electrode 106, and the insulating layer 105 between the source electrode 103 and the drain electrode 104, and the conductive film is connected to the gate electrode 106. And extending over the insulating layer 105 between the source electrode 103 and the drain electrode 104, corresponding to increasing the length of the gate electrode 106, reducing the gap between the gate electrode 106 and the source electrode 103 (drain electrode 104), so that the gate 106 makes it easier to modulate the channel layer 102, thereby reducing parasitic resistance, increasing the transconductance of the device, and increasing the switching speed and gain of the field effect transistor.
  • the substrate 101 includes, but is not limited to, silicon, silicon oxide, boron nitride, or the like which can withstand high temperatures. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer 107 is grown, the use of the high temperature resistant substrate 101 ensures the growth of the conductive thin film layer 107.
  • a buffer layer may be disposed between the substrate 101 and the channel layer 102.
  • the buffer layer is used to reduce the structural difference between the substrate 101 and the channel layer 102, so that the channel layer 102 can be formed.
  • the buffer layer may be a silicon dioxide layer or the like.
  • the channel layer 102 may be a two-dimensional crystalline material layer.
  • the channel layer 102 is implemented by a two-dimensional crystalline material layer. Since the thickness of the two-dimensional crystalline material layer is small and the performance is stable, the two-dimensional crystalline material layer is used as the channel layer, thereby improving the performance of the field effect transistor.
  • the two-dimensional crystalline material layer may be a transition metal sulfide layer (such as a molybdenum disulfide layer), a graphene layer or a black phosphorus layer, and the two-dimensional crystalline material layer has good electrical conductivity.
  • a transition metal sulfide layer such as a molybdenum disulfide layer
  • a graphene layer or a black phosphorus layer and the two-dimensional crystalline material layer has good electrical conductivity.
  • the source electrode 103, the drain electrode 104, and the gate electrode 106 are electrodes formed of any one of the following metal materials or an alloy of two or more kinds of metal materials: platinum Pt, nickel Ni, gold Au, and copper Cu.
  • the insulating layer 105 includes, but is not limited to, a layer of a gate dielectric material that can withstand high temperatures such as aluminum oxide, yttrium oxide, or the like. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer 107 is grown, the selection of the high temperature resistant insulating layer 105 ensures the growth of the conductive thin film layer 107.
  • the conductive thin film layer 107 may be a graphene conductive thin film layer 107 or a transition metal sulfide conductive thin film layer 107.
  • a gap between the conductive thin film layer 107 and the source electrode 103, and a gap exists between the conductive thin film layer 107 and the drain electrode 104.
  • a gap is provided between the conductive thin film layer 107 and the source electrode 103 (drain electrode 104), so that leakage due to the quality of the insulating layer 105 is difficult to ensure.
  • the gap between the conductive thin film layer 107 and the source electrode 103 (drain electrode 104) may be 2 to 10 nm.
  • the field effect transistor provided by the embodiment of the present invention may include more or less film layers as long as the function of the field effect transistor can be realized.
  • FIG. 2 is a flow chart of a method for fabricating a field effect transistor according to an embodiment of the present invention. The method is used to fabricate the field effect transistor shown in FIG. 1. Referring to FIG. 2, the method includes:
  • Step 201 Providing a substrate.
  • the substrate includes, but is not limited to, silicon, silicon oxide, boron nitride, etc., which can withstand high temperatures. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer is grown, the high temperature resistant substrate can be used to ensure the growth of the conductive thin film layer.
  • Step 202 Form a channel layer on the substrate.
  • the channel layer may be a two-dimensional crystalline material layer.
  • Step 202 can include forming a two-dimensional crystalline material layer on the substrate using a micromechanical lift-off method.
  • the two-dimensional crystalline material layer may be a transition metal sulfide layer (such as a molybdenum disulfide layer), a graphene layer or a black phosphorus layer, and the two-dimensional crystalline material layer has good electrical conductivity.
  • a transition metal sulfide layer such as a molybdenum disulfide layer
  • a graphene layer or a black phosphorus layer and the two-dimensional crystalline material layer has good electrical conductivity.
  • the two-dimensional crystalline material layer can also be grown on the substrate by a gas phase process.
  • a channel layer 102 is formed on the substrate 101.
  • Step 203 forming a source electrode and a drain electrode on the channel layer, and the source electrode and the drain electrode are respectively located on both sides of the channel layer.
  • Step 203 may include: forming a source electrode and a drain electrode on the channel layer by an electron beam evaporation process and a lift-off process; or forming a source electrode on the channel layer by a sputtering process and a Lift-off process; Leakage electrode.
  • the source electrode and the drain electrode are electrodes formed of any one of the following metal materials or an alloy of two or more kinds of metal materials: Pt, Ni, Au, and Cu.
  • a source electrode 103 and a drain electrode 104 are formed on the channel layer 102.
  • Step 204 Form an insulating layer on the channel layer on which the active electrode and the drain electrode are formed.
  • Step 204 may include: using Atomic Layer Deposition (ALD) The process deposits an insulating layer on the channel layer on which the active and drain electrodes are formed.
  • ALD Atomic Layer Deposition
  • the insulating layer includes, but is not limited to, a layer of a gate dielectric material that can withstand high temperatures such as aluminum oxide or tantalum oxide. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer is grown, the selection of the high temperature resistant insulating layer ensures the growth of the conductive thin film layer.
  • the insulating layer 105 covers the source electrode 103, the drain electrode 104, and the channel layer 102.
  • Step 205 forming a gate on the insulating layer, and the gate is disposed between the source electrode and the drain electrode.
  • Step 205 may include forming a gate on the channel layer using an electron beam evaporation process and a lift-off Lift-off process; or forming a gate on the channel layer using a sputtering process and a Lift-off process.
  • the gate is an electrode formed of any one of the following metal materials or an alloy of any two or more kinds of metal materials: Pt, Ni, Au, and Cu.
  • a gate electrode 106 is formed on the insulating layer 105.
  • Step 206 Form a conductive thin film layer on the gate electrode, the conductive thin film layer is located between the source electrode and the drain electrode, and the conductive thin film layer covers the gate electrode and extends on the insulating layer between the source electrode and the drain electrode.
  • Step 206 may include annealing the field effect transistor structure formed with the gate electrode, introducing a source gas during annealing, forming a conductive thin film layer on the gate electrode, and the source gas is used for reacting under the catalytic action of the gate electrode to form a conductive layer. Film layer.
  • the annealing temperature is 800-1200 ° C
  • the annealing time is 5-90 minutes.
  • the gate serves as a catalyst for the growth of the conductive thin film layer to form a conductive thin film layer under annealing.
  • the length of the conductive film layer is related to the material, the annealing temperature and the time; for the conductive film layer of different materials, the relationship between the extension length and the annealing temperature and time can be obtained by prior testing. Thereby achieving precise control of the extension length of the conductive film layer.
  • the length of extension of the conductive film is controlled by controlling the annealing time given the material and temperature.
  • the conductive thin film layer may be a graphene conductive thin film layer or a transition metal sulfide conductive thin film layer.
  • the gap between the conductive thin film layer and the source electrode (drain electrode) may be 2 to 10 nm.
  • the conductive thin film layer 107 simultaneously covers the top surface of the gate electrode 106, the side surface of the gate electrode 106, and the insulating layer 105 between the source electrode 103 and the drain electrode 104.
  • the field effect transistor fabricated in the embodiment of the present invention can increase the gate length to enable more regions of the channel layer to be modulated by the gate, thereby increasing the transconductance of the device, thereby improving the switching speed and gain of the field effect transistor. This effect can be verified by simulation, and the simulation results are shown in Figures 2e and 2f.
  • a graphene field effect transistor (using a graphene layer as a channel layer) is used as a simulation object, and the graphene field effect is obtained when the length of the gate modulatable region (the length marked by a in FIG. 1) is 1 ⁇ m and 2 ⁇ m, respectively.
  • the transfer characteristics of the transistor are shown in Figures 2e and 2f. It can be seen from FIG. 2e that the curve corresponding to the broken line is located above the curve corresponding to the solid line, that is, the working current Id of the graphene field effect transistor having the gate-modulable region of 2 ⁇ m is larger under the action of the same gate voltage VG; It can be seen from Fig.
  • a conductive thin film layer is formed on the insulating layer of the top surface of the gate, the side of the gate, and the source electrode and the drain electrode, and the conductive film is connected to the gate electrode at the source electrode and the drain electrode.
  • the extension between the insulating layers is equivalent to increasing the gate length, reducing the gap between the gate and the source electrode (drain electrode), making it easier for the gate to modulate the channel layer, thereby reducing parasitics.
  • the resistor increases the transconductance of the device and increases the switching speed and gain of the field effect transistor.
  • the field effect transistor only adds one step of annealing process to metal catalyzed to form a conductive thin film layer, does not introduce too many complicated processes, and has a simple manufacturing process.
  • the channel layer of the field effect transistor prepared by the method is a transition metal sulfide layer, and the conductive film layer is a graphene conductive film layer.
  • the method includes:
  • Step 301 Providing a substrate.
  • the substrate may be a Si substrate.
  • the method further comprises: performing surface cleaning and heat treatment on the substrate.
  • Step 302 deposit a buffer layer on the substrate.
  • the buffer layer may be a silicon oxide layer or the like, and the silicon oxide layer may have a thickness of 300 nm.
  • Step 303 Forming a transition metal sulfide layer by a micromechanical stripping method and transferring the transition metal sulfide layer to the buffer layer.
  • Step 304 using an electron beam evaporation process on a buffer layer formed with a transition metal sulfide layer Plating Pt film.
  • Step 305 The Pt film is processed by a Lift-off process to form a source electrode and a drain electrode.
  • Step 306 depositing a layer of aluminum oxide as an insulating layer on the transition metal sulfide layer forming the active electrode and the drain electrode using an ALD process.
  • Step 307 plating a Pt film on the insulating layer by an electron beam evaporation process.
  • Step 308 The Pt film is processed by a Lift-off process to form a gate, and the gate is disposed between the source electrode and the drain electrode.
  • Step 309 annealing the gate-forming field effect transistor structure, and introducing a source gas during annealing, and the source gas is used for reacting under the catalytic action of the gate electrode to form a graphene conductive film layer.
  • the source gas may be argon, hydrogen and methane, or argon, hydrogen and acetylene.
  • the annealing temperature may be from 900 to 1100 ° C, and the annealing time may be from 5 to 60 minutes. Preferably, the annealing temperature is 1000 ° C and the annealing time is 30 minutes.
  • argon is a carrier gas
  • hydrogen is a reducing gas
  • methane or acetylene is a carbon source gas
  • methane or acetylene cleaves carbon atoms to form graphene and epitaxy.
  • the gate acts as a catalyst for graphene growth, and forms a graphene conductive thin film layer under annealing. Therefore, when the graphene grows, the gate surface and the vicinity region extend to the periphery, and the extension length and the annealing temperature are Time-dependent; during the growth of the graphene conductive film layer, the graphene conductive film extends slowly to the periphery, and the length of the graphene conductive film extension can be controlled by controlling the annealing time.
  • the channel layer of the field effect transistor prepared by the method is a black phosphorus layer
  • the conductive film layer is a transition metal oxide conductive film layer. Referring to Figure 4, the method includes:
  • Step 401 Providing a substrate.
  • the substrate may be a Si substrate.
  • the method further comprises: performing surface cleaning and heat treatment on the substrate.
  • Step 402 deposit a buffer layer on the substrate.
  • the buffer layer may be a silicon oxide layer or the like, and the silicon oxide layer may have a thickness of 100 nm.
  • Step 403 Forming a black phosphorus layer by a micromechanical stripping method and transferring the black phosphorus layer onto the buffer layer.
  • Step 404 Au film is plated on the buffer layer on which the black phosphorus layer is formed by a sputtering process.
  • Step 405 The Au film is processed by a Lift-off process to form a source electrode and a drain electrode.
  • Step 406 depositing a layer of germanium dioxide as an insulating layer on the black phosphor layer forming the active electrode and the drain electrode using an ALD process.
  • Step 407 Au film is plated on the insulating layer by a sputtering process.
  • Step 408 The Au film is processed by a Lift-off process to form a gate, and the gate is disposed between the source electrode and the drain electrode.
  • Step 409 annealing the gate-forming field effect transistor structure, and introducing a source gas during annealing, and the source gas is used for reacting under the catalytic action of the gate electrode to form a transition metal oxide conductive film layer.
  • the source gas may be argon, hydrogen sulfide, and a transition metal oxide (such as MoO 3 ), or argon, hydrogen sulfide, and a transition metal chloride (such as MoCl 5 ).
  • the annealing temperature may be 800-1050 ° C, and the annealing time may be 10-90 minutes. Preferably, the annealing temperature is 9000 ° C and the annealing time is 60 minutes.
  • argon is a carrier gas, and under high temperature metal catalysis, hydrogen sulfide reacts with a transition metal oxide or a transition metal chloride to form a transition metal sulfide attached to the surface of the field effect transistor structure forming the gate and epitaxially grown.
  • the gate acts as a catalyst for the growth of the transition metal oxide, forming a transition metal oxide conductive thin film layer under annealing, and thus the transition metal oxide grows from the gate surface and the vicinity to the periphery.
  • the extension length is related to the annealing temperature and time; during the growth process of the transition metal oxide conductive film layer, the transition metal oxide conductive film extends slowly to the periphery, and the transition metal oxide can be controlled by controlling the annealing time. The length of the film extension.

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Abstract

La présente invention concerne un transistor à effet de champ et son procédé de fabrication, relevant du domaine technique des composants électroniques. Le transistor à effet de champ comprend : un substrat (101), une couche de canal (102) disposée sur le substrat (101), une électrode de source (103) et une électrode de drain (104) disposées sur la couche de canal (102) et situées respectivement sur deux côtés de la couche de canal (102), une couche d'isolation (105) disposée sur l'électrode de source (103), l'électrode de drain (104) et la couche de canal (102), et une électrode de grille (106) disposée sur la couche d'isolation (105) et entre l'électrode de source (103) et l'électrode de drain (104). Le transistor à effet de champ comprend en outre une couche de film conducteur (107). La couche de film conducteur (107) est disposée entre l'électrode de source (103) et l'électrode de drain (104), et recouvre simultanément une surface supérieure de l'électrode de grille (106), une surface latérale de l'électrode de grille (106) et la couche d'isolation (105) entre l'électrode de source (103) et l'électrode de drain (104). Le film conducteur (107) est connecté à l'électrode de grille (106) et s'étend sur la couche d'isolation (105) entre l'électrode de source (103) et l'électrode de drain (104), ce qui permet d'augmenter la longueur de l'électrode de grille (106). Ainsi, l'électrode de grille (106) peut être ajustée plus facilement par rapport à la couche de canal (102), réduisant la résistance parasite, et augmentant la transconductance des composants ainsi que la vitesse de commutation et le gain du transistor à effet de champ.
PCT/CN2016/089644 2016-07-11 2016-07-11 Transistor à effet de champ et son procédé de fabrication Ceased WO2018010067A1 (fr)

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