WO2018010067A1 - Field-effect transistor and manufacturing method thereof - Google Patents

Abstract

A field-effect transistor and a manufacturing method thereof related to the technical field of electronic components. The field-effect transistor comprises: a substrate (101), a channel layer (102) provided on the substrate (101), a source electrode (103) and a drain electrode (104) provided on the channel layer (102) and respectively located at two sides of the channel layer (102), an insulation layer (105) provided on the source electrode (103), the drain electrode (104) and the channel layer (102), and a gate electrode (106) provided on the insulation layer (105) and between the source electrode (103) and the drain electrode (104). The field-effect transistor further comprises a conductive film layer (107). The conductive film layer (107) is provided between the source electrode (103) and the drain electrode (104), and simultaneously covers a top surface of the gate electrode (106), a side surface of the gate electrode (106) and the insulation layer (105) between the source electrode (103) and the drain electrode (104). The conductive film (107) is connected to the gate electrode (106), and extends on the insulation layer (105) between the source electrode (103) and the drain electrode (104), thereby increasing the length of the gate electrode (106). Thus, the gate electrode (106) can be more easily adjusted with respect to the channel layer (102), reducing parasitic resistance, and increasing transconductance of components as well as the switching speed and gain of the field-effect transistor.

Description

Field effect transistor and manufacturing method thereof Technical field

The invention relates to the technical field of electronic components, in particular to a field effect transistor and a manufacturing method thereof.

Background technique

Field Effect Transistors (FETs), abbreviated as field effect transistors, are a common electronic component whose main structure includes a substrate, a channel layer disposed on the substrate, and disposed on both sides of the channel layer. A source electrode and a drain electrode, an insulating layer disposed on the source electrode, the drain electrode, and the channel layer, and a gate electrode disposed on the insulating layer between the source electrode and the drain electrode.

The FET is usually fabricated by photolithography. During the fabrication process, due to the precision of the fabrication process, a large gap (usually a few microns) is usually left between the gate and the source electrode (drain electrode). The uncovered channel layer between the gate and the source electrode (drain electrode) cannot be gate-modulated, and a parasitic resistance is formed on the unmodulated channel layer, so when the gap is large, the channel layer is formed. The parasitic resistance is also large, resulting in a decrease in the transconductance of the field effect transistor, a slower switching speed, and a reduced gain, which is extremely disadvantageous for the radio frequency application of the field effect transistor.

Summary of the invention

In order to solve the problem that the channel layer under the gap is not modulated by the gate and the parasitic resistance is formed, a gap is usually left between the gate and the source electrode (drain electrode) in the existing field effect transistor, and the present invention provides the problem that the parasitic resistance is formed. A field effect transistor and a method of fabricating the same.

In a first aspect, a field effect transistor is provided, comprising: a substrate, a channel layer disposed on the substrate, and source electrodes disposed on the channel layer and respectively located on both sides of the channel layer And a drain electrode, an insulating layer disposed on the source electrode, the drain electrode, and the channel layer, and a gate disposed on the insulating layer, the gate being disposed at the source electrode and the drain Between the poles, the field effect transistor further includes a conductive thin film layer, the conductive thin film layer being located between the source electrode and the drain electrode, and the conductive thin film layer covering the gate electrode and at the source electrode and The insulating layer between the drain electrodes extends.

In this embodiment, a conductive thin film layer is formed on the insulating layer of the top surface of the gate, the side of the gate, and the source electrode and the drain electrode, and the conductive film is connected to the gate and at the source. Electrode and Extending on the insulating layer between the drain electrodes corresponds to increasing the gate length, reducing the gap between the gate and the source electrode (drain electrode), making it easier for the gate to modulate the channel layer, thereby reducing The parasitic resistance increases the transconductance of the device and improves the switching speed and gain of the field effect transistor.

In conjunction with the first aspect, in a first implementation of the first aspect, the channel layer is a two-dimensional crystalline material layer.

In this implementation, the channel layer is implemented using a two-dimensional crystalline material layer, which improves the performance of the field effect transistor.

In conjunction with the first implementation of the first aspect, in the second implementation of the first aspect, the two-dimensional crystalline material layer is a transition metal sulfide layer, a graphene layer, or a black phosphorus layer.

In combination with the first aspect or the first implementation manner of the first aspect or the second implementation manner of the first aspect, in the third implementation manner of the first aspect, the conductive thin film layer is a graphene conductive thin film layer or a transition metal sulfide Conductive film layer.

In combination with the first aspect or the first implementation to the third implementation of the first aspect, in a fourth implementation manner of the first aspect, a gap exists between the conductive thin film layer and the source electrode, There is a gap between the conductive film layer and the drain electrode.

In a second aspect, a method of fabricating a field effect transistor is provided, the method comprising:

Providing a substrate;

Forming a channel layer on the substrate;

Forming a source electrode and a drain electrode on the channel layer, the source electrode and the drain electrode being respectively located on both sides of the channel layer;

Forming an insulating layer on the channel layer on which the source electrode and the drain electrode are formed;

Forming a gate on the insulating layer, the gate being disposed between the source electrode and the drain electrode;

Forming a conductive thin film layer on the gate, the conductive thin film layer is located between the source electrode and the drain electrode, and the conductive thin film layer covers the gate electrode and is between the source electrode and the drain electrode Extending on the insulating layer.

In this embodiment, a conductive thin film layer is formed on the insulating layer of the top surface of the gate, the side of the gate, and the source electrode and the drain electrode, and the conductive film is connected to the gate and at the source. Extending on the insulating layer between the electrode and the drain electrode, corresponding to increasing the gate length, reducing the gap between the gate and the source electrode (drain electrode), making it easier for the gate to modulate the channel layer, thereby The parasitic resistance is reduced, the transconductance of the device is increased, and the switching speed and gain of the field effect transistor are improved.

In conjunction with the second aspect, in the first implementation of the second aspect, the channel layer is a two-dimensional crystal material Material layer.

In conjunction with the first implementation of the second aspect, in the second implementation of the second aspect, the two-dimensional crystalline material layer is a transition metal sulfide layer, a graphene layer, or a black phosphorus layer.

Wherein, the substrate includes, but is not limited to, silicon, silicon oxide, boron nitride, etc., which can withstand high temperatures.

The insulating layer includes, but is not limited to, a layer of a gate dielectric material that can withstand high temperatures, such as aluminum oxide or tantalum oxide.

The source electrode, the drain electrode, and the gate electrode are electrodes formed of any one of the following metal materials or an alloy of any two or more kinds of metal materials: Pt, Ni, Au, and Cu.

With the second aspect or the second implementation of the second aspect or the second implementation of the second aspect, in the third implementation of the second aspect, the forming the conductive thin film layer on the gate includes:

Annealing the field effect transistor structure forming the gate;

A source gas is introduced during annealing, and the source gas is used to react under the catalytic action of the gate electrode to form the conductive thin film layer.

In conjunction with the third implementation of the second aspect, in the fourth implementation of the second aspect, the conductive thin film layer is a graphene conductive thin film layer or a transition metal sulfide conductive thin film layer.

In conjunction with the fourth implementation of the second aspect, in the fifth implementation manner of the second aspect, when the conductive thin film layer is a graphene conductive thin film layer, the annealing temperature is 900-1100 ° C, and the annealing time is 5-60 minutes.

With reference to the fourth implementation manner of the second aspect, in the sixth implementation manner of the second aspect, when the conductive thin film layer is a graphene conductive thin film layer, the source gas is argon gas, hydrogen gas, and methane, or argon gas, hydrogen gas, and Acetylene.

With reference to the fourth implementation manner of the second aspect, in the seventh implementation manner of the second aspect, when the conductive thin film layer is a transition metal oxide conductive thin film layer, the annealing temperature is 800-1050 ° C, and the annealing time is 10- 90 minutes.

With reference to the fourth implementation manner of the second aspect, in the eighth implementation manner of the second aspect, when the conductive thin film layer is a transition metal sulfide conductive thin film layer, the source gas is argon gas, hydrogen sulfide, and transition group Metal oxides, or argon, hydrogen sulfide, and transition metal chlorides.

Wherein the forming a channel layer on the substrate comprises:

A two-dimensional crystalline material layer is formed on the substrate using a micromechanical lift-off method.

Wherein the forming the source electrode and the drain electrode on the channel layer comprises:

Forming the source electrode on the channel layer by an electron beam evaporation process and a lift-off Lift-off process And a drain electrode; or, the source electrode and the drain electrode are formed on the channel layer by a sputtering process and a Lift-off process.

Wherein the forming an insulating layer on the channel layer on which the source electrode and the drain electrode are formed comprises:

The insulating layer is deposited on the channel layer on which the source and drain electrodes are formed using an atomic layer deposition ALD process.

Wherein the forming a gate on the insulating layer comprises:

The gate is formed on the channel layer by an electron beam evaporation process and a lift-off Lift-off process; or the gate is formed on the channel layer by a sputtering process and a Lift-off process.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in light of the inventive work.

1 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention;

2 is a flow chart of a method for fabricating a field effect transistor according to an embodiment of the present invention;

2a is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention;

2b is a schematic structural view of a field effect transistor according to an embodiment of the present invention;

2c is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention;

2d is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention;

2e is a transfer characteristic diagram of a graphene field effect transistor according to an embodiment of the present invention;

2f is a transfer characteristic diagram of a graphene field effect transistor according to an embodiment of the present invention;

3 is a flow chart of another method for fabricating a field effect transistor according to an embodiment of the present invention;

4 is a flow chart of another method for fabricating a field effect transistor according to an embodiment of the present invention.

detailed description

The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

1 is a schematic structural diagram of a field effect transistor according to an embodiment of the present invention. Referring to FIG. 1, the field effect transistor includes a substrate 101, a channel layer 102 disposed on the substrate 101, and is disposed in the trench. The source electrode 103 and the drain electrode 104 on the track layer 102 and on both sides of the channel layer 102, the insulating layer 105 disposed on the source electrode 103, the drain electrode 104, and the channel layer 102, and the insulating layer 105 are disposed on the insulating layer 105. The gate electrode 106 is disposed between the source electrode 103 and the drain electrode 104. The field effect transistor further includes a conductive thin film layer 107 between the source electrode 103 and the drain electrode 104, and the conductive thin film layer 107 simultaneously covers the gate electrode 106 and the insulating layer 105 between the source electrode 103 and the drain electrode 104. Extend.

In the present embodiment, a conductive thin film layer 107 is formed on the top surface of the gate electrode 106, the side surface of the gate electrode 106, and the insulating layer 105 between the source electrode 103 and the drain electrode 104, and the conductive film is connected to the gate electrode 106. And extending over the insulating layer 105 between the source electrode 103 and the drain electrode 104, corresponding to increasing the length of the gate electrode 106, reducing the gap between the gate electrode 106 and the source electrode 103 (drain electrode 104), so that the gate 106 makes it easier to modulate the channel layer 102, thereby reducing parasitic resistance, increasing the transconductance of the device, and increasing the switching speed and gain of the field effect transistor.

In the embodiment of the present invention, the substrate 101 includes, but is not limited to, silicon, silicon oxide, boron nitride, or the like which can withstand high temperatures. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer 107 is grown, the use of the high temperature resistant substrate 101 ensures the growth of the conductive thin film layer 107.

Optionally, a buffer layer may be disposed between the substrate 101 and the channel layer 102. The buffer layer is used to reduce the structural difference between the substrate 101 and the channel layer 102, so that the channel layer 102 can be formed. On the substrate 101, the buffer layer may be a silicon dioxide layer or the like.

In an embodiment of the invention, the channel layer 102 may be a two-dimensional crystalline material layer. In this implementation, the channel layer 102 is implemented by a two-dimensional crystalline material layer. Since the thickness of the two-dimensional crystalline material layer is small and the performance is stable, the two-dimensional crystalline material layer is used as the channel layer, thereby improving the performance of the field effect transistor.

Specifically, the two-dimensional crystalline material layer may be a transition metal sulfide layer (such as a molybdenum disulfide layer), a graphene layer or a black phosphorus layer, and the two-dimensional crystalline material layer has good electrical conductivity.

In the embodiment of the present invention, the source electrode 103, the drain electrode 104, and the gate electrode 106 are electrodes formed of any one of the following metal materials or an alloy of two or more kinds of metal materials: platinum Pt, nickel Ni, gold Au, and copper Cu.

In the embodiment of the present invention, the insulating layer 105 includes, but is not limited to, a layer of a gate dielectric material that can withstand high temperatures such as aluminum oxide, yttrium oxide, or the like. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer 107 is grown, the selection of the high temperature resistant insulating layer 105 ensures the growth of the conductive thin film layer 107.

In the embodiment of the present invention, the conductive thin film layer 107 may be a graphene conductive thin film layer 107 or a transition metal sulfide conductive thin film layer 107.

Optionally, there is a gap between the conductive thin film layer 107 and the source electrode 103, and a gap exists between the conductive thin film layer 107 and the drain electrode 104. A gap is provided between the conductive thin film layer 107 and the source electrode 103 (drain electrode 104), so that leakage due to the quality of the insulating layer 105 is difficult to ensure.

Specifically, the gap between the conductive thin film layer 107 and the source electrode 103 (drain electrode 104) may be 2 to 10 nm.

The field effect transistor provided by the embodiment of the present invention may include more or less film layers as long as the function of the field effect transistor can be realized.

2 is a flow chart of a method for fabricating a field effect transistor according to an embodiment of the present invention. The method is used to fabricate the field effect transistor shown in FIG. 1. Referring to FIG. 2, the method includes:

Step 201: Providing a substrate.

The substrate includes, but is not limited to, silicon, silicon oxide, boron nitride, etc., which can withstand high temperatures. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer is grown, the high temperature resistant substrate can be used to ensure the growth of the conductive thin film layer.

Step 202: Form a channel layer on the substrate.

Wherein, the channel layer may be a two-dimensional crystalline material layer. Step 202 can include forming a two-dimensional crystalline material layer on the substrate using a micromechanical lift-off method.

Specifically, the two-dimensional crystalline material layer may be a transition metal sulfide layer (such as a molybdenum disulfide layer), a graphene layer or a black phosphorus layer, and the two-dimensional crystalline material layer has good electrical conductivity.

In other embodiments, the two-dimensional crystalline material layer can also be grown on the substrate by a gas phase process.

As shown in FIG. 2a, a channel layer 102 is formed on the substrate 101.

Step 203: forming a source electrode and a drain electrode on the channel layer, and the source electrode and the drain electrode are respectively located on both sides of the channel layer.

Step 203 may include: forming a source electrode and a drain electrode on the channel layer by an electron beam evaporation process and a lift-off process; or forming a source electrode on the channel layer by a sputtering process and a Lift-off process; Leakage electrode.

The source electrode and the drain electrode are electrodes formed of any one of the following metal materials or an alloy of two or more kinds of metal materials: Pt, Ni, Au, and Cu.

As shown in FIG. 2b, a source electrode 103 and a drain electrode 104 are formed on the channel layer 102.

Step 204: Form an insulating layer on the channel layer on which the active electrode and the drain electrode are formed.

Step 204 may include: using Atomic Layer Deposition (ALD) The process deposits an insulating layer on the channel layer on which the active and drain electrodes are formed.

The insulating layer includes, but is not limited to, a layer of a gate dielectric material that can withstand high temperatures such as aluminum oxide or tantalum oxide. Since the field effect transistor structure to be formed needs to be annealed when the conductive thin film layer is grown, the selection of the high temperature resistant insulating layer ensures the growth of the conductive thin film layer.

As shown in FIG. 2c, the insulating layer 105 covers the source electrode 103, the drain electrode 104, and the channel layer 102.

Step 205: forming a gate on the insulating layer, and the gate is disposed between the source electrode and the drain electrode.

Step 205 may include forming a gate on the channel layer using an electron beam evaporation process and a lift-off Lift-off process; or forming a gate on the channel layer using a sputtering process and a Lift-off process.

The gate is an electrode formed of any one of the following metal materials or an alloy of any two or more kinds of metal materials: Pt, Ni, Au, and Cu.

As shown in FIG. 2d, a gate electrode 106 is formed on the insulating layer 105.

Step 206: Form a conductive thin film layer on the gate electrode, the conductive thin film layer is located between the source electrode and the drain electrode, and the conductive thin film layer covers the gate electrode and extends on the insulating layer between the source electrode and the drain electrode.

Step 206 may include annealing the field effect transistor structure formed with the gate electrode, introducing a source gas during annealing, forming a conductive thin film layer on the gate electrode, and the source gas is used for reacting under the catalytic action of the gate electrode to form a conductive layer. Film layer. In the above process, the annealing temperature is 800-1200 ° C, and the annealing time is 5-90 minutes. In this process, the gate serves as a catalyst for the growth of the conductive thin film layer to form a conductive thin film layer under annealing. Since the surface of the gate and the vicinity of the gate extend to the periphery, and the length of the conductive film layer is related to the material, the annealing temperature and the time; for the conductive film layer of different materials, the relationship between the extension length and the annealing temperature and time can be obtained by prior testing. Thereby achieving precise control of the extension length of the conductive film layer. For example, the length of extension of the conductive film is controlled by controlling the annealing time given the material and temperature.

During the annealing process, surface and drain electrode defects and impurities are also reduced, and the contact resistance between the source and the drain is reduced.

The conductive thin film layer may be a graphene conductive thin film layer or a transition metal sulfide conductive thin film layer.

Optionally, there is a gap between the conductive film layer and the source electrode, and a gap exists between the conductive film layer and the drain electrode.

Specifically, the gap between the conductive thin film layer and the source electrode (drain electrode) may be 2 to 10 nm.

As shown in FIG. 1, the conductive thin film layer 107 simultaneously covers the top surface of the gate electrode 106, the side surface of the gate electrode 106, and the insulating layer 105 between the source electrode 103 and the drain electrode 104.

The field effect transistor fabricated in the embodiment of the present invention can increase the gate length to enable more regions of the channel layer to be modulated by the gate, thereby increasing the transconductance of the device, thereby improving the switching speed and gain of the field effect transistor. This effect can be verified by simulation, and the simulation results are shown in Figures 2e and 2f.

Specifically, a graphene field effect transistor (using a graphene layer as a channel layer) is used as a simulation object, and the graphene field effect is obtained when the length of the gate modulatable region (the length marked by a in FIG. 1) is 1 μm and 2 μm, respectively. The transfer characteristics of the transistor are shown in Figures 2e and 2f. It can be seen from FIG. 2e that the curve corresponding to the broken line is located above the curve corresponding to the solid line, that is, the working current Id of the graphene field effect transistor having the gate-modulable region of 2 μm is larger under the action of the same gate voltage VG; It can be seen from Fig. 2f that, when the gate voltage VG is the same, the absolute value of the curve corresponding to the broken line is larger than the absolute value of the curve corresponding to the solid line, that is, with the gate-modulable region of 2 μm under the action of the same gate voltage VG. The transconductance of graphene field effect transistors is larger. Therefore, when the gate length is large, the working current and the transconductance of the graphene field effect transistor are also large, and the performance is good.

In this embodiment, a conductive thin film layer is formed on the insulating layer of the top surface of the gate, the side of the gate, and the source electrode and the drain electrode, and the conductive film is connected to the gate electrode at the source electrode and the drain electrode. The extension between the insulating layers is equivalent to increasing the gate length, reducing the gap between the gate and the source electrode (drain electrode), making it easier for the gate to modulate the channel layer, thereby reducing parasitics. The resistor increases the transconductance of the device and increases the switching speed and gain of the field effect transistor. In addition, compared with the conventional field effect transistor fabrication process, the field effect transistor only adds one step of annealing process to metal catalyzed to form a conductive thin film layer, does not introduce too many complicated processes, and has a simple manufacturing process.

3 is a flow chart of another method for fabricating a field effect transistor according to an embodiment of the present invention. The channel layer of the field effect transistor prepared by the method is a transition metal sulfide layer, and the conductive film layer is a graphene conductive film layer. Referring to Figure 3, the method includes:

Step 301: Providing a substrate.

Wherein, the substrate may be a Si substrate.

Before the step 301, the method further comprises: performing surface cleaning and heat treatment on the substrate.

Step 302: deposit a buffer layer on the substrate.

The buffer layer may be a silicon oxide layer or the like, and the silicon oxide layer may have a thickness of 300 nm.

Step 303: Forming a transition metal sulfide layer by a micromechanical stripping method and transferring the transition metal sulfide layer to the buffer layer.

Step 304: using an electron beam evaporation process on a buffer layer formed with a transition metal sulfide layer Plating Pt film.

Step 305: The Pt film is processed by a Lift-off process to form a source electrode and a drain electrode.

Step 306: depositing a layer of aluminum oxide as an insulating layer on the transition metal sulfide layer forming the active electrode and the drain electrode using an ALD process.

Step 307: plating a Pt film on the insulating layer by an electron beam evaporation process.

Step 308: The Pt film is processed by a Lift-off process to form a gate, and the gate is disposed between the source electrode and the drain electrode.

Step 309: annealing the gate-forming field effect transistor structure, and introducing a source gas during annealing, and the source gas is used for reacting under the catalytic action of the gate electrode to form a graphene conductive film layer.

Wherein, the source gas may be argon, hydrogen and methane, or argon, hydrogen and acetylene. The annealing temperature may be from 900 to 1100 ° C, and the annealing time may be from 5 to 60 minutes. Preferably, the annealing temperature is 1000 ° C and the annealing time is 30 minutes. In the reaction, argon is a carrier gas, hydrogen is a reducing gas, methane or acetylene is a carbon source gas, and under high temperature metal catalysis, methane or acetylene cleaves carbon atoms to form graphene and epitaxy.

In this process, the gate acts as a catalyst for graphene growth, and forms a graphene conductive thin film layer under annealing. Therefore, when the graphene grows, the gate surface and the vicinity region extend to the periphery, and the extension length and the annealing temperature are Time-dependent; during the growth of the graphene conductive film layer, the graphene conductive film extends slowly to the periphery, and the length of the graphene conductive film extension can be controlled by controlling the annealing time.

4 is a flow chart of another method for fabricating a field effect transistor according to an embodiment of the present invention. The channel layer of the field effect transistor prepared by the method is a black phosphorus layer, and the conductive film layer is a transition metal oxide conductive film layer. Referring to Figure 4, the method includes:

Step 401: Providing a substrate.

Wherein, the substrate may be a Si substrate.

Before the step 401, the method further comprises: performing surface cleaning and heat treatment on the substrate.

Step 402: deposit a buffer layer on the substrate.

The buffer layer may be a silicon oxide layer or the like, and the silicon oxide layer may have a thickness of 100 nm.

Step 403: Forming a black phosphorus layer by a micromechanical stripping method and transferring the black phosphorus layer onto the buffer layer.

Step 404: Au film is plated on the buffer layer on which the black phosphorus layer is formed by a sputtering process.

Step 405: The Au film is processed by a Lift-off process to form a source electrode and a drain electrode.

Step 406: depositing a layer of germanium dioxide as an insulating layer on the black phosphor layer forming the active electrode and the drain electrode using an ALD process.

Step 407: Au film is plated on the insulating layer by a sputtering process.

Step 408: The Au film is processed by a Lift-off process to form a gate, and the gate is disposed between the source electrode and the drain electrode.

Step 409: annealing the gate-forming field effect transistor structure, and introducing a source gas during annealing, and the source gas is used for reacting under the catalytic action of the gate electrode to form a transition metal oxide conductive film layer.

The source gas may be argon, hydrogen sulfide, and a transition metal oxide (such as MoO ₃ ), or argon, hydrogen sulfide, and a transition metal chloride (such as MoCl ₅ ). The annealing temperature may be 800-1050 ° C, and the annealing time may be 10-90 minutes. Preferably, the annealing temperature is 9000 ° C and the annealing time is 60 minutes. In the reaction, argon is a carrier gas, and under high temperature metal catalysis, hydrogen sulfide reacts with a transition metal oxide or a transition metal chloride to form a transition metal sulfide attached to the surface of the field effect transistor structure forming the gate and epitaxially grown.

In this process, the gate acts as a catalyst for the growth of the transition metal oxide, forming a transition metal oxide conductive thin film layer under annealing, and thus the transition metal oxide grows from the gate surface and the vicinity to the periphery. And the extension length is related to the annealing temperature and time; during the growth process of the transition metal oxide conductive film layer, the transition metal oxide conductive film extends slowly to the periphery, and the transition metal oxide can be controlled by controlling the annealing time. The length of the film extension.

The above is only the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any change or replacement that can be easily conceived by those skilled in the art within the technical scope of the present disclosure is All should be covered by the scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims (13)

A field effect transistor comprising: Substrate a channel layer disposed on the substrate; Source and drain electrodes disposed on the channel layer and respectively located on both sides of the channel layer; An insulating layer disposed on the source electrode, the drain electrode, and the channel layer; a gate disposed on the insulating layer, the gate being disposed between the source electrode and the drain electrode; The field effect transistor further includes a conductive thin film layer, the conductive thin film layer being located between the source electrode and the drain electrode, and the conductive thin film layer covering the gate electrode and at the source electrode and The insulating layer between the drain electrodes extends. The field effect transistor of claim 1 wherein said channel layer is a two dimensional layer of crystalline material. The field effect transistor according to claim 2, wherein the two-dimensional crystalline material layer is a transition metal sulfide layer, a graphene layer or a black phosphorus layer. The field effect transistor according to any one of claims 1 to 3, wherein the conductive thin film layer is a graphene conductive thin film layer or a transition metal sulfide conductive thin film layer. The field effect transistor according to any one of claims 1 to 4, wherein a gap exists between the conductive thin film layer and the source electrode, and a gap exists between the conductive thin film layer and the drain electrode. A method of fabricating a field effect transistor, characterized in that the method comprises: Providing a substrate; Forming a channel layer on the substrate; Forming a source electrode and a drain electrode on the channel layer, the source electrode and the drain electrode being respectively located on both sides of the channel layer; Forming an insulating layer on the channel layer on which the source electrode and the drain electrode are formed; Forming a gate on the insulating layer, the gate being disposed between the source electrode and the drain electrode; Forming a conductive thin film layer on the gate, the conductive thin film layer is located between the source electrode and the drain electrode, and the conductive thin film layer covers the gate electrode and is between the source electrode and the drain electrode Extending on the insulating layer. The method of claim 6 wherein said channel layer is a two-dimensional layer of crystalline material. The method according to claim 7, wherein the two-dimensional crystalline material layer is a transition metal sulfide layer, a graphene layer or a black phosphorus layer. The method according to any one of claims 6 to 8, wherein the forming a conductive film layer on the gate comprises: Annealing the field effect transistor structure forming the gate; A source gas is introduced during annealing, and the source gas is used to react under the catalytic action of the gate electrode to form the conductive thin film layer. The method according to claim 9, wherein the conductive film layer is a graphene conductive film layer or a transition metal sulfide conductive film layer. The method according to claim 10, wherein when the conductive thin film layer is a graphene conductive thin film layer, the annealing temperature is 900-1100 ° C, and the annealing time is 5 to 60 minutes. The method according to claim 10, wherein when the conductive thin film layer is a graphene conductive thin film layer, the source gas is argon gas, hydrogen gas and methane, or argon gas, hydrogen gas and acetylene. The method according to claim 10, wherein when the conductive thin film layer is a transition metal oxide conductive thin film layer, the annealing temperature is 800-1050 ° C, and the annealing time is 10-90 minutes.

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