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WO2018009182A1 - Mémoire vive résistive à fonctionnalité d'électroformage - Google Patents

Mémoire vive résistive à fonctionnalité d'électroformage Download PDF

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Publication number
WO2018009182A1
WO2018009182A1 PCT/US2016/041096 US2016041096W WO2018009182A1 WO 2018009182 A1 WO2018009182 A1 WO 2018009182A1 US 2016041096 W US2016041096 W US 2016041096W WO 2018009182 A1 WO2018009182 A1 WO 2018009182A1
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WO
WIPO (PCT)
Prior art keywords
electrode
potential
memory material
memory
resistive memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2016/041096
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English (en)
Inventor
Elijah Karpov
Jeffery D. Bielefeld
Roza Kotlyar
Prashant Majhi
Ravi Pillarisetty
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Intel Corp
Original Assignee
Intel Corp
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Filing date
Publication date
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Priority to PCT/US2016/041096 priority Critical patent/WO2018009182A1/fr
Publication of WO2018009182A1 publication Critical patent/WO2018009182A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/253—Multistable switching devices, e.g. memristors having three or more electrodes, e.g. transistor-like devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/52—Structure characterized by the electrode material, shape, etc.
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Definitions

  • the present description relates to resistive random access memory and, in particular, to such a device with an electrically active middle electrode.
  • NVRAM Nonvolatile Random Access Memory
  • Solid state NVRAM is finding greater use in a wide variety of electronics and microelectronics devices and is moving into server and data provider systems. Solid state types of NVRAM are growing in use by offering smaller size and lower power consumption as compared to other types of memory.
  • flash memory the dominant form of NVRAM is flash memory.
  • flash requires a high voltage for programming by block to erase the memory and is limited in speed.
  • CMOS Complementary Metal Oxide Semiconductor
  • Resistive memory is one such alternative.
  • ReRAM resistive random access memory
  • a thin film memory stack is built as a two-terminal device based on a dielectric memory material sandwiched between two conductive electrodes or terminals. This may be referred to as a MIM structure (Metal Insulator Metal).
  • the memory material switches between two different non-volatile states: a high-resistance state (HRS) and a low-resistance state (LRS).
  • HRS high-resistance state
  • LRS Low-resistance state
  • Defects are engineered into the memory material to improve the switching speed and the conductivity of the material.
  • An oxygen exchange layer of Ti, H Zr, or Ta has been used for the defects.
  • More recently directional filaments are electrically formed in the memory material and are controlled to make the memory material change state.
  • Figure 1 i s a cross-sectional side view diagram of an example of a vertical ly stacked thin film MIMIM resistive memory cell built over a substrate according to an embodiment.
  • Figure 2 is a state diagram of the operation of a thin film MIMIM resistive memory cell according to an embodi ment.
  • Figure 3 is cross-sectional side view diagram of an example configuration of two RRAM cell s in series according to an embodiment.
  • Figure 4 is a cross-sectional side view diagram of a switching element formed from two
  • Figure 5 is a cross-sectional side view diagram of an RRAM memory cell configured in metal layers abov e a substrate according to an embodiment.
  • Figure 6 is a cross-sectional side view diagram of an alternative RRAM memory cell configured in metal layers above a substrate according to an embodiment.
  • Figure 7 is an isometric view diagram of a vertical crosspoint array of RRAM memory cell s according to an embodiment.
  • Figure 8 i s an i sometric view diagram of a horizontal crosspoint array of RRAM memory cells according to an embodiment.
  • Figure 9 is a schematic diagram of a memory array and supporting circuits according to an embodiment.
  • Figure 10 i s a block diagram of a computing device suitable for use with embodiments.
  • a M IM IM (Metal Insulator Metal Insulator Metal ) RRAM structure has a middle electrode which can be electrically biased.
  • the MIMIM structure is a stack of two M IM structures in seri es with a shared middle active metal layer to form a third or middle electrode terminal .
  • the middle electrode By bi asing the middle electrode the top and bottom MIM structures may be biased symmetrically to ensure that the filaments in both insulator layers are formed ith tips at the middle electrode.
  • Figure I i s a cross-sectional side view diagram of an example of a vertically stacked thin film MIMIM resistive memory cell 120 built over a substrate 1 16.
  • the substrate may be silicon and suitable for MOS logic circuitry or it may be another type of substrate, suitable for a different application.
  • germanium, SiGe, GaAs, and amorphous materials including glasses, organic polymers, and plastics, etc. may be used as substrates.
  • the upper MIM stack 102 is stacked over the lower MIM stack 104 with a common middle electrode 106.
  • the resulting M IMIM stack has an upper word line 1 10 and a lower word line 1 12 at opposite ends of the stack.
  • the middle electrode may be coupled to a bit line or it may be left to float.
  • the two stacks 102, 103 each include an inactive metal layer 128, 130 closest to the outer word line electrodes 1 12, 1 13.
  • a metal oxide or metal nitride layer may be used as a barrier layer between the memoiy material on each side and the outer word line electrodes.
  • the memory material 124, 126 is between the respective word line electrodes and the middle electrode.
  • the outer inactive electrodes 128, 130 may be made of any suitable conductive material such as a metal or polysilicon. It may be exposed to the memory material or it may be protected by a barrier layer.
  • the middle active metal electrode may be based on Cu, Ag, Ni or any other suitable active metal.
  • the memory material s may be made of any of a variety of different materials and will be described in the context of a programmable metallization cell (PMC) that uses an electrochemical metallization effect to change states.
  • PMC programmable metallization cell
  • a solid electrolyte of oxide or chalcogenide may be used, for example, or a dual layer material .
  • active metal atoms e g., Cu, Pt, or Ag
  • the active metal atoms are driven to form conducting filaments that start at the central active electrode and grow back to the outer inactive electrode.
  • the filaments form the conductive path for the ON state.
  • a negative bias reverses the growth, breaks the filaments, and creates the OFF state.
  • each cell may be in a different state. There may be a filament produced ON state in the lower stack, in the upper stack, in both stacks, or in neither stack . In a typical memory cell array configuration, only the top and bottom electrodes are biased. If thi s approach is applied to a MIM IM RRAM cell as shown in Figure 1, then the middle electrode is floating. As a result, the orientation of the filament tips i s random and depends on its transient potential which varies from cell to cell and between stacks of the same cell . The memory material will not reliably shape into any particular configuration unless a potential is applied to al l three electrodes, top, bottom, and middle.
  • Figure 2 is a state diagram for a memory cell such as that of Figure 1.
  • the states are applied to a graph of the applied voltage (V) on the horizontal scale versus the current flow (I) on the vertical scale.
  • V applied voltage
  • I current flow
  • a positive voltage bias is applied to the outer electrodes 128, 130, for example through the word lines 1 10, 1 12. This causes a transition to a state 172 in which the memory cell conducts very little current.
  • the memory material is indicated as a solid block with or without an upper or lower triangle.
  • the triangles represent the electroformation of conductive filaments between the outer electrodes 102, 104 and the middle electrode 106.
  • a single triangle represents an incomplete conductive path
  • Two connected triangles represent a completed filament conductive path corresponding to an ON state.
  • the polarity of the applied voltage is reversed. As shown by the arrows, from the origin with a negative voltage the voltage is increased until it reaches a transition point 162. At this negativ e v oltage the conductive fi laments start to form and the current flow is increased to a much higher state 164. The memory cell transitions from an OFF state 1 82 to an ON state 1 84. As with the positive applied voltage, as the v oltage increases past the threshold transition level 164, the current increases only slowly and the ON state 1 84 is maintained. If the voltage is then reduced at this stage and returned to the origin 150 or some other low level, then the memory cell state is preserved.
  • Figure 3 is a cross-sectional side view diagram that shows an example configuration of two RRAM cells in series. This enables a built-in selector functionality by using CRS
  • the cell has an upper RRAM portion 204 with an upper metal electrode 206, and a lower inverse RRAM portion 208 with a lower metal electrode 210.
  • a middle electrode 2 1 2 between the two portions is shared.
  • Each portion has a solid electrolyte material 214, 216 as described above.
  • the middle electrode 212 is typically allowed to float. However, by connecting the middle electrode to a known voltage during an initial state, the memory materials 2 14, 2 16 may be set to a known configuration . Thi s provides reliable performance later when the switch electrode and memory electrode are accessed to change the memory state of the stack.
  • the device functions without any read/write transi stor.
  • RRAM acts as the memory cell and the inv erse RRAM acts as the selector.
  • the transistor is avoided. Thi s can significantly reduce the bit cell size and enable stacking.
  • Figure 4 i a cross-sectional side view diagram of a transistor or switch 250 based on the structure of Figure 2.
  • the MIMIM stack has a source 252 at one end, a drain 254 at the opposite end and the middle electrode 256 serv es as the gate.
  • the same memory material i s used for the upper portion 262 between the source and gate and also for the lower portion 264 between the drain and gate.
  • a positiv e bias i s applied to the gate then the filaments grow from the source and the drain to the gate to establish an ON state between the source and drain.
  • a negative bias is applied to the gate, then the filaments move away from the middle electrode and the connection is broken to establish an OFF state.
  • the state of such a switch may be changed within 50- 100ns which is sufficient for many logic circuits.
  • FIG. 5 i s a cross-sectional side view diagram of an RRA memory cell 302 configured in metal layers ov er a substrate and logic circuitry for use in a memory cel l array.
  • the RRAM cell has an upper electrode 304, and a lower electrode 306, typically of a metal such as Cu, Pt, or Ag as described abov e.
  • the RRAM cell also has a middle electrode 308 betw een the upper and lower electrodes and separated from the upper and lower electrodes by memory material as described abov e.
  • the lower electrode is coupled to a metal row word line rail 3 1 6 (M N ).
  • the upper electrode is coupled to a metal column word li ne rail 3 14 (M N+1 _ 2 ). These allow for read and write operations as is typically performed with such memory arrays.
  • the middle electrode 308 is coupled to a different metal rail. For a transistor, this electrode may be coupled to a gate input which will be different for each transistor. For a memory cell, all of the middle electrodes may be coupled to the same power rail 3 1 2 (M N ). This is indicated as being shorted to the lower column word line, however it may be coupled to another source of potential .
  • a horizontal connector or bus bar 322 from the middle electrode 308 is connected to a via 3 10 that connects to a power rail 3 1 2.
  • the power rail is connected to a potential source 3 1 8.
  • the middle electrode potential source is used only to reset or initialize the memory cells. Accordingly, all of the memory cells may be driven with a common voltage 3 1 8 until the filaments are formed so that both upper and lower portions are in the ON state. After this the connection may be broken and the MIM IM structure 302 may be operated as a conventional memory cell .
  • the bus bar 322, the power rail 3 12, or another part of the connection to the power supply 3 1 8 may have a fuse 320. Breaking the fuse, e.g. by exceeding the current capacity of the fuse or by laser, disconnects the middle electrode after the memory cell array has been initialized by electroforming.
  • the word lines are indicated as M N and M N+1 .
  • the lower column line 3 1 6 may be implemented in a metal layer (layer N) that is formed over logic circuitry on a die by patterning the metal layer.
  • the upper row line 3 14 may be implemented in a higher metal layer (layer N+l or higher) by patterning the next metal layer. In this way an array of memory cells may be formed in metal layers that otherwise may not be used for any circuitry.
  • FIG. 6 is a cross-sectional side view diagram of an alternative memory cell in metal layers above a substrate i n which the middle electrode i s coupled to an upper metal layer for electroforming.
  • a memory cell 342 has a lower electrode 346 coupled to a lower metal rail 356 (M N ) and an upper electrode 344 coupled to an upper rail 354 (M N+1 2 ).
  • the memory cell uses a resi stive RAM principle as before to store either an ON or OFF state.
  • a middle electrode 348 is coupled through a connector 362 to a via 350.
  • the via in thi s case is coupled to an upper rail 360 (M N + I ).
  • Thi s as before, is a temporary connection that is for electroforming that is then disconnected at some point.
  • the upper rail 360 of the middle electrode may be connected to the upper rail 354 of the top electrode or it may have a separate power supply (not shown).
  • Figure 7 is an isometric v iew diagram of a crosspoint vertical memory array suitable for use with the present application.
  • the memory array 400 i s embedded over logic circuitry 402.
  • the density of the memory array is increased because the thin film -based selector element is placed in series with the memory element at each cross-section of bit line 410 and word lines 404, 406 since the memory layers 412, 414 are stacked on top of each other.
  • the word lines are fabricated as signal rails 404, 406 in one direction and the bit line 410 i s on a rail orthogonal to the word lines.
  • the many layers of dielectric, the silicon substrate under the circuitry 402 and several other features are not shown in order to not obscure the other features of the drawing.
  • Routing 408 for horizontal word lines 404 and 406 connects the memory cel ls to the circuitry 402 below. Similar routing 416 is included for horizontal bit lines 410.
  • the rails may be implemented in metal layers while the routing i s implemented by vias coupled to metal layers. Additional routing (not shown) is provided to connect the middle electrodes of each memory cell for electroforming. These middle electrodes are between the word lines and the bit lines and may be connected as shown in Figures 5 and 6.
  • Figure 8 i an i sometric view diagram of a crosspoint horizontal memory array 403.
  • the array includes routing 452 for horizontal word lines 454 and 456.
  • Contacts 458 for vertical bit lines 460 are formed directly to underlying logic circuitry (not shown ).
  • the memory cell 462 are fabricated horizontally between the vertically stacked word lines and bit lines.
  • the middle electrode connections are not shown. This may be used for electroforming and then fused, di sconnected, or cut, depending on the particular implementation .
  • the many layers of dielectric, the silicon substrate and the circuitry on the substrate below the metal layers of the word line and bit lines and several other features are not shown in order to not obscure the other features of the drawing.
  • Figures 7 and 8 represent possible crosspoint array configurations for the unique memory array described herein, however, the array may be implemented in any of a variety of other configurations, depending on the intended use and desired form factor and efficiency.
  • Figure 9 is a schematic of a nonv olatile RRAM array 701 including a plurality of resistive memory stacks 702, similar to that of Figure 1 each incorporating upper and middle electrodes with memory material between .
  • the array 705 in this example i s a bidirectional cross point array including any number of independent memory stacks 702, each stack is coupled through a resistive RAM selector element ("S") with the middle and lower electrode.
  • S resistive RAM selector element
  • Each column i associated with a bit line driv en by a column select circuit in column select circuitry 725 coupled to the upper electrode of each RRAM element.
  • Each row is associated w ith a word line driv en by a row select circuit in row select circuitry 730 coupled to the lower electrode of each RRAM selector element.
  • R/W control circuitry 720 receives memory access requests (e.g., from a local processor or communication chip in which the memory is embedded), generates the requisite control signals based on the requests (e.g., read, write 0, or write 1), and controls the row and column select circuitry 725, 730. Voltage supplies 710, 715 are controlled to provide the voltage necessary to bias the array to facilitate the requested action on one or more bitcell s 702. Row and column select circuitry 725, 730 applies the supplied voltage across array 705 to access a selected bitcell( s). Row select ci cuitry 725, column select circuitry 730, and R/W control circuitry 720 may be implemented with any known technology.
  • FIG. 10 i llustrates a computing device 100 in accordance with one implementation.
  • the computing device 100 houses a board 2.
  • the board 2 may include a number of components, including but not limited to a processor 4 and at least one communication chip 6.
  • the processor 4 is physically and electrically coupled to the board 2.
  • the at least one communication chip 6 i s also physically and electrically coupled to the board 2.
  • the communication chip 6 is part of the processor 4.
  • computing device 100 may include other components that may or may not be physically and electrically coupled to the board 2.
  • these other components include, but are not limited to, volatile memory (e.g., DRAM) 8, non-volatile memory (e g., ROM) 9, flash memory (not shown), a graphics processor 1 2, a digital signal processor (not shown ), a crypto processor (not shown), a chipset 14, an antenna 16, a display 18 such as a touchscreen display, a touchscreen controller 20, a haptic actuator array 2 1 , a battery 22, an audio codec (not shown), a video codec (not shown), a power amplifier 24, a global positioning system (GPS) device 26, a compass 28, an accelerometer (not shown), a gyroscope (not shown ), a speaker 30, a camera 32, and a mass storage device (such as hard disk drive) 10, compact disk (CD) (not shown ), digital versatile di sk (DVD) (not shown), and so forth).
  • volatile memory e.g., D
  • the communication chip 6 enables wireless and/or wi ed communications for the transfer of data to and from the computing device 100.
  • the term “wireless " and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channel s, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium . The term does not imply that the associated dev ices do not contain any wires, although in some embodiments they might not.
  • the communication chip 6 may implement any of a number of wireless or wired standards or protocol s, including but not limited to Wi-Fi ( IEEE 802. 1 1 family), WiMAX ( IEEE 802.
  • the computing device 100 may include a plurality of communication chips 6.
  • a first communication chip 6 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second
  • communication chip 6 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • Many of the components of the computing device may include memory on a die with logic devices or may have memory or logic devices on different dies in the same package.
  • Embedded memory may be packaged together with a die that includes memory.
  • the processor, memory devices, communication devices, or other components may all include or be packaged with memory or logic transistors fabricated or configured as described herein.
  • processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the computing device 100 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, wearables, and drones.
  • the computing device 100 may be any other electronic device that processes data.
  • Embodiments may be adapted to be used with a variety of different types of packages for different implementations.
  • References to "one embodiment”, “an embodiment”, “example embodiment”, “various embodiments”, etc., indicate that the embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Further, some embodiments may have some, all, or none of the features described for other embodiments.
  • Coupled is used to indicate that two or more elements co-operate or interact with each other, but they may or may not have intervening physical or electrical components between them.
  • Some embodiments pertain to an apparatus that includes a first resi stive memory material, a first electrode on one side of the first resistive memory material, a second resistiv e memory material, a second electrode on one side of the second resistive memory material, a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resi stive memory material opposite the first electrode and electrically coupled to the second resistive memory material and on a side of the second resistive memory material opposite the second electrode, and a power connector to apply a potential to the middle electrode, the potential being opposite a potential of the first electrode and the second electrode.
  • the fuse compri ses a metal trace that may be broken with an overcurrent.
  • the apparatus i s a memory cell of a crosspoint memory cell array
  • the second electrode is a selector contact
  • the first resistive memory material i s a storage cell of the memory.
  • the first electrode is coupled to a word line and the second electrode is coupled to a bit line.
  • bus bar in a metal layer over a silicon substrate, the bus bar coupled to the middle electrode power connector at one end and to a power rail at another end.
  • bus bar is coupled to the power rai 1 through a through-silicon via.
  • first and second resistive memory materials are a solid electrolyte of chalcogenide.
  • Further embodiments include a metal nitride barrier layer between the middle electrode and the first and second resistive memory materials.
  • the first electrode is coupled to a logic circuit as a source
  • the second electrode i s coupled to the logic circuit as a drain
  • the middle electrode is coupled to the logic circuit as a gate.
  • the first metal layer is formed in a first metal layer of a plurality of metal layers over logic circuitry on a silicon substrate, wherein the second metal layer is formed in a second metal layer of the plurality of metal layers and wherein the apparatus is one of multiple memory cells in an embedded array of memory cell s.
  • Some embodiments pertain to the apparatus above comprised by a computing system having a processor with the above apparatus as embedded memory, a mass memory, and a comm nications chip.
  • Some embodiments pertain to a method that includes applying a potential to a middle electrode between memory materials of a stacked memory cell, applying an opposite polarity potential a first and a second electrode of the stacked memory cell, the first and the second electrodes being on respective opposite side of the middle electrode and the respective memory material, wherein the potential electroforms filaments within the first and second memory materials, removing the potential to the middle electrode after electroforming, and applying opposite potential to the first and second electrodes to set a memory state in the stacked memory cell.
  • removing the potential com pri ses breaking a fuse between a source of the potential and the middle electrode.
  • applying the potential comprises applying the potential to a power rail that i s connected to a plurality of stacked memory cell s to apply a potential to each of the plurality of stacked memory cells simultaneously.
  • applying the potential comprises applying the potential through a patterned metal layer of a plurality of metal layers over logic circuitry of a silicon substrate.
  • Some embodiments pertain to a switchable transistor embedded in metal layers of a semiconductor die that includes a first resistive memory material , a source formed as a first metal electrode in a first metal layer of the die on one side of the first material, a second resistive memory material, a drain formed as a second metal electrode in a second metal layer of the die on one side of the second material, and a gate formed as a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resistive memory material opposite the first electrode and electrically coupled to the second resistive memory material and on a side of the second resistive memory material opposite the second electrode.
  • the gate is coupled to a third metal layer of the die and wherein the gate is coupled to a potential to initially electroform the resistive memory materials before operation.
  • first and second resistive memory materials are a solid electrolyte of chalcogenide.

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Abstract

L'invention porte sur une cellule de mémoire vive résistive et sur un réseau qui comprennent une fonctionnalité d'électroformage. Un exemple comprend un premier matériau de mémoire résistive, une première électrode sur un côté du premier matériau de mémoire résistive, un second matériau de mémoire résistive, une seconde électrode sur un côté du second matériau de mémoire résistive, une électrode intermédiaire entre la première électrode et la seconde électrode, l'électrode intermédiaire étant électriquement couplée au premier matériau de mémoire résistive sur un côté du premier matériau de mémoire résistive opposé à la première électrode et électriquement couplée au second matériau de mémoire résistive et sur un côté du second matériau de mémoire résistive opposé à la seconde électrode, et un connecteur d'alimentation permettant d'appliquer un potentiel à l'électrode intermédiaire, le potentiel étant opposé à un potentiel de la première électrode et de la seconde électrode.
PCT/US2016/041096 2016-07-06 2016-07-06 Mémoire vive résistive à fonctionnalité d'électroformage Ceased WO2018009182A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050181546A1 (en) * 2002-07-08 2005-08-18 Madurawe Raminda U. Methods for fabricating fuse programmable three dimensional integrated circuits
US20050230724A1 (en) * 2004-04-16 2005-10-20 Sharp Laboratories Of America, Inc. 3D cross-point memory array with shared connections
US20110310656A1 (en) * 2010-06-18 2011-12-22 Franz Kreupl Memory Cell With Resistance-Switching Layers Including Breakdown Layer
US20120261636A1 (en) * 2011-04-12 2012-10-18 Feng Zhou Resistive random access memory (ram) cell and method for forming
US20140158967A1 (en) * 2012-12-10 2014-06-12 Winbond Electronics Corp. Self-rectifying rram cell structure and 3d crossbar array architecture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050181546A1 (en) * 2002-07-08 2005-08-18 Madurawe Raminda U. Methods for fabricating fuse programmable three dimensional integrated circuits
US20050230724A1 (en) * 2004-04-16 2005-10-20 Sharp Laboratories Of America, Inc. 3D cross-point memory array with shared connections
US20110310656A1 (en) * 2010-06-18 2011-12-22 Franz Kreupl Memory Cell With Resistance-Switching Layers Including Breakdown Layer
US20120261636A1 (en) * 2011-04-12 2012-10-18 Feng Zhou Resistive random access memory (ram) cell and method for forming
US20140158967A1 (en) * 2012-12-10 2014-06-12 Winbond Electronics Corp. Self-rectifying rram cell structure and 3d crossbar array architecture thereof

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