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WO2018004587A1 - Dispositifs de rram à couches de barrière thermique bidimensionnelles - Google Patents

Dispositifs de rram à couches de barrière thermique bidimensionnelles Download PDF

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Publication number
WO2018004587A1
WO2018004587A1 PCT/US2016/040301 US2016040301W WO2018004587A1 WO 2018004587 A1 WO2018004587 A1 WO 2018004587A1 US 2016040301 W US2016040301 W US 2016040301W WO 2018004587 A1 WO2018004587 A1 WO 2018004587A1
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Prior art keywords
layer
thermal barrier
rram
electrode layer
electrode
Prior art date
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PCT/US2016/040301
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English (en)
Inventor
Prashant Majhi
Elijah V. KARPOV
Ravi Pillarisetty
Uday Shah
Niloy Mukherjee
Tejaswi K. Indukuri
James S. Clarke
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Intel Corp
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Intel Corp
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Priority to PCT/US2016/040301 priority Critical patent/WO2018004587A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/51—Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/52—Structure characterized by the electrode material, shape, etc.
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • Embodiments of the invention are in the field of integrated circuit fabrication and, in particular, approaches for fabricating resistive random access memory (RRAM) stacks with two- dimensional (2D) barrier layers, and the resulting structures and devices.
  • RRAM resistive random access memory
  • shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity.
  • the drive for ever-more capacity, however, is not without issue.
  • the necessity to optimize the performance of each device becomes increasingly significant.
  • Embedded SRAM and DRAM have problems with non-volatility and soft error rates, while embedded FLASH memories require additional masking layers or processing steps during manufacture, require high-voltage for programming, and have issues with endurance and reliability.
  • Nonvolatile memory based on resistance change is known as RRAM or ReRAM.
  • RRAM Nonvolatile memory based on resistance change
  • ReRAM ReRAM
  • the cost benefit and performance benefit of RRAM have not been obvious enough to most companies to proceed with the replacement.
  • operating voltages less than IV and compatible with CMOS logic processes may be desirable but challenging to achieve.
  • Figure 1 A illustrates a cross-sectional view of an RRAM element without any 2D thermal barrier layers.
  • Figure IB illustrates a cross-sectional view of an RRAM element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 2 illustrates cross-sectional views of various operations in a method of fabricating an RRAM element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 3 A illustrates a cross-sectionai view of two RRAM devices, each including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • FIG. 3B illustrates a plan view of a pair of RRAM elements integrated with a common line electrode, each RRAM element including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • FIG. 3C illustrates a plan view of a pair of RRAM elements integrated with discrete via electrodes, each RRAM element including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 4 illustrates a cross-sectional view of an RRAM device fabricated using a damascene process and including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 5 illustrates a cross-sectional view of an RRAM element coupled to a drain side of a transistor selector and having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • FIG. 6A illustrates schematic views of several options for positioning an RRAM element in an integrated circuit, the RRAM element including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 6B illustrates a cross-sectional view of a logic region together with an RRAM memory array integrated on a common substrate, in accordance with an embodiment of the present invention.
  • Figures 7A and 7B illustrate a schematic and corresponding I-V plot, respectively, demonstrating concepts involved with filament formation in an RRAM element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 8 illustrates an operational schematic representing a changing of states for an anionic-based metal-conductive oxide-metal RRAM memon,' element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 9 illustrates a schematic representation of resistance change in a conductive oxide layer induced by changing the concentration of oxygen vacancies in the conductive oxide layer, in accordance with an embodiment of the present invention.
  • Figure 10 illustrates an operational schematic representing a changing of states for a cationic-based metal -conductive oxide-metal RRAM memory element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 11 illustrates a schematic representation of resistance change in a cationic-based conductive oxide layer induced by changing the concentration of cation vacancies in the conductive oxide layer, in accordance with an embodiment of the present invention.
  • Figure 12 illustrates a schematic of a memory bit cell which includes a metal-conductive oxide-metal RRAM memory element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • Figure 13 illustrates a block diagram of an electronic system, in accordance with an embodiment of the present invention.
  • Figure 14 illustrates a computing device in accordance with one embodiment of the invention.
  • Figure 15 illustrates an interposer that includes one or more embodiments of the invention.
  • One or more embodiments are directed to resistive random access memory (RRAM) material stacks with thermal barriers. Particular embodiments are directed to the use of two- dimensional (2D) materials, such as graphene or silicene, as thermal barriers in an RRAM element or device.
  • RRAM resistive random access memory
  • Particular embodiments are directed to the use of two- dimensional (2D) materials, such as graphene or silicene, as thermal barriers in an RRAM element or device.
  • One or more embodiments of the present invention are directed to methods for integrating RRAM memory arrays into a logic processor. Particular embodiments may be suitable for fabricating embedded non-volatile memory (e-NVM). Approaches described herein may provide a fabrication pathway for high performance RRAM ceils and increase the potential of using scaled RRAM ⁇ cells for future e-NVM needs, such as for integration in system on chip (SoC) products.
  • SoC system on chip
  • an RRAM memory thin film stack is designed to improve the switching properties of an RRAM device fabricated therefrom by controlling the thermal properties of the memory stack.
  • 2D materials are integrated within the conductive electrode material, e.g., embedded within the electrode material, to provide a thermal barrier to prevent thermal energy loss. Prevention of thermal energy loss may be essential to the functioning of the RRAM ceil.
  • Embodiments may be implemented to further provide an internal ballast resistance in cases where the material of the contacts is engineered to appropriate resistance levels.
  • Embodiments may be implemented to improve the switching memory performance for both interfacial -based and filamentary-based RRAM. This may be achieved by engineering a 2D materials within the electrode stack. The improved thermal properties that result may ensure that the RRAM memory resets (e.g., resistance change from low resistance to high resistance) at low currents and voltage.
  • 2D materials are implemented to further be used as an internal ballast resistor to control parasitic discharge currents. Such implementations may improve performance and reliability of RRAM memory, increasing its potential or likelihood for use as e-NVM.
  • Figure 1 A illustrates a cross-sectional view of an RRAM element without any 2D thermal barrier layers.
  • an RRAM element material stack 100 includes a bottom electrode disposed above a substrate 101.
  • a resistance switching layer 104 is disposed on the bottom electrode 102.
  • An oxygen exchange layer (OEL) 106 may be included above the resistance switching layer 104.
  • a top electrode 108 is above the resistance switching layer 104 and, in some cases, on the OEL 106.
  • a filament may be included in the resistance switching layer 104, in the case of filament-based RRAM.
  • Downward arrow 1 14, upward arrow 112, and lateral arrows 1 16 represent possible heat dissipation pathways within the RRAM element material stack 100. Such heat dissipation pathways may be a source of reduced performance of an RRAM: device based on the RRAM element material stack 100.
  • An oxide (or other) RRAM-based memor' stack may be fabricated to include 2D materials within one or both electrodes of the RRAM memory stack to reduce heat dissipation.
  • Figure IB illustrates a cross-secti onal view of an RRAM element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • a resistive random access memory (RRAM) element 120 includes a first electrode layer 122 disposed above a substrate 121.
  • the first electrode layer 122 has a two-dimensional (2D) thermal barrier layer 124 embedded therein. Placement of the 2D thermal barrier layer 124 is such that the layer is effectively embedded within a lower portion 122 A and an upper portion 122B of the first electrode layer 122.
  • a resistance switching layer 126 is disposed on the first electrode layer 122 but not in contact with the 2D thermal barrier layer 124 of the first electrode layer 122.
  • a second electrode layer 132 is disposed above the resistance switching layer 126.
  • the second electrode layer 132 has a 2D thermal barrier layer 134 embedded therein. Placement of the 2D thermal barrier layer 134 is such that the layer is effectively embedded within a lower portion 132B and an upper portion 132A of the second electrode layer 132.
  • the RRAM element 120 includes an oxygen exchange layer (OEL) 130 disposed between, as possibly directly between, the second electrode layer 132 and the resistance switching layer 126.
  • OEL oxygen exchange layer
  • the 2D thermal barrier layer 134 is proximate to but not in contact with the OEL 130 (if included) or the resistance switching layer 126 (in the case that an OEL is not included).
  • a filament 128 is included in the resistance switching layer 126 to provide filament-based RRAM, as is described in greater detail below in association with Figures 7 A and 7B. In other embodiment, however, a filament is not included and surface or interface-based RRAM is fabricated.
  • a lower 2D thermal barrier layer 124 is included but an upper 2D thermal barrier layer 134 is not included in stack 120.
  • an upper 2D thermal barrier layer 134 is included but a lower 2D thermal barrier layer 124 is not included in stack 120.
  • both a lower 2D thermal barrier layer 124 and an upper 2D thermal barrier layer 134 are included in stack 120, as is depicted in Figure IB.
  • the 2D thermal barrier layer 124 of the first electrode layer 122 and the second 2D thermal barrier layer 134 of the second electrode layer 132 are composed of the same or essentially the same material. In another embodiment, however, the 2D thermal barrier layer 124 of the first electrode layer 122 and the second 2D thermal barri er layer 134 of the second electrode layer 132 are composed of a different material. In one specific embodiment, one or both of the 2D thermal barrier layers 124 and 134 are composed of graphene, e.g., in the form of one or more stacked layers of carbon atoms arranged in a 2D array.
  • one or both of the 2D thermal barrier layers 124 and 134 are composed of silicene, e.g., in the form of one or more stacked layers of silicon (Si) atoms arranged in a 2D array.
  • one or both of the 2D thermal barrier layers 124 and 134 are composed of a material such as, but not limited to, graphene, silicene, MoS 2 , or WS 2 .
  • the 2D thermal barrier layer is between 1 and 3 atomic layers thick, e.g., in the form of a single layer or a stack of two or three layers of a 2D material such as graphene or silicene.
  • the 2D thermal barrier layer 124 or 134 is spaced apart from the resistance switching layer 126 (or from an OEL of present) by a distance of less than 1 nanometer.
  • the resistance switching layer 126 is an oxide-based material layer including a dielectric oxide material (e.g., such as a layer of Hf0 2 , as is described in association with Figures 7A and 7B) or a conductive oxide material (e.g., as described below in association with Figures 8 and 9),
  • a dielectric oxide material e.g., such as a layer of Hf0 2 , as is described in association with Figures 7A and 7B
  • a conductive oxide material e.g., as described below in association with Figures 8 and 9
  • an OEL 130 may be included in stack 120.
  • a typical resistive random access (REAM) memory stack includes a first metal electrode, a stoichiometric metal oxide switching layer disposed on the first metal electrode, and a second metai electrode disposed on the metal oxide switching layer.
  • an oxygen exchange layer (OEL) may be disposed on the metal oxide switching layer to facilitate resistive switching.
  • a conductive filament is formed during an initial soft dielectric breakdown process.
  • This process involves application of a high voltage typically in the range of 1.5 to 3 V between the two metal electrodes sandwiching the metal oxide switching layer, as is described in greater detail below in association with Figures 7A and 7B.
  • the conductive filament is made-up of oxygen vacancies which migrate in response to the electric field created during the forming process.
  • oxygen vacancies are created during an annealing process at temperatures above, e.g., 350 degrees Celsius.
  • an oxygen exchange layer when disposed above the metal oxide switching layer, it can serve as a more effective oxygen scavenging layer by- taking oxygen from the metal oxide switching layer as a result of its oxygen affinity.
  • An oxygen exchange layer typically is composed of metals which are identical to the metal film in the metal oxide layer or metals with higher oxygen affinity compared to the metal oxide switching layer.
  • an OEL may be implemented to serve as a reservoir for oxygen vacancies, helping to create and dissolve the conductive filament by acting as a source and a sink.
  • advantages of implementing a material stack such as RRAM element 120 for RRAM device fabrication may include one or more of (1)
  • 2D materials are implemented within stack 120 to provide excellent thermal resistance layers. Also, such 2D materials may be good electrical conductors, with a tunable metal-2D contact resistance, which may enable timing of ballast resistance.
  • graphene is implemented to control the thermal budget in scaled cells.
  • Material stack 120 may be fabricated in a series of deposition operations.
  • Figure 2 illustrates cross-sectional views of various operations in a method of fabricating an RRAM element having one or more 2D thermal barrier layers, in accordance with an
  • a method of fabricating a resistive random access memory (RRAM) device includes forming a first portion 122 A of a first electrode layer 122 above a substrate 121.
  • a first two-dimensional (2D) thermal barrier layer 124 is formed on the first portion 122A of the first electrode layer 122.
  • a second portion 122B of the first electrode layer 122 is then formed on the first 2D thermal barrier layer 124.
  • the first 2D thermal barrier layer 124 is formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.
  • a resistance switching layer 126 is formed on the second portion 122B of the first electrode layer 122.
  • a first portion 132B of a second electrode 132 layer is formed above the resistance switching layer 126.
  • an OEL 130 is first formed on the resistance switching layer 126, and the first portion 132B of a second electrode 132 layer is formed on the OEL 130.
  • a second 2D thermal barrier layer 134 is formed on the first portion 132B of the second electrode layer 132.
  • a second portion 132A of the second electrode layer 132 is then formed on the second 2D thermal barrier layer 134.
  • the second 2D thermal barrier layer 134 is formed using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • RRAM: element 120 may be fabricated on a conductive interconnect formed in an inter-layer dielectric (ILD) layer. It is also to be appreciated that the stack of materials described in Figure 2 may ultimately be etched to provide a patterned material stack for RRAM element 120. As a possible example of both such scenarios, Figure 3 A illustrates a cross-sectional view of two RRAM devices, each including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • ILD inter-layer dielectric
  • each of the resistive random access memory (RRAM) devices includes a conductive interconnect 306 disposed in an inter-layer dielectric (ILD) layer 304 disposed above a substrate 302.
  • the ILD layer 306 has an uppermost surface substantially co- planar with an uppermost surface of the conductive interconnect 306.
  • An RRAM element 120 is disposed on the conductive interconnect 306.
  • Each RRAM element 120 includes the material layers described in association with Figure IB, as is depicted in Figure 3,
  • the conductive interconnect 306 includes a conductive line portion 308 and an underlying via portion 310, as is depicted in Figure 3 A.
  • the conductive interconnect is a conductive via.
  • the conductive interconnect includes a conductive fill material 314 surrounded by a barrier layer 312, which may include an upper barrier layer 3 16, as is depicted in Figure 3 A.
  • the conductive fill material 314 but not the barrier layer 312 is recessed to form an opening in which the upper barrier layer 316 is then formed.
  • the upper barrier layer 316 is composed of substantially the same material as barrier layer.
  • the material includes tantalum nitride.
  • the materials of the memory (RRAM) elements are patterned following a deposition process such as described in association with Figure 2.
  • the material layers are patterned using a subtractive etching process.
  • a dielectric sidewall spacer is laterally adjacent to and in contact with sidewalls of the patterned material layers of stacks 120.
  • the dielectric sidewall spacer formation includes conformal deposition of a dielectric material, such as a silicon nitride layer, and subsequent anisotropic etching to form the dielectric sidewall spacer.
  • the a dielectric sidewall spacer is formed laterally adjacent to and in contact with sidewalls of the first electrode laver, the first 2D thermal barrier laver, the resistance switching layer, the second electrode layer and the second 2D thermal barrier layer.
  • one or more interlayer dielectrics are included in an RRAM device structure.
  • ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 2 ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.
  • the FLD layers may include pores or air gaps to further reduce their dielectric constant.
  • etch stop materials may be included as intervening dielectric layers between the ILD layers.
  • Such etch stop layers may be composed of dielectric materials different from the interlayer dielectric material .
  • an etch stop layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof.
  • Other suitable materials may include carbon-based materials, such as silicon carbide.
  • etch stop layers known in the art may be used depending upon the particular implementation.
  • the etch stop layers may be formed by CVD, PVD, or by other deposition methods.
  • the metal lines (such as 308) and vias (such as 310) are composed of one or more metal or other conductive structures,
  • a common example is the use of copper lines and structures that may or may not include barrier layers (such as Ta or TaN layers) between the copper and surrounding ILD material.
  • barrier layers such as Ta or TaN layers
  • metal includes alloys, stacks, and other combinations of multiple metals.
  • the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc.
  • the interconnect lines are also sometimes referred to in the arts as traces, wires, lines, metal, or simply interconnect.
  • substrate 302 is a semiconductor substrate.
  • the semiconductor substrate In one implementation, the
  • semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon- on-insulator substructure.
  • the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group HI -V or group IV materials.
  • germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group HI -V or group IV materials are described here, any material that may serve as a foundation upon which a semiconductor device may be built fails within the spirit and scope of the present invention.
  • an underlying semiconductor substrate or structure such as underlying device layer(s) of an integrated circuit.
  • an underlying semiconductor substrate 121 or 302 represents a general workpiece object used to manufacture integrated circuits.
  • semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials.
  • SOI silicon on insulator
  • the semiconductor substrate depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like.
  • the substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.
  • the illustrated structure depicted in Figure IB or 3 A is fabricated on underlying transistor or other semiconductor device layer(s) formed in or above the substrate 121 or 302. In another embodiment, the illustrated structures depicted in Figure IB or 3 A are fabricated on underlying lower level interconnect layers formed above the substrate 121 or 302, respectively.
  • RRAM elements 120 may be formed on a common conductive line.
  • Figure 3B illustrates a plan view of a pair of RRAM elements integrated with a common line electrode, each RRAM element including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • a conductive interconnect 350 housed in an ILD layer 304 includes two RRAM stacks 120 thereon (e.g., stacks including layers described in association with Figures I B or 3 A). Each RRAM stack 120 is disposed on a portion of an upper barrier layer 316 or a conductive fill material 314 of the conductive interconnect.
  • interconnect in this example is a conductive line coupled to a first and second RRAM stacks 120.
  • adjacent RRAM elements 120 may be formed on respective conductive vias.
  • Figure 3C illustrates a plan view of a pair of RRAM elements integrated with discrete via electrodes, each RRAM: element including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • a pair of conductive vias 360 housed in an ILD layer 304 each has a respective RRAM: stack 120 thereon (e.g., stacks including layers described in association with Figures IB or 3 A).
  • Each via is discrete and includes an exposed upper barrier layer 316 or conductive fill material 314, on which a corresponding RRAM stack 120 is disposed.
  • RRAM material stacks including thermal barrier layers may be fabricated through subtractive patterning of the layers of the RRAM stack 120 materials, as is depicted in the examples above.
  • the layers of an RRAM element may be fabricated in a damascene-like fabrication scheme.
  • Figure 4 illustrates a cross-sectional view of an RRAM device fabricated using a damascene process and including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • a resistive random access memory (RRAM) device includes a conductive interconnect 306 (e.g., one such interconnect described in association with Figure 3 A) disposed in a first inter-layer dielectric (ILD) layer 304 disposed above a substrate 302.
  • a second ILD layer 404 is disposed above the first ILD layer 304.
  • the second ILD layer 404 has an opening exposing the conductive interconnect 306 from a top down perspective.
  • the opening has sidewalls, for example the sloped sidewalls depicted in Figure 4.
  • An RRAM element 406 is disposed on the conductive interconnect 306.
  • the RRAM element 406 includes materials of the first electrode layer 122A/122B, the first 2D thermal barrier layer 124, the resistance switching layer 126, the optional OEL 130, the second electrode layer 132A/132B and the second 2D thermal barrier layer 134 formed in the opening of the second ILD layer 404.
  • second ILD layer 404 is disposed directly on an uppermost surface 402 of the first ILD layer 304, as is depicted in Figure 4.
  • an etch stop layer is disposed between the first ILD layer 304 and the second ILD layer 404.
  • a conductive interconnect of an associated RRAM element stack may be coupled to a drain region of an underlying select transistor disposed on a substrate.
  • Figure 5 illustrates a cross-sectional view of an RRAM element coupled to a drain side of a tra sistor selector and having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • a memory structure 500 includes a transistor 502 disposed in or above an active region 504 of a semiconductor substrate 506.
  • the transistor 502 includes a gate electrode 508 with source/drain regions 510 on either side of the gate electrode 508, and in active region 504 of substrate 506,
  • the source/drain region 510 on the left-hand side of Figure 5 is a source region
  • the source/drain region 510 on the right-hand side of Figure 5 is a drain region.
  • An RRAM element 120 is coupled to the drain region of the transistor 502, but not to the source region of the transistor 502. The arrangement enables driving of the RRAM element 120 by the drain side only.
  • the RRAM element 120 and portions of the transistor 502 may be included in an inter-layer dielectric (ILD) layer 550, as is depicted in Figure 5.
  • ILD inter-layer dielectric
  • the RRAM: element 120 includes a top (second) electrode layer 132A/B having a 2D thermal barrier layer 134 embedded therein, an optional OEL material 130, a resistance switching layer 126, and a bottom (first) electrode layer 122A/B having a and having a 2D thermal barrier layer 124 embedded therein.
  • the RRAM element 120 is, in an embodiment, included as an interrupting feature along a conductive drain contact 530. In one such embodiment,
  • gate contact 534 and source contact 532 are not coupled to, or interrupted by the RRAM element 120, as is depicted in Figure 5.
  • the RRAM element 120 is shown genericaliy along the drain contact 530 without a lateral reference, the actual layer in which the RRAM element 120 is included may be viewed as an interconnect layer (e.g., Ml, M2, M3, M4, etc.) corresponding to a logic region in another area of the substrate 506. It is also to be appreciated that additional interconnect layer(s) may be formed on top of the structure 500 shown in Figure 5, e.g., using standard dual damascene process techniques that are well-known in the art.
  • transistor 502 is a metal-oxide-semiconductor field-effect transistor
  • MOSFET metal-oxide-semiconductor
  • the MOS transistors described herein may be planar transistors, nonplanar transistors, or a combination of both.
  • Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.
  • each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer.
  • the gate dielectric layer may include one layer or a stack of layers.
  • the one or more layers may include silicon oxide, silicon dioxide (Si0 2 ) and/or a high-k dielectric material.
  • the high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.
  • high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.
  • the gate electrode layer of each MOS transistor is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor.
  • the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.
  • metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide,
  • a P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV.
  • metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide.
  • An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.
  • the gate electrode may consist of a "U'-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.
  • at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate.
  • the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures.
  • the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
  • a pair of sidewall spacers 552 may be formed on opposing sides of the gate stack that bracket the gate stack.
  • the sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate
  • a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
  • source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor.
  • the source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process.
  • dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions.
  • An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process.
  • the substrate may first be etched to form recesses at the locations of the source and drain regions.
  • the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide.
  • the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous.
  • the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.
  • integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips.
  • traditional charge-based memory technologies such as DRAM and NAND Flash are now facing severe scalability issues related to increasingly precise charge placement and sensing requirements.
  • embedding charge-based memory directly onto a high performance logic chip is not very attractive for future technology nodes.
  • a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories is resistive random access memory (RRAM), since it relies on resistivity rather than charge as the information carrier.
  • RRAM resistive random access memory
  • an appropriate integrated logic plus RRAM structure and fabrication method is needed.
  • Embodiments of the present invention include such structures and fabrication processes.
  • Embodiments described herein include a fabrication method for embedding RRAM bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.
  • an RRAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit.
  • BEOL back end or back end of line
  • Figure 6A illustrates schematic views of several options for positioning an RRAM ⁇ element in an integrated circuit, the RRAM element including one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • FIG. 6 A five examples (A)-(E) of an RRAM cell situated above a second metal logic layer (M2) or higher are provided.
  • a memory region 600 and a logic region 602 of an integrated circuit are depicted schematically.
  • Each memory region 600 and logic region 602 is associated with a corresponding transistor (or group of transistors) 604 or 606, respectively.
  • Stacks of metallization layers include metal lines 608 and vias 610 that are generally alternating.
  • all arrangements depicted include an RRAM element disposed above a second metal line (M2) in the stack.
  • the RRAM element typically includes a resistance switching layer, such as a conductive oxide memory layer, sandwiched between a bottom electrode and a top electrode, and may be formed in an opening of an insulating layer.
  • a resistance switching layer such as a conductive oxide memory layer
  • One or both of the bottom electrode or the top electrode may include a 2D thermal barrier layer.
  • an RRAM element is fabricated on top of a unique via 650 intended for memory devices.
  • an RRAM element is fabricated first and an upper unique via 660 contacts the RRAM from above.
  • an RRAM element has a top electrode with an increased thickness such that the RRAM element occupies a full via depth, between metal lines.
  • an RRAM element has a top electrode with an increased thickness such that the RRAM ⁇ element occupies a full metal line height.
  • an RRAM element has a top electrode with an increased thickness such that the RRAM element occupies a full interconnect level (via plus metal line). Accordingly, in an embodiment, an RRAM element or an array of RRAM elements can be embedded in a logic chip.
  • FIG. 6B illustrates a cross-sectional view of a logic region together with an RRAM memory array integrated on a common substrate, in accordance with an embodiment of the present invention.
  • a structure 4000 includes a logic region 4020 and an RRAM array region 4040.
  • metal 2 (M2) 4080 and via 1 (VI) 4100 structures are formed above a substrate 4060.
  • the M2 4080 and VI 4100 structures are formed in an inter-layer dielectric layer 4120 disposed over an etch stop layer 4140.
  • a plurality of RRAM stacks 120 is formed in the inter-layer dielectric layer 4200 disposed over the etch stop layer 4220.
  • the plurality of RRAM stacks 120 may be coupled to corresponding ones of the M2 4080 structures by a conductive layer 4240, as is depicted in Figure 6B.
  • a dielectric spacer layer 126 may be formed on sidewalis of portions of the RRAM stacks, as is also depicted in Figure 6B.
  • Each of the RRAM stacks 120 includes a first electrode layer 122A B which may have a 2D thermal barrier layer 124 embedded therein, a switching layer 126, an optional OEL material 130, and a second electrode layer 132A/B which may have a 2D thermal barrier layer 134 embedded therein.
  • a top electrode 4340 may also be included, as is depicted in Figure 6B.
  • an etch stop layer 4360 is disposed on the inter-layer dielectric layer 4200.
  • Metal 4 (M4) 4380 and via to memory 4400 structures are formed in the inter-layer dielectric layer 4420 disposed over the etch stop layer 4360.
  • additional interconnect layer(s) may be formed on top of the M4/via to memory layers of the REAM array region 4040 of Figure 6B, e.g., using standard dual damascene process techniques that are well-known in the art.
  • REAM stacks may actually include numerous layers of very thin films, for the sake of simplicity the RRAM stacks 120 are depicted as describe above. It is also to be appreciated that although in the illustrations the RRAM stacks are shown embedded into a corresponding logic metal 3 (M3) layer, they may instead be embedded into some other interconnect layer (e.g., Ml, M2, M4, etc.)
  • M3 logic metal 3
  • the conductive metal layer 4240 is a tantalum nitride (TaN) layer.
  • the conductive metal layer 4240 is referred to as a "thin via" layer.
  • the top electrode 4340 is composed of a material or stack of materials suitable for electrically contacting the REAM stack 120.
  • the top electrode 4340 is a topographically smooth electrode.
  • the top electrode 4340 has a thickness suitable for good conductivity but has little to no columnar structure formation that would otherwise lead to a rough top surface. Such a topographically smooth electrode may be referred to as amorphous in structure.
  • the top electrode 4340 begins as a hardmask layer, such as a titanium nitride hardmask layer, used for patterning the RRAM stack and is ultimately retained as a conductive contact.
  • metal 2 (M2) 4500 and via I (VI) 4520 structures are formed in the inter-layer dielectric layer 4120 disposed over the etch stop layer 4140.
  • the etch stop layer 4220 is disposed on the inter- layer dielectric layer 4120.
  • Metal 3 (M3) 4540 and via 2 (V2) 4560 structures are formed in the inter-layer dielectric layer 4200 disposed over the etch stop layer 4220.
  • the etch stop layer 4360 is disposed on the inter-layer dielectric layer 4200.
  • Metal 4 (M4) 4580 and via 3 (V3) 4600 structures are formed in the inter-layer dielectric layer 4420 disposed over the etch stop layer 4360. It is to be appreciated that additional interconnect layer(s) may be formed on top of the M4/V3 layers of the logic region 4020 of Figure 6B, e.g., using standard dual damascene process techniques that are well-known in the art.
  • a material stack 700 includes a bottom electrode (BE) 702, an oxide layer 704 such a hafnium oxide layer (HfO 2 ), which may be considered a dielectric oxide layer), and a top electrode (TE) 706.
  • BE bottom electrode
  • HfO 2 hafnium oxide layer
  • TE top electrode
  • the bottom electrode 702 may include a 2D thermal barrier layer 124 embedded therein, and the top electrode 706 may include a 2D thermal barrier layer 134 embedded therein.
  • Oxide vacancies 708 may are depicted as circles in Figure 7A.
  • Oxide RRAM cell filament formation begins with a stoichiometric oxide layer 704 which is subjected to a forming (soft breakdown) operation (1) to provide a low resistance state (LRS).
  • a first reset operation (2) is then performed to provide switching to a high resistance state (FIRS).
  • a set operation (3) is then performed to return to the LRS.
  • Performing operations (l)-(3) involves motion of oxygen vacancies and redox phenomena.
  • Plot 710 of Figure 7B illustrates the I-V characteristics association with operations (1), (2) and (3) of Figure 7A.
  • an RRAM element or device may be an anionic-based conductive oxide memory element.
  • Figure 8 illustrates an operational schematic representing a changing of states for an anionic-based metal-conductive oxide-metal RRAM memory element having one or more 2D thermal barrier layers, in accordance with an embodiment of the present invention.
  • a memory element 800 includes an electrode/conductive oxide/elect ode material stack. Electrode 1 may include a 2D thermal barrier layer 124 embedded therein, and Electrode 2 may include a 2D thermal barrier layer 134 embedded therein.
  • the memory element 800 may begin in a less conductive state (1), with the conductive oxide layer being in a less conductive state 804A.
  • An electrical pulse such as a duration of a positive bias (2) may be applied to provide memory element 800 in a more conductive state (3), with the conductive oxide layer being in a more conductive state 804B,
  • An electrical pulse such as a duration of a negative bias (4) may be applied to again provide memory element 800 having the less conductive state (1),
  • electrical pulsing may be used to change resistance of the memory element 800.
  • a memory element includes an anionic-based conductive oxide layer sandwiched between two electrodes.
  • Resistivity of the conductive oxide layer in low field is, in some embodiments, in the range found typical of conductive films of metal compounds, e.g. TiAiN.
  • the resistivity for such a layer is approximately in the range of 0.1 Ohm cm - 10 kOhm cm when measured at low field.
  • Resistivity of the film is tuned depending in the memory element size to achieve final resistance value in the range compatible with fast read.
  • Composition of the conductive oxide layer may be tuned in such a way that a small change in its composition results in a large change in resistance.
  • Resistance change occurs, in some embodiments, due to a Mott transition, e.g., when injected/extracted charge causes phase transition in the conductive oxide layer between more and less resistive phase configurations.
  • the resistance change can be induced by changing the concentration of oxygen vacancies in the conductive oxide layer.
  • FIG 9 illustrates a schematic representation of resistance change in an anionic-based conductive oxide layer induced by changing the concentration of oxygen vacancies in the conductive oxide layer, in accordance with an embodiment of the present invention.
  • a memory element 900 is shown as deposited (A).
  • the memory element includes a conductive oxide layer 904 between a palladium (Pd) electrode 902 (which may include a 2D thermal barrier layer 124 embedded therein) and a tungsten (W) electrode 906 (which may include a 2D thermal barrier layer 134 embedded therein). Oxygen atoms and oxygen vacancies may be distributed as shown in (A).
  • the memory element 900 upon application of a positive bias, the memory element 900 can be made more conductive. In that state, oxygen atoms migrate to the electrode 906, while vacancies remain throughout the layer 904. Referring to (C) of Figure 9, upon application of a negative bias, the memory element can be made less conductive. That that state, oxygen atoms are distributed more evenly throughout layer 904. Accordingly, in an embodiment, effective composition (e.g., the location of oxygen atoms versus vacancies) of a conductive oxide layer is modified to change resistance of a memory element. In a specific embodiment, an applied electrical field, which drives such compositional change, is tuned to values approximately in the range of I e6-le7 V/cm. Referring again to Figure 9, although surface stage are demonstrated, it is to be appreciated that if filament formation is used, such as described in association with Figures 7A and 7B, vacancies will penetrate the film to a greater extent,
  • one electrode in a memory element including an anionic-based conductive oxide layer is a noble metal based electrode, while the other electrode in is a transition metal for which some of the lower valence oxides are conductive (e.g., to act as an oxygen reservoir). That is, when oxygen atoms migrate to the transition metal oxide, the resulting interfaciai transition metal oxide formed remains conductive.
  • suitable transition metals which form conductive oxides include but are not limited to, W, V, Cr, or Ir.
  • one or both of the electrodes is fabricated from an electro-chromic material.
  • one or both of the electrodes is fabricated from a second, different conductive oxide material.
  • examples of suitable conductive oxides include, but are not limited to: ITO (m 2 0 3 - x Sn0 2 - x ), ln 2 0 3 - x , sub-stoichiometric yttria doped zirconia ( ⁇ 2 0 3 - ⁇ 2- ⁇ ), or Lai-xSr x Gai-yMg y 03-x-o.5(x+y).
  • the conductive oxide layer is composed of a material with two or more metal elements (e.g., as contrasted to common RRAM memories using one metal such as found in binary oxides, such as HfO x or TaOx).
  • the metals used are from adjacent columns of the periodic table.
  • suitable such conductive oxides include, but are not limited to: Y and Zr in Y 2 0 3 - Zr02-x, In and Sn in ImCb-xSnOa-x, or Sr and La in La]-xS x Gai--y gy03.
  • Such materials may be viewed as compositions selected to have aliovalent substitution to significantly increase the number of oxygen vacancies. It is to be appreciated that in some embodiments the change of resistance of such electrode during programming can contribute to the total resistance change.
  • Suitable noble metals include, but are not limited to Pd or Pt.
  • a more complex, yet still all-conductive, stack includes an approximately lOnm Pd first electrode layer, an approximately 3nm ln 2 0 3 . x and/or Sn0 2 - x conductive oxide layer, and a second electrode stack composed of approximately 20nm tungsten/lOnm Pd/lOOnm TiN /55nm W.
  • an RRAM element or device may be a cationic-based conductive oxide memory element.
  • Figure 10 illustrates an operational schematic representing a changing of states for a cationic-based metal-conductive oxide-metal RRAM memory element having one or more 2D thermal barrier layers 124 and/or 134, in accordance with an embodiment of the present invention.
  • memory element 1000 may begin in a more conductive state (1), with a cationic-based conductive oxide layer being in a more conductive state 1004A.
  • An electrical pulse, such as a duration of a positive bias (2) may be applied to provide memory element 1000 in a less conductive state (3), with the cationic-based conductive oxide layer being in a less conductive state 1004B.
  • An electrical pulse such as a duration of a negative bias (4) may be applied to again provide memory element 1000 having the more conductive state (1).
  • electrical pulsing may be used to change resistance of the memory element 1000.
  • Polarity applied is such as to attract active cations of in the memory layer to the intercalation electrode under negative bias.
  • a memory element includes a cationic-based conductive oxide layer sandwiched between two electrodes, one or both of which may include a 2D thermal barrier layer.
  • Resistivity of the cationic-based conductive oxide layer in low field (when device is read) is, in some embodiments, can be as low as found typical of conductive films of metal compounds, e.g. TiAlN.
  • the resistivity for such a layer is approximately in the range of 0.1 Ohm cm - 10 kOhm cm when measured at low field (measured for the specific thickness used in the stack). Resistivity of the film is tuned depending in the memory element size to achieve final resistance value in the range compatible with fast read.
  • Figure 11 illustrates a schematic representation of resistance change in a cationic-based conductive oxide layer induced by changing the concentration of cation vacancies (such as lithium cation vacancies) in the conductive oxide layer, in accordance with an embodiment of the present invention.
  • a memory element 1100 is shown as deposited (A).
  • the memory element includes a cationic-based conductive oxide layer 1104 between a bottom electrode 1 102 (which may include a 2D thermal barrier layer 124 embedded therein) and a top electrode 1 106 (which may include a 2D thermal barrier layer 134 embedded therein).
  • the layer 1104 is a lithium cobalt oxide layer, described in greater details below, and lithium atoms and lithium vacancies are distributed as shown in (A).
  • the memory element 1 100 upon application of a negative bias, the memory element 1 100 can be made more conductive. In that state, lithium atoms migrate to the top electrode 1106, while vacancies remain throughout the layer 1104.
  • the memory element upon application of a positive bias to one of the electrodes, the memory element can be made less conductive. In that state, lithium atoms are distributed more evenly throughout layer 1104, Accordingly, in an embodiment, effective composition (e.g., the location of lithium atoms (or cations) versus vacancies) of a cationic-based conductive oxide layer is modified to change resistance of a memory element, in some embodiments due to stoichiometry-induced Mott transition. In a specific embodiment an applied electrical field, which drives such compositional change during write operation, is tuned to values approximately in the range of Ie6-le7 V/cm.
  • the cationic-based conductive oxide layer 1 104 is composed of a material suitable for cation-based mobility within the layer itself.
  • layer 1 104 of Figure 11 pari (A) is composed of lithium cobalt oxide (LiCo0 2 ).
  • the corresponding layer becomes lithium deficient (e.g., Li 0 . 75 CoO 2 ) when a negative bias is applied and lithium atoms (e.g., as cations) migrate toward electrode 1 106.
  • the corresponding layer becomes lithium rich (e.g., Li> 0 .9 5 CoO 2 ) when a positive bias is applied and lithium atoms (e.g., as cations) migrate away from electrode 106.
  • lithium rich e.g., Li> 0 .9 5 CoO 2
  • compositions with cationic conductivity include, but are not limited to, LiMnO?, Li 4 TiOj.2, LiNi0 2 , LiNb0 3 , Li 3 N:H, LiTiS 2 (all of which are lithium atom or Li + mobility based), Na ?-aiumina (which is sodium atom or Na ":" mobility based), or AgL RbAg 4 I 5 , AgGeAsS 3 (all of which are silver atom or Ag + mobility based).
  • these examples provide materials based on cation mobility or migration, which is typically much faster than anionic-based mobility or migration (e.g., for oxygen atoms or O 2" anions).
  • one electrode (e.g., bottom electrode 1 102) in a memory element including a cationic conductive oxide layer is a noble metal based electrode.
  • suitable noble metals include, but are not limited to palladium (Pd) or platinum (Pt).
  • a memory stack includes a bottom electrode composed of an approximately 10 nanometer thick Pd layer. It is to be understood that use of the terms "bottom” and "top” for electrodes 1102 and 1106 need only be relative and are not necessarily absolute with respect to, e.g., an underlying substrate.
  • the other electrode e.g., top electrode
  • the top electrode in a memory element including a cationic conductive oxide layer is an "intercalation host" for migrating cations.
  • the material of the top electrode is a host in a sense that the material is conductive with or without the presence of the migrating cations and is not substantially altered in the absence or presence of the migrating cations.
  • the top electrode is composed of a material such as, but not limited to, graphite, or metal chalcogenides such as disulfides (e.g., TaS 2 ). Such materials are conductive as well as absorbing of cations such as Li + . This is in contrast to an electrode for an anionic based conductive oxide which may include a metal with a corresponding conductive oxide to accommodate migrating oxygen atoms or anions.
  • FIG. 12 illustrates a schematic of a memory bit cell 1200 which includes a metal-conductive oxide-metal RRAM memory element 1210, in accordance with an embodiment of the present invention.
  • RRAM memory element may be suitable for manufacture on a substrate in common with logic regions of the substrate.
  • the RRAM memory element 1210 may include a first conductive electrode 1212 (which may include a 2D thermal barrier layer 124) with a conductive metal oxide layer 1214 adjacent the first conductive electrode 1212.
  • a second conductive electrode 1216 (which may include a 2D thermal barrier layer 134) is adjacent the conductive metal oxide layer 1214.
  • the second conductive electrode 1216 may be electrically connected to a bit line 1232.
  • the first conductive electrode 1212 may be coupled with a transistor 1234.
  • the transistor 1234 may be coupled with a wordline 1236 and a source line 1238 in a manner that will be understood to those skilled in the art.
  • the memory bit cell 1200 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the memory bit cell 1200. It is to be appreciated that a plurality of the memory bit cells 1200 may be operably connected to one another to form a memory array, wherein the memory array can be incorporated into a non-volatile memory region of a substrate in common with a logic region. It is to be appreciated that the transistor 1234 may be connected to the second conductive electrode 1216 or the first conductive electrode 1212, although only the latter is shown.
  • Figure 13 illustrates a block diagram of an electronic system 1300, in accordance with an embodiment of the present invention.
  • the electronic system 1300 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory.
  • the electronic system 1300 may include a microprocessor 1302 (having a processor 1304 and control unit 1306), a memory device 1308, and an input/output device 1310 (it is to be appreciated that the electronic system 1300 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments).
  • the electronic system 1300 has a set of instructions that define operations which are to be performed on data by the processor 1304, as well as, other transactions between the processor 1304, the memory device 1308, and the input/output device 1310.
  • the control unit 1306 coordinates the operations of the processor 1304, the memory device 1308 and the input/output device 1310 by cycling through a set of operations that cause instructions to be retrieved from the memory device 1308 and executed.
  • the memory device 1308 can include a memory element having a conductive oxide and electrode stack as described in the present description.
  • the memory device 1308 is embedded in the microprocessor 1302, as depicted in Figure 13.
  • the processor 1304, or another component of electronic system 1300 includes an array of RRAM devices, each having one or more 2D thermal barrier layers.
  • FIG 14 illustrates a computing device 1400 in accordance with one embodiment of the invention.
  • the computing device 1400 houses a board 1402.
  • the board 1402 may include a number of components, including but not limited to a processor 1404 and at least one communication chip 1406.
  • the processor 1404 is physically and electrically coupled to the board 1402.
  • the at least one communication chip 1406 is also physically and electrically coupled to the board 1402.
  • the communication chip 1406 is part of the processsor 1404.
  • computing device 1400 may include other components that may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • flash memory e.g., a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna,
  • the communication chip 1406 enables wireless communications for the transfer of data to and from the computing device 1400.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter range wireless
  • Wi-Fi and Bluetooth and a second communication chip 1206 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404.
  • the integrated circuit die of the processor includes one or more arrays, such as RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.
  • the term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1406 also includes an integrated circuit die packaged within the communication chip 1406.
  • the integrated circuit die of the communication chip includes RRAM memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.
  • another component housed within the computing device 1400 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as RRAM: memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.
  • RRAM memory arrays integrated into a logic processor
  • the computing device 1400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device 1400 may be any other electronic device that processes data. Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory.
  • the microelectronic memory may be nonvolatile, wherein the memory can retain stored information even when not powered.
  • One or more embodiments of the present invention relate to the fabrication of RRAM memory arrays integrated into a logic processor.
  • Such arrays may be used in an embedded non-volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memoiy (eDRAM).
  • eDRAM embedded dynamic random access memoiy
  • FIG. 15 illustrates an interposer 1500 that includes one or more embodiments of the invention.
  • the interposer 1500 is an intervening substrate used to bridge a first substrate 1502 to a second substrate 1504.
  • the first substrate 1502 may be, for instance, an integrated circuit die.
  • the second substrate 1 504 may be, for instance, a memoiy module, a computer motherboard, or another integrated circuit die.
  • the purpose of an interposer 1500 is to spread a connection to a wider pitch or to reroute a connection to a different connection.
  • an interposer 1500 may couple an integrated circuit die to a bail grid array (BGA) 1506 that can subsequently be coupled to the second substrate 1504.
  • BGA bail grid array
  • first and second substrates 1502/1504 are attached to opposing sides of the interposer 1500. In other embodiments, the first and second substrates 1502/1504 are attached to the same side of the interposer 500. And in further embodiments, three or more substrates are interconnected by way of the interposer 1500.
  • the interposer 1500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide.
  • the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.
  • the interposer may include metal interconnects 1508 and vias 15 10, including but not limited to through-silicon vias (TSVs) 1512.
  • the interposer 1500 may further include embedded devices 1514, including both passive and active devices.
  • Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices.
  • More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1500.
  • RF radio- frequency
  • embodiments of the invention may be u sed in the fabrication of interposer 1 500.
  • embodiments of the present invention include approaches for fabricating RRAM stacks with two-dimensional (2D) barrier layers, and the resulting structures and devices.
  • a resistive random access memory (RRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate.
  • An RRAM: element is disposed on the conductive interconnect.
  • the RRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect.
  • the first electrode layer has a two-dimensional (2D) thermal barrier layer embedded therein.
  • a resistance switching layer is disposed on the first electrode layer but not in contact with the 2D thermal barrier layer of the first electrode layer.
  • a second electrode layer is disposed above the resistance switching layer.
  • the second electrode layer has a second 2D thermal barrier layer embedded therein.
  • the resistance switching layer is not in contact with the second 2D thermal barrier layer of the second electrode layer.
  • the 2D thermal barrier layer of the first electrode layer and the second 2D thermal barrier layer of the second electrode layer comprises a same material.
  • the 2D thermal barrier layer of the first electrode layer is a different material than the second 2D thermal barrier layer of the second electrode layer.
  • the 2D thermal barrier layer includes a material selected from the group consisting of graphene, silicene, M0S2, and WS2.
  • the 2D thermal barrier layer is between I and 3 atomic layers thick.
  • the 2D thermal barrier layer is spaced apart from the resistance switching layer by a distance of less than I nanometer.
  • the RRAM element further includes an oxygen exchange layer (OEL) disposed between the resistance switching layer and the second electrode layer.
  • OEL oxygen exchange layer
  • the RRAM device further includes a dielectric sidewall spacer laterally adjacent to and in contact with sidewalls of the second electrode layer, the resistance switching layer, the 2D thermal barrier layer, and the first electrode layer of the RRAM: element.
  • the conductive interconnect is a conductive line further coupled to a second RRAM element.
  • the conductive interconnect is a conductive via.
  • a resistive random access memory (RRAM) device in an embodiment, includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate.
  • An RRAM element is disposed on the conductive interconnect.
  • the RRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect.
  • a resistance switching layer is disposed on the first electrode layer.
  • a second electrode layer is disposed above the resistance switching layer.
  • the second electrode layer has a two-dimensional (2D) thermal barrier layer embedded therein. The 2D thermal barrier layer is not in contact with the resistance switching layer.
  • the 2D thermal barrier layer includes a material selected from the group consisting of graphene, silicene, MoS 2 , and WS?,
  • the 2D thermal barrier layer is between 1 and 3 atomic layers thick.
  • the 2D thermal barrier layer is spaced apart from the resistance switching layer by a distance of less than 1 nanometer.
  • the RRAM element further includes an oxygen exchange layer (OEL) disposed between the resistance switching layer and the second electrode layer.
  • OEL oxygen exchange layer
  • the 2D thermal barrier layer is not in contact with the OEL.
  • the second electrode layer is disposed directly on the resistance switching layer.
  • the RRAM device further includes a dielectric sidewall spacer laterally adjacent to and in contact with sidewails of the second electrode layer, the 2D thermal barrier layer, the resistance switching layer, and the first electrode layer of the RRAM element.
  • the conductive interconnect is a conductive line further coupled to a second RRAIVi element.
  • the conductive interconnect is a conductive via.
  • a method of fabricating a resistive random access memory (RRAM) device includes forming a conductive interconnect in an inter-layer dielectric (ILD) layer formed above a substrate.
  • a first portion of a first electrode layer is formed on the conductive interconnect.
  • a first two-dimensional (2D) thermal barrier layer is formed on the first portion of the first electrode layer.
  • a second portion of the first electrode layer is formed on the first 2D thermal barrier layer.
  • a resistance switching layer is formed on the second portion of the first electrode layer.
  • a first portion of a second electrode layer is formed above the resistance switching layer.
  • a second 2D thermal barrier layer is formed on the first portion of the second electrode layer.
  • a second portion of the second electrode layer is formed on the second 2D thermal barrier layer.
  • forming the first 2D thermal barrier layer and forming the second 2D thermal barrier layer includes using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • materials of the first electrode layer, the first 2D thermal barrier layer, the resistance switching layer, the second electrode layer and the second 2D thermal barrier layer are patterned to form an RRAM element of the RRAM device using a subtractive etching process.
  • the method further includes forming a dielectric sidewall spacer laterally adjacent to and in contact with sidewalls of the first electrode layer, the first 2D thermal barrier layer, the resistance switching layer, the second electrode layer and the second 2D thermal barrier layer.
  • materials of the first electrode layer, the first 2D thermal barrier layer, the resistance switching layer, the second electrode layer and the second 2D thermal barrier layer are formed in an opening of a second ILD layer formed above the ELD layer, the opening exposing at least a portion of an uppermost surface of the conductive interconnect.

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  • Semiconductor Memories (AREA)

Abstract

L'invention concerne des approches pour fabriquer des piles RRAM à couches de barrière thermique bidimensionnelles, et structures et dispositifs résultants. Dans un exemple, un dispositif de mémoire vive résistive (RRAM) comprend une interconnexion conductrice disposée dans une couche diélectrique intercouche (ILD) disposée au-dessus d'un substrat. Un élément RRAM est placé sur l'interconnexion conductrice. L'élément de RRAM comprend une première couche d'électrode disposée sur la surface supérieure de l'interconnexion conductrice. La première couche d'électrode possède une couche de barrière thermique bidimensionnelle (2D) intégrée dans celle-ci. Une couche à commutation de résistance est disposée sur la première couche d'électrode mais sans contact avec la couche de barrière thermique 2D de la première couche d'électrode. Une deuxième couche d'électrode () est disposée sur la couche à commutation de résistance.
PCT/US2016/040301 2016-06-30 2016-06-30 Dispositifs de rram à couches de barrière thermique bidimensionnelles Ceased WO2018004587A1 (fr)

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WO2020256777A1 (fr) * 2019-06-19 2020-12-24 Western Digital Technologies, Inc. Cellule de mémoire mram à couple de transfert de spin à barrières thermiques empilées
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US11374058B2 (en) 2018-09-04 2022-06-28 Imec Vzw Memory selector and memory device including same
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