[go: up one dir, main page]

WO2018006446A1 - 薄膜晶体管阵列基板及其制造方法 - Google Patents

薄膜晶体管阵列基板及其制造方法 Download PDF

Info

Publication number
WO2018006446A1
WO2018006446A1 PCT/CN2016/090845 CN2016090845W WO2018006446A1 WO 2018006446 A1 WO2018006446 A1 WO 2018006446A1 CN 2016090845 W CN2016090845 W CN 2016090845W WO 2018006446 A1 WO2018006446 A1 WO 2018006446A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
passivation layer
pattern
passivation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/090845
Other languages
English (en)
French (fr)
Inventor
卢马才
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/300,247 priority Critical patent/US10186531B2/en
Publication of WO2018006446A1 publication Critical patent/WO2018006446A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes

Definitions

  • the present invention relates to the field of manufacturing thin film transistors, and more particularly to a thin film transistor array substrate and a method of fabricating the same.
  • the Fringe Field Switching (FFS) mode thin film transistor has a wide viewing angle and transmittance, and is generally widely used in the fabrication process of a thin film transistor tube array substrate, which is usually required to be used 6-8 times.
  • FFS Fringe Field Switching
  • the production process is complicated and the manufacturing cost is increased accordingly.
  • the invention provides a thin film transistor array substrate and a manufacturing method thereof, which can reduce the number of exposures, simplify the manufacturing process and reduce the cost.
  • the manufacturing method of the thin film transistor of the present invention includes:
  • the second passivation layer, the organic insulating layer, the first passivation layer, and a portion of the gate insulating layer are etched by the etching process according to the pixel electrode layer pattern, the common electrode layer pattern, and the cured region pattern on the photoresist layer. Defining a pixel electrode layer pattern, a common electrode layer pattern, and a cured layer pattern; wherein the organic insulating layer has a region exposing the second passivation layer, and opposite sides of each of the pattern regions on the second passivation layer are protruded Covering both sides of the organic insulating layer;
  • a common electrode layer is formed on the organic insulating layer.
  • the step of forming an organic insulating layer on the first passivation layer includes forming a first via hole and a second via hole on the organic insulating layer, the first via hole and the second via hole exposing portion first passivation
  • the first via is used to connect to the drain and the first via is provided with a pixel electrode, and the second via is used to communicate with the gate line.
  • Defining the pixel electrode layer pattern, the common electrode layer pattern, and the solidified layer pattern includes etching the second passivation layer, the organic insulating layer, the first passivation layer, and a portion of the gate insulating layer using a first dry etching gas, and adding The second dry etching gas and the first etching gas etch a region exposing the organic insulating layer of the second passivation layer.
  • the second etching gas is the same as the first etching gas or is oxygen.
  • Defining the pixel electrode layer pattern, the common electrode layer pattern, and the solidified layer pattern includes replenishing the organic insulating layer using oxygen.
  • the first passivation layer and the second passivation layer are formed by chemical vapor deposition.
  • each electrode of the pixel electrode layer has a gap with both sides of the organic insulating layer covered by the second passivation layer.
  • the first passivation layer and the second passivation layer material are SiNx or SiO.
  • the present invention also provides a thin film transistor array substrate, comprising at least a substrate, forming a gate insulating layer with the gate of the substrate, a gate line, and a gate electrode covering the gate and the gate line substrate;
  • a first passivation layer formed on the gate insulating layer, the active layer, the source and the drain of the substrate;
  • each pattern region on the second passivation layer protrude from both sides of the organic insulating layer covered by the second passivation layer.
  • each electrode of the pixel electrode layer has a gap with both sides of the organic insulating layer covered by the second passivation layer.
  • the pixel electrode layer and the common electrode layer of the thin film transistor manufacturing method of the present invention are formed by deposition, and the second passivation layer and the organic insulating layer for forming the pixel electrode layer and the common electrode layer are formed by one etching, so that the entire thin film transistor is fabricated.
  • the second passivation layer and the organic insulating layer for forming the pixel electrode layer and the common electrode layer are formed by one etching, so that the entire thin film transistor is fabricated.
  • at least one patterning process is saved, the processing steps of the thin film transistor are simplified, and the manufacturing cost of the thin film transistor is reduced.
  • FIG. 1 is a flow chart of a method of fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • FIGS. 2 to 9 are schematic views of a thin film transistor in each manufacturing process of a thin film transistor according to a preferred embodiment of the present invention.
  • FIG. 1 is a flow chart of a method for fabricating a thin film transistor according to a preferred embodiment of the present invention.
  • the manufacturing method of the thin film transistor (TFT) includes the following steps.
  • Step S1 forming a gate electrode, a gate line, and a gate insulating layer covering the gate, the gate line, and the substrate on the substrate.
  • a first metal layer (not shown) is formed on a surface of the substrate 10, and the first metal layer is formed to include the gate electrode 11 and the gate line 111 by a patterning process.
  • a pattern of the first metal layer selected from the group consisting of copper, tungsten, chromium, aluminum, and combinations thereof.
  • the gate electrode 11 is formed on the first metal layer patterning process by a prior art patterning process such as photoresisting, exposure, and development.
  • a gate insulating layer 12 is formed on the gate electrode 11, the gate line 111, and the substrate 10.
  • the gate insulating layer 12 covers the surface of the substrate 10 and the gate electrode 11.
  • the gate insulating layer 12 is formed on a surface of the substrate 10 not covering the first metal layer, and on the gate electrode 11 and the gate line 111.
  • the material of the gate insulating layer 12 is selected from one of silicon oxide, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof.
  • step S2 an active layer 13, a source 14 and a drain 15 are formed on the gate insulating layer 12.
  • an oxide semiconductor layer and a second metal layer covering the semiconductor layer are formed on the gate insulating layer 12, and the oxide semiconductor layer is formed into an active layer 13, a source 14 and a drain 15 by a patterning process. That is, it can be formed here using a reticle process employed in prior art processes.
  • the active layer can be formed by dividing into two photomasks, then forming a second metal layer on the active layer 13 and the exposed gate insulating layer 12, and forming the thin film transistor by patterning the second metal layer.
  • the source 14 and the drain 15 are both connected to the active layer 13 .
  • the material of the second metal layer is selected from one of copper, tungsten, chromium, aluminum, and combinations thereof.
  • step S3 depositing a first passivation layer 16 on the gate insulating layer 12, the active layer 13, the source 14 and the drain 15 of the substrate 10; mainly formed by chemical vapor deposition.
  • step S4 forming an organic insulating layer 17 on the first passivation layer 16, the organic insulating layer 17 exposing a portion of the first passivation layer 16; mainly comprising forming a pattern on the organic insulating layer 17 by a patterning process a via 171 and a second via 172, the first via 171 and the second via 172 exposing a portion of the first passivation layer 16 for connecting to the drain 15 and the first via
  • a pixel electrode is provided in 171, and a second via hole 172 is used to communicate with the gate line 111.
  • step S5 depositing on the organic insulating layer 17 and the first passivation layer 16
  • the second passivation layer 18 is formed by chemical vapor deposition, and the material is SiNx or SiO, and may be other organic or inorganic materials.
  • the second passivation layer 18 covers the hole walls of the first via 171 and the second via 172.
  • step S6 coating the photoresist layer 19 on the second passivation layer 18, and patterning the photoresist layer 19 to define a pixel electrode layer pattern, a common electrode layer pattern, and a surface opposite to the active layer. Cured layer pattern. Specifically, a plurality of pattern regions broken through the notches are formed on the photoresist layer 19, and include a plurality of first notches 191, a first pattern region 192 separated by a plurality of notches 191, and the first via holes. The second notch 193 penetrating through the 171 and the third notch 194 penetrating the second via hole 172. A side of the second notch 193 away from the first pattern region 192 is a cured layer pattern 195. The side of the third notch 194 away from the first pattern region 192 is also the first pattern region 192.
  • step S7 the second passivation layer 18, the organic insulating layer 17, and the first step are performed by an etching process according to the pixel electrode layer pattern, the common electrode layer pattern, and the cured region pattern on the photoresist layer 19.
  • the passivation layer 16 and a portion of the gate insulating layer 12 define a pixel electrode layer pattern, a common electrode layer pattern, and a cured layer pattern.
  • the organic insulating layer 17 has a region exposing the second passivation layer 18, and opposite sides of each pattern region on the second passivation layer 18 protrude from both sides of the organic insulating layer 17 covered by the same .
  • the region of the organic insulating layer 17 having the exposed second passivation layer 18 is exposed through the first notch 191, and the first notch extends into the portion of the organic insulating layer 17.
  • the first pattern region 192 is covered by the pattern region 181 of the second passivation layer 18 .
  • each of the pattern regions 181 on the second passivation layer 18 protrude from both sides of the organic insulating layer 17 covered by the same, that is, the machine insulation pattern separated by the first notches 191
  • the vertically falling conductive layer is layered on each of the pattern regions 181 on the second passivation layer 18, and the organic insulation
  • the layer 17 exposes the region of the second passivation layer 18 through the first gap, and the two sides of the machine insulating pattern 171 separated by the first notch 191 are not stained with the conductive layer, and at the same time, due to the relative two of each pattern region 181
  • the side 182 is convex, and the conductive layer in the region where the organic insulating layer 17 has the exposed second passivation layer 18 is not in contact with both sides of the machine insulating pattern 171.
  • the second passivation layer 18, the organic insulating layer 17, the first passivation layer 16 and a portion of the gate insulating layer 12 are etched using a first dry etching gas, and the second dry etching gas is added.
  • the first etching gas etches a region exposing the organic insulating layer 17 of the second passivation layer 18, that is, a region of the machine insulating pattern 171 spaced apart by the first notch 191, so that both sides of the machine insulating pattern 171 are etched
  • the amount of engraving is increased, and thus the opposite sides 182 of each of the pattern regions 181 on the second passivation layer 18 are protruded from both sides of the machine insulating pattern 171 covered by the second passivation layer 18 .
  • the second etching gas is the same as the first etching gas or is oxygen. In other embodiments, both sides of the machine insulating pattern 171 of the organic insulating layer 17 may be additionally etched using oxygen.
  • Step S8 The photoresist layer 19 is peeled off.
  • step S9 depositing a conductive layer material on the defined second passivation layer 18 and a region of the organic insulating layer 17 exposing the second passivation layer 18, the conductive material being on the second passivation layer 18
  • the pixel electrode layer 20 is formed thereon, including a portion inside the first via hole; and the common electrode layer 21 is formed on the organic insulating layer 17 exposing the organic insulating layer 17.
  • each electrode of the pixel electrode layer 20 and the two sides of the organic insulating layer covered by the second passivation layer 18, that is, both sides of the machine insulating pattern 171 have a gap 172, which can prevent pixels The electrode is short-circuited to the common electrode.
  • a vertically falling conductive layer is layered on each of the pattern regions 181 on the second passivation layer 18, and the organic insulating layer 17 passes through the first gap.
  • the regions of the second passivation layer 18 are exposed, and the sides of the machine insulating pattern 171 separated by the first notches 191 are not stained with conductive layers, and at the same time, since the opposite sides 182 of each of the pattern regions 181 are convex,
  • the organic insulating layer 17 has a conductive layer in a region where the second passivation layer 18 is exposed and is not in contact with both sides of the machine insulating pattern 171. This process saves the mask step and simplifies the processing.
  • the pixel electrode layer and the common electrode layer of the thin film transistor manufacturing method of the present invention are formed by deposition, and the second passivation layer 18 and the organic insulating layer for forming the pixel electrode layer and the common electrode layer are formed by one etching, and thus the entire thin film transistor Only four masks are used in the manufacturing process, which reduces the number of mask processes and saves production costs.
  • the present invention provides a thin film transistor including at least a substrate 10, a gate electrode 11 of the substrate 10, a gate line 111, and a gate insulating layer 12 covering the gate electrode 11 and the gate line 111 substrate.
  • a first passivation layer 16 is formed on the gate insulating layer 12, the active layer 13, the source 14 and the drain 15 of the substrate 10.
  • the insulating layer 17 includes a region exposing the second passivation layer 18; specifically, exposed through the first via and the second via.
  • the common electrode layer 21 is formed on the pixel electrode layer 20 formed on the second passivation layer and on the organic insulating layer 17 on which the second passivation layer is exposed.
  • each pattern region on the second passivation layer 18 protrude from both sides of the organic insulating layer 17 covered by the same.
  • Each of the electrodes of the pixel electrode layer 20 has a gap with both sides of the organic insulating layer covered by the second passivation layer.
  • the present invention also provides a method for fabricating a thin film transistor for the above two embodiments.
  • the patterning process refers to a patterning process, which may include a photolithography process, or The photolithography process and the etching step are included, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.; the photolithography process refers to the use of a photoresist, including film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the display device formed by the method for manufacturing a thin film transistor according to the embodiment of the present invention may be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED television, an electronic paper, a digital photo frame, a mobile phone, or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管的制造方法，其包括：在基板（10）的栅极绝缘层（12）、有源层（13）、源极（14）和漏极（15）上依次沉积形成第一钝化层（16）、有机绝缘层（17）及第二钝化层（18）；在第二钝化层（18）上涂布光阻层（19），并对光阻层（19）进行构图工艺以定义像素电极层图案、公共电极层图案及与有源层相对的固化层图案；通过蚀刻工艺在所述第二钝化层（18）、有机绝缘层（17）、第一钝化层（16）及部分栅极绝缘层（12），定义像素电极层图案、公共电极层图案及固化层图案，剥离光阻层（19）；在被定义的第二钝化（18）层上形成公共电极层（21），于露出第二钝化层（18）的有机绝缘层（17）上形成像素电极层（20）。

Description

薄膜晶体管阵列基板及其制造方法
本发明要求2016年7月5日递交的发明名称为“薄膜晶体管阵列基板及其制造方法”的申请号201610523648.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及薄膜晶体管的制造领域，尤其涉及一种薄膜晶体管阵列基板及其制造方法。
背景技术
现有技术中的(Fringe Field Switching简称FFS)模式的薄膜晶体管拥有较大视角及透过率目前广泛应用，通常在薄膜晶体管管阵列基板制作过程通常需要6-8次mask(曝光)，分别用于形成栅线及栅极，有源层，蚀刻阻挡层，源漏极，钝化层、电极及过孔等，生产工艺要复杂，制作成本相应增加。
发明内容
本发明提供一种薄膜晶体管阵列基板及制造方法，能减少曝光次数，够简化制造工艺，降低成本。
本发明所述薄膜晶体管的制造方法包括：
在基板上形成栅极、栅极线及覆盖栅极、栅极线基板的栅极绝缘层；
在所述栅极绝缘层上形成有源层、源极和漏极；
在所述基板的栅极绝缘层、有源层、源极和漏极上沉积形成第一钝化层；
在第一钝化层上形成有机绝缘层，所述有机绝缘层露出部分第一钝化层；
在所述有机绝缘层及第一钝化层上沉积形成第二钝化层；
在第二钝化层上涂布光阻层，并对光阻层进行构图工艺以定义像素电极层图案、公共电极层图案及与有源层相对的固化层图案；
根据所述光阻层上的像素电极层图案、公共电极层图案及固化区域图案通过蚀刻工艺在所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层， 定义像素电极层图案、公共电极层图案及固化层图案；其中，有机绝缘层具有露出第二钝化层的区域，所述第二钝化层上的每一图案区域的相对两侧凸出被其覆盖的所述有机绝缘层的两侧；
剥离光阻层；
在被定义的所述第二钝化层上以及有机绝缘层的露出第二钝化层的区域沉积导电层材料，导电材料于有机绝缘层上形成像素电极层，于露出第二钝化层的有机绝缘层上形成公共电极层。
其中，所述在第一钝化层上形成有机绝缘层步骤包括在有机绝缘层上形成第一过孔与第二过孔，所述第一过孔与第二过孔露出部分第一钝化层，第一过孔用于与漏极连接并且第一过孔内设有像素电极，第二过孔用于与栅极线连通。
其中，步骤根据所述光阻层上的像素电极层图案、公共电极层图案及固化区域图案通过蚀刻所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层，定义像素电极层图案、公共电极层图案及固化层图案包括使用第一干蚀刻气体对所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层进行蚀刻，以及增加第二干蚀刻气体与第一蚀刻气体蚀刻露出第二钝化层的有机绝缘层的区域。
其中，第二蚀刻气体与第一蚀刻气体相同或者为氧气。
其中，步骤根据所述光阻层上的像素电极层图案、公共电极层图案及固化区域图案通过蚀刻所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层，定义像素电极层图案、公共电极层图案及固化层图案包括使用氧气补充蚀刻所述有机绝缘层。
其中，所述第一钝化层与第二钝化层通过化学气相沉淀方式形成。
其中，所述像素电极层的每一电极与被所述第二钝化层覆盖的所述有机绝缘层的两侧具有间隙。
其中，所述第一钝化层与第二钝化层材料为SiNx或SiO。
本发明还提供一种薄膜晶体管阵列基板，至少包括基板，形成与所述基板的栅极、栅极线及覆盖栅极、栅极线基板的栅极绝缘层；
形成于所述栅极绝缘层上的有源层、源极和漏极；
形成于所述基板的栅极绝缘层、有源层、源极和漏极上的第一钝化层；
形成与第一钝化层上的有机绝缘层及第二钝化层，所述有机绝缘层包括露出第二钝化层的区域；
形成于第二钝化层的像素电极层以及形成于露出第二钝化层的有机绝缘层上形成公共电极层；
其中，所述第二钝化层上的每一图案区域的相对两侧凸出被其覆盖的所述有机绝缘层的两侧。
其中，所述像素电极层的每一电极与被所述第二钝化层覆盖的所述有机绝缘层的两侧具有间隙。
本发明所述的薄膜晶体管制造方法的像素电极层与公共电极层通过沉积形成，供形成像素电极层与公共电极层的第二钝化层及有机绝缘层通过一次蚀刻形成，因此整个薄膜晶体管制造相对与现有技术节省了至少一次构图工艺，简化薄膜晶体管的加工工艺步骤，降低薄膜晶体管的制作成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管的制造方法的流程图。
图2至图9为本发明较佳实施方式的薄膜晶体管的各个制造流程中薄膜晶体管的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，其为本发明一较佳实施方式的薄膜晶体管的制造方法的流程 图。所述薄膜晶体管(thin film transistor，TFT)的制造方法包括如下步骤。
步骤S1：在基板上形成栅极、栅极线及覆盖栅极、栅极线、基板的栅极绝缘层。
请参阅图2，具体包括，步骤S11，在所述基板10的一表面上上形成第一金属层(图未示)，通过构图工艺使第一金属层形成包括栅极11及栅极线111的图案；所述第一金属层的材质选自铜、钨、铬、铝及其组合的其中之一。本实施方式中通过现有技术的涂光阻、曝光、显影等构图工艺对所述第一金属层构图工艺形成栅极11。
步骤S12，在栅极11、栅极线111、基板10上形成栅极绝缘层12，请参阅图3，栅极绝缘层12覆盖所述基板10的表面及所述栅极11。具体的在所述基板10未覆盖所述第一金属层的表面及所述栅极11、栅极线111上形成所述栅极绝缘层12。所述栅极绝缘层12的材质选择氧化硅、氮化硅层，氮氧化硅层及其组合的其中之一。
请参阅图3，步骤S2：在所述栅极绝缘层12上形成有源层13、源极14和漏极15。具体为，在所述栅极绝缘层12上形成氧化物半导体层及覆盖半导体层的第二金属层，通过构图工艺使氧化物半导体层形成有源层13、源极14和漏极15，也就是说此处可以使用现有技术工艺采用的一道光罩工艺形成。当然也可以分为两道光罩先形成有源层，然后在有源层13及裸露的栅极绝缘层12上形成第二金属层，通过构图工艺所述第二金属层，形成所述薄膜晶体管的源极14和漏极15，其中，所述源极14和漏极15均与所述有源层13连接。所述第二金属层的材质选自铜、钨、铬、铝及其组合的其中之一。
请参阅图4，步骤S3：在所述基板10的栅极绝缘层12、有源层13、源极14和漏极15上沉积形成第一钝化层16；主要通过化学气相沉淀方式形成。
请参阅图5，步骤S4：在第一钝化层16上形成有机绝缘层17，所述有机绝缘层17露出部分第一钝化层16；主要包括通过构图工艺在有机绝缘层17上形成第一过孔171与第二过孔172，所述第一过孔171与第二过孔172露出部分第一钝化层16，第一过孔171用于与漏极15连接并且第一过孔171内设有像素电极，第二过孔172用于与栅极线111连通。
请参阅图6，步骤S5：在所述有机绝缘层17及第一钝化层16上沉积形成 第二钝化层18。第二钝化层18通过化学气相沉淀方式形成，材料为SiNx或SiO，也可以为其他有机物或无机物材料。所述第二钝化层18覆盖所述第一过孔171与第二过孔172的孔壁。
请参阅图7，步骤S6：在第二钝化层18上涂布光阻层19，并对光阻层19进行构图工艺以定义像素电极层图案、公共电极层图案及与有源层相对的固化层图案。具体的，在所述光阻层19上形成多个通过缺口断开的图案区域，包括多个第一缺口191、通过多个缺口191间隔的第一图案区域192，与所述第一过孔171贯通的第二缺口193以及与第二过孔172贯通的第三缺口194。所述第二缺口193远离第一图案区域192的一侧为固化层图案195。第三缺口194远离第一图案区域192的一侧也为第一图案区域192。
请参阅图8，步骤S7：根据所述光阻层19上的像素电极层图案、公共电极层图案及固化区域图案通过蚀刻工艺在所述第二钝化层18、有机绝缘层17、第一钝化层16及部分栅极绝缘层12，定义像素电极层图案、公共电极层图案及固化层图案。其中，有机绝缘层17具有露出第二钝化层18的区域，所述第二钝化层18上的每一图案区域的相对两侧凸出被其覆盖的所述有机绝缘层17的两侧。具体的，有机绝缘层17具有露出第二钝化层18的区域是通过第一缺口191露出的，并且第一缺口延伸至部分有机绝缘层17内。所述第一图案区域192覆盖的为第二钝化层18的图案区域181。所述第二钝化层18上的每一图案区域181的相对两侧182凸出被其覆盖的所述有机绝缘层17的两侧，也就是说通过第一缺口191间隔开的机绝缘图案171的两侧，如此在第二钝化层18上沉积导电层时，垂直落下来的导电层会分层形成于所述第二钝化层18上的每一图案区域181上，以及有机绝缘层17通过第一缺口露出第二钝化层18的区域，而被第一缺口191间隔开的机绝缘图案171的两侧不会沾上导电层，同时，由于每一图案区域181的相对两侧182凸出，在有机绝缘层17具有露出第二钝化层18的区域内的导电层不与机绝缘图案171的两侧接触。
本步骤中，包括使用第一干蚀刻气体对所述第二钝化层18、有机绝缘层17、第一钝化层16及部分栅极绝缘层12进行蚀刻，以及增加第二干蚀刻气体与第一蚀刻气体蚀刻露出第二钝化层18的有机绝缘层17的区域，也就是通过第一缺口191间隔开的机绝缘图案171的区域，使机绝缘图案171的两侧被蚀 刻量增多，进而实现所述第二钝化层18上的每一图案区域181的相对两侧182凸出被其覆盖的所述机绝缘图案171的两侧。本实施例中，第二蚀刻气体与第一蚀刻气体相同或者为氧气。其它实施方式中还可以使用氧气补充蚀刻所述有机绝缘层17的所述机绝缘图案171的两侧。
步骤S8：剥离光阻层19。
请参阅图9，步骤S9：在被定义的所述第二钝化层18上以及有机绝缘层17的露出第二钝化层18的区域沉积导电层材料，导电材料于第二钝化层18上形成像素电极层20，包括第一过孔内的部分；于露出有机绝缘层17的有机绝缘层17上形成公共电极层21。其中，所述像素电极层20的每一电极与被所述第二钝化层18覆盖的所述有机绝缘层的两侧，也就是说机绝缘图案171的两侧具有间隙172，可以防止像素电极与公共电极接触短路。在第二钝化层18上沉积导电层时，垂直落下来的导电层会分层形成于所述第二钝化层18上的每一图案区域181上，以及有机绝缘层17通过第一缺口露出第二钝化层18的区域，而被第一缺口191间隔开的机绝缘图案171的两侧不会沾上导电层，同时，由于每一图案区域181的相对两侧182凸出，在有机绝缘层17具有露出第二钝化层18的区域内的导电层不与机绝缘图案171的两侧接触，此工艺节省了光罩步骤，简化了加工过程。
本发明所述的薄膜晶体管制造方法的像素电极层与公共电极层通过沉积形成，供形成像素电极层与公共电极层的第二钝化层18及有机绝缘层通过一次蚀刻形成，因此整个薄膜晶体管制造只用了四道光罩，减少了光罩工艺次数，可以节约制作成本。
本发明提供一种薄膜晶体管，所述薄膜晶体管至少包括基板10，形成所述基板10的栅极11、栅极线111及覆盖栅极11、栅极线111基板的栅极绝缘层12。
形成于所述栅极绝缘层12的有源层13及与有源层13连接的源极14和漏极15。
形成于所述基板10的栅极绝缘层12、有源层13、源极14和漏极15上的第一钝化层16。
依次形成与第一钝化层16上的有机绝缘层17及第二钝化层18，所述有 机绝缘层17包括露出第二钝化层18的区域；具体通过第一过孔及第二过孔露出。
形成于第二钝化层上的像素电极层20以及形成于露出有第二钝化层的有机绝缘层17上形成公共电极层21。
其中，所述第二钝化层18上的每一图案区域的相对两侧凸出被其覆盖的所述有机绝缘层17的两侧。所述像素电极层20的每一电极与被所述第二钝化层覆盖的所述有机绝缘层的两侧具有间隙。
本发明针对上述两种实施例还提供了薄膜晶体管的制造方法，在阐述具体制备方法之前，应该理解，在本发明中，所述构图工艺即是指构图工艺，可包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影，等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
通过本发明实施例薄膜晶体管的制造方法形成的显示器件，可以为：液晶面板、液晶电视、液晶显示器、OLED面板、OLED电视、电子纸、数码相框、手机等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种薄膜晶体管的制造方法，其中，所述薄膜晶体管的制造方法包括：
    在基板上形成栅极、栅极线及覆盖栅极、栅极线基板的栅极绝缘层；
    在所述栅极绝缘层上形成有源层、源极和漏极；
    在所述基板的栅极绝缘层、有源层、源极和漏极上沉积形成第一钝化层；
    在第一钝化层上形成有机绝缘层，所述有机绝缘层露出部分第一钝化层；
    在所述有机绝缘层及第一钝化层上沉积形成第二钝化层；
    在第二钝化层上涂布光阻层，并对光阻层进行构图工艺以定义像素电极层图案、公共电极层图案及与有源层相对的固化层图案；
    根据所述光阻层上的像素电极层图案、公共电极层图案及固化区域图案通过蚀刻工艺在所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层，定义像素电极层图案、公共电极层图案及固化层图案；其中，有机绝缘层具有露出第二钝化层的区域，所述第二钝化层上的每一图案区域的相对两侧凸出被其覆盖的所述有机绝缘层的两侧；
    剥离光阻层；
    在被定义的所述第二钝化层上以及有机绝缘层的露出第二钝化层的区域沉积导电层材料，导电材料于有机绝缘层上形成公共电极层，于露出第二钝化层的有机绝缘层上形成像素电极层。
  2. 如权利要求1所述的薄膜晶体管的制造方法，其中，所述在第一钝化层上形成有机绝缘层步骤包括在有机绝缘层上形成第一过孔与第二过孔，所述第一过孔与第二过孔露出部分第一钝化层，第一过孔用于与漏极连接并且第一过孔内设有像素电极，第二过孔用于与栅极线连通。
  3. 如权利要求1所述的薄膜晶体管的制造方法，其中，步骤根据所述光阻层上的像素电极层图案、公共电极层图案及固化区域图案通过蚀刻所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层，定义像素电极层图案、公共电极层图案及固化层图案包括使用第一干蚀刻气体对所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层进行蚀刻，以及增加第二干蚀刻气体与第一蚀刻气体蚀刻露出第二钝化层的有机绝缘层的区域。
  4. 如权利要求3所述的薄膜晶体管的制造方法，其中，第二蚀刻气体与第一蚀刻气体相同或者为氧气。
  5. 如权利要求1所述的薄膜晶体管的制造方法，其中，步骤根据所述光阻层上的像素电极层图案、公共电极层图案及固化区域图案通过蚀刻所述第二钝化层、有机绝缘层、第一钝化层及部分栅极绝缘层，定义像素电极层图案、公共电极层图案及固化层图案包括使用氧气补充蚀刻所述有机绝缘层。
  6. 如权利要求1所述的薄膜晶体管的制造方法，其中，所述第一钝化层与第二钝化层通过化学气相沉淀方式形成。
  7. 如权利要求1所述的薄膜晶体管的制造方法，其中，所述像素电极层的每一电极与被所述第二钝化层覆盖的所述有机绝缘层的两侧具有间隙。
  8. 如权利要求1所述的薄膜晶体管的制造方法，其中，所述第一钝化层与第二钝化层材料为SiNx或SiO。
  9. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管至少包括基板，形成与所述基板的栅极、栅极线及覆盖栅极、栅极线基板的栅极绝缘层；
    形成于所述栅极绝缘层上的有源层、源极和漏极；
    形成于所述基板的栅极绝缘层、有源层、源极和漏极上的第一钝化层；
    形成与第一钝化层上的有机绝缘层及第二钝化层，所述有机绝缘层包括露出第二钝化层的区域；
    形成于第二钝化层的像素电极层以及形成于露出第二钝化层的有机绝缘层上形成公共电极层；
    其中，所述第二钝化层上的每一图案区域的相对两侧凸出被其覆盖的所述有机绝缘层的两侧。
  10. 如权利要求9所述的薄膜晶体管阵列基板，其中，所述像素电极层的每一电极与被所述第二钝化层覆盖的所述有机绝缘层的两侧具有间隙。
PCT/CN2016/090845 2016-07-05 2016-07-21 薄膜晶体管阵列基板及其制造方法 Ceased WO2018006446A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/300,247 US10186531B2 (en) 2016-07-05 2016-07-21 Thin film transistor array substrate and method of manufacturing thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610523648.6A CN106129063B (zh) 2016-07-05 2016-07-05 薄膜晶体管阵列基板及其制造方法
CN201610523648.6 2016-07-05

Publications (1)

Publication Number Publication Date
WO2018006446A1 true WO2018006446A1 (zh) 2018-01-11

Family

ID=57469498

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/090845 Ceased WO2018006446A1 (zh) 2016-07-05 2016-07-21 薄膜晶体管阵列基板及其制造方法

Country Status (3)

Country Link
US (1) US10186531B2 (zh)
CN (1) CN106129063B (zh)
WO (1) WO2018006446A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785382A (zh) * 2017-12-05 2018-03-09 深圳市华星光电半导体显示技术有限公司 阵列基板的制作方法及显示装置的制作方法
CN108183089B (zh) * 2017-12-28 2019-12-31 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法
CN109616496B (zh) * 2018-11-15 2020-08-11 武汉华星光电半导体显示技术有限公司 Oled触控显示屏的制作方法
CN110600425B (zh) * 2019-08-20 2023-07-04 武汉华星光电技术有限公司 阵列基板的制备方法及阵列基板
CN112864090B (zh) * 2021-01-19 2023-01-24 Tcl华星光电技术有限公司 一种薄膜晶体管基板的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103123911A (zh) * 2012-10-23 2013-05-29 友达光电股份有限公司 像素结构及其制作方法
CN103151304A (zh) * 2012-11-02 2013-06-12 友达光电股份有限公司 显示面板的阵列基板及其制作方法
CN105140178A (zh) * 2015-07-24 2015-12-09 深圳市华星光电技术有限公司 有机薄膜晶体管阵列基板及其制作方法
CN105336626A (zh) * 2015-12-08 2016-02-17 深圳市华星光电技术有限公司 与数据线导通的薄膜晶体管的制备方法及薄膜晶体管

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW522570B (en) * 2001-11-06 2003-03-01 Hannstar Display Corp Manufacturing method of thin film transistor array substrate and its structure
KR100494709B1 (ko) * 2002-04-19 2005-06-13 비오이 하이디스 테크놀로지 주식회사 자기정렬 전극을 가지는 액정표시소자의 제조방법
KR101394938B1 (ko) * 2011-05-03 2014-05-14 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조 방법
CN102830560A (zh) * 2012-08-27 2012-12-19 京东方科技集团股份有限公司 一种阵列基板及其制作方法
CN103926752B (zh) * 2013-07-30 2017-04-19 上海中航光电子有限公司 一种液晶显示器、平面转换模式的阵列基板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103123911A (zh) * 2012-10-23 2013-05-29 友达光电股份有限公司 像素结构及其制作方法
CN103151304A (zh) * 2012-11-02 2013-06-12 友达光电股份有限公司 显示面板的阵列基板及其制作方法
CN105140178A (zh) * 2015-07-24 2015-12-09 深圳市华星光电技术有限公司 有机薄膜晶体管阵列基板及其制作方法
CN105336626A (zh) * 2015-12-08 2016-02-17 深圳市华星光电技术有限公司 与数据线导通的薄膜晶体管的制备方法及薄膜晶体管

Also Published As

Publication number Publication date
CN106129063A (zh) 2016-11-16
CN106129063B (zh) 2019-06-25
US10186531B2 (en) 2019-01-22
US20180175079A1 (en) 2018-06-21

Similar Documents

Publication Publication Date Title
JP5593047B2 (ja) 液晶表示装置のアレイ基板の製造方法
US10128281B2 (en) Array substrate, fabrication method thereof and display device
KR101901045B1 (ko) 박막 트랜지스터 및 그 준비 방법, 어레이 기판, 및 디스플레이 장치
CN109166865B (zh) 阵列基板及其制造方法、显示面板
CN108198825B (zh) 一种阵列基板及其制备方法、显示面板
WO2014124568A1 (zh) 薄膜晶体管、阵列基板及其制作方法及显示装置
WO2016119324A1 (zh) 阵列基板及其制作方法、显示装置
CN106129063B (zh) 薄膜晶体管阵列基板及其制造方法
WO2018090482A1 (zh) 阵列基板及其制备方法、显示装置
CN111048524A (zh) 阵列基板及制备方法、显示面板
WO2013127201A1 (zh) 阵列基板和其制造方法以及显示装置
WO2015149482A1 (zh) 阵列基板及其制作方法、显示装置
WO2013181915A1 (zh) Tft阵列基板及其制造方法和显示装置
CN109037241B (zh) Ltps阵列基板及其制造方法、显示面板
TWI459477B (zh) 畫素結構及其製作方法
WO2016078169A1 (zh) 薄膜晶体管的制造方法
WO2019100465A1 (zh) 顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
WO2016026207A1 (zh) 阵列基板及其制作方法和显示装置
CN106229298A (zh) 一种阵列基板及其制作方法
CN105529274A (zh) 薄膜晶体管的制作方法、阵列基板和显示装置
CN102655116B (zh) 阵列基板的制造方法
WO2018077239A1 (zh) 显示基板及其制造方法、显示装置
WO2023283998A1 (zh) 显示面板及其制备方法、显示装置
US10007175B2 (en) Mask and method for manufacturing thin film transistor using the same
WO2016011685A1 (zh) 共平面型氧化物半导体tft基板的制作方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15300247

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16907950

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16907950

Country of ref document: EP

Kind code of ref document: A1