WO2018084732A1

WO2018084732A1 - Ldpc codes for incremental redundancy harq (ir-harq) schemes

Info

Publication number: WO2018084732A1
Application number: PCT/RU2016/000742
Authority: WO
Inventors: Gleb Vyacheslavovich KALACHEV; Pavel Anatolyevich Panteleev; Vladimir Sergeevich POLOVNIKOV; Ivan Leonidovich Mazurenko; Elyar Eldarovich Gasanov; Aleksey Aleksandrovich LETUNOVSKIY
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-11-01
Filing date: 2016-11-01
Publication date: 2018-05-11
Anticipated expiration: 2019-05-01

Abstract

Provided is a IR-HARQ scheme comprising determining a first low-density-parity-check, LDPC, matrix, wherein a second submatrix of the first LDPC matrix has a dual diagonal structure, determining a codeword based on a sequence of information bits and the first LDPC matrix, transmitting the codeword, receiving, in relation to the transmitted codeword, an IR-HARQ message, determining a second LDPC matrix, wherein a first submatrix of the second LDPC matrix is determined by splitting rows of a first submatrix of the first LDPC matrix and a second submatrix of the second LDPC matrix has a dual diagonal structure, determining a desired column weight distribution of the second LDPC matrix, adding rows to the first submatrix and to the second submatrix of the second LDPC matrix, wherein a number of nonzero entries in the columns of the rows added to the first submatrix of the second LDPC matrix is based on the desired column weight distribution and wherein entries in the columns of the rows added to the second submatrix of the second LDPC matrix are zero, determining additional parity bits for the codeword based on the sequence of information bits and the second LDPC matrix, and transmitting the additional parity bits.

Description

LDPC CODES FOR INCREMENTAL REDUNDANCY HARQ (IR-HARQ) SCHEMES

FIELD

The present disclosure relates to a low-density-parity-check (LDPC) based incremental redundancy (IR) hybrid automatic repeat request (HARQ) scheme. BACKGROUND

Fig. 1 shows a block diagram illustrating a digital communications system 10 in which processes of the present disclosure may be implemented. The digital communications system 10 includes a transmitting side comprising an encoder 12 and a receiving side comprising a decoder 14. The input of the encoder 12 at the transmitting side is, for example, an information sequence IS₁ of k bits to which a redundancy sequence of r bits is added in an encoding operation performed by the encoder 12, thereby producing an encoded information sequence IS ₂ of k + r = n bits which may be forwarded to a modulator 16.

The modulator 16 may transform the encoded sequence IS ₂ into a modulated signal vector CH_IN which is in turn transmitted through a wired or wireless channel 18 such as, for example, a conductive wire, an optical fiber, a radio channel, a microwave channel or an infrared channel. Since the channel 18 is usually subject to noisy disturbances, the channel output CH_OUT may differ from the channel input CH_IN.

At the receiving side, the channel output vector CH_OUT may be processed by a demodulator 20 which produces some likelihood ratio. The decoder 14 may use the redundancy in the received information sequence IS ₃ in a decoding operation performed by the decoder 14 to correct errors in the received information sequence IS ₃ and produce a decoded information sequence IS ₄. The decoded information sequence IS ₄ is an estimate of the encoded information sequence IS ₂ from which (an estimate of) the information sequence ISi can be extracted. The encoding operation and the decoding operation may be governed by an LDPC code. In the general formulation of channel coding, an LDPC code may employ a generator matrix G for the encoding operation performed by the encoder 12 and a parity-check matrix H for the decoding operation performed by the decoder 14. For an LDPC code with an information sequence ISi of size 1 x k , a codeword IS ₂ of size 1 x n , and a redundancy (parity) sequence of r = (n - k) bits, the generator matrix G has size k x n and the parity-check matrix H has size r x n = (n - k)x n .

The parity-check matrix H_rxn and the generator matrix G_kxn enjoy the orthogonality property, which states that for any generator matrix G_kxn with k linearly independent rows there exists a parity-check matrix H_rxn with r = (n - k) linearly independent rows. Thus, any row of the generator matrix G_kxn is orthogonal to the rows of the parity-check matrix H_rxn such that the following equation is satisfied:

The encoding operation can be performed by means of a multiplication between the information sequence ISi and the generator matrix G_kxn , wherein the result of the multiplication is the encoded information sequence IS2:

At the receiving side, due to the orthogonality property between the generator matrix G_kxn and the parity-check matrix H_rxn , the following equation should be satisfied:

where IS ₄ is the decoded received information sequence of size 1 x n . If the above equation is verified, the information sequence estimate IS ₄ may be assumed to be correct.

Once the parity-check matrix H_rxn is generated, it is possible to obtain the generator matrix and vice versa. Accordingly, any process of determining a parity-check matrix H_rxn may

be mapped to an equivalent process of obtaining a generator matrix G_kxn and vice versa, so that any process disclosed throughout the description and claims in relation to determining a parity- check matrix shall be understood as encompassing the equivalent process of obtaining a

generator matrix G_kxn and vice versa.

Moreover, it should be noted that LDPC codes having a parity-check matrix H_rxn of a particular structure such as, for example, a parity-check matrix H_rxn having a parity part of dual diagonal structure may allow encoding the information sequence ISi using (only) the parity-check matrix so that obtaining the generator matrix may not be required (cf. T. J. Richardson and

R. L. Urbanke, "Efficient encoding of low-density parity-check codes", IEEE TRANSACTIONS ON INFORMATION THEORY, Volume 47, Issue 2, Pages 638-656, August 2002).

A particular form of the parity-check matrix

is a regular quasi-cyclic (QC) LDPC matrix which can be divided into quadratic submatrices i.e. circulant matrices (or

"circulants" for short), which may, for example, be obtained from cyclically right-shifting an N x N identity matrix l(0) by p_{j t} positions:

with N = nl L (cf. M. P. C. Fossorier, "Quasi-Cyclic Low-Density Parity-Check Codes from Circulant Permutation Matrices", IEEE TRANSACTIONS ON INFORMATION THEORY, Volume 50, Issue 8, Pages 1788-1793, August 2004). Thus, a regular QC-LDPC matrix may be defined by a base matrix B which satisfies:

Moreover, a base matrix B of an irregular QC-LDPC matrix may be obtained by

where " o" denotes the Hadamard product and

denotes a mask matrix with Alternatively, the base matrix B of an irregular QC-

LDPC matrix

may be obtained by (only) partially labelling the base matrix B with shift values

with not labelled entries (which are sometimes represented by a value of "-1" or an asterisk "*") representing zero matrices of size N N .

Furthermore, it is to note that a QC-LDPC matrix H ^QC (and more generally any LDPC code) can also be described by its equivalent bipartite graph ("Tanner graph"), wherein each edge of the Tanner graph connects one variable node of a plurality of variable nodes to one check node of a plurality of check nodes. For example, a LDPC matrix H_rxn of r rows and n columns can be represented by its equivalent bipartite graph with r check nodes and n variable nodes which has edges between the check nodes and the variable nodes if there are corresponding "Is" in the LDPC matrix H_rxn (cf. R. Tanner, "A Recursive Approach to Low Complexity Codes",

IEEE TRANSACTIONS IN INFORMATION THEORY, Volume 27, Issue 5, Pages 533-547, September 1981). In this regard, it is to note that the variable nodes represent codeword bits and the check nodes represent parity-check equations. A finite set of connected edges in the Tanner graph, wherein the set starts and ends at the same node and satisfies the condition that no node (except the initial and final node) appears more than once forms a "cycle". The "length" of the cycle is the number of edges of the set. The "girth" of the Tanner graph (or "girth" in short) is the length of the shortest cycle(s) in the graph. In this regard, it is noted that short cycles in a Tanner graph of an LDPC code may prevent decoding algorithms from converging. Furthermore, short cycles may degrade the performance of the decoder 14, because they affect the independence of the extrinsic information exchanged in the iterative decoding. Accordingly, shift values are to be chosen that achieve a high girth of the Tanner graph representation of the respective LDPC matrix.

Moreover, a LDPC code may contain Trapping Sets (TSs). More particularly, a (a,b) TS contains b check nodes which have an odd number of connections to a variable nodes. Accordingly, when the a variable nodes are wrong, only the b check nodes will be unsatisfied which may lead to a high error floor, as a belief propagation algorithm employed in the decoder 14 may be "trapped" in a false minimum. While known approaches to channel coding have proven to perform well for a wide variety of scenarios, there is still an ongoing research to provide sophisticated solutions that achieve high data throughput with decent encoding/decoding resources.

SUMMARY According to a first aspect of the present invention, there is provided an apparatus, the apparatus being configured to determine a first LDPC matrix, wherein a second submatrix of the first LDPC matrix has a dual diagonal structure, determine a codeword based on a sequence of information bits and the first LDPC matrix, transmit the codeword, receive an IR-HARQ message, determine a second LDPC matrix, wherein a first submatrix of the second LDPC matrix is based on split rows of a first submatrix of the first LDPC matrix and wherein a second submatrix of the second LDPC matrix has a dual diagonal structure, determine a desired column weight distribution of the second LDPC matrix, add rows to the first submatrix and to the second submatrix of the second LDPC matrix, wherein a number of non-zero entries in the columns of the added rows of the first submatrix of the second LDPC matrix is based on the desired column weight distribution and wherein entries in the columns of the added rows of the second submatrix of the second LDPC matrix are zero, determine additional parity bits for the codeword based on the sequence of information bits and the second LDPC matrix, and transmit the additional parity bits.

Hence, a column weight distribution of the second LDPC code used for determining the additional parity bits can be efficiently derived from the first LDPC code and brought into agreement with a desired column weight distribution, thereby improving the quality of the second LDPC code.

In this regard, it is noted that the term "IR-HARQ message" as used throughout the description and claims in particular refers to a signal which indicates that a previously transmitted codeword cannot be correctly decoded by a receiver of the codeword.

Furthermore, the term "column weight" as used throughout the description and claims in particular refers to the number of non-zero entries in a column of a LDPC matrix. Moreover, it is noted that the term "column weight" as used throughout the description and claims can be interchanged by the term "variable node degree" which confers the same meaning. Hence, the term "column weight distribution" as used throughout the description and claims equally refers to fractions of columns of a LDPC matrix having a certain number or range of non-zero entries, and to fractions of edges emanating from variable nodes of a particular degree.

Moreover, it is noted that the term "split row" as used throughout the description and claims in particular refers to a process of distributing entries of a row (which is split) onto multiple rows. In the case of a LDPC matrix made up of "0s" and "Is", each column of a matrix consisting of rows onto which entries of a split row have been distributed has at most one non-zero entry. In other words, by "splitting a row", the "Is" in the "split row" are distributed onto multiple rows which, if summed (in a vector-sense), give the "split row".

With regard to the term "matrix" as used throughout the description and claims, it is to be noted that values forming a "matrix" do not necessarily have to be physically stored in matrix- (or array-) form, presented in matrix- (or array-) form, or used in matrix algebra throughout a process involving the matrix. Thus, a set of (integer) values with assigned row and column indices or a set of (integer) values which are stored in a (logical) memory array shall also fall under the term "matrix" as used throughout the description and claims.

In a first possible implementation form of the apparatus according to the first aspect, columns of the first LDPC matrix are divided up into columns of the first submatrix of the first LDPC matrix, columns of the second submatrix of the first LDPC matrix, and intermediate columns, wherein each intermediate column has three non-zero entries.

Hence, the parity bits of the codeword can be determined based on the first LDPC matrix without the need to obtain a generator matrix G_kxn , thereby improving encoding efficiency.

In this regard, it is noted that the term "intermediate columns" as used throughout the description and claims in particular refers to a set of consecutive columns that are placed between a first submatrix (e.g., a first set of consecutive columns) and a second submatrix (e.g., a second set of consecutive columns). In a second possible implementation form of the apparatus according to the first aspect as such or according to the first implementation form of the first aspect, columns of the second LDPC matrix are divided up into columns of the first submatrix of the second LDPC matrix, columns of the second submatrix of the second LDPC matrix, intermediate columns, wherein each intermediate column has three non-zero entries, and additional columns, the number of the additional columns being equal to the number of rows added to the first submatrix of the second LDPC matrix.

In a third possible implementation form of the apparatus according to the first aspect as such or according to the first or second implementation form of the first aspect, rows of the second LDPC matrix comprising the added rows further comprise a submatrix having a dual diagonal structure.

In a fourth possible implementation form of the apparatus according to the third implementation form of the first aspect, the rows of the second LDPC matrix comprising the added rows further comprise a column, adjacent the submatrix, having three non-zero entries. Hence, further additional parity bits can be determined based on the second LDPC matrix without the need to obtain a generator matrix G_kxn , thereby further improving encoding efficiency.

In a fifth possible implementation form of the apparatus according to the first aspect as such or according to any one of the first to the fourth implementation form of the first aspect, the apparatus is configured to determine the number of non-zero entries in the columns of the rows added to the first submatrix of the second LDPC matrix by progressively growing edges in a corresponding Tanner graph representation, wherein entries in the first submatrix of the second LDPC matrix and entries in the second submatrix of the second LDPC matrix remain unchanged. Hence, a desired column weight distribution can be efficiently generated without modifying the code structure inherited from the first LDPC code by row splitting, thereby protecting code quality. In this regard, the expression "progressively growing edges in a corresponding Tanner graph representation" as used throughout the description and claims in particular refers to a process of progressively establishing edges between variable nodes and check nodes in the Tanner graph representation of the LDPC matrix, in an edge-by-edge manner. For example, edges between variable nodes and check nodes may be progressively established by labelling entries in rows whose entries participate in large cycles having a high ACE (cf. T. Tian et al., "Selective Avoidance of Cycles in Irregular LDPC Code Construction", IEEE TRANSACTIONS ON COMMUNICATIONS, Volume 52, No. 8, Pages 1242-1247, August 2004), thereby maximizing cycle length. In a sixth possible implementation form of the apparatus according to the first aspect as such or according to any one of the first to the fifth implementation form of the first aspect, entries in the same row of the first submatrix of the first LDPC matrix are distributed onto different rows of the first submatrix of the second LDPC matrix.

Hence, a structure of the first LDPC code can be maintained, thereby protecting the quality of the second LDPC code used for determining the additional parity bits.

In a seventh possible implementation form of the apparatus according to the first aspect as such or according to any one of the first to the sixth implementation form of the first aspect, the apparatus is an encoder configured to implement an IR-HARQ scheme.

According to a second aspect of the present invention, there is provided a method of determining additional parity bits in an IR-HARQ scheme, comprising determining a first LDPC matrix, wherein a second submatrix of the first LDPC matrix has a dual diagonal structure, determining a codeword based on a sequence of information bits and the first quasi- cyclic low density parity check matrix, transmitting the codeword, receiving, in relation to the transmitted codeword, an IR-HARQ message, determining a second LDPC matrix, wherein a first submatrix of the second LDPC matrix is determined by splitting rows of a first submatrix of the first LDPC matrix and wherein a second submatrix of the second LDPC matrix has a dual diagonal structure, determining a desired column weight distribution of the second LDPC matrix, adding rows to the first submatrix and to the second submatrix of the second LDPC matrix, wherein a number of non-zero entries in the columns of the rows added to the first submatrix of the second LDPC matrix is based on the desired column weight distribution and wherein entries in the columns of the rows added to the second submatrix of the second LDPC matrix are zero, determining additional parity bits for the codeword based on the sequence of information bits and the second LDPC matrix, and transmitting the additional parity bits.

Hence, a column weight distribution of the second LDPC code used for determining the additional parity bits can be brought into agreement with a desired column weight distribution, thereby improving the quality of the second LDPC code.

In a first possible implementation form of the method according to the second aspect, columns of the first LDPC matrix are divided up into columns of the first submatrix of the first LDPC matrix, columns of the second submatrix of the first LDPC matrix, and intermediate columns, wherein each intermediate column has three non-zero entries.

In a second possible implementation form of the method according to the second aspect as such or according to the first implementation form of the second aspect, columns of the second LDPC matrix are divided up into columns of the first submatrix of the second LDPC matrix, columns of the second submatrix of the second LDPC matrix, intermediate columns, wherein each intermediate column has three non-zero entries, and additional columns, the number of the additional columns being equal to the number of rows added to the first submatrix of the second LDPC matrix.

In a third possible implementation form of the method according to the second aspect as such or according to the first or second implementation form of the second aspect, rows of the second LDPC matrix comprising the added rows further comprise a submatrix having a dual diagonal structure. In a fourth possible implementation form of the method according to the second aspect as such or according to any one of the first to the third implementation form of the second aspect, the rows of the second LDPC matrix comprising the added rows further comprise a column, adjacent the submatrix, having three non-zero entries. Hence, further additional parity bits can be determined based on the second LDPC matrix without the need to obtain a generator matrix G_kxn , thereby further improving encoding efficiency.

In a fifth possible implementation form of the method according to the second aspect as such or according to any one of the first to the third implementation form of the second aspect, the method further comprises determining the number of non-zero entries in the columns of the rows added to the first submatrix of the second LDPC matrix by progressively growing edges in a corresponding Tanner graph representation, wherein entries in the first submatrix of the second LDPC matrix and entries in the second submatrix of the second LDPC matrix remain unchanged. Hence, a desired column weight distribution can be efficiently generated without modifying the code structure inherited from the first LDPC code by row splitting, thereby protecting code quality.

In a sixth possible implementation form of the method according to the second aspect as such or according to any one of the first to the third implementation form of the second aspect, splitting rows of the first submatrix of the first LDPC matrix comprises distributing entries in the same row of the first submatrix of the first LDPC matrix onto different rows of the first submatrix of the second LDPC matrix.

Hence, a structure of the first LDPC code can be maintained, thereby protecting the quality of the second LDPC code used for determining the additional parity bits. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic illustration of a digital communication system;

Fig. 2 is a flow chart of a process of calculating additional parity bits in an IR-HARQ scheme that may be implemented in the digital communication system of Fig. 1 ; and

Fig. 3 is an optional step of the process of the flow chart shown in Fig. 2. DETAILED DESCRIPTION

Fig. 2 is a flow chart of a process 22 of determining additional parity bits in an IR-HARQ scheme. The IR-HARQ scheme may be implemented in a digital communication apparatus such as, for example, the encoder 12 of the digital communication system 10 shown in Fig. 1. For instance, the encoder 12 may be an evolved Node B (eNodeB) and the decoder 14 may be a user equipment (UE) or vice versa. Furthermore, the IR-HARQ scheme may be implemented by a computer-readable medium storing instructions that, when executed by a computer, cause the computer to perform the process 22.

The process 22 starts at 24 with determining a first LDPC code such as a first QC-LDPC code. After determining the first LDPC code, the process 22 may be continued at 26 with encoding a sequence of information bits such as the sequence of information bits ISi using the first LDPC code. If the LDPC matrix H_rxn of the first LDPC code (which is also referred to as the first

LDPC matrix H_rxn throughout the description and claims) has a dual diagonal structure, the sequence of information bits ISi may be encoded without explicitly determining the corresponding generator matrix G_kxn .

For example, the first LDPC code may be an irregular repeat-accumulate (IRA) LDPC code such as an IRA QC-LDPC code. Thus, the first LDPC matrix H_rxn may be a first QC-LDPC matrix H_rxn having a parity part with a dual diagonal structure and N weight-3 columns as exemplified by the following base matrix Β_γ (with e being a positive integer and e < N):

After transmitting the codeword at 28, the encoder 12 may receive at 30 an indication that the transmitted codeword cannot be decoded correctly. For example, the encoder 12 may receive a message from the decoder 14 or another entity which, for instance, generates the message after a timeout (within which an indication that the codeword has been correctly encoded is expected) has lapsed. The indication that the transmitted codeword cannot be decoded correctly may thus be explicit or implicit. In response to the message, the encoder 12 may determine a second LDPC code to determine additional parity bits for the sequence of information bits ISi .

As indicated at 32, generating the second LDPC code may involve splitting sub-rows of the first LDPC matrix H_rxn . For example, generating the second LDPC code may involve splitting rows of the information part (indicated in the base matrix above by a broken line) of the

first QC-LDPC matrix H _xn (and extending the dual diagonal structure of the parity part) as exemplified by the following base matrix B₂ :

In the exemplary row splitting given by the base matrix B₂ , a row splitting factor of s = 2 has been used, i.e., the entries in one row of the information part of the first QC-LDPC matrix H_{r n} are distributed onto two rows. However, the row splitting factor s may be determined based on the number of additional parity bits to be determined. For example, if / additional parity bits are to be determined, the row splitting factor s may be given by:

I.e., the row splitting factor s may be based on the ratio of the additional parity bits and the number of parity bits of the codeword. After splitting the rows of the information part of the first LDPC matrix H_rxn by the row splitting factor s, the process 22 may continue at 34 with determining a desired column weight distribution of a LDPC matrix H_fxo of the second LDPC code (which is also referred to as the second LDPC matrix H_fxo throughout the description and claims).

For example, the desired column weight distribution of the second LDPC matrix H_fxo may be

determined based on an optimal column weight distribution in view of a pre-defined (performance) criterion to be met by the second LDPC code (cf. T. J. Richardson and R. L. Urbanke, "The Capacity of Low-Density Parity-Check Codes Under Message-Passing Decoding", IEEE TRANSACTIONS ON INFORMATION THEORY, Volume 47, No. 2, Pages 599-618, February 2001, or T. J. Richardson et al., "Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes", IEEE TRANSACTIONS ON INFORMATION THEORY, Volume 47, No. 2, Pages 619-637, February 2001). After determining the desired column weight distribution of the second LDPC matrix the

process 22 may continue at 36 by adding f -sr additional rows and o - (k + sr) additional columns to the LDPC matrix that incorporates the split rows (and the extended dual

diagonal structure of the parity part) of the first LDPC matrix H_rxn as exemplified by the following base matrix B₃ (which shows a an example of a second QC-LDPC matrix

The added rows can be divided into three submatrices. The first submatrix (indicated by the broken line on the left side) contains the subrows added to the information part. The second submatrix (indicated by the broken line in the middle) contains the subrows added to the parity part. The third submatrix (indicated by the broken line on the right side) contains subrows of the added columns. As shown, the number of added columns may correspond to the number of added rows which allows the third submatrix to have a dual diagonal structure (with N weight- 3 columns). While the entries of the first submatrix are yet to be labelled as indicated by the asterisks, all entries of the second submatrix are to remain zero.

In this regard, column weights of the columns of the first submatrix of the second LDPC matrix H_fxo may be derived based on the desired column weight distribution and the column weights of the columns of the first submatrix of the first LDPC matrix H_rxn . Thus, labelling entries of a column of the first submatrix of the second LDPC matrix H_{f 0} may be stopped if the weight of the column meets the derived column weight. Once having labelled the entries of the columns of the first submatrix of the second LDPC matrix H_fxo in accordance with the derived column weights, the second LDPC code may be used to determine additional parity bits as indicated at 38. After having determined the additional parity bits, the additional parity may be transmitted to and used by the decoder for decoding the codeword. If encoding of the codeword nevertheless fails, further additional parity bits or the whole codeword may be (re)transmitted.

As indicated at 40 in Fig. 3, the columns of the first submatrix of the second LDPC matrix H _xo may be labelled by progressively growing edges in the Tanner graph. For instance, edges between variable nodes and check nodes of the Tanner graph of the first submatrix of the second LDPC matrix H _xo may be progressively established on a column-by-column basis. Moreover, labelling entries in a column of the first submatrix of the second LDPC matrix H_fxo may be performed in accordance with combinatorial characteristics of the second LDPC code. For instance, labelling entries of a column of the first submatrix of the second LDPC matrix H_fxo may be performed in accordance with an ACE of the nodes involved. More particularly, a potential harm of a TS of the second LDPC code may be estimated based on the ACE characteristics of cycles that the TS consists of. The ACE of a given cycle C in the Tanner graph denoted as ACE(O) is defined as

where d(v) is the degree of a variable node v and E(V_C ) is the set of variable nodes involved in the cycle C. In general, the bigger the ACE value of a TS is, the less harmful the TS is in terms of the probability of a message passing LDPC decoder (such as, for example, decoder 14) getting stuck in bit positions corresponding to the variable nodes of the TS.

In this regard, labelling entries in a column of the first submatrix of the second LDPC matrix H_fxo may involve analyzing cycles in the Tanner graph defined by the labelled entries.

Labelling entries in the first submatrix of the second LDPC matrix thus starts from a given

protograph and not an empty protograph. For each variable node and for each check node in the Tanner graph defined by the labelled entries of the second LDPC matrix H_fxo , a maximum of minimal cycle lengths in which the variable node or the check node is involved may be determined. For the cycles having the maximum of the minimal cycle lengths, the ACE may be calculated and cycles having a maximum ACE may be determined.

Moreover, for determining the biggest minimal ACE, the ACE may be calculated by analyzing cycles of all lengths, not just the shortest cycles. From the cycles having the maximum ACE, a row of the first submatrix of the second LDPC matrix H_fxo having a minimal weight of all rows comprising check nodes involved in the cycles may be determined and an entry in the determined row may be labeled. By this, a uniform or close-to-uniform row- weight distribution can be achieved. Labelling entries in a column of the first submatrix of the second LDPC matrix H_fxo may then be repeated until a column weight in accordance with the derived column weight is achieved.

Claims

1. An apparatus, the apparatus being configured to: determine a first low-density-parity-check, LDPC, matrix, wherein a second submatrix of the first LDPC matrix has a dual diagonal structure; determine a codeword based on a sequence of information bits and the first LDPC matrix; transmit the codeword; receive an incremental redundancy, IR, hybrid automatic repeat request, HARQ, message; determine a second LDPC matrix, wherein a first submatrix of the second LDPC matrix is based on split rows of a first submatrix of the first LDPC matrix and wherein a second submatrix of the second LDPC matrix has a dual diagonal structure; determine a desired column weight distribution of the second LDPC matrix; add rows to the first submatrix and to the second submatrix of the second LDPC matrix, wherein a number of non-zero entries in the columns of the added rows of the first submatrix of the second LDPC matrix is based on the desired column weight distribution and wherein entries in the columns of the added rows of the second submatrix of the second LDPC matrix are zero; determine additional parity bits for the codeword based on the sequence of information bits and the second LDPC matrix; and transmit the additional parity bits.

2. The apparatus of claim 1 , wherein columns of the first LDPC matrix are divided up into columns of the first submatrix of the first LDPC matrix, columns of the second submatrix of the first LDPC matrix, and intermediate columns, wherein each intermediate column has three non-zero entries.

3. The apparatus of claim 1 or 2, wherein columns of the second LDPC matrix are divided up into columns of the first submatrix of the second LDPC matrix, columns of the second submatrix of the second LDPC matrix, intermediate columns, wherein each intermediate column has three non-zero entries, and additional columns, the number of the additional columns being equal to the number of rows added to the first submatrix of the second LDPC matrix.

4. The apparatus of any one of claims 1 to 3, wherein rows of the second LDPC matrix comprising the added rows further comprise a submatrix having a dual diagonal structure.

5. The apparatus of claim 4, wherein the rows of the second LDPC matrix comprising the added rows further comprise a column, adjacent the submatrix, having three non-zero entries.

6. The apparatus of any one of claims 1 to 5, wherein the apparatus is configured to: determine the number of non-zero entries in the columns of the rows added to the first submatrix of the second LDPC matrix by progressively growing edges in a corresponding Tanner graph representation, wherein entries in the first submatrix of the second LDPC matrix and entries in the second submatrix of the second LDPC matrix remain unchanged.

7. The apparatus of any one of claims 1 to 6, wherein entries in the same row of the first submatrix of the first LDPC matrix are distributed onto different rows of the first submatrix of the second LDPC matrix.

8. The apparatus of any one of claims 1 to 7, wherein the apparatus is an encoder configured to implement an IR-HARQ scheme.

9. A method of determining additional parity bits in an incremental redundancy,

IR, hybrid automatic repeat request, HARQ, scheme, comprising: determining a first low-density-parity-check, LDPC, matrix, wherein a second submatrix of the first LDPC matrix has a dual diagonal structure; determining a codeword based on a sequence of information bits and the first quasi- cyclic low density parity check matrix; transmitting the codeword; receiving, in relation to the transmitted codeword, an IR-HARQ message; determining a second LDPC matrix, wherein a first submatrix of the second LDPC matrix is determined by splitting rows of a first submatrix of the first LDPC matrix and wherein a second submatrix of the second LDPC matrix has a dual diagonal structure; determining a desired column weight distribution of the second LDPC matrix; adding rows to the first submatrix and to the second submatrix of the second LDPC matrix, wherein a number of non-zero entries in the columns of the rows added to the first submatrix of the second LDPC matrix is based on the desired column weight distribution and wherein entries in the columns of the rows added to the second submatrix of the second LDPC matrix are zero; determining additional parity bits for the codeword based on the sequence of information bits and the second LDPC matrix; and transmitting the additional parity bits.

10. The method of claim 9, wherein columns of the first LDPC matrix are divided up into columns of the first submatrix of the first LDPC matrix, columns of the second submatrix of the first LDPC matrix, and intermediate columns, wherein each intermediate column has three non-zero entries.

11. The method of claim 9 or 10, wherein columns of the second LDPC matrix are divided up into columns of the first submatrix of the second LDPC matrix, columns of the second submatrix of the second LDPC matrix, intermediate columns, wherein each intermediate column has three non-zero entries, and additional columns, the number of the additional columns being equal to the number of rows added to the first submatrix of the second LDPC matrix.

12. The method of any one of claims 9 to 1 1 , wherein rows of the second LDPC matrix comprising the added rows further comprise a submatrix having a dual diagonal structure.

13. The method of claim 12, wherein the rows of the second LDPC matrix comprising the added rows further comprise a column, adjacent the submatrix, having three non-zero entries.

14. The method of any one of claims 9 to 13, further comprising: determining the number of non-zero entries in the columns of the rows added to the first submatrix of the second LDPC matrix by progressively growing edges in a corresponding Tanner graph representation, wherein entries in the first submatrix of the second LDPC matrix and entries in the second submatrix of the second LDPC matrix remain unchanged.

15. The method of any one of claims 9 to 14, wherein splitting rows of the first submatrix of the first LDPC matrix comprises distributing entries in the same row of the first submatrix of the first LDPC matrix onto different rows of the first submatrix of the second LDPC matrix.