WO2009078514A1

WO2009078514A1 - Apparatus and method for generating parity check matrix for ldpc code and ldpc encoding/decoding appartus using the same

Info

Publication number: WO2009078514A1
Application number: PCT/KR2008/003197
Authority: WO
Inventors: Jong-Ee Oh; Chanho Yoon; Cheol-Hui Ryu; Sok-Kyu Lee
Original assignee: Electronics and Telecommunications Research Institute ETRI
Current assignee: Electronics and Telecommunications Research Institute ETRI
Priority date: 2007-12-17
Filing date: 2008-06-09
Publication date: 2009-06-25
Anticipated expiration: 2010-06-17
Also published as: KR20090064709A

Abstract

Provides are an apparatus and method for generating a LDPC code having a simple coding structure, a fast decoding convergence speed, a variable information length, and a variable coding rate, and a LDPC encoding/decoding apparatus using the same. The apparatus for generating a LDPC code includes a first parity check matrix generating unit for generating a first parity check matrix formed of a first information block and a parity block; and a q parity check matrix generating unit for generating a q parity check matrix by adding a q information block to the generate q-1 parity check matrix where 1<q≤Q and Q is an integer greater than 2.

Description

APPARATUS AND METHOD FOR GENERATING PARITY

CHECK MATRIX FOR LDPC CODE AND LDPC ENCODING/

DECODING APPARTUS USING THE SAME

Technical Field

[1] The present invention relates to a technology for an error correction code of a wired/ wireless communication system; and, more particularly, to an apparatus and method for generating a parity check matrix of a low density parity check (LDPC) code having a simple coding structure, a fast decoding convergence speed, a variable information length, and a variable coding rate, and a LDPC encoding/decoding apparatus using the same.

[2] This work was supported by the IT R&D program of MIC/IITA [2006-S-002-02,

"IMT- Advanced Radio Transmission Technology with Low Mobility"].

[3]

Background Art

[4] In a wired/wireless communication system, a receiving end may have difficulty to demodulate a transmitted signal due to noise, interference, and fading on a transmission channel.

[5] Many methods were introduced to reduce an error generation rate which increases in proportion to a transmit rate. Among them, using an error correction code is one of representative methods for reducing the error generation rate. Lately, almost wireless communication systems use the error correction code. Particularly, a low density parity check (LDPC) code has been receiving attention as an error correction code for a next generation high capacity wireless communication system because the LDPC code provides excellent error correction performance and enables a high speed decoder to be embodied with low complexity.

[6] As a method for decoding the LDPC code, a serial or partial parallel decoding method and a parallel decoding method were introduced. Since the serial or partial parallel decoding method repeatedly uses the small number of common blocks for processing a variable node and a check node, it is possible to advantageously reduce a hardware size. However, the serial or partial parallel decoding method cannot support high speed decoding. On the contrary, the parallel decoding method can advantageously support high speed decoding by exchanging information in parallel through variable node processing blocks and check node processing blocks, which are optimized to each parity check matrix. However, the parallel decoding method also has a disadvantage of a large hardware size. That is, the larger the hardware size increases, the more various code rates are supported.

[7] Meanwhile, a wired/wireless communication system must use an error correction code having a variable information length and a variable code rate in order to adaptively use modulation and coding scheme (MCS) according to a channel state or in order to perform hybrid automatic repeat request (H-ARQ). Therefore, various decoding methods for supporting various MCS levels were introduced, for example, a method for embodying independent decoders according to each of information lengths and code rates or a method for applying an information shortening scheme or a puncturing scheme although one hardware is used. However, the former method has a shortcoming of a large hardware size, and the later method has a disadvantage that error correction performance of a LDPC code significantly deteriorates because of randomly using one of the information shortening scheme and the parity puncturing scheme.

[8] As described above, the parallel decoding method is better for a high speed wireless communication system supporting a fast processing speed of several giga bits per second. Lately, it has been required to use a LDPC code having a variable information length and a variable code rate having excellent error correction performance in order to effectively apply an adaptive modulation and demodulation scheme. It has been also required that the complexity of encoding and decoding of the LDPC code must be low. However, it is not easy to process entire LDPC codes in parallel due to high complexity of random connection of variable nodes and check nodes.

[9] Therefore, it is a technical aspect of the present invention to provide a partial parallel processing method and apparatus for providing a maximum decoding processing speed with realizable complexity.

[10]

Disclosure of Invention Technical Problem

[11] An embodiment of the present invention is directed to providing an apparatus and method for generating a parity check matrix of a LDPC code and a LDPC encoding/ decoding apparatus using the same in order to provide a LDPC code having constraint for having a simple encoding structure and a fast decoding convergence speed, a variable information length, and a variable coding rate.

[12] Another embodiment of the present invention is directed to providing an apparatus and method for generating a parity check matrix of a LDPC code and a LDPC encoding/decoding apparatus using the same in order to provide a LDPC code having low encoding/decoding complexity, a fast decoding convergence speed, a variable information length, and a variable coding rate with excellent error correction per- formance.

[13] Other objects and advantages of the present invention can be understood by the following description, and become apparent with reference to the embodiments of the present invention. Also, it is obvious to those skilled in the art of the present invention that the objects and advantages of the present invention can be realized by the means as claimed and combinations thereof.

[14]

Technical Solution

[15] In accordance with an aspect of the present invention, there is provided an apparatus for generating a parity check matrix of a low density parity check (LDPC) code, including a first parity check matrix generating unit for generating a first parity check matrix formed of a first information block and a parity block; and a q parity check matrix generating means for generating a q parity check matrix by adding a q information block to the generate q-1 parity check matrix where l<q≤Q and Q is an integer greater than 2.

[16] The apparatus may further include an information shortening means for generating at least one of parity check matrixes different from the first to Q parity check matrixes by applying information shortening on at least one of the first to q parity check matrixes.

[17] The apparatus may further include a puncturing means for generating at least one of parity check matrixes different from the first to Q parity check matrixes by puncturing at least one of the first to q parity check matrixes.

[18] In accordance with another aspect of the present invention, there is provided an apparatus for generating a parity check matrix for a low density parity check (LDPC) code, including a basic parity check matrix generating unit for generating at least one of basic parity check matrixes; and an expanded parity check matrix generating unit for generating at least one of expanded parity check matrixes by applying row splitting on an information of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.

[19] The apparatus may further include an information shortening unit for generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by applying information shortening on at least one of the basic parity check matrix and the expanded parity check matrix.

[20] The apparatus may further include a puncturing unit for generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by puncturing at least one of the basic parity check matrix and the expanded parity check matrix.

[21] In accordance with still another aspect of the present invention, there is provided an apparatus for encoding a low density parity code (LDPC), including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrixes; and an encoding unit for encoding an information word based on the selected parity check matrix from the parity check matrix selecting unit. The plurality of parity check matrixes includes a first parity check matrix formed of a first information block and a parity block, and a q parity check matrix formed by adding a q information block to a q-1 parity check matrix where l<q≤Q and Q is an integer is greater than 2.

[22] In accordance with yet another aspect of the present invention, there is provided an apparatus for encoding a low density parity check (LDPC) code including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrixes; and an encoding unit for encoding an information word based on the selected parity check matrix from the parity check matrix selecting unit. The plurality of parity check matrixes include at least one of basic parity check matrixes and at least one of expanded parity check matrixes generated by expanding a parity block of the basic parity check matrix by applying row splitting on an information block of the basic parity check matrix.

[23] In accordance with another aspect of the present invention, there is provided an apparatus for decoding a low density parity check (LDPC) code, including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrix; and a decoding unit for decoding a received codeword based on the selected parity check matrix from the parity check matrix selecting unit. The plurality of parity check matrixes includes a first parity check matrix formed of a first information block and a parity block and a q parity check matrix generated by adding a q information block to a q-1 parity check matrix wherein l<q≤Q and Q is an integer greater than 2.

[24] In accordance with yet another aspect of the present invention, there is provided an apparatus for decoding a low density parity check (LDPC) code, including: a parity check matrix selecting unit for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrixes; and a decoding unit for decoding a received codeword based on the parity check matrix selected by the parity check matrix selecting unit. The plurality of parity check matrixes includes at least one of basic parity check matrixes and at least one of expanded parity check matrixes generated by applying row splitting on an information block of the basic parity check matrix and expanding a parity block of the basic parity check matrix.

[25] In accordance with yet another aspect of the present invention, there is provided a method for generating a parity check matrix of a low density parity check (LDPC) code, including: generating a first parity check matrix formed of a first information block and a parity block; and generating a q parity check matrix by adding a q information block to the generate q-1 parity check matrix where l<q≤Q and Q is an integer greater than 2.

[26] In accordance with yet another aspect of the present invention, there is provided a method for generating a parity check matrix of a low density parity check (LDPC) code, including: generating at least one of basic parity check matrixes; and generating at least one of expanded parity check matrixes by applying row splitting on an information of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.

[27]

Advantageous Effects

[28] According to the present invention, it is possible to embody a decoder having a variable information length and a variable code rate using one partial parallel processing hardware. Therefore, decoding can be performed at high speed.

[29] According to the present invention, it is also possible to generate a low density parity check (LDPC) code having a simple encoding structure and a fast decoding convergence speed and supporting a variable information length and a variable code rate while providing excellent error correction performance.

[30] According to the present invention, it is possible to easily embody a high speed

LDPC decoder and to simply embody hardware performing high speed decoding.

[31] Therefore, the present invention provides a LDPC code of a variable information length and a variable code rate, which has a low complexity for encoding/decoding and provides excellent error correction and error detection performance.

[32]

Brief Description of the Drawings

[33] Fig. 1 is a diagram structurally illustrating relation among parity check matrices exemplary shown in Table 1.

[34] Fig. 2 is a diagram for describing an information shortening scheme and a puncturing scheme in a parity check matrix in accordance with an embodiment of the present invention.

[35] Fig. 3 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with an embodiment of the present invention.

[36] Fig. 4 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with another embodiment of the present invention.

[37] Fig. 5 is a diagram illustrating a LDPC encoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention. [38] Fig. 6 is a diagram illustrating a LDPC decoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.

[39] Fig. 7 is a flowchart illustrating a method for generating a parity check matrix in accordance with an embodiment of the present invention.

[40] Fig. 8 is a flowchart illustrating a method for generating a parity check matrix in accordance with another embodiment of the present invention.

[41] Fig. 9 is a flowchart illustrating a LDPC encoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.

[42] Fig. 10 is a flowchart illustrating a LDPC decoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.

[43]

Best Mode for Carrying Out the Invention

[44] The advantages, features and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, which is set forth hereinafter.

[45] A LDPC code was introduced by Gallager. The LDPC code is defined as a matrix formed of Is and Os as elements. In the matrix, most elements are Os and few elements are Is.

[46] The LDPC code is classified into a regular LDPC code and an irregular LDPC code.

The regular LDPC code is a LDPC code introduced by Gallager. In a parity check matrix of the regular LDPC code, all rows have the same number of Is and all columns also have the same number of Is. On the contrary, a parity check matrix of the irregular LDPC code includes rows having the different number of Is and columns having the different number of Is. In general, it was widely known that the error correction performance of the irregular LDPC code is better than that of the regular LDPC code.

[47] Meanwhile, a Quasi-cyclic LDPC code was introduced by Fossorier in an article entitled "Quasi-cyclic low density parity check codes from circulant permutation matrices", IEEE Trans. Inform. Theory, vol. 50, pp. 1788-1794, Aug. 414. In the Quasi-cyclic LDPC code, elements of a parity check matrix are cyclic- shifted identity matrices and 0 matrices instead of Os and Is on GF(2).

[48] Hereinafter, the technical aspect of the present invention will be described under an assumption of using the Quasi-cyclic LDPC code. However, it is obvious to those skilled in the art that the elements of a parity check matrix may be applied to LDPC codes that are described in GF(2). [49] Also, the technical aspect of the present invention will be described under fixed conditions of a sub-matrix size, the number of sub-matrices in a parity check matrix, and degree distribution of a parity check matrix. However, it is obvious to those skilled in the art that the present invention also relates to a method for changing a length of a n x n sub-matrix, a method for changing the number of sub-matrices, and a method for obtaining an information length and a coding rate changed through information bit row splitting according to variation of degree distribution of a parity check matrix.

[50] Eq. 1 shows 5x5 cyclic-permutation i πatrices.

Eq. 1

[52]

[53] As showr L in Eq. l, a sub-matrix S₁ Is obtained by cyclic- shifting columns of an identify matrix to the right as much as i.

[54] Hereinafter, a parity check matrix formed of 38x38 sub-matrices will be exemplary used for describing the technical aspect of the present invention. In this case, the sub- matrix is a cyclic permutation matrix, which is obtained by cyclic-shifting a 38x38 identify matrix or a 38x38 0 matrix.

[55] Table 1 shows LDPC parity check matrices according to an embodiment of the present invention.

[56] [57] Table 1

[Table 1] [Table ]

[58] [59] As shown in Table 1, 20 LDPC parity check matrices are generated by a method for generating a parity check matrix according to the present invention. The 20 LDPC parity check matrices have 456, 912, 1368, 1824, and 2280 bits of information lengths, and 456, 912, 1368, and 1824 bits of parity lengths. Therefore, it is possible to embody an encoder/decoder supporting 20 variable information lengths and code rates based on combination of the information lengths and parity lengths shown in Table 1.

[60] Fig. 1 is a diagram structurally illustrating relation among parity check matrices exemplary shown in Table 1. [61] In Fig. 1, a small square denotes a 456 x 456 matrix. C¹ _J blocks and P blocks denote information block and parity block, which are parts of each parity check matrix. These blocks will be described in detail using Eq. 2 to Eq. 8 and Eq. 12 in later.

[62] In general, a parity check matrix with excellent error correction performance is generated through optimizing degree distribution of a parity check matrix and cyclic distribution on a factor graph. Since the parity check matrices used in the present embodiment are related to each others, optimization is not independently performed for each of the parity check matrices. That is, optimization is performed simultaneously for all of the parity check matrices. Furthermore, optimization is performed using constraints of simple encoding and fast decoding convergence.

[63] Eq.2 is an equation exemplary showing a parity check matrix having a parity length of 456 bits and supporting 5 code rates. That is, Eq.2 is H¹ of Fig.1.

J

Eq.2

[65] Eq.3 is an equation exemplary showing a matrix P¹ which is a parity block in a parity check matrix of Eq.2.

[66]

0 0 - - - - - - - - - -

- 1 1 - - - - - - - - -

- - 2 2 - - - - - - - -

- - - 3 3 - - - - - - -

- - - - 4 4 - - - - - -

- - - - - 5 5 - - - - -

P

6 - - - - - 6 6 - - - -

- - - - - - - 7 7 - - -

_ _ _ _ _ _ _ _ _{8 8} _ _

- - - - - - - - - 9 9 -

- - - - - - - - - - 10 10

_!! _ _ _ _ _ _ _ _ _ _ π

Eq.3

[67]

[68] In Eq.3, "-" denotes 38x380 matrix. Each of the numerals, which is not "-", denotes a 38x38 cyclic permutation matrix S₁, where "i" is 0 to 11. The parity block P¹ includes m mod 38 cyclic permutation matrices at (0,0), (6,0), (11,0), and (m, m-1) and (m, m) where l≤m≤l 1, and 0 matrices at remaining positions. That is, in case of a cyclic permutation matrix, remaining after dividing a row value of a basic matrix by 38 is used as elements of a cyclic permutation matrix. The parity check matrix is designed as described above because of constraint for making values of cyclic permutation matrices in the same column of a basic matrix not to be equal. Such a constraint is commonly applied to parity blocks and information blocks. Also, a parity check matrix having simple encoding and fast decoding convergence characteristics can be obtained by the constraint.

[69] In the present embodiment, the parity check matrix is also designed to make remaining values after dividing the values by 19 to be different as well as making values of cyclic permutation matrices in the same column to be different. Such a constraint may be useful if a convergence speed of a decoder increases two times while complexity increases two times or if a size of a sub-matrix increases or decreases two times.

[70] Since such a parity block P¹ is a dual-diagonal sub-matrix, it can be used to embody a partial block based parallel LDPC encoder. If the parity block having a form of a dual diagonal sub-matrix, encoding complexity can be minimized. Although the parity block P¹ is a matrix satisfying linearly independent condition, the parity block P¹ according to the present embodiment may be divided into independent 38 matrices satisfying linearly independent condition. If the parity blocks shown in Eq. 3 are used, it is possible to embody an encoder having low complexity and a decoder having a fast decoding convergence speed.

[71] The dual diagonal parity block was introduced in an article by Richardson, entitled

"Efficient Encoding of Low-Density Parity-Check Codes", IEEE Trans, on Inform. Theory, Vol. 47, No. 2, Feb. 411. Therefore, detailed description thereof is omitted.

[72] Eq. 4 to Eq. 8 are equations exemplary showing the first to fifth information blocks C

¹O, C¹I, C¹Z, C¹S, and C₄, in Eq. 2.

[73]

- 19° - 26¹ - 5² - - 4³ -

30° - 5¹ - - - - O² - - 30³ -

23° 2¹ — — — O² — - - - - 15³

— — 14° 15¹ — — 5² - - 12³ - -

0° — 19¹ — 12² — — 29³

- 17° - 18¹ -- -- -- 36²

C¹ =

— 5° 20¹ — — — 17² I I³ -

31° — — 31¹ 30² — — - 5³

14° - - 16¹ - 3² - 35³

32° 34¹ — — — — 30²

— — 30° 25¹ — — — 31² I I³

35° 17¹ 9² I³

Eq. 4

[74] - 17³ 12° - - 2T - - - 27² -

- 36³ - 24° - - - 28¹ - 33² -

8³ 7° - - - I I¹ - - - - - 22²

17³ - 30^c - 33²

- 8° I I¹

18³ 28° - - - - 36¹ - - -

23³ - 10° - 35¹ - - - 27² -

- 31³ 28° - - 32¹ 17² -

- 14³ - 6° - 10¹ - - - 32²

- O³ 7° - 20¹ - - - 35²

Eq. 5

[75]

24² 27³ 10° 14¹

8² 28³ — — — 19° — — — — 26¹ —

14² - O³ — — 29° — — — — — 21¹

- 15² - 6³ - - - 6° - 4¹ - -

— — 32² 17³ — — — — — — 16° I I¹

10² — 18³ — 5° 6¹ — — —

C¹ = 15² O³ 32° 5¹

— — 23² 2³ 22° — — — — — 6¹ —

28² 2³ - — — — — — 33° 28¹ — —

- 8² - 24³ — 15° 12¹ — — — — —

6² - I I³ - 33° - - - 5¹ - - -

- 36² - 28³ - - - 19° - - - 31¹

Eq. 6

[76] - - 15¹ 2² - - I I³ 3°

- I¹ - 4² - - 16³ - 33°

15¹ O² - 34³

32¹ - 3² - 32³ - - 33° - - -

- 21¹ - 31² - - T - - - 24°

16¹ 36² - - - - - 31³ 15° - -

³ ^ - S² - - 5³ - - - - 0°

- 5¹ - 37² 6³ - - 6^ϋ

- 37¹ 19² - - - - 9³ - 32° 27¹ - 16² - 37³ 36°

- 30¹ 16² - 15³ - 24° ^> 2

3

Eq. 7

[77]

37° 26¹ - - - 24² - 34³ -

30° - 28¹ - 18² - - - - 10³

7° 29¹ - 25² - - 33³

29° - - 3¹ - - 3² - 10³ - - -

- - 35° 7¹ - - - - - 6² 6³ -

6° 20¹ - - - - - - 31² - - 30³

C¹ -

- - 28° 16¹ 35² - - 34³ - - - -

31° 21¹ - - - 26² O³ - - - - -

18° - 22¹ - - - - 35² - 33³ - -

2° - - 15¹ 22² - - - - - 20³ -

- - 34° 21¹ - 2² - - 25³ - - -

27° 33¹ _ _ _ _ 15² _ _ _ _ 18³

Eq. 8

[78]

[79] In Eq. 4 to Eq. 8, integers denote cyclic permutation matrices obtained by cyclic- shifting 38x38 identify matrices to the right as much as the integer itself. "-" denotes a 38x38 0 matrix like Eq. 3. For example, in Eq. 4, 37¹ denotes cyclic permutation matrix S₃₇.

[80] In Eq. 4 and Eq. 8, exponents are used to generate information blocks included in parity check matrices H², H³, and H⁴ of Eq. 9 to Eq. 11, which are generated by applying row splitting at first to fifth information blocks of Eq. 2. The row splitting will be described in later with reference to Eq. 12.

[81] The first information block O₀ in Eq. 4 and the parity check matrix [C¹ _O P¹] formed of a parity block P¹ in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 456 bits and a code rate of 1/2.

[82] The first and second information blocks O₀ andC'i in Eq. 4 and Eq. 5 and a parity check matrix [C¹ _I O₀ P¹] formed of parity block P¹ shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 912-bits and a code rate of 2/3.

[83] The first to third blocks C¹ _O, C¹ _I1 and O₂ shown in Eq. 4 to Eq. 6 and a parity check matrix [O₂ C¹ _I O₀ P¹] formed of parity block P¹ shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 1368 bits and a code rate of 3/4.

[84] The first to fourth blocks C¹ _O, C¹ _I, C_2, and O₃ shown in Eq. 4 to Eq. 7 and a parity check matrix [O₃ O₂ C¹ _I C¹ _O P¹] formed of parity block P¹ shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 1824 bits and a code rate of 4/5.

[85] The first to fifth blocks C¹ _O, C¹ _I, C_2, C_3, and O₄ shown in Eq. 4 to Eq. 8 and a parity check matrix [O₄ O₃ O₂ C¹I C¹ _O P¹] formed of parity block P¹ shown in Eq. 3 are used for encoding and decoding a LDPC code having an information length of 2280 bits and a code rate of 5/6.

[86] As shown in Eq. 4 to Eq. 8, the parity check matrices designed for obtaining a fast decoding convergence speed is an example of design that makes values of cyclic permutation matrices in the same column not to be the same and makes remaining values after dividing the values by 19 not to be the same. As described above, such restriction may be useful when a convergence speed of a decoder increases two times while complexity increases two times.

[87] Meanwhile, the matrices in Eq. 3 to Eq. 8 are examples for describing a technical aspect of the present invention. It is obvious to those skilled in the art that various matrices having matrix sizes of Eq. 3 to Eq. 8 may be generated through optimization of degree distribution and cycle distribution beside the matrices in Eq. 3 to Eq. 8.

[88] Eq. 9 to Eq. 11 show parity check matrices having parity lengths of 912 bits, 1368 bits, and 1824 bits, and supporting five code rates. That is, Eq. 9 to Eq. 11 denote H², H³, and H⁴ in Fig. 1.

Eq. 9 [90]

Eq. 10

[92]

Eq. 11

[94]

[95] The information blocks H², H³, and H⁴ are generated by applying row splitting shown in Eq. 12 to the information block H¹. That is, O₁Is obtained by applying row splitting to Oi where j=2, 3, 4, and i=0, 1, 2, 3, and 4. For example, C³ ₂ of Eq. 10 is obtained by applying row splitting on O₂.

[96] The parity blocks H², H³, and H⁴ are generated by expanding a parity block H¹ with the same structure. That is, the parity block P² of Eq. 9 includes m mode 38 cyclic permutation matrices at (0, 0), (12, 0), and (23, 0) and (m, m-1) and (m, m) where l≤m<23 and 0 matrices at other positions. Therefore, the parity block p² has the same structure of the parity block P¹ in Eq. 3. Also, a parity block P³ of Eq. 10 includes m mode 38 cyclic permutation matrices at (0, 0), (18, 0), (35, 0), and (m, m-1), and (m, m) where l≤m<35 and 0 matrices at remaining positions. Therefore, the parity block P 3 has the same structure of the parity block P¹ shown in Eq. 3. Furthermore, a parity block P⁴ of Eq. 11 includes m mode 38 cyclic permutation matrices at (0, 0), (24, 0), (47, 0), and (m, m-1), and (m, m) where l≤m<47 and 0 matrices at remaining positions. Therefore, the parity block P⁴ has the same structure of the parity block P¹ shown in Eq. 3.

[97] The parity check matrices [C² ₀ P²], [C²! C² ₀ P²], [C² ₂ C²! C² ₀ P²], [C² ₃ C² ₂ C²! C² ₀ P²] and [C² ₄ C² ₃ C² ₂ C²i C² ₀ P²] can support information lengths and code rates shown in Table 1.

[98] As described above, the exponents of Eq. 4 to Eq. 8 are used to generate each information block of parity check matrices H², H³, and H⁴ by applying row splitting to each of information blocks of the parity check matrix H¹. The row splitting according to the present embodiment is performed using Eq. 12.

[99]

[100] 4

where /(C) =

, , f x , ymod / = (z + £)mod / where g*(-i) = -i, gV) = / / . , /.

-1 ,ymodj ≠ (i + k)modj

Eq. 12

[101] [102] Eq. 12 is an equation expressing row splitting according to the present embodiment. In of Eq. 12, "-1" denotes 0 sub-matrix.

[103] In Eq. 12, C_™ denotes sub matrices at (m, n) of an information block formed of MN sub-matrices where m = 1, 2, ..., M, and n = 1, 2, ..., N. If C is C¹O in./ϊ(C)of Eq. 12, M is 12 and N is 12, and C₁₂ is 27°.

[104] Three embodiments of the present invention for designing a LDPC code having a variable information length and a variable code rate are disclosed. The first embodiment generates a new parity check matrix by adding a second information block to a parity check matrix formed of a first information block and a parity block, which is different from the parity check matrix in an information length or a code rate. The second embodiment generates a new parity check matrix different from a basic parity check matrix in an information length or a code rate by generating an expanded information block through applying row splitting to the base information block and by generating an expanded parity block having the same structure of the base parity block when a parity check matrix formed of the basic information block and the basic parity block is provided. The third embodiment is combination of the first and third embodiments.

[105] In the present embodiments, a target information block for row splitting is a basic information block, and an expanded information block is an information block obtained by applying row splitting to the basic information block. Also, a target parity block for expanding is a basic parity block, and an expanded parity block is a result parity block of expanding the basic parity block. [106] In the first embodiment, parity check matrices are generated by expanding information blocks with a parity block fixed, and an information block is expanded in order to generate an excellent parity check matrix in a view of degree distribution and cycle distribution.

[107] In the second embodiment, an expanded parity check matrix is generated to be different from a basic parity check matrix through performing row splitting on an information block having a basic parity check matrix. Here, a row splitting scheme is applied to generate a parity check matrix good in degree distribution and cycle distribution.

[108] The three embodiments will be described based on generation of a large parity check matrix from a small parity check matrix, and it is obvious to those skilled in the art that inverse operations are also possible.

[109] In case of the first embodiment, a large parity check matrix is generated first. Then, a small parity check matrix may be generated by removing a part of an information block in the generated large parity check matrix. In case of the second embodiment, a large basic parity check matrix is generated first. Then, a small parity check matrix may be generated by applying row combining, which is an inverse operation of row splitting, to the information block of the generated basic parity check matrix and applying parity part switching that uses a predetermined part of a parity block of the generated basic parity check matrix. Here, the row combining can be expressed parity combining of parity part. The parity part switching can be expressed as parity combining of a parity part.

[110] Meanwhile, it is possible to design a LDPC code supporting more various information lengths and code rates by applying an information shortening scheme and a puncturing scheme on a method for designing a LDPC code having a variable information length and a variable code rate according to the present embodiment.

[I l l] Fig. 2 is a diagram for describing an information shortening scheme and a puncturing scheme in a parity check matrix in accordance with an embodiment of the present invention.

[112] Fig. 2 shows an example of shortening information as much as K-K_eff bits and puncturing n_p parity bits in a k x n parity check matrix shown in a right upper corner. Here, a k x n parity check matrix basically supports a k/n code rate and a k information length.

[113] A vector, shown in a left upper corner, is a k x 1 input message vector. The vector includes an information word formed of k_eff information bits and k-k_eff Os filled by information shortening. That is, an information length according to the present embodiment is k_eff. A n-bits code word is generated by multiplying such an input message vector with a parity check matrix. Then, n_p parity bits are punctured from the generated code ward, and k-k_eff Os are deleted. As a result, a length of a final code word becomes n-k+k_efrn_p. In this case, a k_eff information length and a k_eff/(n-k+k_efrn_p) code rate may be provided, which are different from a k/n code rate and a k information length that are basically provided by a parity check matrix.

[114] Although Fig. 2 shows examples of information shortening and puncturing for parity bits, it is possible to apply only one of information shortening and puncturing. Further various information lengths and code rates may be supported if information shortening and puncturing are effectively applied.

[115] In the present embodiment, information shortening and puncturing are performed without a parity check matrix changed by performing 0 fading before multiplying an input message vector and a parity check matrix and performing puncturing after multiplying an input message vector and a parity check matrix. Beside of the described method, a code word having a n-k+k_eff-n_p length may be generated by generating a parity check matrix having a new size k_effX(n-k+k_eff-n_p) by applying information shortening and puncturing to a parity check matrix itself and multiplying the generated parity check matrix with an input message vector having a length of keffxl. In this case, a parity check matrix having a size of k_effX(n-k+k_eff-n_p) is obtained by removing the left most k_eff columns, the right most n_p columns, and the upper most k_eff rows.

[116] Since it is obvious to those skilled in the art that a LDPC code according to the present embodiment can be easily encoded and decoded through performing various well-known encoding/decoding methods, descriptions of encoding/decoding operations are omitted.

[117] Fig. 3 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with an embodiment of the present invention.

[118] As shown in Fig. 3, an apparatus for generating a parity check matrix according to the present embodiment includes a first parity check matrix generator 31 for generating a first parity check matrix and q parity check matrix generators 32 to 35 for generating q parity check matrices by adding an q information block to the generated q-1 parity check matrix where l<q≤Q and Q is an integer greater than 2.

[119] The parity check matrix generating apparatus further includes an information shortening unit 36 for generating the first to Q parity check matrices and at least one of parity check matrices by applying information shortening at least one of the first to Q parity check matrices.

[120] The parity check matrix generating apparatus according to the present embodiment further includes a puncturing unit 37 for generating at least one of parity check matrices different from the first to Q parity check matrices by applying puncturing on at least one of the first to Q parity check matrices.

[121] Here, the q parity check matrix generators 32 to 35 generates a q parity check matrix by performing degree distribution and cycle distribution with constraints for a simple encoding structure and a fast decoding convergence speed.

[122] The apparatus for generating a parity check matrix according to the present embodiment will be described in detail with reference to Eq. 2 to Eq. 8.

[123] The first parity check matrix generator 31 generates a first parity matrix [O₀ P¹] formed of a first information block O₀ shown in Eq. 4 and a parity block P₁ shown in Eq. 3.

[124] The second parity check matrix generator 32 generates a second parity check matrix [C¹ _I CO P¹] by adding a second information block C¹ _I of Eq. 5 to the first parity check matrix [C₀ P¹] generated by the first parity check matrix generator 31.

[125] The third parity check matrix generator 33 generates a second parity check matrix [C l₂ C¹ _I CO P¹] by adding a third information block O₂ of Eq. 6 to the second parity check matrix [C¹ _I O₀ P¹] generated by the second parity check matrix generator 32.

[126] The fourth parity check matrix generator 34 generates a third parity check matrix [O₃ O₂ C¹ _I C¹ _O P¹] by adding a fourth information block O₃ of Eq. 7 to the third parity check matrix [O₂ C¹I C¹ _O P¹] generated by the third parity check matrix generator 33.

[127] The fifth parity check matrix generator 35 generates a fifth parity check matrix [O₄ C !₃ C₂ C¹I C¹ _O P¹] by adding a fifth information block O₄ of Eq. 8 to the fourth parity check matrix [O₃ O₂ C¹ _I C¹ _O P¹] generated by the fourth parity check matrix generator 34.

[128] The information shortening unit 36 generates at least one of parity check matrices different from the first to fifth parity check matrices by applying information shortening to at least one of the first to fifth parity check matrices generated by the first to fifth parity check matrices 31 to 35.

[129] The puncturing unit 37 generates at least one of parity check matrices different from the first to fifth parity check matrices by applying puncturing scheme on at least one of the first to fifth parity check matrices generated by the first to fifth parity check matrix generators 31 to 35.

[130] Fig. 4 is a diagram illustrating an apparatus for generating a parity check matrix in accordance with another embodiment of the present invention.

[131] As shown in Fig. 4, the apparatus for generating a parity check matrix according to the present embodiment includes a basic parity check matrix generator 41 for generating at least one of basic parity check matrices and an expanded parity check matrix generator 42 for generating at least one of expanded parity check matrices by applying row splitting on an information block of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.

[132] Also, the apparatus for generating a parity check matrix according to the present embodiment further includes an information shortening unit 43 for generating at least one of parity check matrices different from the expanded parity check matrix by applying information shortening to at least one of the basic parity check matrix and the expanded parity check matrix.

[133] Furthermore, the apparatus for generating a parity check matrix according to the present embodiment further includes a puncturing unit 44 for generating at least one of parity check matrices different from the basic parity check matrix and the expanded parity check matrix by applying a puncturing scheme on at least one of the basic parity check matrix and the expanded parity check matrix.

[134] Here, the basic parity check matrix generator 41 generates a first basic parity check matrix formed of a first basic information block and a basic parity block, and generates a q basic parity check matrix by adding a q basic information block to the generated q- 1 basic parity check matrix where l<q≤Q and Q is an integer greater than 2. The expanded parity check matrix generator 42 generates an expanded parity block by expanding the basic parity block, generates a q expanded information block by applying row splitting on the q basic information block, and generates a q expanded parity check matrix formed of the expanded parity block and the first to Q expanded information blocks.

[135] The expanded parity check matrix generator 42 generates an expanded parity block having the same structure of the basic parity block. Here, the basic parity block and the expanded parity block has a form of a dual diagonal matrix in order to have a simple encoder and a fast decoding convergence speed.

[136] The basic parity check matrix generator 41 generates a basic parity check matrix by optimizing constraints for having simple encoding and fast decoding convergence characteristics, degree distribution, and cycle distribution. The expanded parity check matrix generator 42 generates an expanded parity check matrix by optimizing constraints for having simple encoding and fast decoding convergence characteristics, degree distribution, and cycle distribution.

[137] That is, the apparatus for generating a parity check matrix according to the present embodiment shown in Fig. 4 generates matrices H², H³, and H⁴ of Eq. 9 to Eq. 11 from the matrix H¹ of Eq. 2.

[138] The basic parity check matrix generator 41 generates at least one of basic parity check matrices. For example, the basic parity check matrix generator 41 shown in Fig. 4 will be described with assumption that the basic parity check matrix generator 41 generates one basic parity matrix [C¹ P¹].

[139] The expanded parity check matrix generator 42 generates C² by applying row splitting on the information block C¹ of the basic parity check matrix [C¹ P¹], and generates a parity block P² having the same structure of the P¹ by expanding the parity block P¹ of the basic parity check matrix [C¹ P¹]. As a result, an expanded parity check matrix [C² P²] is generated.

[140] The information shortening unit 43 generates at least one of parity check matrices different from the basic parity check matrix [C¹ P¹] and the expanded parity check matrix [C² P²] by applying information shortening on at least one of the basic parity check matrix [C¹ P¹] and the expanded parity check matrix [C² P²].

[141] The puncturing unit 44 generates at least one of parity check matrices different from the basic parity check matrix [C¹ P¹] and the expanded parity check matrix [C² P²] by puncturing at least one of the basic parity check matrix [C¹ P¹] and the expanded parity check matrix [C² P²].

[142] The expanded parity check matrix generator 42 may generates expanded parity check matrices [C² ₀ P²], [C²! C² ₀ P²], [C² ₂ C²! C² ₀ P²], [C² ₃ C² ₂ C²! C² ₀ P²], and [C² ₄ C² ₃ C² ₂ C²! C²o P²] from the first to fifth basic parity check matrices if the basic parity check matrix generator 41 generates the first to fifth basic parity check matrices [O₀ P¹], [C¹ _I C₀ P¹ ], [O₂ C¹I O₀ F], [O₃ O₂ O₁ O₀ F], and [O₄ O₃ O₂ O₁ O₀ F].

[143] Fig. 5 is a diagram illustrating a LDPC encoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.

[144] The LDPC encoding apparatus supporting a variable information length and a variable code rate according to the present embodiment includes a parity check matrix selector 51 for selecting a parity check matrix corresponding to inputted coding parameter among a plurality of parity check matrices, and an encoder for encoding inputted information word based on the parity check matrix selected by the parity check matrix selector 51. The plurality of parity check matrices include a first parity check matrix formed of a first information block and a parity block and a q parity check matrix formed by adding a q information block to a q-1 parity check matrix where l<q≤Q and Q is an integer greater than 2.

[145] Here, the inputted coding parameter includes a code rate and a length of the inputted information word.

[146] The plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on at least one of the first to Q parity check matrices.

[147] The plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the first to Q parity check matrices.

[148] A LDPC encoding apparatus supporting a variable information length and a variable code rate according to another embodiment of the present invention includes a parity check matrix selector 51 for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrices and an encoder for encoding an inputted information word based on the parity check matrix selected by the parity check matrix selector 51. The plurality of parity check matrices includes at least one of expanded parity check matrices generated by applying row splitting on at least one of the basic parity check matrix and the basic parity check matrix and expanding a parity block of the basic parity check matrix.

[149] Here, the inputted coding parameter includes a code rate and a length of the inputted information word.

[150] The plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on the basic parity check matrix and the expanded parity check matrix.

[151] The plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the basic parity check matrix and the expanded parity check matrix.

[152] Hereinafter, each of constituent elements will be described with reference to Fig. 5.

[153] The parity check matrix selector 51 selects a parity check matrix corresponding to an inputted coding parameter among the plurality of parity check matrices. Here, the plurality of parity check matrices denote parity check matrices generated the apparatuses shown in Figs. 3 and 4. The inputted coding parameters are a parameter used for selecting a parity check matrix, such as an information length and a coding rate. However, the parity check matrix is not limited thereto.

[154] The encoder 52 encodes an inputted information word based on the selected parity check matrix from the parity check matrix selector 51 and outputs a code word.

[155] Fig. 6 is a diagram illustrating a LDPC decoding apparatus having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.

[156] Referring to Fig. 6, the LDPC decoding apparatus according to the present embodiment includes a parity check matrix selector 61 for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrices and a decoder 62 for decoding a received codeword based on the parity check matrix selected by the parity check matrix selector 61. The plurality of parity check matrices includes a first parity check matrix formed of a first information block and a parity block and a q parity check matrix formed by adding a q information block into a q-1 parity check matrix where l<q≤Q and Q is an integer greater than 2.

[157] The inputted decoding parameter includes a code rate and an information length of the received codeword.

[158] The plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on at least one of the first to Q parity check matrices. The decoder 62 performs decoding by setting a probability that the information shortening bit is 0 to 1 if the selected parity check matrix is a matrix with information shortening applied.

[159] The plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the first to Q parity check matrices, and the decoder 62 performs decoding by setting a probability that the information shortening bit is 0 to 1/2 if the selected parity check matrix is a matrix with puncturing applied.

[160] A LDPC decoding apparatus supporting a variable information length and a variable code rate according to another embodiment includes a parity check matrix selector 61 for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrices, and a decoder for decoding a received codeword based on the parity check matrix selected by the parity check matrix selector 61. The plurality of parity check matrices include at least one of expanded parity check matrices by applying row splitting on an at least one of the basic parity check matrix and the information block of the basic parity check matrix and expanding a parity block of the basic parity check matrix.

[161] Here, the inputted decoding parameters includes a code rate and an information length of the receive codeword.

[162] The plurality of parity check matrices further include at least one of parity check matrices generated by applying information shortening on at least one of the basic parity check matrix and the expanded parity check matrix. The decoder 62 performs decoding by setting a probability that an information shortening bit is 0 to 1 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with information shortening applied.

[163] Also, the plurality of parity check matrices further include at least one of parity check matrices generated by puncturing at least one of the basic parity check matrix and the expanded parity check matrix, and the decoder 62 performs decoding by setting a probability that an information shortening bit is 1 to 1/2 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with information shortening applied.

[164] Hereinafter, each of constituent elements will be described with reference to Fig. 6.

[165] The parity check matrix selector 61 selects a parity check matrix corresponding to an input decoding parameter from a plurality of parity check matrices. Here, a plurality of parity check matrices denote parity check matrices generated by the apparatuses shown in Figs. 3 and 4. The inputted decoding parameter is a parameter used to select a parity check matrix, for example, a code rate and an information length of a received codeword. However, the inputted decoding parameter is not limited thereto.

[166] The decoder 62 decodes a received codeword based on the parity check matrix selected by the parity check matrix selector 61. Here, a message passing algorithm (MPA) is used as a decoding algorithm. The decoder 62 performs decoding by setting a probability that an information shortening bit is 0 to 1 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with information shortening scheme applied. The decoder 62 performs decoding by setting a probability that an information shortening bit is 1 to 1/2 if the parity check matrix selected by the parity check matrix selector 61 is a matrix with the puncturing scheme applied.

[167] Fig. 7 is a flowchart illustrating a method for generating a parity check matrix in accordance with an embodiment of the present invention.

[168] Referring to Fig. 7, the method for generating a parity check matrix according to the present embodiment includes steps performed in a time domain in the apparatus for generating a parity check matrix shown in Fig. 3. Therefore, the description of the apparatus for generating a parity check matrix of Fig. 3 is also applied to a method for generating a parity check matrix according to the present embodiment although some parts of detail description of the method may be omitted.

[169] Hereinafter, the method for generating a parity check matrix according to the present embodiment will be described with reference to Figs. 3 and 7.

[170] At step S71, the first parity check matrix generates a first parity check matrix formed of a first information block and a parity block.

[171] At step S72, the second parity check matrix generates a second parity check matrix by adding a second information block to the generated first parity check matrix.

[172] At step S73, the third parity check matrix generates a third parity check matrix by adding a third information block to the generated second parity check matrix.

[173] At step S74, the fourth parity check matrix generates a fourth parity check matrix by adding a fourth information block to the generated third parity check matrix.

[174] At step S75, the fifth parity check matrix generates a fifth parity check matrix by adding a fifth information block to the generated fourth parity check matrix.

[175] At step S76, the information storing unit 36 additionally generates at least one of parity check matrices different from the first to fifth parity check matrices by applying information shortening on at least one of the generated first to fifth parity check matrices, and the puncturing unit 37 additionally generates at least one of parity check matrices different from the first to fifth parity check matrices by puncturing at least one of the first to fifth parity check matrices.

[176] Fig. 8 is a flowchart illustrating a method for generating a parity check matrix in accordance with another embodiment of the present invention.

[177] Referring to Fig. 8, the method for generating a parity check matrix according to another embodiment includes steps performed in a time domain by the apparatus for generating a parity check matrix shown in Fig. 4. Therefore, the description of the apparatus for generating a parity check matrix of Fig. 4 is also applied to a method for generating a parity check matrix according to the present embodiment although a part of detail description of the method is omitted.

[178] The method for generating a parity check matrix according to another embodiment will be describe with Figs. 4 and 8.

[179] At step S81, the basic parity check matrix generator 41 generates at least one of basic parity check matrices.

[180] At step S 82, the expanded parity check matrix generator 42 generates at least one of expanded parity check matrices by applying row splitting on an information block of the basic parity check matrix and expanding a parity block of the basic parity check matrix.

[181] At step S83, the information shortening unit 43 generates at least one of parity check matrices different from the basic parity check matrix and the expanded parity check matrix by applying information shortening on at least one of the generated basic parity check matrix and the expanded parity check matrix, and the puncturing unit 44 generates at least one of parity check matrices different from the basic parity check matrix and the expanded parity check matrix by puncturing at least one of the generated basic parity check matrix and the expanded parity check matrix.

[182] Fig. 9 is a flowchart illustrating a LDPC encoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention.

[183] Referring to Fig. 9, the LDPC encoding method supporting a variable information length and a variable code rate according to the present embodiment includes steps performed in time series by the LDPC encoding apparatus supporting a variable information length and a variable code rate of Fig. 5. Therefore, the description of the LDPC encoding apparatus of Fig. 5 is also applied to the LDPC encoding method according to the present embodiment although a part of detail description of the method is omitted.

[184] The LDPC encoding method according to the present embodiment will be described with reference to Figs. 5 and 9.

[185] At step S91, the parity check matrix selector 51 selects a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrices. Here, the plurality of parity check matrices denote parity check matrices generated the apparatuses shown in Figs. 3 and 4.

[186] At step S92, the encoder 52 encodes an inputted information word based on the selected parity check matrix.

[187] Fig. 10 is a flowchart illustrating a LDPC decoding method having simple encoding and fast decoding convergence characteristics, variable information length, and a variable coding rate in accordance with an embodiment of the present invention. [188] Referring to Fig. 10, the LDPC decoding method supporting a variable information length and a variable code rate according to the present embodiment includes steps performed in time series by the LDPC decoding apparatus supporting a variable information length and a variable code rate of Fig. 6. Therefore, the description of the LDPC decoding apparatus of Fig. 6 is also applied to the LDPC decoding method according to the present embodiment although a part of detail description of the method is omitted.

[189] The LDPC decoding method according to the present embodiment will be described with reference to Figs. 6 and 10.

[190] At step SlOl, the parity check matrix selector 61 selects a parity check matrix corresponding to an inputted decoding parameter from the plurality of parity check matrices. Here, the plurality of parity check matrices denote parity check matrices generated by the apparatuses shown in Figs. 3 and 4.

[191] At step SlOl, the decoder 62 decodes a received codeword based on the selected parity check matrix.

[192] The methods of the present invention may be programmed in a computer language. Codes and code segments constituting the computer program may be easily inferred by a computer programmer skilled in the art. Furthermore, the computer program may be stored in a computer-readable recording medium including all kinds of media such as CD-ROM, RAM, ROM, floppy disk, hard disk and magneto-optical disk, and read and executed by a computer to embody the methods.

[193] The present application contains subject matter related to Korean Patent Application No. 2007-0132008, filed in the Korean Intellectual Property Office on December 17, 2007, the entire contents of which are incorporated herein by reference.

[194] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

[1] An apparatus for generating a parity check matrix of a low density parity check

(LDPC) code, comprising: a first parity check matrix generating means for generating a first parity check matrix formed of a first information block and a parity block; and a q parity check matrix generating means for generating a q parity check matrix by adding a q information block to the generate q-1 parity check matrix where l<q≤Q and Q is an integer greater than 2.

[2] The apparatus of claim 1, further comprising an information shortening means for generating at least one of parity check matrixes different from the first to Q parity check matrixes by applying information shortening on at least one of the first to q parity check matrixes.

[3] The apparatus of claim 1, further comprising a puncturing means for generating at least one of parity check matrixes different from the first to Q parity check matrixes by puncturing at least one of the first to q parity check matrixes.

[4] The apparatus of claim 1, wherein the q parity check matrix generation means generates a q parity check matrix by optimizing restriction for having a simple encoding structure and a fast decoding convergence speed, degree distribution, and cycle distribution.

[5] An apparatus for generating a parity check matrix for a low density parity check

(LDPC) code, comprising: a basic parity check matrix generating means for generating at least one of basic parity check matrixes; and an expanded parity check matrix generating means for generating at least one of expanded parity check matrixes by applying row splitting on an information of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.

[6] The apparatus of claim 5, further comprising an information shortening means for generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by applying information shortening on at least one of the basic parity check matrix and the expanded parity check matrix.

[7] The apparatus of claim 5, further comprising a puncturing means for generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by puncturing at least one of the basic parity check matrix and the expanded parity check matrix.

[8] The apparatus of claim 5, wherein the basic parity check matrix generating means generates a first basic parity check matrix formed of a first basic information block and a basic parity block and a q basic parity check matrix by adding a q basic information block to a generated q-1 basic parity check matrix where l<q≤Q and Q is an integer greater than 2, and the expanded parity check matrix generating means generates an expanded parity block by expanding the basic parity block, generates a q expanded information block by applying row splitting on the q basic information block, and generates a q expanded parity check matrix formed of the expanded parity block and the first to Q expanded information blocks.

[9] The apparatus of claim 8, wherein the expanded parity check matrix generating means generates the expanded parity block having a structure identical to the basic parity block.

[10] The apparatus of claim 9, wherein the basic parity block and the expanded parity block have a form of a dual diagonal matrix with restriction for having a simple encoder and a fast decoding convergence speed.

[11] The apparatus of claim 5, wherein the basic parity check matrix generating means generates a basic parity check matrix by optimizing restriction for having a simple encoding structure and a fast decoding convergence speed, degree distribution, and cycle distribution, and the expanded parity check matrix generating means generates an expanded parity check matrix by optimizing restriction for having a simple encoding structure and a fast decoding convergence speed, degree distribution, and cycle distribution.

[12] An apparatus for encoding a low density parity code (LDPC), comprising: a parity check matrix selecting means for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrixes; and an encoding mans for encoding an information word based on the selected parity check matrix from the parity check matrix selecting means, wherein the plurality of parity check matrixes includes a first parity check matrix formed of a first information block and a parity block, and a q parity check matrix formed by adding a q information block to a q-1 parity check matrix where l<q≤Q and Q is an integer is greater than 2.

[13] The apparatus of claim 12, wherein the plurality of parity check matrixes further include at least one of parity check matrixes generated by applying information shortening on at least of the first to q parity check matrixes.

[14] The apparatus of claim 12, wherein the plurality of parity check matrixes further includes at least one of parity check matrixes generated by puncturing at least one of the first to q parity check matrixes.

[15] An apparatus for encoding a low density parity check (LDPC) code, comprising: a parity check matrix selecting means for selecting a parity check matrix corresponding to an inputted coding parameter from a plurality of parity check matrixes; and an encoding means for encoding an information word based on the selected parity check matrix from the parity check matrix selecting means, wherein the plurality of parity check matrixes include at least one of basic parity check matrixes and at least one of expanded parity check matrixes generated by expanding a parity block of the basic parity check matrix by applying row splitting on an information block of the basic parity check matrix.

[16] The apparatus of claim 15, wherein the plurality of parity check matrixes further includes at least one of parity check matrixes generated by applying information shortening on at least of one of the basic parity check matrix and the expanded parity check matrix.

[17] The apparatus of claim 15, wherein the plurality of parity check matrixes further include at least one of parity check matrixes generated by puncturing at least one of the basic parity check matrix and the expanded parity check matrix.

[18] An apparatus for decoding a low density parity check (LDPC) code, comprising: a parity check matrix selecting means for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrix; and a decoding means for decoding a received codeword based on the selected parity check matrix from the parity check matrix selecting means, wherein the plurality of parity check matrixes includes a first parity check matrix formed of a first information block and a parity block and a q parity check matrix generated by adding a q information block to a q- 1 parity check matrix wherein l<q≤Q and Q is an integer greater than 2.

[19] The apparatus of claim 18, wherein the plurality of parity check matrixes further includes at least one of parity check matrixes generated by applying information shortening at least one of the first to q parity check matrixes, and the decoding means performs decoding by setting a probability that an information shortening bit is 0 to 1 if the selected parity check matrix is a matrix with information shortening applied

[20] The apparatus of claim 18, wherein the plurality of parity check matrixes further includes at least one of parity check matrixes generated by puncturing at least one of the first to q parity check matrixes, and the decoding means performs decoding by setting a probability that an in- formation shortening bit is 0 to 1/2 if the selected parity check matrix is a matrix with puncturing applied.

[21] An apparatus for decoding a low density parity check (LDPC) code, comprising: a parity check matrix selecting means for selecting a parity check matrix corresponding to an inputted decoding parameter from a plurality of parity check matrixes; and a decoding means for decoding a received codeword based on the parity check matrix selected by the parity check matrix selecting means, wherein the plurality of parity check matrixes includes at least one of basic parity check matrixes and at least one of expanded parity check matrixes generated by applying row splitting on an information block of the basic parity check matrix and expanding a parity block of the basic parity check matrix.

[22] The apparatus of claim 21, wherein the plurality of parity check matrixes further include at least one of parity check matrixes generated by applying information shortening on at least one of the basic parity check matrix and the expanded parity check matrix, and the decoding means perform setting a probability that an information shortening bit is 0 to 1 if the selected parity check matrix is a matrix with information shortening applied.

[23] The apparatus of claim 21, wherein the plurality of parity check matrixes further includes at least one of parity check matrixes generated by puncturing at least one of the basic parity check matrix and the expanded parity check matrix, and the decoding means performs decoding by setting a probability that an information shortening bit is 0 to 1/2 if the selected parity check matrix is a matrix with puncturing applied.

[24] A method for generating a parity check matrix of a low density parity check

(LDPC) code, comprising: generating a first parity check matrix formed of a first information block and a parity block; and generating a q parity check matrix by adding a q information block to the generate q-1 parity check matrix where l<q≤Q and Q is an integer greater than

2

[25] The method of claim 24, further comprising generating at least one of parity check matrixes different from the first to q parity check matrixes by applying information shortening on at least one of the first to Q parity check matrixes.

[26] The method of claim 24, further comprising generating at least one of parity check matrixes different from the first to Q parity check matrixes by puncturing at least one of the first to Q parity check matrixes.

[27] A method for generating a parity check matrix of a low density parity check

(LDPC) code, comprising: generating at least one of basic parity check matrixes; and generating at least one of expanded parity check matrixes by applying row splitting on an information of the generated basic parity check matrix and expanding a parity block of the generated basic parity check matrix.

[28] The method of claim 27, further comprising generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by applying information shortening on at least one of the basic parity check matrix and the expanded parity check matrix.

[29] The method of claim 27, further comprising generating at least one of parity check matrixes different from the basic parity check matrix and the expanded parity check matrix by puncturing at least one of the basic parity check matrix and the expanded parity check matrix.