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WO2017118004A1 - 阵列基板及其制作方法以及显示装置 - Google Patents

阵列基板及其制作方法以及显示装置 Download PDF

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Publication number
WO2017118004A1
WO2017118004A1 PCT/CN2016/093240 CN2016093240W WO2017118004A1 WO 2017118004 A1 WO2017118004 A1 WO 2017118004A1 CN 2016093240 W CN2016093240 W CN 2016093240W WO 2017118004 A1 WO2017118004 A1 WO 2017118004A1
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Prior art keywords
layer
array substrate
active layer
barrier
source
Prior art date
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Ceased
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PCT/CN2016/093240
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English (en)
French (fr)
Inventor
林子锦
赵海生
彭志龙
孙东江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US15/537,209 priority Critical patent/US20170373099A1/en
Publication of WO2017118004A1 publication Critical patent/WO2017118004A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6725—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having supplementary regions or layers for improving the flatness of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • a basic structure of a TFT-LCD includes an array substrate, a counter substrate, and a liquid crystal layer interposed between the array substrate and the opposite substrate.
  • a plurality of sub-pixel units arranged in a matrix are disposed on the array substrate, and each of the sub-pixel units is provided with a thin film transistor (TFT).
  • the thin film transistor generally includes a gate electrode, a gate insulating layer, an active layer, a source and drain, and the like.
  • the embodiment of the invention provides an array substrate, a manufacturing method thereof, and a display device, which are used to solve the problem that the electrical process of the TFT is poor due to the contact between the residue of the active layer and the conductive layer in the prior art.
  • At least one embodiment of the present invention provides an array substrate including: a gate insulating layer; an active layer; a source and a drain, the source and drain are in contact with the active layer; a first conductive layer; and a barrier insulating layer
  • the gate insulating layer is located on a surface of the active layer, the barrier insulating layer is located on another surface of the active layer, and the barrier insulating layer is at least in the active layer and the source drain
  • the contact region of the pole includes a first hollow structure; the barrier insulating layer is configured to block contact of the residue of the active layer outside the region where the first hollow structure is located with the first conductive layer.
  • At least one embodiment of the present invention provides an array substrate including: forming a gate insulating layer; forming a first patterned active layer; forming a second patterned source and drain in contact with the active layer, and third Pattern a first conductive layer; and a fourth patterned barrier insulating layer; the gate insulating layer is located on a surface of the active layer, and the barrier insulating layer is located on the other surface of the active layer, and The barrier insulating layer has a first hollow structure at least in a contact region of the active layer and the source and drain; the barrier insulating layer is configured to block residues of the active layer to overlap at least one conductive layer .
  • At least one embodiment of the present invention also provides a display device comprising the array substrate of any of the above claims.
  • one surface of the active layer is provided with a gate insulating layer, and the other surface is provided with a barrier insulating layer, which can effectively block the residues of the active layer from respectively connecting the data lines and
  • the pixel electrode avoids poor electrical process of the TFT.
  • the height difference of the surface of the entire array substrate after the formation of the active layer is reduced, the flatness of the surface of the film layer is improved, and the film layer caused by a large difference in the surface height of the film layer or a large slope angle is reduced. Breaking phenomenon.
  • FIG. 1 is a schematic diagram of a residue of an active layer overlapped with a data line and a pixel electrode in the prior art
  • FIG. 2(a) is a schematic structural view of an array substrate according to the present invention as a bottom gate structure array substrate;
  • FIG. 2(b) is a second schematic structural view of an array substrate according to the present invention as a bottom gate structure array substrate;
  • FIG. 2(c) is a third structural schematic view of the array substrate according to the present invention as a bottom gate structure array substrate;
  • FIG. 2(d) is a fourth structural schematic view of the array substrate according to the present invention as a bottom gate structure array substrate;
  • FIG. 3 is a schematic structural view of an array substrate according to the present invention as a top gate structure array substrate;
  • FIG. 4 is a flow chart showing steps of a method for fabricating a bottom gate junction array substrate according to an embodiment of the present invention
  • FIG. 5 is a flow chart showing the steps of a method for fabricating a top gate junction array substrate according to an embodiment of the present invention.
  • patterning can be performed by first depositing SiN x , a-Si, N+a-Si, and then patterning the deposited mixed film layer to form a patterned Active layer.
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display device.
  • the array substrate includes: a gate insulating layer, an active layer, a source and a drain in contact with the active layer, and a first conductive layer; and further, the array substrate further includes: a barrier insulating layer.
  • the gate insulating layer is located on a surface of the active layer, and the barrier insulating layer is located on the other surface of the active layer, and the barrier insulating layer has a first hollow structure at least in a contact region between the active layer and the source and drain; Contacting the residue of the active layer with any of the first conductive layers.
  • the active layer is insulated from the adjacent first conductive layer, thereby avoiding the residue of the active layer overlapping any of the first conductive layers, and particularly avoiding residues of the active layer overlapping the pixel electrode and the data.
  • the problem of poor TFT electrical electricity caused by the lap joint is solved.
  • the barrier layer is increased, and the thickness of the film layer can be appropriately adjusted, the height difference of the surface of the entire array substrate after the formation of the active layer is reduced, and the flatness of the surface of the film layer is improved. Therefore, in the case where the gradient angle of the surface of the film layer is small, the subsequent film layer can be better deposited, and the film layer fracture phenomenon caused by a large difference in the surface height of the film layer or a large slope angle can be reduced.
  • the first conductive layer involved in the embodiment of the present invention includes any one of a data line, a pixel electrode, a gate line, and a common electrode.
  • the barrier isolation layer has a second hollow structure in a region where the pixel electrode is located. Therefore, it is ensured that the barrier insulating layer can better block the residue of the active layer from overlapping with the other first conductive layer, and at the same time, can enhance the transmission of the entire array substrate by the second hollow structure formed in the region where the pixel electrode is located. rate.
  • FIG. 2(a) is a schematic structural view of an array substrate as a bottom gate structure array substrate according to an embodiment of the present invention.
  • the first conductive layer is used as a pixel electrode as an example.
  • the gate line 22 is located on the substrate substrate 21, the gate insulating layer 23 is over the gate line 22 and covers the array substrate, and the active layer 24 is located on the gate insulating layer 23.
  • the barrier layer 25 is disposed on the active layer 24, and the barrier layer 25 exposes the active layer 24 through the first hollow structure at the contact region S of the active layer 24 and the source and drain electrodes 26 (assuming an active layer is formed) There is a residue a), the source drain 26 is on the barrier edge layer 25 and is in contact with the exposed active layer 24.
  • the pixel electrode 27 is in overlapping contact with the source and drain electrodes 26, and the barrier insulating layer 25 blocks the overlap of the pixel electrode 27 with the residue a which may exist below.
  • the first open structure of the barrier insulating layer 25 in the contact region S between the active layer 24 and the source and drain electrodes 26 may be a via, and the source and drain electrodes 26 respectively pass through the via and the underlying active.
  • Layer 24 is in contact to ensure thin film transistor characteristics.
  • the above-mentioned bottom gate structure array substrate means that the thin film transistor on the array substrate adopts a bottom gate structure.
  • the top gate structure array substrate represents a top gate structure of the thin film transistor on the array substrate.
  • the pixel electrode 27 described above is a first conductive layer.
  • FIG. 2(b) is another schematic structural view of the array substrate according to the present invention as a bottom-gate structure array substrate, as shown in FIG. 2(b).
  • the array substrate is similar in structure to the array substrate of FIG. 2(a) except that the barrier insulating layer 25 is disposed flush with the active layer 24, and the barrier insulating layer 25 passes through the contact region S of the active layer 24 and the source and drain electrodes 26.
  • the first hollow structure exposes the active layer 24 such that the source and drain electrodes 26 are respectively in contact with the active layer 24, thereby ensuring the characteristics of the thin film transistor.
  • the array substrate further includes a gate 29, and the gate 29 is electrically connected to the gate line 22.
  • the gate electrode 29 is disposed corresponding to the active layer 24, that is, the orthographic projection of the gate electrode 29 on the substrate substrate 21 at least partially overlaps with the orthographic projection of the active layer 24 on the substrate substrate 21, thereby An electrical signal is applied to the gate 29 to change the electrical characteristics of the active layer 24 to effect switching of the thin film transistor.
  • the gate electrode 29 and the gate line 22 can be simultaneously formed by the same patterning process by one patterning process.
  • the first hollow structure 255 may be a via corresponding to the source and drain.
  • the embodiments of the present invention include, but are not limited to, the first hollow structure may also be completely removed from the contact region in the contact region.
  • FIG. 3 is a schematic structural view of the array substrate according to the present invention as a top gate structure array substrate.
  • the source and drain electrodes 32 are located on the substrate substrate 31, and the barrier insulating layer 33 is located above the source and drain electrodes 32.
  • the barrier insulating layer 33 is on the active layer 34 and the source and drain electrodes 32.
  • the contact region S exposes the source drain 32 through the first hollow structure; the active layer 34 is on the barrier isolation layer 33 and is in contact with the exposed source and drain 32; the gate insulating layer 35 is located on the active layer 34 And covering the array substrate; the gate line 36 is located above the gate insulating layer 35.
  • a pixel electrode 37 is further provided on the same film layer of the source/drain 32, and is in contact with the source and drain electrodes 32.
  • the array substrate provided in this embodiment in the process of forming the active layer, especially in the deposition process or the etching process, if the surface of the film layer (for example, the surface of the active layer) is attached Any foreign matter such as dust or debris may cause the formed active layer to retain residues in other areas that should be etched away.
  • the array substrate provided in this embodiment is provided with an anti-insulation edge layer on the active layer (bottom gate structure) or the source/drain (top gate structure), and the contact isolation layer has contact between the active layer and the source and drain.
  • the region has a first hollow structure to ensure the effectiveness of the TFT; therefore, the presence of the barrier insulating layer effectively blocks the contact of the active layer with other adjacent film layers (the source and drain electrodes can be in contact with the active layer through the first hollow structure) Therefore, the residue of the active layer is prevented from overlapping any of the first conductive layers, and the residue of the active layer is effectively prevented from overlapping the pixel electrode (the pixel electrode is located above or below the source drain, and the pixel electrode).
  • the problem of the TFT electrical connection caused by the lap joint structure is solved by the overlap with the drain, in view of the presence of the barrier insulating layer, the separation of the residue from the pixel electrode and the data line.
  • the barrier layer is increased, and the thickness of the film layer can be appropriately adjusted, the height difference of the surface of the entire array substrate after the formation of the active layer is reduced, and the flatness of the surface of the film layer is improved. Therefore, in the case where the gradient angle of the surface of the film layer is small, the subsequent film layer can be better deposited, and the film layer fracture phenomenon caused by a large difference in the surface height of the film layer or a large slope angle can be reduced.
  • the provided array substrate is a bottom gate structure array substrate, as shown in FIGS.
  • the barrier insulating layer 25 is disposed on the active layer 24 and covers the entire gate insulating layer 23, and the barrier insulating layer 25 is provided with the first hollow structure above the active layer 24 or is completely removed, and therefore, the height difference of the array substrate in the region where the active layer 24 is provided and other regions can be reduced.
  • the risk of film breakage due to a large difference in the surface height of the film layer or a large slope angle can be reduced.
  • the thickness of the barrier insulating layer 25 is greater than or equal to the thickness of the active layer 24.
  • the barrier insulating layer can better reduce the height difference of the array substrate between the region where the active layer is disposed and other regions.
  • the first conductive layer and the source and drain electrodes may be disposed in the same layer.
  • the pixel electrode 27 is disposed in the same layer as the source and drain electrodes 26, reducing the passivation layer, thereby reducing the thickness of the array substrate and improving the light transmission of the entire array substrate. Over rate.
  • the barrier insulating layer 25 may have a second hollow structure 257 in the region where the pixel electrode 27 is located, thereby improving light transmission of the entire array substrate. rate.
  • the material of the barrier insulating layer is selected as a resin. Since the resin material has good insulation, it can well block the overlap of the residue of the active layer with other first conductive layers. It should be noted that in order to increase the light transmittance of the entire array substrate, a material having a small light transmittance may be used as the material for the barrier insulating layer.
  • the material of the barrier insulating layer is a photosensitive resin. Since the photosensitive resin can be decomposed well under illumination, when the barrier insulating layer is patterned, it is only necessary to expose and develop the corresponding region to dissolve, thereby obtaining a desired pattern. Thereby, the process flow is simplified, and the problem of cumbersome process flow caused by the use of other non-photosensitive materials and the participation of photoresist is avoided.
  • the present invention also provides a method for fabricating an array substrate, comprising the steps of: forming a gate insulating layer; forming a first patterned active layer; a second patterned source and drain of the active layer contact, and a third patterned first conductive layer; further comprising: forming a fourth patterned barrier insulating layer, wherein the gate insulating layer is located at the active a surface of the layer, the barrier insulating layer is located on the other surface of the active layer, and the barrier insulating layer has a first hollow structure at least in a contact area of the active layer and the source and drain; The barrier insulating layer is used to block residues of the active layer from overlapping at least any of the first conductive layers.
  • the above steps do not reflect the obvious production sequence.
  • the patterning process mentioned in the following embodiments of the present invention includes at least steps of photoresist coating or dripping, exposure, development, photolithography etching, and the like.
  • the method for fabricating the array substrate provided by the present invention will be specifically described below according to the type of the array substrate.
  • the embodiment provides a method for fabricating an array substrate.
  • the array substrate is a bottom gate structure array substrate.
  • the method for fabricating the array substrate includes the following steps 41-44:
  • Step 41 Form a gate insulating layer covering the array substrate over the gate.
  • a gate insulating layer may be formed by depositing one or more insulating layers on the entire array substrate by physical deposition or chemical deposition, and the gate insulating layer covers the gate and the array substrate.
  • the method of forming the gate insulating layer is not limited, and the material of the gate insulating layer is not limited.
  • the gate insulating layer may be a single-layer insulating layer or a composite insulating layer including a plurality of insulating layers, which is not limited herein.
  • the step 41 the step of forming a gate on the substrate is also included, and the forming process may refer to a common forming step, which is not described herein again.
  • Step 42 Forming a first patterned active layer over the gate insulating layer.
  • a semiconductor layer is deposited on the array substrate on which the gate and the gate insulation are formed by chemical vapor deposition or thermal evaporation, and the semiconductor layer is generally sequentially deposited with SiN x , a-Si in this order. , N + a-Si, and then forming a photoresist layer of a predetermined thickness on the array substrate on which the semiconductor layer is formed, at which time the photoresist layer covers the entire semiconductor layer for forming the active layer;
  • the first mask exposes and develops the photoresist layer, retains the photoresist directly above the active layer to be formed, and removes the photoresist at the remaining positions, and then etches the exposed semiconductor layer, and finally The remaining photoresist is stripped to expose the remaining semiconductor layer as the first patterned active layer.
  • the photoresist according to the present invention may be a positive photoresist or a negative photoresist.
  • Step 43 depositing an insulating material on the active layer, forming a fifth patterned barrier insulating layer by a patterning process, and blocking the insulating layer to expose the active layer through the first hollow structure in a contact region between the active layer and the source and drain .
  • this step 43 Based on the active layer formed in the above step 42, considering the possibility that there may be residues in the process of forming the active layer, in order to avoid the problem of poor electrical conductivity of the TFT in order to avoid the overlap of the residue with the other first conductive layers, this step 43. forming a first patterned active layer, depositing one or more insulating layers by a physical vapor deposition or chemical vapor deposition process, and forming a fifth patterned barrier insulating layer by a patterning process, the barrier insulating layer The active layer is exposed through the first hollow structure at a contact area of the active layer and the source and drain.
  • the fifth patterned barrier insulating layer is formed by a patterning process
  • one of the following methods may be selected according to the type of the insulating material:
  • the insulating layer is a non-photosensitive resin at this time, for the array substrate on which the insulating layer is deposited, a photoresist of a predetermined thickness (for example, a positive photoresist) is formed on the insulating layer, and the fifth pattern is formed.
  • the mask plate exposes the photoresist corresponding to the active layer region in the insulating layer, and then develops the exposed array substrate to peel the exposed photoresist, and peels off the photoresist region.
  • the insulating layer is etched, and the photoresist corresponding to the active layer region is stripped, and the active layer is exposed to form a fifth patterned barrier insulating layer.
  • the insulating layer is a photosensitive resin at this time, for the array substrate on which the insulating layer is deposited, it is not necessary to form a photoresist of a predetermined thickness on the insulating layer, and directly use the fifth patterned mask to the insulating layer. Exposing the photosensitive resin corresponding to the active layer region, and then, onto the exposed array substrate The development process is performed to dissolve the exposed photosensitive resin, and finally the active layer is exposed to form a fifth patterned barrier layer.
  • the two methods can form the desired patterned barrier layer.
  • the method of using the photosensitive resin in the second method is more convenient, and it is not necessary to apply the photoresist and the stripping treatment of the photoresist. Simplifies the preparation process.
  • Step 44 Form a second patterned source and drain over the barrier isolation layer such that the source and drain are in contact with the exposed active layer.
  • source and drain electrodes that are not in contact with each other and are connected to the active layer through the via or exposed active layer surface are formed.
  • the embodiment provides a method for fabricating an array substrate.
  • the array substrate is a top gate structure array substrate.
  • the method for fabricating the array substrate includes the following steps 51-54:
  • Step 51 deposit an insulating material over the second patterned source drain, and form a sixth patterned barrier insulating layer by a patterning process, wherein the insulating edge layer passes through the first contact region of the active layer and the source and drain.
  • the hollow structure exposes the source drain.
  • an insulating material is deposited over the second patterned source drain using the deposition process described above, and a sixth patterned resistive isolation layer is formed using a patterning process similar to step 43, the barrier isolation layer being at the active layer and source
  • the contact area of the drain exposes the source drain through the first hollow structure.
  • a first patterned hollow structure having two via holes is formed on a portion of the insulating layer corresponding to the active layer by using a sixth patterned mask, thereby passing through the two vias
  • the source and drain that is, the source and drain, are respectively exposed.
  • the method further includes the step of forming a second patterned source and drain on the substrate, the source and drain can be formed by referring to a common forming method, and the source and drain materials are also The embodiments of the present invention are not described herein again with reference to the conventional design.
  • Step 52 forming a first patterned active layer over the barrier isolation layer such that the active layer is in contact with the exposed source and drain.
  • step 51 Forming a semiconductor layer based on the barrier insulating layer having two via holes formed in step 51, the semiconductor layer is respectively in contact with the source and drain at positions of the two via holes, and then patterning the semiconductor layer to form a first pattern Active layer.
  • This step is similar to step 42. It can be seen that even if the residue of the active layer is formed in this step, in view of the existence of the barrier insulating layer, the residue does not overlap with the pixel electrode or other first conductive layer, thereby ensuring good protection.
  • the electrical benignness of TFT is the residue of the active layer is formed in this step, in view of the existence of the barrier insulating layer, the residue does not overlap with the pixel electrode or other first conductive layer, thereby ensuring good protection.
  • Step 53 forming a gate insulating layer covering the array substrate over the active layer.
  • Step 54 Form a gate line over the gate insulating layer.
  • the gate and the gate lines can be formed by the same patterning process by the same material.
  • the residue of the active layer may establish a connection between the data line and the pixel electrode, that is, the data line and the pixel electrode are overlapped, It is also possible to establish a connection between the data line and the common electrode, as well as other first conductive layers, such as gate lines, etc., and the present invention does not list the specific locations where the overlap occurs.
  • the order of preparation of the pixel electrode and the source and drain electrodes may be interchanged, and the present invention is not specifically limited thereto.
  • This embodiment provides a display device including the various types of array substrates in the above embodiments.
  • the display device can be any product or component having a display function such as a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other indispensable components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as limiting the invention.

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Abstract

一种阵列基板及其制作方法以及显示装置。该阵列基板包括栅绝缘层(23)、有源层(24)、源漏极(26)、第一导电层(27)、以及阻隔绝缘层(25)。源漏极(26)与有源层(24)相接触，栅绝缘层(23)位于有源层(24)的一表面，阻隔绝缘层(25)位于有源层(24)的另一表面，且阻隔绝缘层(25)至少在有源层(24)与源漏极(26)的接触区域(S)包括第一镂空结构(255)，阻隔绝缘层(25)被配置为阻隔有源层(24)在第一镂空结构(255)所在区域之外的残留物与第一导电层(27)的接触。由此，该阵列基板解决了残留物搭接第一导电层(27)所造成的TFT电学不良的问题。

Description

阵列基板及其制作方法以及显示装置 技术领域
本发明实施例涉及一种阵列基板及其制作方法以及显示装置。
背景技术
随着显示技术的不断发展，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称：TFT-LCD)越来越受到市场的欢迎。通常，TFT-LCD的基本结构包括阵列基板、对置基板，以及夹设在阵列基板和对置基板之间的液晶层。
阵列基板上设置有呈矩阵排列的多个亚像素单元，每个亚像素单元都设置有薄膜晶体管(TFT)。薄膜晶体管通常包括栅极、栅绝缘层、有源层以及源漏极等。
发明内容
本发明实施例提供一种阵列基板及其制作方法、显示装置，用以解决现有技术中存在由于有源层的残留物与导电层接触而造成TFT电学性工艺不良的问题。
本发明至少一实施例提供一种阵列基板，其包括：栅绝缘层；有源层；源漏极，所述源漏极与所述有源层相接触；第一导电层；以及阻隔绝缘层，所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域包括第一镂空结构；所述阻隔绝缘层被配置为阻隔所述有源层在所述第一镂空结构所在区域之外的残留物与所述第一导电层的接触。
本发明至少一实施例提供一种阵列基板，其包括：形成栅绝缘层；形成第一图案化的有源层；形成与所述有源层接触的第二图案化的源漏极，第三图案 化的第一导电层；以及形成第四图案化的阻隔绝缘层；所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有第一镂空结构；所述阻隔绝缘层被配置为阻隔所述有源层的残留物至少搭接任一导电层。
本发明至少一实施例还提供一种显示装置，其包括权利要求上述任一的阵列基板。
在本发明实施例中，有源层的一表面设置有栅绝缘层，另一表面设置有阻隔绝缘层，该阻隔绝缘层可以有效阻隔所述有源层的残留物分别连接所述数据线和所述像素电极，避免TFT电学性工艺不良。而且，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中有源层的残留物与数据线以及像素电极搭接的示意图；
图2(a)为本发明所涉及的阵列基板为底栅结构阵列基板的结构示意图之一；
图2(b)为本发明所涉及的阵列基板为底栅结构阵列基板的结构示意图之二；
图2(c)为本发明所涉及的阵列基板为底栅结构阵列基板的结构示意图之三；
图2(d)为本发明所涉及的阵列基板为底栅结构阵列基板的结构示意图之四；
图3为本发明所涉及的阵列基板为顶栅结构阵列基板的结构示意图；
图4为本发明实施例提供的底栅结阵列基板的制作方法的步骤流程图；以及
图5为本发明实施例提供的顶栅结阵列基板的制作方法的步骤流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常，在有源层(或半导体层)的制备工艺中，可通过先沉积SiNx、a-Si、N+a-Si，然后再对沉积的混合膜层进行构图工艺，以形成图案化的有源层。
然而，在研究中，本申请的发明人发现：在具体的制备过程中，由于制备环境、设备或其他异常原因，不可避免会导致上述的混合膜层上附着尘埃、碎屑等异物。这些异物可在沉积过程中附着，也可在涂胶过程或在刻蚀的过程附着。在进行干刻工艺的时候，由于混合膜层的某些位置处有异物，导致干刻所用的气体无法与膜层接触反应，致使膜层出现残留物，例如，在利用干刻工艺图案化有源层的时，在存在异物的区域，有源层无法被刻蚀从而留下残留物。 进而，如图1所示，在后续制作源漏极11以及像素电极12的时候，若有源层13的残留物a足够大，就有可能会导致该残留物a在数据线14与像素电极12之间建立电连接，参照图1所示，这种电连接容易造成TFT电学性工艺不良。
本发明至少一实施例提供一种阵列基板及其制作方法以及显示装置。该阵列基板包括：栅绝缘层、有源层、与有源层接触的源漏极以及第一导电层；此外，该阵列基板还包括：阻隔绝缘层。该栅绝缘层位于有源层的一表面，阻隔绝缘层位于有源层的另一表面，且阻隔绝缘层至少在有源层与源漏极的接触区域具有第一镂空结构；阻隔绝缘层用于阻隔有源层的残留物与任一第一导电层的接触。该阵列基板的结构中，除有源层的一表面设置有栅绝缘层之外，另外一表面(除有源层与源漏极的接触区域外)还设置有阻隔绝缘层，从而，能够很好的将有源层与相邻其他第一导电层隔绝，进而，避免了有源层的残留物搭接任一第一导电层，尤其有效避免了有源层的残留物搭接像素电极与数据线的情况，从而，解决了搭接所造成的TFT电学不良的问题。同时，由于增加了阻隔绝缘层，且该膜层的厚度可适当调整，从而，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，因而，在膜层表面的坡度角较小的情况下，能够使得后续膜层更好的沉积，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。
本发明实施例中所涉及的第一导电层包括数据线、像素电极、栅线、公共电极中的任意一种。
在本发明实施例中，该阻隔绝缘层在所述像素电极所在区域具有第二镂空结构。从而，在保证阻隔绝缘层能够较好的阻隔有源层的残留物与其他第一导电层搭接，同时，还能够通过在像素电极所在区域形成的第二镂空结构提升整个阵列基板的透过率。
下面通过具体的实施例对本发明阵列基板及其制作方法以及显示装置进行详细的描述，本发明包括但并不限于以下实施例。
实施例一
本实施例提供一种阵列基板，图2(a)为本发明实施例提供的阵列基板为底栅结构阵列基板的一种结构示意图。本实施例以第一导电层为像素电极为例进行说明。如图2(a)所示，该阵列基板中，栅线22位于衬底基板21之上，栅绝缘层23位于栅线22之上且覆盖阵列基板，有源层24位于栅绝缘层23之上，阻隔绝缘层25位于有源层24之上，阻隔绝缘层25在有源层24与源漏极26的接触区域S通过第一镂空结构暴露出有源层24(假设形成的有源层24存在残留物a)，源漏极26位于阻隔绝缘层25之上，且与暴露出的有源层24相接触。此外，像素电极27与源漏极26搭接接触，且阻隔绝缘层25阻隔了像素电极27与下方可能存在的残留物a的搭接。其中，在该结构中，阻隔绝缘层25在有源层24与源漏极26的接触区域S呈现出的第一镂空结构可为过孔，源漏极26分别通过过孔与下层的有源层24接触，从而保证薄膜晶体管特性。需要说明的是，上述的底栅结构阵列基板是指该阵列基板上的薄膜晶体管采用底栅结构。同样地，顶栅结构阵列基板则代表该阵列基板上的薄膜晶体管采用顶栅结构。另外，上述的像素电极27为第一导电层。
例如，在本实施例一示例提供的阵列基板中，图2(b)为本发明所涉及的阵列基板为底栅结构阵列基板的另一种结构示意图，如图2(b)所示，该阵列基板与图2(a)的阵列基板的结构类似，区别在于：阻隔绝缘层25与有源层24齐平设置，阻隔绝缘层25在有源层24与源漏极26的接触区域S通过第一镂空结构暴露出有源层24，使得源漏极26分别与有源层24接触，从而保证薄膜晶体管特性。
例如，在本实施例一示例提供的阵列基板中，如图2(c)所示，该阵列基板还包括栅极29，栅极29与栅线22电连接。栅极29与有源层24对应设置，也就是说，栅极29在衬底基板21上的正投影与有源层24在衬底基板21上的正投影至少部分重叠，由此，可通过对栅极29施加电信号来改变有源层24的电学特性，从而实现薄膜晶体管的开关。栅极29和栅线22可采用同种材料通过一次构图工艺同时形成。
例如，在本实施例一示例提供的阵列基板中，如图2(c)所示，第一镂空结构255可为与源漏极对应的过孔。当然，本发明实施例包括但不限于此，第一镂空结构还可为阻隔绝缘层在接触区域完全被去除。
例如，在本实施例一示例提供的阵列基板中，图3为本发明所涉及的阵列基板为顶栅结构阵列基板的一种结构示意图。如图3所示，在该阵列基板中，源漏极32位于衬底基板31之上，阻隔绝缘层33位于源漏极32之上，阻隔绝缘层33在有源层34与源漏极32的接触区域S通过第一镂空结构暴露出源漏极32；有源层34位于阻隔绝缘层33之上，且与暴露出的源漏极32相接触；栅绝缘层35位于有源层34之上且覆盖阵列基板；栅线36位于栅绝缘层35之上。此外，在源漏极32的同一膜层，还设置有像素电极37，且与源漏极32搭接接触。
在本实施例提供的上述三种阵列基板的结构膜层中，在形成有源层的过程中，尤其是在沉积过程或刻蚀过程中，若膜层表面(例如，有源层表面)附着有尘埃或碎屑等异物，则会导致形成的有源层在其他本应该被刻蚀掉的区域保留有残留物。然而，本实施例提供的阵列基板在有源层(底栅结构)或源漏极(顶栅结构)之上设置有阻隔绝缘层，并且该阻隔绝缘层在有源层与源漏极的接触区域保留有第一镂空结构以保证TFT有效性；因此，该阻隔绝缘层的存在有效阻隔了有源层与相邻其他膜层的接触(源漏极可通过第一镂空结构与有源层接触)，从而避免了有源层的残留物搭接任一第一导电层，尤其有效避免了有源层的残留物搭接像素电极(该像素电极位于源漏极之上或之下，且像素电极与漏极相搭接，鉴于阻隔绝缘层的存在，阻隔了残留物与像素电极搭接)与数据线的情况，进而，解决了搭接结构所造成的TFT电学不良的问题。同时，由于增加了阻隔绝缘层，且该膜层的厚度可适当调整，从而，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，因而，在膜层表面的坡度角较小的情况下，能够使得后续膜层更好的沉积，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。例如，当本实施例提 供的阵列基板为底栅结构阵列基板时，如图2(a)-2(c)所示，阻隔绝缘层25设置在有源层24上并覆盖整个栅绝缘层23，并且，阻隔绝缘层25在有源层24的上方设置有第一镂空结构或被完全去除，因此，可降低该阵列基板在设置有有源层24的区域与其他区域的高度差。在后续形成源漏极和像素电极时，可降低因膜层表面高度差较大或坡度角较大而造成的膜层断裂的风险。
例如，在本实施例一示例提供的阵列基板中，如图2(a)-2(c)所示，阻隔绝缘层25的厚度大于或等于有源层24的厚度。由此，阻隔绝缘层可较好地降低阵列基板在设置有有源层的区域与其他区域的高度差。
例如，在本实施例一示例提供的阵列基板中，第一导电层与源漏电极可同层设置。例如，如图2(a)-2(c)所示，像素电极27与源漏极26同层设置，减少了钝化层，从而减少了阵列基板的厚度以及提高了阵列基板整体的光透过率。
例如，在本实施例一示例提供的阵列基板中，如图2(d)所示，阻隔绝缘层25在像素电极27所在区域可具有第二镂空结构257，从而提高阵列基板整体的光透过率。
例如，在本实施例一示例提供的阵列基板中，阻隔绝缘层的材质选择为树脂。由于树脂材料具有较好的绝缘性，能够很好的阻隔有源层的残留物与其他第一导电层的搭接。需要说明的是，为提高阵列基板整体的光透过率，阻隔绝缘层的材质可选用光透过率较小的树脂。
例如，在本实施例一示例提供的阵列基板中，阻隔绝缘层的材质为感光树脂。由于感光树脂在光照情况下能够很好的分解，因此，在对该阻隔绝缘层进行图案化时，只需对相应的区域进行曝光、显影即可溶解，得到所需的图案。从而，简化了工艺流程，避免了使用其他不感光的材质而需要光刻胶的参与而造成的工艺流程繁琐的问题。
与上述阵列基板属于同一发明构思，本发明还提供了一种阵列基板的制作方法，其包括以下步骤：形成栅绝缘层；形成第一图案化的有源层；形成与所 述有源层接触的第二图案化的源漏极，第三图案化的第一导电层；此外，还包括：形成第四图案化的阻隔绝缘层，其中，栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有第一镂空结构；所述阻隔绝缘层用于阻隔所述有源层的残留物至少搭接任一第一导电层。
需要说明的是，上述步骤并不体现明显的制作顺序。另外，本发明以下实施例提到的构图工艺至少包括光刻胶涂覆或滴注、曝光、显影、光刻刻蚀等步骤。
下面根据阵列基板的类型分别对本发明提供的阵列基板的制作方法进行具体介绍。
实施例二
本实施例提供一种阵列基板的制作方法，该阵列基板为底栅结构阵列基板，如图4所示，该阵列基板的制作方法包括以下步骤41-44：
步骤41：在栅极之上形成覆盖阵列基板的栅绝缘层。
例如，该步骤41中可采用物理沉积方式或化学沉积方式在整个阵列基板上沉积一层或多层绝缘层形成栅绝缘层，该栅绝缘层覆盖住栅极以及阵列基板。形成栅极绝缘层的方法不限，栅极绝缘层的材料不限。另外，栅极绝缘层可为单层绝缘层也可为包括多层绝缘层的复合绝缘层，本发明实施例在此不作限制。
需要说明的是，在该步骤41之前，还包括在衬底基板上形成栅极的步骤，其形成过程可参照通常的形成步骤，本发明实施例在此不再赘述。
步骤42：在栅绝缘层之上形成第一图案化的有源层。
例如，在形成有所述栅极和栅极绝缘的阵列基板之上采用化学气相沉积法或热蒸镀等方法沉积一半导体层，该半导体层中一般由先后顺序依次沉积SiNx，a-Si，N+a-Si，然后，在形成有所述半导体层的阵列基板上形成一层设定厚度的光刻胶层，此时光刻胶层覆盖整个用于形成有源层的半导体层；通过第 一掩模板对光刻胶层进行曝光和显影，保留待形成的有源层正上方的光刻胶，其余位置的光刻胶完全去除，然后，对暴露出的半导体层进行刻蚀，最后将保留的光刻胶剥离，暴露出保留的半导体层作为第一图案化的有源层。本发明所涉及的光刻胶可以为正性光刻胶也可以为负性光刻胶。
步骤43：在有源层之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，阻隔绝缘层在有源层与源漏极的接触区域通过第一镂空结构暴露出有源层。
基于上述步骤42形成的有源层，考虑到在形成有源层的过程中可能会有残留物，为了避免残留物与其他第一导电层的搭接而导致TFT电性不良的问题，该步骤43在形成第一图案化的有源层之上，利用物理气相沉积或化学气相沉积工艺沉积一层或多层绝缘层，并利用构图工艺形成第五图案化的阻隔绝缘层，该阻隔绝缘层在有源层与源漏极的接触区域通过第一镂空结构暴露出有源层。
例如，在利用构图工艺形成第五图案化的阻隔绝缘层时，可根据绝缘材料的类型选择以下方式之一进行：
方式一：
若此时绝缘层为非感光树脂，针对沉积有绝缘层的阵列基板，在该绝缘层之上形成一层设定厚度的光刻胶(例如为正性光刻胶)，利用第五图案化的掩膜板对绝缘层中对应有源层区域的光刻胶进行曝光，之后，对经过曝光处理的阵列基板进行显影处理，将经过曝光处理的光刻胶剥离，对剥离光刻胶的区域处的绝缘层进行刻蚀处理，并剥离对应有源层区域的光刻胶，暴露出有源层，形成第五图案化的阻隔绝缘层。
方式二：
若此时绝缘层为感光树脂，针对沉积有绝缘层的阵列基板，不需要在该绝缘层之上形成一层设定厚度的光刻胶，直接利用第五图案化的掩膜板对绝缘层中对应有源层区域的感光树脂进行曝光，之后，对经过曝光处理的阵列基板进 行显影处理，将经过曝光处理的感光树脂溶解掉，最终暴露出有源层，形成第五图案化的阻隔绝缘层。
综上，两种方式都可以形成所需图案化的阻隔绝缘层，然而，方式二中利用感光树脂的方案更为便捷，不需要涂布光刻胶以及对光刻胶的剥离处理，从而，简化了制备流程。
步骤44：在阻隔绝缘层之上形成第二图案化的源漏极，以使得源漏极与暴露出的有源层相接触。
例如，在形成有第五图案化的阻隔绝缘层之上，形成互不接触且均通过过孔或暴露出的有源层表面与有源层连接的源漏极。
实施例三
本实施例提供一种阵列基板的制作方法，该阵列基板为顶栅结构阵列基板，如图5所示，该阵列基板的制作方法包括以下步骤51-54：
步骤51：在第二图案化的源漏极之上沉积绝缘材料，利用构图工艺形成第六图案化的阻隔绝缘层，其中，隔绝缘层在有源层与源漏极的接触区域通过第一镂空结构暴露出源漏极。
例如，在第二图案化的源漏极之上利用上述沉积工艺沉积绝缘材料，并利用与步骤43类似的构图工艺形成第六图案化的阻隔绝缘层，该阻隔绝缘层在有源层与源漏极的接触区域通过第一镂空结构暴露出源漏极。例如，结合图3所示的结构，利用第六图案化的掩膜板，在绝缘层上对应有源层的区域形成具有两个过孔的第一镂空结构，从而，通过这两个过孔分别暴露出源极和漏极，即源漏极。
需要说明的是，在该步骤51之前，还包括在衬底基板上形成第二图案化的源漏极的步骤，该源漏极的形成可参照通常的形成方法，源漏极材料也与可参照通常的设计，本发明实施例在此不再赘述。
步骤52：在阻隔绝缘层之上形成第一图案化的有源层，以使得有源层与暴露出的源漏极相接触。
基于步骤51形成的具有两个过孔的阻隔绝缘层，沉积一半导体层，该半导体层在两个过孔的位置分别与源漏极接触，然后，对该半导体层进行构图工艺形成第一图案化的有源层。该步骤与步骤42类似。由此可见，即使在该步骤中形成有源层的残留物，鉴于阻隔绝缘层的存在，也不会造成该残留物与像素电极或其他的第一导电层搭接，从而，很好的保证了TFT的电学良性。
步骤53：在有源层之上形成覆盖所述阵列基板的栅绝缘层。
步骤54：在栅绝缘层之上形成栅线。
需要说明的是，栅极和栅线可采用同种材料通过一次构图工艺形成。另外，在本发明实施例中，仅示出了必要的膜层结构，其中，有源层的残留物可能会在数据线与像素电极之间建立连接，即搭接数据线与像素电极，此外，还有可能会在数据线与公共电极之间建立连接，以及其他的第一导电层，例如：栅线等，本发明并不一一列举搭接所发生的具体位置。
另外，在制备阵列基板的过程中，像素电极与源漏极的制备顺序可以互换，本发明并不对此进行具体限定。
综上，以上两种制备方案均示出了主要的工艺流程，其实，还包括一些其他膜层的制备，本发明在此不作描述。
实施例四
本实施例提供了一种显示装置，该显示装置包括上述实施例中的各类阵列基板。该显示装置可以为液晶面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。
本申请要求于2016年01月04日递交的中国专利申请第201610006819.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种阵列基板，包括：
    栅绝缘层；
    有源层；
    源漏极，所述源漏极与所述有源层相接触；
    第一导电层；以及
    阻隔绝缘层，
    其中，所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域包括第一镂空结构；所述阻隔绝缘层被配置为阻隔所述有源层在所述第一镂空结构所在区域之外的残留物与所述第一导电层的接触。
  2. 如权利要求1所述的阵列基板，其中，所述第一导电层与所述源漏电极同层设置。
  3. 如权利要求1所述的阵列基板，其中，所述阻隔绝缘层在像素电极所在区域具有第二镂空结构。
  4. 如权利要求1所述的阵列基板，其中，所述第一导电层包括数据线、像素电极、栅线以及公共电极中任意一种。
  5. 如权利要求1所述的阵列基板，其中，所述阵列基板为底栅结构阵列基板，所述栅绝缘层位于栅线之上且覆盖所述阵列基板，所述有源层位于所述栅绝缘层之上，所述阻隔绝缘层位于所述有源层之上，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过所述第一镂空结构暴露出所述有源层，所述源漏极位于所述绝缘阻隔层之上，且与暴露出的有源层相接触。
  6. 如权利要求1所述的阵列基板，其中，所述阵列基板为底栅结构阵列基板，所述栅绝缘层位于所述栅线之上且覆盖所述阵列基板，所述有源层位于所述栅绝缘层之上，所述阻隔绝缘层与所述有源层齐平设置，所述阻隔绝缘层 在所述有源层与所述源漏极的接触区域通过所述第一镂空结构暴露出所述有源层，所述源漏极位于所述绝缘阻隔层之上，且与暴露出的有源层相接触。
  7. 如权利要求1所述的阵列基板，其中，所述阵列基板为顶栅结构阵列基板，所述阻隔绝缘层位于所述源漏极之上，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过所述第一镂空结构暴露出所述源漏极，所述有源层位于所述阻隔绝缘层之上，且与暴露出的所述源漏极相接触，所述栅绝缘层位于所述有源层之上且覆盖所述阵列基板，栅线位于所述栅绝缘层之上。
  8. 如权利要求5-7中任一项所述的阵列基板，还包括：
    栅极，其中，所述栅极与所述栅线同层设置。
  9. 如权利要求1-7中任一项所述的阵列基板，其中，所述阻隔绝缘层的厚度大于或等于所述有源层的厚度。
  10. 如权利要求1-7中任一项所述的阵列基板，其中，所述阻隔绝缘层的材质包括树脂。
  11. 如权利要求10所述的阵列基板，其中，所述阻隔绝缘层的材质为感光树脂。
  12. 一种阵列基板的制作方法，包括：
    形成栅绝缘层；
    形成第一图案化的有源层；
    形成与所述有源层接触的第二图案化的源漏极，第三图案化的第一导电层；以及
    形成第四图案化的阻隔绝缘层；
    其中，所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有第一镂空结构；所述阻隔绝缘层被配置为阻隔所述有源层的残留物至少搭接任一导电层。
  13. 如权利要求12所述的方法，其中，所述阻隔绝缘层被配置为阻隔所 述有源层的残留物与所述第一导电层的接触。
  14. 如权利要求12或13所述的方法，其中，所述阵列基板为底栅结构阵列基板，所述阵列基板的制作方法还包括：
    在栅极之上形成覆盖所述阵列基板的栅绝缘层；
    在所述栅绝缘层之上形成第一图案化的有源层；
    在所述有源层之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过所述第一镂空结构暴露出有源层；以及
    在所述阻隔绝缘层之上形成第二图案化的源漏极，以使得所述源漏极与暴露出的有源层相接触。
  15. 如权利要求14所述的方法，其中，在栅极之上形成覆盖所述阵列基板的栅绝缘层还包括：
    在衬底基板上形成栅极。
  16. 如权利要求12或13所述的方法，其中，所述阵列基板为顶栅结构阵列基板，则所述方法还包括：
    在第二图案化的源漏极之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过第一镂空结构暴露出所述源漏极；
    在所述阻隔绝缘层之上形成第一图案化的有源层，以使得所述有源层与暴露出的源漏极相接触；
    在所述有源层之上形成覆盖所述阵列基板的栅绝缘层；
    在所述栅绝缘层之上形成栅线。
  17. 一种显示装置，包括权利要求1-11中任一项所述的阵列基板。
PCT/CN2016/093240 2016-01-04 2016-08-04 阵列基板及其制作方法以及显示装置 Ceased WO2017118004A1 (zh)

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