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WO2017115573A1 - Four à diffusion horizontal et procédé de fabrication de cellules solaires - Google Patents

Four à diffusion horizontal et procédé de fabrication de cellules solaires Download PDF

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Publication number
WO2017115573A1
WO2017115573A1 PCT/JP2016/083807 JP2016083807W WO2017115573A1 WO 2017115573 A1 WO2017115573 A1 WO 2017115573A1 JP 2016083807 W JP2016083807 W JP 2016083807W WO 2017115573 A1 WO2017115573 A1 WO 2017115573A1
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WIPO (PCT)
Prior art keywords
boat
diffusion furnace
horizontal
silicon wafer
horizontal diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2016/083807
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English (en)
Japanese (ja)
Inventor
聖 沖本
中村　仁志
崇 澤井
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2017558878A priority Critical patent/JP6479218B2/ja
Priority to TW105142682A priority patent/TWI606603B/zh
Publication of WO2017115573A1 publication Critical patent/WO2017115573A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10P32/00—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a horizontal diffusion furnace used in an impurity diffusion process of a semiconductor wafer such as silicon and a method for manufacturing a solar battery cell.
  • One of the semiconductor device manufacturing processes is a heat treatment process, for example, a process of diffusing impurities into a semiconductor substrate such as a silicon wafer to form a pn junction.
  • a quartz cylindrical process tube is used as a process chamber, and a heater is disposed on the outer peripheral side of the process tube.
  • the surface of the semiconductor substrate disposed in the process tube is introduced by continuously introducing a source gas containing a dopant into the heated process tube. Impurity diffusion can occur.
  • Diffusion furnaces are divided into vertical furnaces and horizontal furnaces due to the difference in process tube arrangement.
  • the semiconductor substrate is rotated in the process tube to improve the uniformity of the impurity diffusion process.
  • horizontal furnaces with excellent productivity are often used, and large horizontal furnaces having quartz process tubes with a total length of about 1000 mm to 2000 mm are used. .
  • a quartz child boat in which a plurality of semiconductor substrates are arranged side by side is placed on a quartz parent boat for transfer and transferred to the horizontal heat treatment furnace.
  • the supply of the source gas to the semiconductor substrate is a main factor that affects the uniformity of the impurity diffusion amount in the semiconductor substrate. Variations in the supply of the source gas to the semiconductor substrate cause the amount of impurity diffusion in the semiconductor substrate to vary within the surface of the semiconductor substrate. The variation in the diffusion amount of impurities in the semiconductor substrate adversely affects the characteristics and yield of products manufactured using the semiconductor substrate in which impurities are diffused.
  • low temperature raw material gas that is not sufficiently heated tends to stay in the lower part of the horizontal furnace. Furthermore, in the lower part of the horizontal furnace, in the semiconductor substrate installed near the source gas supply port, the in-plane distribution occurs in the temperature of the semiconductor substrate due to the low temperature source gas, and the in-plane impurity diffusion amount Variations are likely to occur.
  • Patent Document 1 discloses, among wafer support grooves in a wafer support boat made of quartz, wafer support grooves at both ends in the longitudinal direction and wafer support grooves adjacent to the reinforcing portion. Discloses a method of preventing the influence of turbulent flow by placing a dummy wafer having the same shape as the wafer.
  • Patent Document 1 a wafer cannot be arranged in a region where wheels are arranged in the longitudinal direction, and the arrangement position is greatly restricted. Therefore, there is no degree of freedom in arrangement of the wafer, and productivity is increased. Low.
  • the impurity diffusion process is performed by increasing the flow rate of the source gas compared to the case where the impurity diffusion process is performed on a small amount of the semiconductor substrate.
  • the turbulent flow of the source gas in the heat treatment furnace during the impurity diffusion process is increased, and a low-temperature source gas that is not sufficiently warmed is supplied to the semiconductor substrate, and the in-plane distribution of the impurity diffusion amount in the semiconductor substrate.
  • the present invention has been made in view of the above, and an object of the present invention is to obtain a horizontal diffusion furnace capable of performing a diffusion process with high in-plane uniformity of impurity diffusion amount in a substrate to be processed.
  • the horizontal diffusion furnace is arranged in a horizontal state, a process gas supply port is provided on one end side, and a process gas exhaust port is provided on the other end side.
  • a horizontally long process tube and a heater for heating the inside of the process tube.
  • the horizontal diffusion furnace has a first boat that holds the substrate to be processed in a standing state and a plurality of moving wheels at the bottom, and is movable, and the first boat is placed in the process tube.
  • a horizontally long second boat placed in a horizontal state, and a first shielding plate that covers an upper portion of a moving wheel in the second boat.
  • the present invention it is possible to obtain a horizontal diffusion furnace capable of performing a diffusion process with a high in-plane uniformity of the impurity diffusion amount in the substrate to be processed.
  • mold diffusion furnace concerning Embodiment 1 of this invention The figure which shows the measurement position of the sheet resistance value of the silicon wafer in Embodiment 1 of this invention
  • Side view of a comparative horizontal diffusion furnace in which a quartz dummy wafer is placed on one side of the child boat A perspective view of a child boat provided in a comparative horizontal diffusion furnace Side view showing an enlarged view of the vicinity of one child boat in a comparative horizontal diffusion furnace
  • Plan view of the parent boat in the horizontal diffusion furnace according to the second embodiment of the present invention The side view which expands and shows one child boat vicinity in the horizontal type
  • the characteristic view which shows in-plane distribution of the sheet resistance value of the silicon wafer of Example 1, Example 2, and Comparative Example 1 in Embodiment 2 of this invention The characteristic view which shows standard deviation (sigma) of the sheet resistance value of 9 points
  • the characteristic view which shows the relationship between the standard deviation (sigma) of the sheet resistance value of 9 points
  • Sectional drawing which shows the manufacturing process of the photovoltaic cell concerning Embodiment 3 of this invention.
  • Sectional drawing which shows the manufacturing process of the photovoltaic cell concerning Embodiment 3 of this invention.
  • FIG. 1 is a side view of a horizontal diffusion furnace 20 according to a first embodiment of the present invention.
  • FIG. 1 shows a member of the horizontal diffusion furnace 20 that can be seen through the side surface of the quartz tube 8.
  • FIG. 2 is a plan view of the parent boat 3 in the horizontal diffusion furnace 20 according to the first embodiment of the present invention.
  • FIG. 3 is a perspective view of the sub boat 1 in which the substrate to be processed is arranged in the horizontal diffusion furnace 20 according to the first embodiment of the present invention.
  • FIG. 4 is an enlarged side view showing the vicinity of one child boat 1 in the horizontal diffusion furnace 20 according to the first embodiment of the present invention.
  • the horizontal diffusion furnace 20 includes a p-type silicon wafer for forming an n-type impurity layer on the surface of a p-type silicon wafer 2 that is a substrate to be processed in the manufacturing process of solar cells.
  • 2 is a horizontal diffusion furnace that can be used in a phosphorus diffusion step of diffusing phosphorus into 2.
  • the horizontal diffusion furnace 20 is loaded with a child boat 1 which is a first quartz boat used as a wafer holding unit in which a plurality of silicon wafers 2 are arranged at regular intervals, and a child boat 1 holding the silicon wafer 2. And a parent boat 3 which is a second boat which is transported into the horizontal diffusion furnace 20 and is a quartz moving table.
  • the horizontal diffusion furnace 20 is a process tube having an elongated cylindrical shape, and includes a quartz tube 8 disposed in a horizontal state, and a heater 9 installed around the quartz tube 8 to heat the inside of the quartz tube 8. .
  • the child boat 1 holds 10 to 50 silicon wafers 2 in a standing state at regular intervals.
  • the parent boat 3 is a frame-shaped member having a rectangular shape in which two elongated bar members are connected in parallel.
  • the parent boat 3 loads a plurality of child boats 1 holding the silicon wafers 2 and conveys them to the horizontal diffusion furnace.
  • the parent boat 3 has a wheel 4, which is a moving wheel for transporting it into the quartz tube 8, at the lower part and is movable. Further, the parent boat 3 secures a soaking area within the wheel reinforcing portion 5 that reinforces the wheel shaft connecting the wheels 4, the parent boat reinforcing portion 6 that reinforces the parent boat 3, and the quartz tube 8.
  • the first portion is directly above the wheel 4, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6 for transporting the parent boat 3.
  • a shielding plate 14 is provided.
  • the first shielding plate 14 has a size and a shape that cover a region immediately above the wheel 4, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6 in a plan view of the parent boat 3.
  • the 1st shielding board 14 is heat-processed with a to-be-processed substrate in a diffusion furnace at the time of a diffusion process.
  • the material of the first shielding plate 14 is preferably a material excellent in heat resistance at a high temperature, and the same quartz material as that of the sub boat 1 and the main boat 3 is used. Other materials can be used as long as they are heat resistant to the temperature during the diffusion treatment and do not react with the gas introduced into the diffusion furnace.
  • the first shielding plate 14 is fixed to the parent boat 3 by means capable of withstanding the temperature during the diffusion process such as screwing.
  • the quartz tube 8 is provided with a supply port 10 to which a source gas 13 as a process gas is supplied at one end in the longitudinal direction, and an exhaust port 11 for exhausting the gas in the quartz tube 8 is the other end in the longitudinal direction. It is provided on the upper surface of the side. That is, the quartz tube 8 has a structure in which the raw material gas 13 is introduced from the supply port 10 and the gas in the quartz tube 8 is exhausted from the exhaust port 11.
  • the source gas 13 is, for example, vaporized phosphorus trichloride (POCl 3 ) and mixed with a carrier gas such as nitrogen gas (N 2 ) and oxygen gas (O 2 ).
  • Phosphorus trichloride (POCl 3 ) is mixed with nitrogen gas (N 2 ) and oxygen gas (O 2 ) and introduced into the quartz tube 8 and exhibits the following reaction.
  • the other end side in the longitudinal direction of the quartz tube 8 is a furnace port that is an entrance / exit of the parent boat 3 on which the child boat 1 is loaded, and a quartz door 12 for opening and closing the furnace port is installed. Yes. By closing the door 12, the temperature in the quartz tube 8 can be stabilized.
  • a piping system (not shown) that performs switching of the source gas 13 and control of the flow rate of the source gas is arranged upstream of the supply port 10 for introducing the source gas 13 into the quartz tube 8.
  • FIG. 1 in a state where the inside of the quartz tube 8 is heated by the heater 9, the parent boat 3 on which the child boat 1 is loaded is introduced into the quartz tube 8 from the furnace port of the quartz tube 8 and is arranged in a horizontal state.
  • the in-plane directions of the front and back surfaces of the silicon wafer 2 in the quartz tube 8 are parallel to the direction in which the source gas 13 is introduced into the quartz tube 8, that is, parallel to the central axis of the quartz tube 8. Installed.
  • the door 12 is closed, the raw material gas 13 is introduced into the quartz tube 8, and phosphorus is diffused.
  • the temperature in the quartz tube 8 during the diffusion treatment is about 800 ° C. to 1000 ° C.
  • the supply of the source gas 13 is stopped, and the inside of the quartz tube 8 is purged with an inert gas such as nitrogen.
  • the door 12 is opened, the parent boat 3 is taken out, and the phosphorus diffusion process for the silicon wafer 2 is completed.
  • the phosphorus diffusion processing conditions for the silicon wafer 2 are such that the total flow rate of the source gas 13 and the carrier gas is 30 [slm], and the diffusion processing is performed at 800 ° C. for 15 minutes. The temperature is raised to 875 ° C., and the treatment is further performed for 15 minutes.
  • FIG. 5 is a diagram showing a measurement position of the sheet resistance value of the silicon wafer 2 in the first embodiment of the present invention.
  • the vertical and horizontal directions of the measurement region shown in FIG. 5 coincide with the orientation of the silicon wafer 2 shown in FIGS.
  • the measurement area may be simply referred to as an area.
  • FIG. 6 shows the in-plane distribution of the sheet resistance value of the silicon wafer of Example 1.
  • FIG. 6 is a characteristic diagram showing the in-plane distribution of the sheet resistance values of the silicon wafers 2 of Example 1 and Comparative Example 1 according to Embodiment 1 of the present invention.
  • a silicon wafer subjected to phosphorus diffusion processing in the horizontal diffusion furnace in which the first shielding plate 14 is removed from the horizontal diffusion furnace 20 is used as a silicon wafer of Comparative Example 1, and the sheet resistance value of the silicon wafer of Comparative Example 1 is set. In-plane distribution was measured. The measurement position of the sheet resistance is the same as that in the first embodiment. The in-plane distribution of the sheet resistance value of the silicon wafer of Comparative Example 1 is also shown in FIG.
  • the low-temperature source gas 13 that has not been sufficiently heated tends to stay in the lower region of the quartz tube 8.
  • the low-temperature source gas 13 that is supplied to the quartz tube 8 and is not sufficiently warmed reaches the peripheral portions of the wheel 4, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6 in the lower region of the quartz tube 8.
  • the turbulent flow is caused by the presence of the wheel 4, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6, and the low-temperature source gas 13 is wound up toward the lower portion of the silicon wafer 2.
  • the increase in sheet resistance in the region F in the silicon wafer of Comparative Example 1 occurs because the lower part of the silicon wafer 2 is cooled by the low temperature source gas 13 being rolled up toward the lower part of the silicon wafer 2.
  • the wheel 4, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6 are not heated sufficiently and remain in the peripheral portions of the parent boat reinforcing portion 6.
  • the low temperature source gas 13 that reaches and is wound up toward the lower part of the silicon wafer 2 is shielded by the first shielding plate 14. That is, as indicated by an arrow X1 in FIG. 4, the low temperature source gas 13 wound up toward the lower portion of the silicon wafer 2 due to the wheel 4, the wheel reinforcing portion 5 and the parent boat reinforcing portion 6 is first shielded. It is shielded by the plate 14.
  • the horizontal diffusion furnace 20 can suppress variation in the in-plane distribution of the sheet resistance in the silicon wafer 2, that is, the in-plane distribution of the diffusion amount of phosphorus, and the diffusion of phosphorus in the plane in the silicon wafer 2. The amount can be kept uniform.
  • the same amount of source gas 13 is supplied to one silicon wafer 2 in batch processing in which a large amount of silicon wafers 2 are collectively processed at a time for the purpose of ensuring productivity. Therefore, the impurity diffusion process may be performed by increasing the flow rate of the source gas 13. Even in this case, in the horizontal diffusion furnace 20 including the first shielding plate 14, it reaches the peripheral portions of the wheel 4, the wheel reinforcement portion 5, and the parent boat reinforcement portion 6 at a low temperature without being sufficiently heated. It is possible to shield the low temperature raw material gas 13 wound up toward the lower part of the silicon wafer 2 and prevent the low temperature raw material gas 13 from being blown onto the silicon wafer 2.
  • the source gas 13 is heated in the quartz tube 8 as the position is farther from the supply port 10 of the source gas 13. For this reason, the in-plane non-uniformity of the sheet resistance of the silicon wafer 2 caused by the low temperature raw material gas 13 is suppressed as the silicon wafer 2 installed in the sub boat 1 away from the supply port 10 of the raw material gas 13 is suppressed. Tend to be.
  • the first shielding plate 14 is preferably installed even at a position away from the supply port 10 of the source gas 13.
  • the first shielding plate 14 which is a separate component, is installed above the wheel 4 of the parent boat 3, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6.
  • the structure of the parent boat 3 is a structure in which the wheels 4, the reinforcing portions 5 of the wheels, and the upper portions of the reinforcing portions 6 of the parent boat are shielded in advance, the same effects can be obtained structurally.
  • the first shielding plate 14 may be installed only on the upper portion of the wheel 4. That is, when the wheel reinforcing portion 5 and the parent boat reinforcing portion 6 are not provided, the lower portion of the silicon wafer 2 of the low temperature raw material gas 13 caused by the wheel reinforcing portion 5 and the parent boat reinforcing portion 6 is provided. No hoisting occurs. However, when the wheel reinforcing portion 5 and the parent boat reinforcing portion 6 are present as in the first embodiment, the low temperature source gas 13 caused by the wheel reinforcing portion 5 and the parent boat reinforcing portion 6 is reduced.
  • a first shielding plate 14 is provided on the upper part of the reinforcing part 5 of the wheel and the reinforcing part 6 of the parent boat in addition to the upper part of the wheel 4.
  • FIG. 7 is a side view of a comparative horizontal diffusion furnace in which a quartz dummy wafer 101 is arranged on one side of the child boat 1.
  • FIG. 7 shows a member of a horizontal diffusion furnace that can be seen through the side surface of the quartz tube 8.
  • FIG. 8 is a perspective view of the child boat 1 provided in the comparative horizontal diffusion furnace.
  • FIG. 9 is an enlarged side view showing the vicinity of one child boat 1 in a comparative horizontal diffusion furnace.
  • the comparative horizontal diffusion furnace has the same structure as that of the horizontal diffusion furnace 20 except that the dummy wafer 101 is arranged in the sub boat 1 and the first shielding plate 14 is not installed.
  • a quartz dummy wafer 101 is arranged on one side which is the supply port 10 side in the child boat 1 of the comparative horizontal diffusion furnace. By providing such a dummy wafer 101, it is possible to block the source gas 13 flowing from the supply port 10 side at the same height as the silicon wafer 2.
  • the comparative horizontal diffusion furnace cannot sufficiently suppress the influence of the turbulent flow of the low temperature raw material gas 13 that occurs around the wheel 4, the reinforcing portion 5 of the wheel, and the reinforcing portion 6 of the parent boat. That is, in order to suppress the low temperature source gas 13 from flowing into the lower part of the silicon wafer 2, the dummy wafer 101 is installed at a position other than the upper part of the wheel 4, the wheel reinforcing part 5, and the parent boat reinforcing part 6. Therefore, the arrangement position of the child boat 1 in the parent boat 3 is greatly restricted, and productivity is lowered. As shown in FIGS.
  • the low temperature source gas 13 is moved to the lower portion of the silicon wafer 2 as indicated by an arrow X2. It flows in. Further, even when the dummy wafer 101 is installed at the upper part of the wheel 4 and the upper part of the wheel reinforcing part 5, the low temperature raw material gas 13 similarly flows into the lower part of the silicon wafer 2.
  • the first shielding plate 14 is installed at the upper part of the periphery of the wheel 4, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6. Can be prevented from being supplied to the lower portion of the silicon wafer 2. Therefore, even when the child boat 1 is installed on the first shielding plate 14 as shown in FIGS. 10 and 11, as shown by the arrow X3, the wheel 4, the wheel reinforcing portion 5 and the parent boat reinforcing portion 6 are provided. It is possible to suppress the low temperature source gas 13 wound up toward the lower part of the silicon wafer 2 from being supplied to the lower part of the silicon wafer 2 and to keep the in-plane impurity diffusion amount in the silicon wafer 2 uniform. it can.
  • FIG. 10 is a side view of the horizontal diffusion furnace 20 according to the first embodiment of the present invention, and is a side view showing a case where the child boat 1 is installed on the first shielding plate 14.
  • FIG. 11 is an enlarged side view showing the vicinity of one child boat 1 in the horizontal diffusion furnace 20 according to the first embodiment of the present invention, and shows a case where the child boat 1 is installed on the first shielding plate 14. It is a side view.
  • the source gas 13 In addition to vaporized POCl 3 , a material obtained by vaporizing another material containing phosphorus such as hydrogen phosphide (PH 3 ) can also be used. Therefore, a gas containing at least one of POCl 3 or PH 3 can be used as the source gas 13.
  • boron (B) when boron (B) is diffused as a p-type impurity, a material gas such as boron trichloride (BCl 3 ), boron tribromide (BBr 3 ), diborane (B 2 H 6 ) is vaporized. 13 can be introduced into the quartz tube 8. Therefore, as the source gas 13, a gas containing at least one of BCl 3 , BBr 3 and B 2 H 6 can be used.
  • BCl 3 boron trichloride
  • BBr 3 boron tribromide
  • B 2 H 6 diborane
  • the horizontal diffusion furnace 20 according to the first embodiment is not limited to the production of solar cells, and even when used for heat treatment of a semiconductor wafer such as a silicon wafer used for a power device or an optical device, the same as described above. The effect is obtained.
  • the horizontal diffusion furnace 20 covers the wheels 4, the wheel reinforcing portions 5, and the upper portions of the parent boat reinforcing portions 6 with the first shielding plate 14, so that the wheels 4, wheels It is possible to suppress the low temperature source gas 13 from being wound up to the lower portion of the silicon wafer 2 due to the reinforcing portion 5 and the reinforcing portion 6 of the parent boat. Thereby, the horizontal diffusion furnace 20 can suppress the occurrence of variation in the in-plane distribution of the sheet resistance in the silicon wafer 2, that is, the in-plane distribution of the diffusion amount of phosphorus. The amount of diffusion can be kept uniform.
  • the horizontal diffusion furnace 20 can perform a diffusion process that improves the in-plane uniformity of the phosphorus diffusion amount in the silicon wafer 2 and improves the device characteristics and yield of the silicon wafer 2. be able to.
  • Embodiment 2 in the solar cell manufacturing process, a phosphorus diffusion process for diffusing phosphorus to form an n-type impurity layer on the surface of the p-type silicon wafer 2 is performed.
  • the horizontal diffusion furnace to be used will be described.
  • the phosphorus diffusion processing conditions for the silicon wafer 2 are the same as in the first embodiment, the total flow rate of the source gas 13 and the carrier gas is 30 [slm], and the diffusion processing is performed at 800 ° C. for 15 minutes. After being performed, the temperature is raised to 875 ° C., and the treatment is further performed for 15 minutes.
  • FIG. 12 is a side view of the horizontal diffusion furnace 30 according to the second embodiment of the present invention.
  • FIG. 12 shows members of the horizontal diffusion furnace 30 that can be seen through the side surface of the quartz tube 8.
  • FIG. 13 is a plan view of the parent boat 3 in the horizontal diffusion furnace 30 according to the second embodiment of the present invention.
  • FIG. 14 is an enlarged side view showing the vicinity of one child boat 1 in the horizontal diffusion furnace 30 according to the second embodiment of the present invention.
  • the horizontal diffusion furnace 30 according to the second embodiment includes a wheel 4, a wheel reinforcing portion 5, and a first shielding plate 14 that covers a portion directly above the parent boat reinforcing portion 6.
  • a plurality of second shielding plates 16 that cover the region immediately below the child boat 1 are installed, and the region between the heat barriers 7 in which the child boat 1 can be disposed within the surface of the parent boat 3 is generally shielded. It is said that. That is, the horizontal diffusion furnace 30 according to the second embodiment is different from the horizontal diffusion furnace 20 according to the first embodiment in that the second shielding plate 16 is provided.
  • the second shielding plate 16 is disposed in a region between the adjacent first shielding plate 14 and the first shielding plate 14 in a plan view of the parent boat 3. Thereby, in the parent boat 3, the region between the heat barriers 7 located at both ends in the central axis direction of the quartz tube 8 is covered with the first shielding plate 14 and the second shielding plate 16.
  • the second shielding plate 16 has a size and shape that covers a region where the first shielding plate 14 is not disposed in a region between the heat barriers 7 in a plan view of the parent boat 3.
  • the second shielding plate 16 has a structure in which a plurality of supply holes 17 for supplying the source gas 13 from the lower portion of the second shielding plate 16 to the silicon wafer 2 of the child boat 1 are dispersed and opened in the plane. Yes.
  • the ratio of the area occupied by the supply holes 17 in the plane of the second shielding plate 16, that is, the aperture ratio may be 20% or more and 50% or less. Preferably, it is 20% here.
  • the second shielding plate 16 is heat treated together with the substrate to be processed in the diffusion furnace during the diffusion treatment.
  • the material of the second shielding plate 16 is preferably a material excellent in heat resistance at a high temperature similarly to the first shielding plate 14, and the same quartz material as that of the child boat 1 and the parent boat 3 is used. .
  • Other materials can be used as long as they are heat resistant to the temperature during the diffusion treatment and do not react with the gas introduced into the diffusion furnace.
  • the second shielding plate 16 is fixed to the parent boat 3 by means capable of withstanding the temperature during the diffusion process such as screwing.
  • the silicon wafer 2 accommodated in the sub-boat 1 closest to the supply port 10 in the quartz tube 8, that is, The silicon wafer 2 housed in the rightmost child boat 1 shown in FIG. 12 was used as the silicon wafer of Example 2, and the in-plane distribution of sheet resistance was measured.
  • the sheet resistance is measured at nine points in the measurement areas A, B, C, D, E, F, G, H, and I in the plane of the silicon wafer 2, as shown in FIG. It was.
  • the vertical and horizontal directions of the measurement region shown in FIG. 5 coincide with the orientation of the silicon wafer 2 shown in FIGS.
  • FIG. 15 shows the in-plane distribution of the sheet resistance values of the silicon wafers of Example 1, Comparative Example 1, and Example 2 described above.
  • FIG. 15 is a characteristic diagram showing the in-plane distribution of sheet resistance values of silicon wafers 2 of Example 1, Example 2 and Comparative Example 1 according to Embodiment 2 of the present invention.
  • the first shielding plate 14 is installed above the wheel 4, the wheel reinforcing portion 5, and the parent boat reinforcing portion 6, thereby increasing the heights of the regions E to H, particularly the region F. Sheet resistance is suppressed.
  • region G located in the center part of the lower part of the silicon wafer 2 since the low-temperature raw material gas 13 which is not fully heated is supplied in small quantities, it exists in the tendency for sheet resistance to become high.
  • the second shielding plate 16 in which the supply hole 17 is formed is installed directly below the sub-boat 1 so that the minimum amount of raw material necessary for the phosphorus diffusion treatment is obtained. While supplying the gas 13 to the lower part of the silicon wafer 2, the supply amount of the low temperature raw material gas 13 which is not sufficiently warmed to the lower part of the silicon wafer 2 is suppressed. As a result, in the horizontal diffusion furnace 30, it is possible to suppress an increase in sheet resistance in the region G located at the lower central portion of the silicon wafer 2.
  • FIG. 16 is a characteristic diagram showing the standard deviation ⁇ of the sheet resistance values at nine points in the plane of the silicon wafers of Example 1, Comparative Example 1 and Example 2 in the second embodiment of the present invention.
  • the standard deviation ⁇ of the sheet resistance value of the silicon wafer of Example 1 is significantly smaller than the standard deviation ⁇ of the sheet resistance value of the silicon wafer of Comparative Example 1. That is, the uniformity of the in-plane distribution of the sheet resistance value is significantly improved in the silicon wafer of Example 1 compared to the silicon wafer of Comparative Example 1.
  • the standard deviation ⁇ of the sheet resistance value of the silicon wafer of Example 2 is a smaller value than the standard deviation ⁇ of the sheet resistance value of the silicon wafer of Example 1. That is, the silicon wafer of Example 2 is better than the silicon wafer of Example 1 in that the uniformity of the in-plane distribution of the sheet resistance value is further improved.
  • FIG. 17 is a characteristic diagram showing the relationship between the sheet resistance value of the region G and the opening ratio of the supply hole 17 in the second shielding plate 16 in the silicon wafer of Example 2 according to Embodiment 2 of the present invention.
  • FIG. 18 is a characteristic showing the relationship between the standard deviation ⁇ of the sheet resistance value at nine points in the surface of the silicon wafer of Example 2 according to Embodiment 2 of the present invention and the aperture ratio of the supply hole 17 in the second shielding plate 16.
  • the aperture ratio is 0%
  • the raw material gas 13 is not supplied to the silicon wafer 2 from the lower portion, so that the sheet resistance value of the region G in the silicon wafer becomes high, and the in-plane sheet resistance value is standard.
  • the deviation ⁇ increases.
  • the aperture ratio is 20% and when the aperture ratio is 50%, the sheet resistance value of the region G in the silicon wafer is lower than in the case of the aperture ratio of 100%, and the standard deviation ⁇ of the in-plane sheet resistance value is ⁇ . Becomes smaller. Therefore, the aperture ratio is preferably 20% to 50%.
  • the opening ratio may be changed depending on the distance from the supply port 10 of the source gas 13.
  • the raw material gas 13 In a place near the supply port 10 in the quartz tube 8, the raw material gas 13 has a high flow rate, and a low temperature raw material gas 13 that is not sufficiently warmed is supplied to the silicon wafer 2. For this reason, in order to suppress the influence of the low temperature raw material gas 13 in the silicon wafer 2, it is preferable that the opening ratio of the supply hole 17 is low.
  • the arrangement intervals of the supply holes 17 are preferably set at the same opening size at equal intervals so that the supply amount of the raw material gas 13 to the silicon wafer 2 installed in the sub-boat 1 is not biased.
  • the second shielding plate 16 As a form of installation of the second shielding plate 16, as in the first embodiment, the second shielding plate 16 is installed on the upper part of the wheel 4, the wheel reinforcing part 5, and the parent boat reinforcing part 6 of the parent boat 3, and the supply hole 17 is not opened.
  • region directly under the subboat 1 and the supply hole 17 opened like this Embodiment 2 can be arrange
  • a shielding plate in which the first shielding plate 14 and the second shielding plate 16 are configured as one shielding plate may be mounted on the parent boat 3.
  • the horizontal diffusion furnace 30 according to the second embodiment has the same effect as the horizontal diffusion furnace 20 according to the first embodiment because it includes the first shielding plate 14. Further, the horizontal diffusion furnace 30 according to the second embodiment includes the second shielding plate 16 that shields the lower region of the child boat 1, and the supply hole 17 formed in the second shielding plate 16 includes the child boat 1. Since an appropriate amount of source gas 13 can be supplied to the lower portion of the substrate, in-plane variation of the sheet resistance of the silicon wafer 2 can be further suppressed, and device characteristics and yield of the silicon wafer 2 can be further improved.
  • FIG. 19 is a top view of the solar battery cell according to the third embodiment of the present invention.
  • 20 is a cross-sectional view of the solar battery cell according to the third embodiment of the present invention, taken along the line XX-XX in FIG.
  • FIGS. 21 and 22 are cross-sectional views showing the manufacturing process of the solar battery cell according to the third embodiment of the present invention.
  • the n-type impurity diffusion layer 42 as the second conductivity type semiconductor layer
  • It is explanatory drawing which shows the process of forming the p-type impurity diffusion layer as 1 conductivity type semiconductor layer, and the p-type single crystal silicon wafer 41 which has a texture structure.
  • a p-type single crystal silicon wafer 41 as a first conductive semiconductor substrate for a solar battery cell according to the present embodiment has a light receiving surface that has unevenness 41T and a texture structure that reduces light reflection is a first main surface. 41A. Then, an n-type impurity diffusion layer 42 as a second conductivity type semiconductor layer is formed on the first main surface where the texture structure is formed, and an antireflection film 43 is laminated on the n-type impurity diffusion layer 42.
  • a light receiving surface grid electrode and a light receiving surface bus electrode are formed in a comb shape as the light receiving surface electrode 44 that penetrates the antireflection film 43 and is connected to the n-type impurity diffusion layer 42.
  • a back electrode 45 made of aluminum (Al) is formed on the entire back surface 41B, which is the second main surface facing the light receiving surface 41A of the p-type single crystal silicon wafer 41.
  • pyramidal irregularities 41T are formed on the surface of the p-type single crystal silicon wafer 41 as a texture structure for reducing the light reflectance as shown in FIG.
  • the p-type single crystal silicon wafer 41 is etched with an alkaline aqueous solution such as a sodium hydroxide aqueous solution.
  • An additive may be added to the alkaline aqueous solution.
  • the p-type single crystal silicon wafer 41 is put into the horizontal diffusion furnace 20.
  • the p-type single crystal silicon wafer 41 is heated in the presence of phosphorus oxychloride (POCl 3 ) vapor to form a surface layer on one surface side of the p-type single crystal silicon wafer 41 as shown in FIG.
  • An n-type impurity diffusion layer 42 is formed to form a pn junction.
  • a phosphorus glass layer mainly composed of glass formed on the surface of the n-type impurity diffusion layer 42 is mixed with hydrofluoric acid (HF), nitric acid (HNO 3 ), sulfuric acid (H 2 SO 4 ), or the like. Is removed by wet etching using an etchant.
  • a silicon nitride film (SiN film) is formed on the n-type impurity diffusion layer 42 by plasma CVD (Chemical Vapor Deposition) as the antireflection film 43.
  • a light receiving surface grid electrode made of silver (Ag) and a light receiving surface bus electrode are screened in a comb shape on the n-type impurity diffusion layer 42. Formed by printing method. Further, a back electrode made of aluminum (Al) is formed on the entire back surface 41B of the p-type single crystal silicon wafer 41 by a screen printing method. Thereafter, the p-type single crystal silicon wafer 41 is baked in a baking furnace. A light receiving surface electrode 44 and a back surface electrode 45 are formed. Thereby, the solar cell concerning this Embodiment 3 shown in FIG. 19 and FIG. 20 is manufactured.
  • the solar cell is manufactured using the horizontal diffusion furnace 20 shown in the first embodiment in the step of forming the n-type impurity diffusion layer 42. Then, the photoelectric conversion efficiency was compared.
  • the photoelectric conversion efficiency of the solar battery cell produced using the horizontal diffusion furnace 20 according to the first embodiment was defined as the solar battery cell of Example 3.
  • a solar cell produced by using a horizontal diffusion furnace without a shielding plate having the same configuration as the horizontal diffusion furnace 20 except that the first shielding plate 14 was not provided was used as a solar cell of Comparative Example 2. And the photoelectric conversion efficiency of the photovoltaic cell of Example 3 and Comparative Example 2 was measured.
  • FIG. 23 is a diagram showing photoelectric conversion efficiencies of solar cells in Example 3 and Comparative Example 2 in Embodiment 3 of the present invention.
  • the photoelectric conversion efficiency shown in FIG. 23 is an average value of photoelectric conversion efficiencies of 120 solar cells.
  • the photoelectric conversion efficiency of the solar battery cell of Example 3 manufactured using the horizontal diffusion furnace 20 according to the first embodiment including the first shielding plate 14 is manufactured using the horizontal diffusion furnace without the shielding plate. It turns out that it is improving rather than the photoelectric conversion efficiency of the photovoltaic cell of comparative example 2. Thereby, it was confirmed that the photoelectric conversion efficiency of the solar battery cell can be improved by using the horizontal diffusion furnace 20 including the first shielding plate 14.
  • the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

Abstract

L'invention concerne un four à diffusion horizontal (20) qui comprend : un tube de quartz (8) allongé horizontalement, disposé dans un état horizontal, et pourvu d'un orifice d'alimentation en gaz de traitement (10) sur un côté d'extrémité et d'un orifice d'échappement de gaz de traitement sur l'autre côté d'extrémité ; et un dispositif de chauffage (9) chauffant l'intérieur du tube de quartz (8). En outre, ce four à diffusion horizontal (20) comprend : une nacelle fille (1) contenant des tranches de silicium (2) dans un état vertical ; une nacelle mère (3) allongée horizontalement, pouvant se déplacer au moyen d'une pluralité de roues (4) dans sa partie inférieure, portant la nacelle fille (1), et transportée dans un état horizontal à l'intérieur du tube de quartz (8) ; et une première plaque isolante (14) recouvrant une partie située au-dessus des roues (4) sur la nacelle mère (3).
PCT/JP2016/083807 2015-12-28 2016-11-15 Four à diffusion horizontal et procédé de fabrication de cellules solaires Ceased WO2017115573A1 (fr)

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TW105142682A TWI606603B (zh) 2015-12-28 2016-12-22 橫型擴散爐及太陽電池單元的製造方法

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CN115274924A (zh) * 2022-07-20 2022-11-01 无锡松煜科技有限公司 一种改善扩散方阻均匀性和稳定性的方法
US20230212786A1 (en) * 2020-06-04 2023-07-06 Sumco Corporation Method of heat-treating silicon wafer using lateral heat treatment furnace
CN119050199A (zh) * 2024-08-20 2024-11-29 绵阳炘皓新能源科技有限公司 一种降低topcon电池片高温工序粉尘污染的方法

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US12320034B2 (en) * 2020-06-04 2025-06-03 Sumco Corporation Method of heat-treating silicon wafer using lateral heat treatment furnace
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