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WO2017154089A1 - Drive device - Google Patents

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Publication number
WO2017154089A1
WO2017154089A1 PCT/JP2016/057076 JP2016057076W WO2017154089A1 WO 2017154089 A1 WO2017154089 A1 WO 2017154089A1 JP 2016057076 W JP2016057076 W JP 2016057076W WO 2017154089 A1 WO2017154089 A1 WO 2017154089A1
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WO
WIPO (PCT)
Prior art keywords
circuit
electrode
capacitor
scan
screen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2016/057076
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French (fr)
Japanese (ja)
Inventor
圭介 岩脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
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Filing date
Publication date
Application filed by Pioneer Corp filed Critical Pioneer Corp
Priority to PCT/JP2016/057076 priority Critical patent/WO2017154089A1/en
Publication of WO2017154089A1 publication Critical patent/WO2017154089A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03BAPPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B21/00Projectors or projection-type viewers; Accessories therefor
    • G03B21/54Accessories
    • G03B21/56Projection screens
    • G03B21/60Projection screens characterised by the nature of the surface
    • G03B21/62Translucent screens
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to a driving device for driving a display unit.
  • Patent Document 1 discloses a display device that displays an image projected from a projector or the like when a transparent body such as glass is used as a screen and the screen is in a scattering state.
  • the output stage of the common electrode drive circuit includes a plurality of sub output stages each capable of outputting a voltage to the common electrode, and the common electrode potential of each polarity. It is described that each supply period is divided into a plurality of partial periods and a voltage is supplied to the common electrode.
  • the common electrode is shared, but a plurality of scan electrodes may be provided.
  • the method of Patent Document 2 has a problem that the circuit on the scan electrode side becomes complicated and the circuit scale increases.
  • an object of the present invention is to provide a drive device that can reduce, for example, radiated noise and can prevent an image display from being affected.
  • a first control circuit is connected between the second control circuit in which the output impedance is larger than before and after the change, and the first drive circuit that drives the first control circuit and the first control circuit.
  • a constant circuit wherein the first time constant circuit and the second electrode are connected by wiring.
  • FIG. 2 is a circuit diagram of the driving device shown in FIG. 1.
  • FIG. 4 is a timing chart of driving waveforms by the circuit shown in FIG. 3.
  • FIG. 5 is a timing chart showing the internal operation of part A and part B in FIG. 4.
  • FIG. 5 is an explanatory diagram showing a current flowing through a scan drive circuit during a portion A in FIG. 4. 4 is a comparison of simulation results between the circuit shown in FIG. 3 and a conventional circuit.
  • FIG. FIG. 2 is a circuit diagram of the driving device shown in FIG. 1.
  • FIG. 9 is a circuit diagram of the driving device shown in FIG. 8. It is a timing chart of the drive waveform by the circuit shown in FIG. It is the schematic block diagram which showed the structural example of the other screen which can utilize the circuit shown by FIG.
  • FIG. 13 is a schematic cross-sectional view of the screen shown in FIG. 12. It is a circuit diagram of the drive device in the case of a screen in a normal mode. It is a timing chart of the drive waveform by the circuit shown in FIG. It is typical sectional drawing which showed the structural example of the screen provided with the touch panel.
  • a driving apparatus periodically changes a voltage applied to a second electrode of the display unit, a first control circuit that controls a voltage applied to the first electrode of the display unit, A second control circuit in which the output impedance at the time of change is greater than before and after the change, and a first time constant electrically connected between the first drive circuit and the first control circuit for driving the first control circuit And a circuit.
  • the first time constant circuit and the second electrode are connected by wiring.
  • the scan electrode (first electrode) also changes gradually by the first time constant circuit under the influence of the change of the common electrode.
  • the common electrode does not change at the timing of changing to the scattering state, the first time constant circuit does not act and the scan electrode can be changed sharply. Therefore, it is possible to reduce the radiation noise during the common inversion driving and not to affect the video display.
  • the first time constant circuit and the second electrode are connected by wiring, the voltage change time on the common side and the voltage change time on the scan side can be made equal when the common is inverted. Therefore, it is possible to prevent the liquid crystal from being erroneously scattered due to a potential difference between the two electrodes during common inversion.
  • the first control circuit is a push-pull circuit composed of two transistors, and the first time constant circuit includes a capacitor connected between the gate of the transistor and the second electrode, the capacitor and the first You may be comprised by the resistor connected between drive circuits.
  • the common electrode second electrode
  • the common electrode changes, so that the input capacitance of the gate of the transistor constituting the push-pull circuit is apparently increased, and the switching of the transistor is delayed. Can do.
  • the common electrode does not change, the input capacitance of the gate of the transistor does not increase apparently, so that a steep change can be made.
  • a second drive circuit for driving the second control circuit and a second time constant circuit connected between the second control circuit may be provided. By doing so, the common electrode can be gradually changed by the second time constant circuit.
  • the second control circuit includes a push-pull circuit composed of two transistors.
  • the second time constant circuit has one side connected to the second electrode and the drain or source of the transistor, and the other side connected to the gate of the transistor. And a resistor connected between the gate and the second drive circuit.
  • the apparent capacitance of the gate can also be increased on the second electrode (common electrode) side, and the switching of the transistors can be delayed.
  • the circuit configuration can be made substantially the same as that of the first electrode (scan electrode) side, and the circuit design can be facilitated.
  • a plurality of first control circuits may be provided, and a plurality of first time constant circuits may be provided corresponding to the first control circuit.
  • the plurality of first time constant circuits may be connected to the second electrode by a common wiring. By doing in this way, the circuit connected to the second electrode can be reduced and the circuit can be simplified.
  • a display device 100 including a driving device according to a first embodiment of the present invention will be described with reference to FIGS.
  • the display device 100 includes a screen 1, a common drive circuit 2, a scan drive circuit 3, a drive control circuit 4, and a projector 5.
  • the screen 1 may be any screen that can change the optical state by voltage application and can be driven by common inversion driving.
  • the scattering state is an image state
  • the screen 1 may be, for example, a light control screen that uses a liquid crystal material and changes a scattering state and a transparent transmission state in which scattering of incident light is small.
  • Examples of the light control screen include a screen using a liquid crystal element such as a polymer dispersed liquid crystal.
  • FIG. 2 shows a schematic cross-sectional view of the screen 1 capable of controlling the optical state.
  • the screen 1 shown in FIG. 2 has an optical layer 15 in which a composite material containing liquid crystal is sandwiched between a pair of transparent glass plates 11 and 12.
  • a common electrode 13 is formed on the entire surface of one glass plate 11 on the optical layer 15 side.
  • a scan electrode 14 is formed on the entire surface of the other glass plate 12 on the optical layer 15 side.
  • An intermediate layer made of an insulator may be formed between the electrodes 13 and 14 and the optical layer 15.
  • the common electrode 13 and the scan electrode 14 are formed as transparent electrodes by using, for example, ITO (indium tin oxide).
  • the optical layer 15 is disposed between the common electrode 13 and the scan electrode 14.
  • a voltage is applied to the screen 1 so that a potential difference is generated between the scan electrode 14 as the first electrode and the common electrode 13 as the second electrode.
  • the optical state in the optical layer 15 changes depending on the voltage applied to the common electrode 13 and the scan electrode 14.
  • the screen 1 is classified into a reverse mode and a normal mode according to a state when a voltage is applied so as to generate a potential difference.
  • the screen 1 operating in the reverse mode is in a transparent transmissive state in a normal state where no voltage is applied. When a voltage is applied, it becomes a scattering state with a scattering rate of parallel rays according to the applied voltage.
  • the screen operating in the normal mode the screen 1 is in a scattering state in a normal state where no voltage is applied.
  • a transparent transmission state with parallel light transmittance corresponding to the applied voltage is obtained.
  • a predetermined scattering state corresponds to an image state
  • a transparent transmission state having a higher parallel light transmittance corresponds to a non-image state.
  • the reverse mode will be described.
  • the common drive circuit 2 applies a predetermined voltage to the common electrode 13 based on the control of the drive control circuit 4. Details will be described later.
  • the scan drive circuit 3 applies a predetermined voltage to the scan electrode 14 based on the control of the drive control circuit 4. Details will be described later.
  • the drive control circuit 4 controls the common drive circuit 2 and the scan drive circuit 3 so that the screen 1 is switched to the scattering state in accordance with the projection timing of the projector 5.
  • the drive control circuit 4 acquires an image periodic signal such as a vertical synchronization signal from the projector 5 by, for example, a wireless signal, and performs synchronization control between the screen 1 and the projector 5.
  • Projector 5 projects image light when screen 1 is in a scattering state.
  • the projector 5 can use a transmissive or reflective liquid crystal light valve that sequentially shifts the black state (state in which no projection light is emitted) on the screen 1 during the scanning period, but other elements may be used.
  • the projector 5 may perform raster scanning in a video scanning cycle and project video light (image light) on the display surface of the screen 1 in a dot sequential manner. That is, video light is projected intermittently at a predetermined cycle.
  • a laser projector that reflects and shakes the irradiation direction of the intensity-modulated light beam with a movable mirror can be used.
  • the projector 5 only needs to be able to project video light modulated by video information (image information) onto the screen 1.
  • video information is obtained from a video signal input to the projector 5.
  • Video signals include, for example, NTSC (National Television Standards Committee), analog video signals such as PAL (Phase Alternation by Line), MPEG-TS (Moving Picture Experts Group-Transport Stream) format, HDV (High -There are video signals in digital format such as Definition (Video) format.
  • the projector 5 may receive not only a moving image video signal but also a still image video signal such as JPEG (Joint Photographic Experts Group). In this case, the projector 5 may scan the screen 1 repeatedly with the same video light for displaying a still image.
  • FIG. 3 shows a circuit example of the common drive circuit 2 and the scan drive circuit 3 according to this embodiment.
  • the common drive circuit 2 and the scan drive circuit 3 constitute a drive device 10 according to this embodiment.
  • the common drive circuit 2 includes FETs 21 and 22, resistors 23 and 24, capacitors 25 and 26, and a gate driver 27.
  • the FET 21 is a P-channel FET (Field-Effect-Transistor), the source is connected to the power supply Vb, the drain is the drain of the FET 22, one side of the capacitor 26, the other side of the capacitor 25, and the common electrode 13 of the liquid crystal element (screen 1).
  • the scan drive circuit 3 is connected to one side of the capacitor 36 and the other side of the capacitor 35, and the gate is connected to one side of the resistor 23 and one side of the capacitor 25.
  • the FET 22 is an N-channel FET, the source is grounded, and the drain is the drain of the FET 21, one side of the capacitor 26, the other side of the capacitor 25, the common electrode 13 of the liquid crystal element, and one side of the capacitor 36 of the scan drive circuit 3.
  • the other side of the capacitor 35 is connected, and the gate is connected to one side of the resistor 24 and the other side of the capacitor 26.
  • the resistor 23 has one side connected to the gate of the FET 21 and one side of the capacitor 25, and the other side connected to the gate driver 27.
  • the resistor 24 has one side connected to the gate of the FET 22 and the other side of the capacitor 26, and the other side connected to the gate driver 27.
  • the capacitor 25 has one side connected to the gate of the FET 21 and one side of the resistor 23, and the other side connected to one side of the capacitor 26, the drain of the FET 21, the drain of the FET 22, one side of the capacitor 36 of the scan drive circuit 3, and the other side of the capacitor 35. Connected to the side.
  • the capacitor 26 has one side connected to the other side of the capacitor 25, the drain of the FET 21, the drain of the FET 22, one side of the capacitor 36 of the scan drive circuit 3, and the other side of the capacitor 35, and the other side to one of the gate of the FET 22 and one of the resistors 23. Connected to the side.
  • the gate driver 27 is a driver circuit that outputs a drive signal for the common electrode 13 under the control of the drive control circuit 4.
  • the FET 21 and the FET 22 are push-pull circuits composed of two transistors and function as a second control circuit.
  • the gate driver 27 functions as a second drive circuit that drives the second control circuit, and includes a time constant circuit including a resistor 23 and a capacitor 25, a time constant circuit including a resistor 24 and a capacitor 26, Functions as a second time constant circuit.
  • the scan drive circuit 3 includes FETs 31 and 32, resistors 33 and 34, capacitors 35 and 36, and a gate driver 37.
  • the FET 31 is a P-channel FET, the source is connected to the power supply Vb, the drain is connected to the drain of the FET 32 and the scan electrode 14 of the liquid crystal element, and the gate is connected to one side of the resistor 33 and one side of the capacitor 35. Yes.
  • the FET 32 is an N-channel FET, the source is grounded, the drain is connected to the drain of the FET 31 and the scan electrode 14 of the liquid crystal element, and the gate is connected to one side of the resistor 34 and the other side of the capacitor 36.
  • the resistor 33 has one side connected to the gate of the FET 31 and one side of the capacitor 35, and the other side connected to the gate driver 37.
  • the resistor 34 has one side connected to the gate of the FET 32 and the other side of the capacitor 36, and the other side connected to the gate driver 37.
  • the capacitor 35 has one side connected to the gate of the FET 31 and one side of the resistor 33, and the other side connected to one side of the capacitor 36 and the common electrode 13. That is, the capacitor 35 is also connected to the drain of the FET 21 of the common drive circuit 2, the drain of the FET 22, the other side of the capacitor 25, and one side of the capacitor 26.
  • the capacitor 36 has one side connected to the other side of the capacitor 35 and the common electrode 13, and the other side connected to the gate of the FET 32 and one side of the resistor 34. That is, the capacitor 36 is also connected to the drain of the FET 21, the drain of the FET 22, the other side of the capacitor 25, and one side of the capacitor 26 of the common drive circuit 2.
  • the gate driver 37 is a driver circuit that outputs a drive signal for the scan electrode 14 under the control of the drive control circuit 4.
  • the FET 31 and the FET 32 are push-pull circuits composed of two transistors and function as a first control circuit.
  • the gate driver 37 functions as a first drive circuit that drives the first control circuit, and includes a time constant circuit including a resistor 33 and a capacitor 35, a time constant circuit including a resistor 34 and a capacitor 36, Functions as a first time constant circuit. Further, the first time constant circuit and the common electrode 13 are directly connected by wiring.
  • FIG. 4 is a timing chart showing drive waveforms of the common electrode 13 and the scan electrode 14 shown in FIG.
  • the common electrode 13 is changed to, for example, Vb volt and 0 volt at a constant period, for example, every frame by the common inversion driving.
  • the scan electrode 14 applies a pulsed voltage so that a potential difference from the common electrode 13 is generated at the timing of the scattering state.
  • FIG. 5A shows a timing chart of the internal operations of the common drive circuit 2 and the scan drive circuit 3 in the portion A of FIG. 4, and the timings of the internal operations of the common drive circuit 2 and the scan drive circuit 3 in the portion B of FIG. The chart is shown in FIG.
  • the common drive circuit 2 side will be described.
  • the common Lo gate signal (the gate control signal of the FET 22) output from the gate driver 27 is set to the Hi level in order to turn on the FET 22. Then, a current flows in the direction of the resistor 24 that charges the gate capacitance of the FET 22 and the gate and source of the FET 22.
  • the gate voltage of the FET 22 exceeds the threshold voltage
  • the drain voltage of the FET 22 the potential of the common electrode 13 starts to gradually decrease, and the current for charging the capacitor 26 increases.
  • the apparent capacity of the capacitor 26 increases, the charge current of the gate capacity decreases, and the FET 22 is turned on later (FETs 22VGS and VGS are gate-source voltages). Therefore, the voltage change of the common electrode 13 becomes slow (dV / dt becomes low). That is, in the common drive circuit 2, the output impedance when the common voltage changes is larger than before and after the change.
  • the scan drive circuit 3 side will be described.
  • the common Lo gate signal output from the gate driver 27 becomes Hi level, and at the same time, the scan Lo gate signal output from the gate driver 37 also becomes Hi level.
  • a current (see FIG. 6A) flowing through the gate capacitance of the FET 32 flows and tries to turn on the FET 32.
  • the common electrode 13 falls at the same time as the scan Lo gate signal becomes Hi level, the current passes through the capacitor 36.
  • the current flowing through the common electrode 13 increases. In other words, the apparent capacitance of the capacitor 36 is increased, thereby reducing the current flowing through the gate capacitance of the FET 32 and turning on the FET 32 (FET 32VGS). Therefore, the voltage change of the scan electrode 14 is also delayed. Therefore, as shown in FIG. 4 and FIG. 5, the voltage change becomes gentle (dV / dt becomes low) in both the common electrode 13 and the scan electrode 14.
  • portion B in FIG. 4 will be described with reference to FIG.
  • the voltage of the common electrode 13 is constant. Therefore, since there is no increase in the current flowing through the capacitor 36 to the common electrode 13, the gate capacitance of the FET 32 is charged at a high speed, and the voltage change of the scan electrode 14 is fast. That is, the change in the voltage of the scan electrode 14 becomes steep.
  • Fig. 7 shows the simulation results of the circuit shown in Fig. 3 and the conventional circuit.
  • 7 is a simulation result of a circuit without a time constant circuit using a conventional capacitor or resistor
  • a countermeasure is a simulation result of the circuit shown in FIG.
  • the capacitive coupling noise in FIG. 7 is a waveform of noise corresponding to a change in the common voltage and the scan voltage
  • the capacitive coupling noise (FFT) is a waveform of capacitive coupling noise in the period of one cycle of the waveform of the common electrode 13 (Fast Fourier Transform). )
  • FFT capacitive coupling noise
  • the scan drive circuit 3 that controls the voltage applied to the scan electrode 14 of the screen 1 and the voltage applied to the common electrode 13 of the screen 1 are periodically changed, and the output impedance at the time of change is And a common drive circuit 2 that is larger than before and after the change.
  • the scan drive circuit 3 includes a push-pull circuit in which the drains of two FETs are connected to each other, and further includes a gate driver 37 that drives the push-pull circuit, and a capacitor that is connected between the push-pull circuit and the gate driver 37. And a time constant circuit composed of a capacitor 36 and a resistor 34.
  • the time constant circuit composed of the capacitor 35 and the resistor 33 and the time constant circuit composed of the capacitor 36 and the resistor 34 are directly connected to the common electrode 13 by wiring.
  • the scan electrode 14 is gradually changed by the time constant circuit under the influence of the change of the common electrode 13.
  • the common electrode 13 does not change at the timing of changing to the scattering state, the time constant circuit does not act and the scan electrode 14 can be changed sharply. Therefore, it is possible to reduce the radiation noise during the common inversion driving and not to affect the video display.
  • the time constant circuit composed of the capacitor 35 and the resistor 33 and the time constant circuit composed of the capacitor 36 and the resistor 34 are directly connected to the common electrode 13, the voltage change time (dV / dt) and the voltage change time (dV / dt) on the scan side can be made equal. Therefore, it is possible to prevent the liquid crystal from being erroneously scattered due to a potential difference between the two electrodes during common inversion.
  • the time constant circuit includes capacitors 35 and 36 connected between the gate of the FET and the common electrode, and a resistor 33 connected between the capacitor 35 and the gate driver 37, and between the capacitor 36 and the gate driver 37. And a resistor 34 connected to the.
  • the common drive circuit 2 includes a push-pull circuit in which the drains of two FETs are connected to each other, and includes a gate driver 27, a capacitor 25 connected between the push-pull circuit and the gate driver 27, and a resistor 23. And a time constant circuit including a capacitor 26 and a resistor 24.
  • the time constant circuit is connected between the capacitors 25 and 26 connected between the gate and drain of the FET, the resistor 23 connected between the capacitor 25 and the gate driver 27, and the capacitor 26 and the gate driver 27. And a resistor 24.
  • the common electrode 13 can be gradually changed by the second time constant circuit, and the common electrode 13 side can have substantially the same circuit configuration as the scan electrode 14 side. Can be easily.
  • a display device according to a second embodiment of the present invention will be described with reference to FIGS.
  • the same parts as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.
  • This embodiment is different in that the screen is a screen 1A divided into a plurality of areas as shown in FIGS. Accordingly, the scan drive circuit 3A has n of the first scan drive circuit 301 to the nth scan drive circuit 30n (n is the number of divisions), and the common drive circuit 2 and the scan drive circuit 3A are used in this embodiment. 10A of drive devices concerning this are comprised.
  • the common electrode 13 is formed on the entire surface as in the first embodiment.
  • the scan electrode 14 is divided into a plurality of parts, and each of the divided scan electrodes is provided on the screen 1A.
  • the first scan drive circuit 301 to the nth scan drive circuit 30n are connected.
  • FIG. 10 shows a circuit diagram of the common drive circuit 2 and the scan drive circuit 3A according to the present embodiment.
  • FIG. 10 shows an example in which the screen 1A is divided into four parts.
  • the first scan drive circuit 301 includes FETs 31a and 32a, resistors 33a and 34a, capacitors 35a and 36a, and a gate driver 37a.
  • the second scan drive circuit 302 includes FETs 31b and 32b, resistors 33b and 34b, capacitors 35b and 36b, and a gate driver 37b.
  • the third scan drive circuit 303 includes FETs 31c and 32c, resistors 33c and 34c, capacitors 35c and 36c, and a gate driver 37c.
  • the fourth scan drive circuit 304 includes FETs 31d and 32d, resistors 33d and 34d, capacitors 35d and 36d, and a gate driver 37d.
  • the circuit configuration of these scan drive circuits is the same as that of the first embodiment. That is, a plurality of first control circuits are provided, and a plurality of first time constant circuits are provided corresponding to the first control circuits.
  • the drain of the FET of each scan drive circuit is connected to the scan electrode in the corresponding region. Further, the other end side of the capacitor 35 a and one end side of the capacitor 36 a are connected to the common electrode 13. The other end side of the capacitor 35b and one end side of the capacitor 36b, the other end side of the capacitor 35b and one end side of the capacitor 36b, the other end side of the capacitor 35b, and one end side of the capacitor 36b are also connected to the common electrode 13 in the same manner.
  • the wiring that connects the common electrode 13 and each scan drive circuit is a common wiring.
  • FIG. 11 shows a timing chart of operations of the common drive circuit 2 and the scan drive circuit 3A according to the present embodiment.
  • the screen 1A By configuring the screen 1A as in the present embodiment, it is possible to switch between the scattering state and the transmission state for each divided region. Further, as shown in FIG. 11, by shifting the voltage waveform applied to each of the first scan electrode, the second scan electrode, and the third scan electrode, the portion irradiated with the image light about the screen 1A is The video state is maintained. Thereby, the image light that scans the screen 1A is scattered by the screen 1A in the scattering state. On the other hand, the portion of the screen 1A that is not irradiated with the image light is controlled to a non-image state. Each divided region is controlled to a transparent transmission state in a non-video state during most periods when scanning with video light is not performed. Therefore, the see-through characteristic of the screen 1A can be obtained while maintaining the visibility of the image during the projection period of the image light.
  • FIG. 8 etc. demonstrated the example in which one screen is divided
  • the screen 1B shown in FIG. 12 has three screens stacked as shown in FIG.
  • the screen 1B includes a first screen having an optical layer 15a between the common electrode 13a and the scan electrode 14a, a second screen having an optical layer 15b between the common electrode 13b and the scan electrode 14b, and a common electrode 13c.
  • a third screen having an optical layer 15c is formed between the scan electrode 14c.
  • the first screen is sandwiched between the transparent glass plate 12 and the transparent glass plate 16, the second screen is sandwiched between the glass plate 16 and the transparent glass plate 17, and the third screen is the glass plate 17 and the transparent glass plate. 11. That is, in the screen 1B, three screens are formed between the glass plates 11 and 12, and the screens are arranged with the glass plates 16 and 17 spaced apart.
  • the first scan drive circuit 301 to the third scan drive circuit 303 (in the case of FIG. 12, the screen 1B has three layers so that there are three) are the scan electrodes of each screen. It is connected to the.
  • the circuit configuration is the same as in FIG. 10 (however, there are three scan drive circuits).
  • a plurality of scan drive circuits are provided, and each scan drive circuit is provided with a time constant circuit corresponding to a push-pull circuit.
  • the reverse mode liquid crystal screen has been described.
  • the normal mode may be used.
  • a circuit diagram in the normal mode is shown in FIG. In FIG. 14, the channel of the FET of the scan drive circuit 3 is changed. That is, the FET 31 that is a P-channel FET becomes an N-channel FET 31N, and the FET 32 that is an N-channel FET becomes a P-channel FET 32N.
  • the FET 31N has a drain connected to the power supply Vb and a source connected to the source of the FET 32N.
  • the FET 32N has a drain grounded and a source connected to the source of the FET 31N.
  • FIG. 15 shows an example of drive waveforms in the circuit of FIG. In the normal mode, since there is a scattering state when there is no potential difference between the common electrode 13 and the scan electrode 14, a pulsed waveform as shown in FIG. To do.
  • FIG. 16 shows an example in which a touch panel 18 is provided on the common electrode 13 side.
  • the capacitor is described as an independent element, but the parasitic capacitance of the transistor may be used.
  • the common drive circuit 2 may be configured as described in Patent Document 2 instead of the time constant circuit including a capacitor and a resistor as illustrated. In short, any configuration may be used as long as the common electrode 13 is gradually changed.

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Abstract

This drive device is provided with a scan drive circuit (3) for controlling the voltage applied to a scan electrode of a screen, and a common drive circuit (2) for periodically changing the voltage applied to a common electrode of the screen and also gradually changing the applied voltage. The scan drive circuit (3) is provided with a push-pull circuit in which drains of two FETs (31, 32) are connected, and a gate driver (37) for driving the push-pull circuit, and is further provided with a time constant circuit comprising capacitors (35, 36) and resistors (33, 34), the time constant circuit being connected between the push-pull circuit and the gate driver (37). The time constant circuit and the common electrode are also connected by wiring.

Description

駆動装置Drive device

 本発明は、表示部を駆動する駆動装置に関する。 The present invention relates to a driving device for driving a display unit.

 例えばガラスのような透明体をスクリーンとして、そのスクリーンが散乱状態のときにプロジェクタ等から投射した画像をそのスクリーンに表示する表示装置は、例えば特許文献1のように既に知られている。 For example, Patent Document 1 discloses a display device that displays an image projected from a projector or the like when a transparent body such as glass is used as a screen and the screen is in a scattering state.

 特許文献1のようなスクリーンとして液晶表示装置を用いる場合、液晶素子は、直流駆動すると寿命が短くなることから一定周期毎に正負交流電圧を加えて駆動する交流駆動を行うのが一般的である。その中で、例えばフレーム毎等の映像周期毎に交流駆動することをフレーム反転方式といい、更に、コモン電極のバイアス電圧を反転する方法をコモン反転方式という。コモン反転方式は正負二電源を用意する必要がないため、回路構成が簡単になるメリットがある。 When a liquid crystal display device is used as a screen as in Patent Document 1, since the life of a liquid crystal element is shortened when DC driving is performed, it is common to perform AC driving in which positive and negative AC voltages are applied at regular intervals. . Among them, for example, AC driving for every video cycle such as every frame is called a frame inversion method, and a method for inverting the bias voltage of the common electrode is called a common inversion method. The common inversion method has the advantage of simplifying the circuit configuration because it is not necessary to prepare two positive and negative power supplies.

 しかしながら、コモン反転駆動の場合、コモン電極電位が反転する瞬間に、コモン電極への電位供給経路に、大きなピークを有する充放電電流が発生し、この電流が放射ノイズの原因となるという問題がある。 However, in the case of common inversion driving, a charging / discharging current having a large peak is generated in the potential supply path to the common electrode at the moment of inversion of the common electrode potential, and this current causes radiation noise. .

 上記した問題に対しては、例えば特許文献2に、コモン電極駆動回路の出力段に、それぞれがコモン電極に電圧を出力することが可能な複数のサブ出力段を備え、各極性のコモン電極電位の各供給期間を複数の部分期間に分割してコモン電極に電圧を供給することが記載されている。 To solve the above problem, for example, in Patent Document 2, the output stage of the common electrode drive circuit includes a plurality of sub output stages each capable of outputting a voltage to the common electrode, and the common electrode potential of each polarity. It is described that each supply period is divided into a plurality of partial periods and a voltage is supplied to the common electrode.

特許第5774675号公報Japanese Patent No. 5774675 特許第5323924号公報Japanese Patent No. 5323924

 特許文献1のようなスクリーンとして液晶表示装置を用いる場合、コモン電極と対向する電極(スキャン電極とも呼ばれる)の電位を任意の期間に変化させることで、透過状態と散乱状態とに変化させて、散乱状態の際に映像を表示させる。コモン反転方式の場合、スキャン電極もコモン電極の電位の反転と共に電位を反転させる必要があるので、特許文献2に記載の方法をスキャン電極にも適用することで、コモン電極だけでなくスキャン電極の変化によるコモン反転時に発生する放射ノイズを低減することは可能である。 When a liquid crystal display device is used as a screen as in Patent Document 1, by changing the potential of an electrode (also referred to as a scan electrode) facing the common electrode in an arbitrary period, the transmission state and the scattering state are changed, Display video in the scattered state. In the case of the common inversion method, since it is necessary to invert the potential of the scan electrode together with the inversion of the potential of the common electrode, by applying the method described in Patent Document 2 to the scan electrode as well, It is possible to reduce the radiation noise generated at the time of common inversion due to a change.

 しかしながら、特許文献2の方法をスキャン電極にも適用すると、透過状態と散乱状態とに変化させるタイミングにおいても波形の変化が緩やかになってしまい、散乱状態への変化が遅れて映像等の表示に影響を及ぼしてしまう。 However, if the method of Patent Document 2 is applied also to the scan electrode, the waveform changes gradually at the timing of changing to the transmission state and the scattering state, and the change to the scattering state is delayed to display an image or the like. It will have an effect.

 また、スクリーンを複数分割したり、複数のスクリーンを積層したりして構成した際に、コモン電極は共通化されるが、スキャン電極は複数設けられることがある。その場合、特許文献2の方法ではスキャン電極側の回路が複雑化して回路規模が増大してしまうという問題もある。 Also, when the screen is divided into a plurality of parts or a plurality of screens are laminated, the common electrode is shared, but a plurality of scan electrodes may be provided. In that case, the method of Patent Document 2 has a problem that the circuit on the scan electrode side becomes complicated and the circuit scale increases.

 そこで、本発明は、上述した問題に鑑み、例えば、放射ノイズを低減するとともに、映像表示に影響を及ぼさないようにすることができる駆動装置を提供することを課題とする。 Therefore, in view of the above-described problems, an object of the present invention is to provide a drive device that can reduce, for example, radiated noise and can prevent an image display from being affected.

 上記課題を解決するため出力インピーダンスが前記変化前後よりも大きくなる第2制御回路と、前記第1制御回路を駆動する第1ドライブ回路と前記第1制御回路との間に接続される第1時定数回路と、を備え、前記第1時定数回路と前記第2電極とが配線により接続されていることを特徴とする駆動装置である。 In order to solve the above-mentioned problem, a first control circuit is connected between the second control circuit in which the output impedance is larger than before and after the change, and the first drive circuit that drives the first control circuit and the first control circuit. And a constant circuit, wherein the first time constant circuit and the second electrode are connected by wiring.

本発明の第1の実施例にかかる駆動装置を備えた表示装置の概略構成図である。It is a schematic block diagram of the display apparatus provided with the drive device concerning the 1st Example of the present invention. 図1に示されたスクリーンの模式的な断面図である。It is typical sectional drawing of the screen shown by FIG. 図1に示された駆動装置の回路図である。FIG. 2 is a circuit diagram of the driving device shown in FIG. 1. 図3に示された回路による駆動波形のタイミングチャートである。FIG. 4 is a timing chart of driving waveforms by the circuit shown in FIG. 3. 図4のA部分とB部分の内部動作を示したタイミングチャートである。FIG. 5 is a timing chart showing the internal operation of part A and part B in FIG. 4. 図4のA部分の際にスキャン駆動回路に流れる電流を示した説明図である。FIG. 5 is an explanatory diagram showing a current flowing through a scan drive circuit during a portion A in FIG. 4. 図3に示された回路と従来の回路とのシミュレーション結果の比較である。4 is a comparison of simulation results between the circuit shown in FIG. 3 and a conventional circuit. 本発明の第2の実施例にかかる駆動装置を備えた表示装置の概略構成図である。It is a schematic block diagram of the display apparatus provided with the drive device concerning the 2nd Example of this invention. 図8に示されたスクリーンの模式的な断面図である。It is typical sectional drawing of the screen shown by FIG. 図8に示された駆動装置の回路図である。FIG. 9 is a circuit diagram of the driving device shown in FIG. 8. 図8に示された回路による駆動波形のタイミングチャートである。It is a timing chart of the drive waveform by the circuit shown in FIG. 図10に示された回路を利用できる他のスクリーンの構成例を示した概略構成図である。It is the schematic block diagram which showed the structural example of the other screen which can utilize the circuit shown by FIG. 図12に示されたスクリーンの模式的な断面図である。FIG. 13 is a schematic cross-sectional view of the screen shown in FIG. 12. ノーマルモードのスクリーンの場合の駆動装置の回路図である。It is a circuit diagram of the drive device in the case of a screen in a normal mode. 図14に示された回路による駆動波形のタイミングチャートである。It is a timing chart of the drive waveform by the circuit shown in FIG. タッチパネルが設けられているスクリーンの構成例を示した模式的な断面図である。It is typical sectional drawing which showed the structural example of the screen provided with the touch panel.

 以下、本発明の一実施形態にかかる駆動装置を説明する。本発明の一実施形態にかかる駆動装置は、表示部の第1電極に印加する電圧を制御する第1制御回路と、前記表示部の第2電極に印加する電圧を周期的に変化させるとともに、変化時の出力インピーダンスが変化前後よりも大きくなる第2制御回路と、前記第1制御回路を駆動する第1ドライブ回路と前記第1制御回路との間に電気的に接続される第1時定数回路と、を備えている。そして、第1時定数回路と第2電極とが配線により接続されている。このようにすることにより、第1電極をスキャン電極、第2電極をコモン電極とすれば、コモン反転方式の駆動(コモン反転駆動)により、コモン電極(第2電極)が第2制御回路により電圧が緩やかに変化するため、スキャン電極(第1電極)もコモン電極の変化の影響を受けて第1時定数回路により緩やかに変化する。また、散乱状態に変化させるタイミングでは、コモン電極は変化しないので、第1時定数回路が作用せず、スキャン電極を急峻に変化させることができる。よって、コモン反転駆動時の放射ノイズを低減するとともに、映像表示に影響を及ぼさないようにすることができる。 Hereinafter, a drive device according to an embodiment of the present invention will be described. A driving apparatus according to an embodiment of the present invention periodically changes a voltage applied to a second electrode of the display unit, a first control circuit that controls a voltage applied to the first electrode of the display unit, A second control circuit in which the output impedance at the time of change is greater than before and after the change, and a first time constant electrically connected between the first drive circuit and the first control circuit for driving the first control circuit And a circuit. The first time constant circuit and the second electrode are connected by wiring. Thus, if the first electrode is a scan electrode and the second electrode is a common electrode, the common electrode (second electrode) is driven by the second control circuit by the common inversion driving (common inversion driving). Therefore, the scan electrode (first electrode) also changes gradually by the first time constant circuit under the influence of the change of the common electrode. In addition, since the common electrode does not change at the timing of changing to the scattering state, the first time constant circuit does not act and the scan electrode can be changed sharply. Therefore, it is possible to reduce the radiation noise during the common inversion driving and not to affect the video display.

 また、第1時定数回路と第2電極が配線により接続されているので、コモン反転時にコモン側の電圧変化時間とスキャン側の電圧変化時間を同等にすることができる。したがって、コモン反転時に、2つの電極間に電位差が生じて誤って液晶が散乱状態になることを防止することができる。 Also, since the first time constant circuit and the second electrode are connected by wiring, the voltage change time on the common side and the voltage change time on the scan side can be made equal when the common is inverted. Therefore, it is possible to prevent the liquid crystal from being erroneously scattered due to a potential difference between the two electrodes during common inversion.

 また、第1制御回路は、2つのトランジスタで構成されるプッシュプル回路であって、第1時定数回路は、トランジスタのゲートと第2電極との間に接続されたコンデンサ及び該コンデンサと第1ドライブ回路との間に接続された抵抗で構成されていてもよい。このようにすることにより、コモン反転駆動時には、コモン電極(第2電極)が変化することにより、プッシュプル回路を構成するトランジスタのゲートの入力容量が見かけ上大きくなり、トランジスタの切り替えを遅くすることができる。また、コモン電極が変化しない場合は、トランジスタのゲートの入力容量が見かけ上大きくならないので、急峻な変化をさせることができる。 The first control circuit is a push-pull circuit composed of two transistors, and the first time constant circuit includes a capacitor connected between the gate of the transistor and the second electrode, the capacitor and the first You may be comprised by the resistor connected between drive circuits. In this way, during common inversion driving, the common electrode (second electrode) changes, so that the input capacitance of the gate of the transistor constituting the push-pull circuit is apparently increased, and the switching of the transistor is delayed. Can do. Further, when the common electrode does not change, the input capacitance of the gate of the transistor does not increase apparently, so that a steep change can be made.

 また、第2制御回路を駆動する第2ドライブ回路と、該第2制御回路との間に接続される第2時定数回路と、を備えてもよい。このようにすることにより、第2時定数回路によりコモン電極を緩やかに変化させることができる。 Further, a second drive circuit for driving the second control circuit and a second time constant circuit connected between the second control circuit may be provided. By doing so, the common electrode can be gradually changed by the second time constant circuit.

 また、第2制御回路は、2つのトランジスタで構成されるプッシュプル回路を含み、第2時定数回路は、一方側が第2電極及びトランジスタのドレイン又はソースと接続され、他方側がトランジスタのゲートに接続されたコンデンサと、ゲートと第2ドライブ回路との間に接続された抵抗と、で構成されていてもよい。このようにすることにより、第2電極(コモン電極)側もゲートの見かけ上の容量を大きくしてトランジスタの切り替えを遅くすることができる。また、第1電極(スキャン電極)側と略同じ回路構成とすることができ、回路設計を容易にすることができる。 The second control circuit includes a push-pull circuit composed of two transistors. The second time constant circuit has one side connected to the second electrode and the drain or source of the transistor, and the other side connected to the gate of the transistor. And a resistor connected between the gate and the second drive circuit. By doing so, the apparent capacitance of the gate can also be increased on the second electrode (common electrode) side, and the switching of the transistors can be delayed. Further, the circuit configuration can be made substantially the same as that of the first electrode (scan electrode) side, and the circuit design can be facilitated.

 また、第1制御回路を複数備えるとともに、第1時定数回路も第1制御回路に対応して複数備えてもよい。このようにすることにより、1つのスクリーンを複数に分割して、それぞれ個別に散乱状態と透過状態とを変化させたり、複数のスクリーンを積層して、それぞれ個別に散乱状態と透過状態とを変化させたりすることが可能となる。また、そのような場合においても放射ノイズを低減させることができる。 Further, a plurality of first control circuits may be provided, and a plurality of first time constant circuits may be provided corresponding to the first control circuit. By doing this, one screen is divided into a plurality of parts, and the scattering state and the transmission state are individually changed, or a plurality of screens are laminated, and the scattering state and the transmission state are individually changed. It is possible to make it. Also in such a case, radiation noise can be reduced.

 また、複数の第1時定数回路は共通の配線により第2電極と接続されていてもよい。このようにすることにより、第2電極と接続する配線を少なくして、回路を簡略化することができる。 The plurality of first time constant circuits may be connected to the second electrode by a common wiring. By doing in this way, the circuit connected to the second electrode can be reduced and the circuit can be simplified.

 本発明の第1の実施例にかかる駆動装置を備える表示装置100を図1乃至図7を参照して説明する。表示装置100は図1に示すように、スクリーン1と、コモン駆動回路2と、スキャン駆動回路3と、駆動制御回路4と、投影機5と、を備えている。 A display device 100 including a driving device according to a first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the display device 100 includes a screen 1, a common drive circuit 2, a scan drive circuit 3, a drive control circuit 4, and a projector 5.

 スクリーン1は、電圧の印加により光学状態を変化できるものであって、コモン反転駆動により駆動ができるものであればよい。スクリーン1の光学状態は、散乱状態が映像状態であり、それよりも入射光の散乱が小さく且つ平行光線透過率が高い透明な透過状態が非映像状態である。即ち、光に対し透過状態と散乱状態とを切り替え可能となっている。 The screen 1 may be any screen that can change the optical state by voltage application and can be driven by common inversion driving. As for the optical state of the screen 1, the scattering state is an image state, and the transparent transmission state in which the scattering of incident light is smaller and the parallel light transmittance is higher than that is the non-image state. That is, it is possible to switch between a transmission state and a scattering state with respect to light.

 スクリーン1は、例えば、液晶材料を用い、散乱状態と入射光の散乱が小さい透明な透過状態を変化させる調光スクリーンなどでよい。調光スクリーンには、例えば、高分子分散液晶などの液晶素子を用いたものなどがある。 The screen 1 may be, for example, a light control screen that uses a liquid crystal material and changes a scattering state and a transparent transmission state in which scattering of incident light is small. Examples of the light control screen include a screen using a liquid crystal element such as a polymer dispersed liquid crystal.

 図2に、光学状態を制御可能なスクリーン1の模式的な断面図を示す。図2に示したスクリーン1は、一対の透明なガラス板11、12の間に液晶を含む複合材料等を挟み込んだ光学層15を有する。一方のガラス板11の光学層15側には、全面にコモン電極13が形成される。他方のガラス板12の光学層15側には、全面にスキャン電極14が形成される。なお、電極13、14と光学層15との間に、絶縁体からなる中間層を形成してもよい。 FIG. 2 shows a schematic cross-sectional view of the screen 1 capable of controlling the optical state. The screen 1 shown in FIG. 2 has an optical layer 15 in which a composite material containing liquid crystal is sandwiched between a pair of transparent glass plates 11 and 12. A common electrode 13 is formed on the entire surface of one glass plate 11 on the optical layer 15 side. A scan electrode 14 is formed on the entire surface of the other glass plate 12 on the optical layer 15 side. An intermediate layer made of an insulator may be formed between the electrodes 13 and 14 and the optical layer 15.

 また、コモン電極13およびスキャン電極14は、たとえばITO(酸化インジウム・スズ)により、透明電極として形成される。光学層15は、コモン電極13とスキャン電極14との間に配置される。 Further, the common electrode 13 and the scan electrode 14 are formed as transparent electrodes by using, for example, ITO (indium tin oxide). The optical layer 15 is disposed between the common electrode 13 and the scan electrode 14.

 スクリーン1は、第1電極としてのスキャン電極14と第2電極としてのコモン電極13との間に電位差を生じるように電圧が印加される。光学層15内の光学状態は、コモン電極13とスキャン電極14の印加電圧により変化する。 A voltage is applied to the screen 1 so that a potential difference is generated between the scan electrode 14 as the first electrode and the common electrode 13 as the second electrode. The optical state in the optical layer 15 changes depending on the voltage applied to the common electrode 13 and the scan electrode 14.

 スクリーン1は、電位差を生じるように電圧が印加された際の状態によりリバースモードとノーマルモードに分類される。リバースモードで動作するスクリーン1は、電圧を印加していない通常状態において、スクリーン1が透明な透過状態となる。電圧を印加すると、印加電圧に応じた平行光線の散乱率の散乱状態となる。ノーマルモードで動作するスクリーンでは、電圧を印加していない通常状態において、スクリーン1が散乱状態となる。電圧を印加すると、印加電圧に応じた平行光線透過率の透明な透過状態となる。そして、スクリーン1の光学状態は、所定の散乱状態が映像状態に対応し、それよりも平行光線透過率が高い透明な透過状態が非映像状態に対応する。なお、以下の説明では、リバースモードで説明する。 The screen 1 is classified into a reverse mode and a normal mode according to a state when a voltage is applied so as to generate a potential difference. The screen 1 operating in the reverse mode is in a transparent transmissive state in a normal state where no voltage is applied. When a voltage is applied, it becomes a scattering state with a scattering rate of parallel rays according to the applied voltage. In the screen operating in the normal mode, the screen 1 is in a scattering state in a normal state where no voltage is applied. When a voltage is applied, a transparent transmission state with parallel light transmittance corresponding to the applied voltage is obtained. As for the optical state of the screen 1, a predetermined scattering state corresponds to an image state, and a transparent transmission state having a higher parallel light transmittance corresponds to a non-image state. In the following description, the reverse mode will be described.

 コモン駆動回路2は、駆動制御回路4の制御に基づいてコモン電極13に対して所定の電圧を印加する。詳細は後述する。 The common drive circuit 2 applies a predetermined voltage to the common electrode 13 based on the control of the drive control circuit 4. Details will be described later.

 スキャン駆動回路3は、駆動制御回路4の制御に基づいてスキャン電極14に対して所定の電圧を印加する。詳細は後述する。 The scan drive circuit 3 applies a predetermined voltage to the scan electrode 14 based on the control of the drive control circuit 4. Details will be described later.

 駆動制御回路4は、投影機5の投影タイミングに合わせてスクリーン1を散乱状態に切り替えるようにコモン駆動回路2とスキャン駆動回路3とを制御する。駆動制御回路4は、投影機5から例えば無線信号等により垂直同期信号等の画像周期信号を取得してスクリーン1と投影機5との同期制御を行う。 The drive control circuit 4 controls the common drive circuit 2 and the scan drive circuit 3 so that the screen 1 is switched to the scattering state in accordance with the projection timing of the projector 5. The drive control circuit 4 acquires an image periodic signal such as a vertical synchronization signal from the projector 5 by, for example, a wireless signal, and performs synchronization control between the screen 1 and the projector 5.

 投影機5は、スクリーン1が散乱状態の際に映像光を投射する。投影機5は、走査周期中にスクリーン1上で黒状態(投射光が出ない状態)を順次シフトさせる透過型あるいは反射型液晶ライトバルブなどを使用できるが、これ以外の素子を用いてもよい。また、投影機5は、映像の走査周期においてラスター走査し、スクリーン1の表示面に映像光(画像光)を点順次で投射するものでもよい。つまり、映像光が所定の周期で間欠的に投射される。あるいは、強度変調された光ビームの照射方向を可動ミラーで反射して振るような、例えばレーザプロジェクタなどを用いることができる。 Projector 5 projects image light when screen 1 is in a scattering state. The projector 5 can use a transmissive or reflective liquid crystal light valve that sequentially shifts the black state (state in which no projection light is emitted) on the screen 1 during the scanning period, but other elements may be used. . Further, the projector 5 may perform raster scanning in a video scanning cycle and project video light (image light) on the display surface of the screen 1 in a dot sequential manner. That is, video light is projected intermittently at a predetermined cycle. Alternatively, for example, a laser projector that reflects and shakes the irradiation direction of the intensity-modulated light beam with a movable mirror can be used.

 投影機5は、スクリーン1へ映像情報(画像情報)により変調された映像光を投射できるものであればよい。なお、映像情報は、投影機5に入力される映像信号から得られる。映像信号には、たとえば、NTSC(National Television Standards Committee)方式、PAL(Phase Alternation by Line)方式のようなアナログ方式の映像信号、MPEG-TS(Moving Picture Experts Group - Transport Stream)フォーマット、HDV(High-Definition Video)フォーマットのようなデジタルフォーマットの映像信号がある。投影機5には、動画の映像信号だけでなく、たとえばJPEG(Joint Photographic Experts Group)のような静止画の映像信号が入力されてもよい。この場合、投影機5は、静止画を表示するための同じ映像光で、スクリーン1を繰り返し走査すればよい。 The projector 5 only needs to be able to project video light modulated by video information (image information) onto the screen 1. Note that the video information is obtained from a video signal input to the projector 5. Video signals include, for example, NTSC (National Television Standards Committee), analog video signals such as PAL (Phase Alternation by Line), MPEG-TS (Moving Picture Experts Group-Transport Stream) format, HDV (High -There are video signals in digital format such as Definition (Video) format. The projector 5 may receive not only a moving image video signal but also a still image video signal such as JPEG (Joint Photographic Experts Group). In this case, the projector 5 may scan the screen 1 repeatedly with the same video light for displaying a still image.

 図3に本実施例に係るコモン駆動回路2とスキャン駆動回路3との回路例を示す。コモン駆動回路2とスキャン駆動回路3とで本実施例に係る駆動装置10を構成する。コモン駆動回路2は、FET21、22と、抵抗23、24と、コンデンサ25、26と、ゲートドライバ27と、を備えている。 FIG. 3 shows a circuit example of the common drive circuit 2 and the scan drive circuit 3 according to this embodiment. The common drive circuit 2 and the scan drive circuit 3 constitute a drive device 10 according to this embodiment. The common drive circuit 2 includes FETs 21 and 22, resistors 23 and 24, capacitors 25 and 26, and a gate driver 27.

 FET21は、PチャネルFET(Field Effect Transistor)であり、ソースが電源Vbに接続され、ドレインがFET22のドレインとコンデンサ26の一方側とコンデンサ25の他方側と液晶素子(スクリーン1)のコモン電極13及びスキャン駆動回路3のコンデンサ36の一方側とコンデンサ35の他方側に接続され、ゲートが抵抗23の一方側及びコンデンサ25の一方側に接続されている。 The FET 21 is a P-channel FET (Field-Effect-Transistor), the source is connected to the power supply Vb, the drain is the drain of the FET 22, one side of the capacitor 26, the other side of the capacitor 25, and the common electrode 13 of the liquid crystal element (screen 1). The scan drive circuit 3 is connected to one side of the capacitor 36 and the other side of the capacitor 35, and the gate is connected to one side of the resistor 23 and one side of the capacitor 25.

 FET22は、NチャネルFETであり、ソースが接地され、ドレインがFET21のドレインとコンデンサ26の一方側とコンデンサ25の他方側と液晶素子のコモン電極13及びスキャン駆動回路3のコンデンサ36の一方側とコンデンサ35の他方側に接続され、ゲートが抵抗24の一方側及びコンデンサ26の他方側に接続されている。 The FET 22 is an N-channel FET, the source is grounded, and the drain is the drain of the FET 21, one side of the capacitor 26, the other side of the capacitor 25, the common electrode 13 of the liquid crystal element, and one side of the capacitor 36 of the scan drive circuit 3. The other side of the capacitor 35 is connected, and the gate is connected to one side of the resistor 24 and the other side of the capacitor 26.

 抵抗23は、一方側がFET21のゲート及びコンデンサ25の一方側に接続され、他方側がゲートドライバ27に接続されている。 The resistor 23 has one side connected to the gate of the FET 21 and one side of the capacitor 25, and the other side connected to the gate driver 27.

 抵抗24は、一方側がFET22のゲート及びコンデンサ26の他方側に接続され、他方側がゲートドライバ27に接続されている。 The resistor 24 has one side connected to the gate of the FET 22 and the other side of the capacitor 26, and the other side connected to the gate driver 27.

 コンデンサ25は、一方側がFET21のゲート及び抵抗23の一方側に接続され、他方側がコンデンサ26の一方側とFET21のドレインとFET22のドレイン及びスキャン駆動回路3のコンデンサ36の一方側とコンデンサ35の他方側に接続されている。 The capacitor 25 has one side connected to the gate of the FET 21 and one side of the resistor 23, and the other side connected to one side of the capacitor 26, the drain of the FET 21, the drain of the FET 22, one side of the capacitor 36 of the scan drive circuit 3, and the other side of the capacitor 35. Connected to the side.

 コンデンサ26は、一方側がコンデンサ25の他方側とFET21のドレインとFET22のドレイン及びスキャン駆動回路3のコンデンサ36の一方側とコンデンサ35の他方側に接続され、他方側がFET22のゲート及び抵抗23の一方側に接続されている。 The capacitor 26 has one side connected to the other side of the capacitor 25, the drain of the FET 21, the drain of the FET 22, one side of the capacitor 36 of the scan drive circuit 3, and the other side of the capacitor 35, and the other side to one of the gate of the FET 22 and one of the resistors 23. Connected to the side.

 ゲートドライバ27は、駆動制御回路4の制御によりコモン電極13に対する駆動信号を出力するドライバ回路である。 The gate driver 27 is a driver circuit that outputs a drive signal for the common electrode 13 under the control of the drive control circuit 4.

 上記の説明から明らかなように、FET21とFET22とは2つのトランジスタで構成されるプッシュプル回路であり、第2制御回路として機能する。また、ゲートドライバ27が、第2制御回路を駆動する第2ドライブ回路として機能し、抵抗23とコンデンサ25から構成される時定数回路と、抵抗24とコンデンサ26から構成される時定数回路と、が第2時定数回路として機能する。 As apparent from the above description, the FET 21 and the FET 22 are push-pull circuits composed of two transistors and function as a second control circuit. The gate driver 27 functions as a second drive circuit that drives the second control circuit, and includes a time constant circuit including a resistor 23 and a capacitor 25, a time constant circuit including a resistor 24 and a capacitor 26, Functions as a second time constant circuit.

 スキャン駆動回路3は、FET31、32と、抵抗33、34と、コンデンサ35、36と、ゲートドライバ37と、を備えている。 The scan drive circuit 3 includes FETs 31 and 32, resistors 33 and 34, capacitors 35 and 36, and a gate driver 37.

 FET31は、PチャネルFETであり、ソースが電源Vbに接続され、ドレインがFET32のドレインと液晶素子のスキャン電極14に接続され、ゲートが抵抗33の一方側及びコンデンサ35の一方側に接続されている。 The FET 31 is a P-channel FET, the source is connected to the power supply Vb, the drain is connected to the drain of the FET 32 and the scan electrode 14 of the liquid crystal element, and the gate is connected to one side of the resistor 33 and one side of the capacitor 35. Yes.

 FET32は、NチャネルFETであり、ソースが接地され、ドレインがFET31のドレインと液晶素子のスキャン電極14に接続され、ゲートが抵抗34の一方側及びコンデンサ36の他方側に接続されている。 The FET 32 is an N-channel FET, the source is grounded, the drain is connected to the drain of the FET 31 and the scan electrode 14 of the liquid crystal element, and the gate is connected to one side of the resistor 34 and the other side of the capacitor 36.

 抵抗33は、一方側がFET31のゲート及びコンデンサ35の一方側に接続され、他方側がゲートドライバ37に接続されている。 The resistor 33 has one side connected to the gate of the FET 31 and one side of the capacitor 35, and the other side connected to the gate driver 37.

 抵抗34は、一方側がFET32のゲート及びコンデンサ36の他方側に接続され、他方側がゲートドライバ37に接続されている。 The resistor 34 has one side connected to the gate of the FET 32 and the other side of the capacitor 36, and the other side connected to the gate driver 37.

 コンデンサ35は、一方側がFET31のゲート及び抵抗33の一方側に接続され、他方側がコンデンサ36の一方側とコモン電極13に接続されている。つまり、コンデンサ35は、コモン駆動回路2のFET21のドレイン、FET22のドレイン、コンデンサ25の他方側、コンデンサ26の一方側とも接続されている。 The capacitor 35 has one side connected to the gate of the FET 31 and one side of the resistor 33, and the other side connected to one side of the capacitor 36 and the common electrode 13. That is, the capacitor 35 is also connected to the drain of the FET 21 of the common drive circuit 2, the drain of the FET 22, the other side of the capacitor 25, and one side of the capacitor 26.

 コンデンサ36は、一方側がコンデンサ35の他方側とコモン電極13に接続され、他方側がFET32のゲート及び抵抗34の一方側に接続されている。つまり、コンデンサ36は、コモン駆動回路2のFET21のドレイン、FET22のドレイン、コンデンサ25の他方側、コンデンサ26の一方側とも接続されている。 The capacitor 36 has one side connected to the other side of the capacitor 35 and the common electrode 13, and the other side connected to the gate of the FET 32 and one side of the resistor 34. That is, the capacitor 36 is also connected to the drain of the FET 21, the drain of the FET 22, the other side of the capacitor 25, and one side of the capacitor 26 of the common drive circuit 2.

 ゲートドライバ37は、駆動制御回路4の制御によりスキャン電極14に対する駆動信号を出力するドライバ回路である。 The gate driver 37 is a driver circuit that outputs a drive signal for the scan electrode 14 under the control of the drive control circuit 4.

 上記の説明から明らかなように、FET31とFET32とは2つのトランジスタで構成されるプッシュプル回路であり、第1制御回路として機能する。また、ゲートドライバ37が、第1制御回路を駆動する第1ドライブ回路として機能し、抵抗33とコンデンサ35から構成される時定数回路と、抵抗34とコンデンサ36から構成される時定数回路と、が第1時定数回路として機能する。また、第1時定数回路とコモン電極13とが配線により直接接続されている。 As is clear from the above description, the FET 31 and the FET 32 are push-pull circuits composed of two transistors and function as a first control circuit. The gate driver 37 functions as a first drive circuit that drives the first control circuit, and includes a time constant circuit including a resistor 33 and a capacitor 35, a time constant circuit including a resistor 34 and a capacitor 36, Functions as a first time constant circuit. Further, the first time constant circuit and the common electrode 13 are directly connected by wiring.

 図3に示したコモン駆動回路2とスキャン駆動回路3との動作を図4乃至図6を参照して説明する。図4は、図3に示したコモン電極13とスキャン電極14との駆動波形を示すタイミングチャートである。 The operation of the common drive circuit 2 and the scan drive circuit 3 shown in FIG. 3 will be described with reference to FIGS. FIG. 4 is a timing chart showing drive waveforms of the common electrode 13 and the scan electrode 14 shown in FIG.

 コモン電極13は、図4に示したようにコモン反転駆動により、例えば1フレーム毎等の一定周期毎に例えばVbボルトと0ボルトとに変化する。スキャン電極14は、散乱状態にするタイミングでコモン電極13と電位差が生じるようにパルス状の電圧を印加する。 As shown in FIG. 4, the common electrode 13 is changed to, for example, Vb volt and 0 volt at a constant period, for example, every frame by the common inversion driving. The scan electrode 14 applies a pulsed voltage so that a potential difference from the common electrode 13 is generated at the timing of the scattering state.

 ここで、図4のA部分とB部分についてコモン駆動回路2とスキャン駆動回路3との動作を説明する。図4のA部分におけるコモン駆動回路2とスキャン駆動回路3の内部動作のタイミングチャートを図5(a)に示し、図4のB部分におけるコモン駆動回路2とスキャン駆動回路3の内部動作のタイミングチャートを図5(b)に示す。 Here, the operations of the common drive circuit 2 and the scan drive circuit 3 will be described with respect to the portions A and B in FIG. FIG. 5A shows a timing chart of the internal operations of the common drive circuit 2 and the scan drive circuit 3 in the portion A of FIG. 4, and the timings of the internal operations of the common drive circuit 2 and the scan drive circuit 3 in the portion B of FIG. The chart is shown in FIG.

 まず、図4のA部分の動作について図5(a)を参照して説明する。まず、コモン駆動回路2側から説明する。コモン駆動回路2では、FET22をオンすべく、ゲートドライバ27が出力するコモンLoゲート信号(FET22のゲート制御信号)がHiレベルになる。すると、FET22のゲート容量をチャージする抵抗24、FET22のゲート、ソースの方向に電流が流れる。しかし、FET22のゲート電圧が閾値電圧を越えると徐々にFET22のドレイン電圧=コモン電極13の電位が徐々に下がり始め、コンデンサ26をチャージする電流が増える。すなわちコンデンサ26の見かけ上の容量が大きくなりゲート容量のチャージ電流が減りFET22のオンが遅くなる(FET22VGS、VGSはゲートソース間電圧)。よってコモン電極13の電圧変化が遅くなる(dV/dtが低くなる)。即ち、コモン駆動回路2は、コモン電圧変化時の出力インピーダンスが変化前後よりも大きくなる。 First, the operation of part A in FIG. 4 will be described with reference to FIG. First, the common drive circuit 2 side will be described. In the common drive circuit 2, the common Lo gate signal (the gate control signal of the FET 22) output from the gate driver 27 is set to the Hi level in order to turn on the FET 22. Then, a current flows in the direction of the resistor 24 that charges the gate capacitance of the FET 22 and the gate and source of the FET 22. However, when the gate voltage of the FET 22 exceeds the threshold voltage, the drain voltage of the FET 22 = the potential of the common electrode 13 starts to gradually decrease, and the current for charging the capacitor 26 increases. That is, the apparent capacity of the capacitor 26 increases, the charge current of the gate capacity decreases, and the FET 22 is turned on later (FETs 22VGS and VGS are gate-source voltages). Therefore, the voltage change of the common electrode 13 becomes slow (dV / dt becomes low). That is, in the common drive circuit 2, the output impedance when the common voltage changes is larger than before and after the change.

 次に、スキャン駆動回路3側を説明する。スキャン駆動回路3では、ゲートドライバ27が出力するコモンLoゲート信号がHiレベルになると同時にゲートドライバ37が出力するスキャンLoゲート信号もHiレベルになる。このとき、FET32のゲート容量に流れる電流(図6(1)を参照)が流れFET32をオンしようとするが、スキャンLoゲート信号がHiレベルになると同時にコモン電極13が立下がるため、コンデンサ36を通してコモン電極13に流れる電流(図6(2)を参照)が増大する。つまり、コンデンサ36の見かけ上の容量が大きくなるということであり、これによってFET32のゲート容量に流れる電流が減りFET32のオンが遅くなる(FET32VGS)。よってスキャン電極14の電圧変化も遅くなる。したがって、図4や図5に示したように、コモン電極13、スキャン電極14ともに電圧の変化が緩やかになる(dV/dtが低くなる)。 Next, the scan drive circuit 3 side will be described. In the scan drive circuit 3, the common Lo gate signal output from the gate driver 27 becomes Hi level, and at the same time, the scan Lo gate signal output from the gate driver 37 also becomes Hi level. At this time, a current (see FIG. 6A) flowing through the gate capacitance of the FET 32 flows and tries to turn on the FET 32. However, since the common electrode 13 falls at the same time as the scan Lo gate signal becomes Hi level, the current passes through the capacitor 36. The current flowing through the common electrode 13 (see FIG. 6 (2)) increases. In other words, the apparent capacitance of the capacitor 36 is increased, thereby reducing the current flowing through the gate capacitance of the FET 32 and turning on the FET 32 (FET 32VGS). Therefore, the voltage change of the scan electrode 14 is also delayed. Therefore, as shown in FIG. 4 and FIG. 5, the voltage change becomes gentle (dV / dt becomes low) in both the common electrode 13 and the scan electrode 14.

 次に、図4のB部分の動作について図5(b)を参照して説明する。図4のB部分においてはコモン電極13の電圧は一定である。そのため、コンデンサ36を通してコモン電極13に流れる電流の増大がないためFET32のゲート容量チャージが高速で行われ、スキャン電極14の電圧変化は速い。つまり、スキャン電極14の電圧の変化が急峻になる。 Next, the operation of portion B in FIG. 4 will be described with reference to FIG. In part B of FIG. 4, the voltage of the common electrode 13 is constant. Therefore, since there is no increase in the current flowing through the capacitor 36 to the common electrode 13, the gate capacitance of the FET 32 is charged at a high speed, and the voltage change of the scan electrode 14 is fast. That is, the change in the voltage of the scan electrode 14 becomes steep.

 なお、図4乃至図6では、立下り変化時について説明したが、立上がり変化時においても、コモン駆動回路2側がFET21、コンデンサ25、抵抗23が動作し、スキャン駆動回路3側がFET31、コンデンサ35、抵抗33が動作するのであって、基本的な作用は上記説明と同様である。つまり、コモン電極13の電圧が変化する場合は、コモン電極13、スキャン電極14ともに緩やかに変化し、スキャン電極14のみ変化する場合は急峻に変化する。 4 to 6, the falling change has been described. Even at the rising change, the FET 21, capacitor 25, and resistor 23 operate on the common drive circuit 2 side, and the FET 31, capacitor 35, and the scan drive circuit 3 side operate. The resistor 33 operates, and the basic action is the same as described above. That is, when the voltage of the common electrode 13 changes, both the common electrode 13 and the scan electrode 14 change gently, and when only the scan electrode 14 changes, it changes sharply.

 図7に図3に示した回路と従来の回路とによるシミュレーション結果を示す。図7の対策なしは従来のコンデンサや抵抗による時定数回路が無い回路のシミュレーション結果、対策有りは図3に示した回路のシミュレーション結果である。また、図7の容量結合ノイズはコモン電圧、スキャン電圧の変化に対応したノイズの波形、容量結合ノイズ(FFT)はコモン電極13の波形1周期期間における容量結合ノイズの波形をFFT(Fast Fourier Transform)により周波数解析した結果である。 Fig. 7 shows the simulation results of the circuit shown in Fig. 3 and the conventional circuit. 7 is a simulation result of a circuit without a time constant circuit using a conventional capacitor or resistor, and a countermeasure is a simulation result of the circuit shown in FIG. Further, the capacitive coupling noise in FIG. 7 is a waveform of noise corresponding to a change in the common voltage and the scan voltage, and the capacitive coupling noise (FFT) is a waveform of capacitive coupling noise in the period of one cycle of the waveform of the common electrode 13 (Fast Fourier Transform). ) And frequency analysis results.

 図7によれば、対策なしの場合は、コモン電極13とスキャン電極14とが同時に変化するタイミングで大きなレベルの容量結合ノイズが発生しているが、対策有りの場合は、コモン電極13とスキャン電極14とが同時に変化するタイミングで容量結合ノイズが抑えられていることが明らかとなった。 According to FIG. 7, when no countermeasure is taken, a large level of capacitive coupling noise is generated at the timing when the common electrode 13 and the scan electrode 14 change simultaneously, but when the countermeasure is taken, the common electrode 13 and the scan are scanned. It became clear that capacitive coupling noise was suppressed at the timing when the electrode 14 changed simultaneously.

 本実施例によれば、スクリーン1のスキャン電極14に印加する電圧を制御するスキャン駆動回路3と、スクリーン1のコモン電極13に印加する電圧を周期的に変化させるとともに、変化時の出力インピーダンスが変化前後よりも大きくなるコモン駆動回路2と、を備えている。そして、スキャン駆動回路3は、2つのFETのドレイン同士が接続されたプッシュプル回路を備え、更にプッシュプル回路を駆動するゲートドライバ37とプッシュプル回路とゲートドライバ37との間に接続されるコンデンサ35と抵抗33からなる時定数回路と、コンデンサ36と抵抗34からなる時定数回路と、を備えている。そして、コンデンサ35と抵抗33からなる時定数回路と、コンデンサ36と抵抗34からなる時定数回路と、は、コモン電極13と配線により直接接続されている。このようにすることにより、コモン反転駆動により、コモン電極13がコモン駆動回路2により緩やかに変化する際には、コモン電極13の変化の影響を受けて時定数回路によりスキャン電極14が緩やかに変化する。また、散乱状態に変化させるタイミングでは、コモン電極13は変化しないので、時定数回路が作用せず、スキャン電極14を急峻に変化させることができる。よって、コモン反転駆動時に放射ノイズを低減するとともに、映像表示に影響を及ぼさないようにすることができる。 According to the present embodiment, the scan drive circuit 3 that controls the voltage applied to the scan electrode 14 of the screen 1 and the voltage applied to the common electrode 13 of the screen 1 are periodically changed, and the output impedance at the time of change is And a common drive circuit 2 that is larger than before and after the change. The scan drive circuit 3 includes a push-pull circuit in which the drains of two FETs are connected to each other, and further includes a gate driver 37 that drives the push-pull circuit, and a capacitor that is connected between the push-pull circuit and the gate driver 37. And a time constant circuit composed of a capacitor 36 and a resistor 34. The time constant circuit composed of the capacitor 35 and the resistor 33 and the time constant circuit composed of the capacitor 36 and the resistor 34 are directly connected to the common electrode 13 by wiring. In this way, when the common electrode 13 is gradually changed by the common drive circuit 2 due to the common inversion drive, the scan electrode 14 is gradually changed by the time constant circuit under the influence of the change of the common electrode 13. To do. In addition, since the common electrode 13 does not change at the timing of changing to the scattering state, the time constant circuit does not act and the scan electrode 14 can be changed sharply. Therefore, it is possible to reduce the radiation noise during the common inversion driving and not to affect the video display.

 また、コンデンサ35と抵抗33からなる時定数回路と、コンデンサ36と抵抗34からなる時定数回路と、がコモン電極13と直接接続されているので、コモン反転時にコモン側の電圧変化時間(dV/dt)とスキャン側の電圧変化時間(dV/dt)を同等にすることができる。したがって、コモン反転時に、2つの電極間に電位差が生じて誤って液晶が散乱状態になることを防止することができる。 Since the time constant circuit composed of the capacitor 35 and the resistor 33 and the time constant circuit composed of the capacitor 36 and the resistor 34 are directly connected to the common electrode 13, the voltage change time (dV / dt) and the voltage change time (dV / dt) on the scan side can be made equal. Therefore, it is possible to prevent the liquid crystal from being erroneously scattered due to a potential difference between the two electrodes during common inversion.

 また、時定数回路は、FETのゲートとコモン電極との間に接続されたコンデンサ35、36及びコンデンサ35とゲートドライバ37との間に接続された抵抗33とコンデンサ36とゲートドライバ37との間に接続された抵抗34とで構成されている。このようにすることにより、コモン反転駆動時には、コモン電極13が変化することにより、プッシュプル回路を構成するFETのゲートの入力容量が見かけ上大きくなり、FETの切り替えを遅くすることができる。また、コモン電極13が変化しない場合は、FETのゲートの入力容量が見かけ上大きくならないので、急峻な変化をさせることができる。 The time constant circuit includes capacitors 35 and 36 connected between the gate of the FET and the common electrode, and a resistor 33 connected between the capacitor 35 and the gate driver 37, and between the capacitor 36 and the gate driver 37. And a resistor 34 connected to the. By doing so, when the common inversion drive is performed, the common electrode 13 is changed, so that the input capacitance of the gate of the FET constituting the push-pull circuit is apparently increased, and switching of the FET can be delayed. Further, when the common electrode 13 does not change, the input capacitance of the gate of the FET does not increase apparently, so that a steep change can be made.

 また、コモン駆動回路2は、2つのFETのドレイン同士が接続されたプッシュプル回路を含み、ゲートドライバ27と、プッシュプル回路とゲートドライバ27との間に接続されるコンデンサ25と抵抗23からなる時定数回路と、コンデンサ26と抵抗24からなる時定数回路と、を備えている。そして、時定数回路は、FETのゲートとドレイン間に接続されたコンデンサ25、26及びコンデンサ25とゲートドライバ27との間に接続された抵抗23とコンデンサ26とゲートドライバ27との間に接続された抵抗24とで構成されている。このようにすることにより、第2時定数回路によりコモン電極13を緩やかに変化させることができ、さらに、コモン電極13側もスキャン電極14側と略同じ回路構成とすることができ、回路設計を容易にすることができる。 The common drive circuit 2 includes a push-pull circuit in which the drains of two FETs are connected to each other, and includes a gate driver 27, a capacitor 25 connected between the push-pull circuit and the gate driver 27, and a resistor 23. And a time constant circuit including a capacitor 26 and a resistor 24. The time constant circuit is connected between the capacitors 25 and 26 connected between the gate and drain of the FET, the resistor 23 connected between the capacitor 25 and the gate driver 27, and the capacitor 26 and the gate driver 27. And a resistor 24. In this way, the common electrode 13 can be gradually changed by the second time constant circuit, and the common electrode 13 side can have substantially the same circuit configuration as the scan electrode 14 side. Can be easily.

 本発明の第2の実施例にかかる表示装置を図8乃至図13を参照して説明する。なお、前述した第1の実施例と同一部分には、同一符号を付して説明を省略する。 A display device according to a second embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.

 本実施例は、図8及び図9に示したように、スクリーンが複数の領域に分割されたスクリーン1Aとなっている点が異なる。したがって、スキャン駆動回路3Aは、第1スキャン駆動回路301~第nスキャン駆動回路30n(nは分割数)のn個を有しており、コモン駆動回路2とスキャン駆動回路3Aとで本実施例にかかる駆動装置10Aを構成する。 This embodiment is different in that the screen is a screen 1A divided into a plurality of areas as shown in FIGS. Accordingly, the scan drive circuit 3A has n of the first scan drive circuit 301 to the nth scan drive circuit 30n (n is the number of divisions), and the common drive circuit 2 and the scan drive circuit 3A are used in this embodiment. 10A of drive devices concerning this are comprised.

 スクリーン1Aは、図9に示したように、コモン電極13は第1の実施例と同様に全面に形成されているが、スキャン電極14が複数に分割されており、各分割されたスキャン電極に第1スキャン駆動回路301~第nスキャン駆動回路30nが接続されている。 As shown in FIG. 9, in the screen 1A, the common electrode 13 is formed on the entire surface as in the first embodiment. However, the scan electrode 14 is divided into a plurality of parts, and each of the divided scan electrodes is provided on the screen 1A. The first scan drive circuit 301 to the nth scan drive circuit 30n are connected.

 図10に本実施例にかかるコモン駆動回路2とスキャン駆動回路3Aの回路図を示す。図10は、スクリーン1Aが4分割の場合の例である。 FIG. 10 shows a circuit diagram of the common drive circuit 2 and the scan drive circuit 3A according to the present embodiment. FIG. 10 shows an example in which the screen 1A is divided into four parts.

 第1スキャン駆動回路301は、FET31a、32aと、抵抗33a、34aと、コンデンサ35a、36aと、ゲートドライバ37aと、を備えている。第2スキャン駆動回路302は、FET31b、32bと、抵抗33b、34bと、コンデンサ35b、36bと、ゲートドライバ37bと、を備えている。第3スキャン駆動回路303は、FET31c、32cと、抵抗33c、34cと、コンデンサ35c、36cと、ゲートドライバ37cと、を備えている。第4スキャン駆動回路304は、FET31d、32dと、抵抗33d、34dと、コンデンサ35d、36dと、ゲートドライバ37dと、を備えている。これらのスキャン駆動回路の回路構成は第1の実施例と同じである。即ち、第1制御回路を複数備えるとともに、第1時定数回路も第1制御回路に対応して複数備えている。 The first scan drive circuit 301 includes FETs 31a and 32a, resistors 33a and 34a, capacitors 35a and 36a, and a gate driver 37a. The second scan drive circuit 302 includes FETs 31b and 32b, resistors 33b and 34b, capacitors 35b and 36b, and a gate driver 37b. The third scan drive circuit 303 includes FETs 31c and 32c, resistors 33c and 34c, capacitors 35c and 36c, and a gate driver 37c. The fourth scan drive circuit 304 includes FETs 31d and 32d, resistors 33d and 34d, capacitors 35d and 36d, and a gate driver 37d. The circuit configuration of these scan drive circuits is the same as that of the first embodiment. That is, a plurality of first control circuits are provided, and a plurality of first time constant circuits are provided corresponding to the first control circuits.

 図10に示したように、各スキャン駆動回路のFETのドレインは対応する領域のスキャン電極に接続されている。また、コンデンサ35aの他端側とコンデンサ36aの一端側は、コモン電極13と接続されている。コンデンサ35bの他端側とコンデンサ36bの一端側、コンデンサ35bの他端側とコンデンサ36bの一端側、コンデンサ35bの他端側とコンデンサ36bの一端側も同様にコモン電極13と接続されている。このコモン電極13と各スキャン駆動回路とを接続する配線は共通の配線となっている。 As shown in FIG. 10, the drain of the FET of each scan drive circuit is connected to the scan electrode in the corresponding region. Further, the other end side of the capacitor 35 a and one end side of the capacitor 36 a are connected to the common electrode 13. The other end side of the capacitor 35b and one end side of the capacitor 36b, the other end side of the capacitor 35b and one end side of the capacitor 36b, the other end side of the capacitor 35b, and one end side of the capacitor 36b are also connected to the common electrode 13 in the same manner. The wiring that connects the common electrode 13 and each scan drive circuit is a common wiring.

 図11に本実施例にかかるコモン駆動回路2及びスキャン駆動回路3Aの動作のタイミングチャートを示す。本実施例にようにスクリーン1Aを構成することで、各分割領域毎に散乱状態と透過状態とを切り替えることができる。また、図11に示したように、第1スキャン電極、第2スキャン電極、第3スキャン電極の各電極に印加する電圧波形をずらすことで、スクリーン1Aについての映像光が照射される部位は、映像状態に維持される。これにより、スクリーン1Aを走査する映像光は、散乱状態のスクリーン1Aで散乱される。一方、スクリーン1Aについての映像光が照射されない部位は、非映像状態に制御される。各分割領域は、映像光により走査されていない殆どの期間において、非映像状態の透明な透過状態に制御される。よって、映像光の投影期間中に、映像の視認性を保ちつつ、スクリーン1Aのシースルー特性が得られる。 FIG. 11 shows a timing chart of operations of the common drive circuit 2 and the scan drive circuit 3A according to the present embodiment. By configuring the screen 1A as in the present embodiment, it is possible to switch between the scattering state and the transmission state for each divided region. Further, as shown in FIG. 11, by shifting the voltage waveform applied to each of the first scan electrode, the second scan electrode, and the third scan electrode, the portion irradiated with the image light about the screen 1A is The video state is maintained. Thereby, the image light that scans the screen 1A is scattered by the screen 1A in the scattering state. On the other hand, the portion of the screen 1A that is not irradiated with the image light is controlled to a non-image state. Each divided region is controlled to a transparent transmission state in a non-video state during most periods when scanning with video light is not performed. Therefore, the see-through characteristic of the screen 1A can be obtained while maintaining the visibility of the image during the projection period of the image light.

 なお、図8等では1つのスクリーンが複数の領域に分割される例を説明したが、図12及び図13に示したように、複数のスクリーンを積層したものであってもよい。図12に示したスクリーン1Bは、図13に示したように、3つのスクリーンが積層されている。 In addition, although FIG. 8 etc. demonstrated the example in which one screen is divided | segmented into a some area | region, as shown in FIG.12 and FIG.13, what laminated | stacked the some screen may be sufficient. The screen 1B shown in FIG. 12 has three screens stacked as shown in FIG.

 スクリーン1Bは、コモン電極13aとスキャン電極14aとの間に光学層15aを有する第1スクリーンと、コモン電極13bとスキャン電極14bとの間に光学層15bを有する第2スクリーンと、コモン電極13cとスキャン電極14cとの間に光学層15cを有する第3スクリーンと、が形成されている。そして、第1スクリーンは透明なガラス板12と透明なガラス板16に挟まれ、第2スクリーンはガラス板16と透明なガラス板17に挟まれ、第3スクリーンはガラス板17と透明なガラス板11に挟まれている。つまり、スクリーン1Bは、ガラス板11と12の間に3つのスクリーンが形成され、各スクリーンはガラス板16、17で間隔を空けて配置されている。 The screen 1B includes a first screen having an optical layer 15a between the common electrode 13a and the scan electrode 14a, a second screen having an optical layer 15b between the common electrode 13b and the scan electrode 14b, and a common electrode 13c. A third screen having an optical layer 15c is formed between the scan electrode 14c. The first screen is sandwiched between the transparent glass plate 12 and the transparent glass plate 16, the second screen is sandwiched between the glass plate 16 and the transparent glass plate 17, and the third screen is the glass plate 17 and the transparent glass plate. 11. That is, in the screen 1B, three screens are formed between the glass plates 11 and 12, and the screens are arranged with the glass plates 16 and 17 spaced apart.

 図12におけるスキャン駆動回路3Aは、図8と同様に第1スキャン駆動回路301~第3スキャン駆動回路303(図12の場合はスクリーン1Bが3層のため3つとなる)が各スクリーンのスキャン電極に接続されている。回路構成は図10と同様である(但し、スキャン駆動回路は3つとなる)。 In the scan drive circuit 3A in FIG. 12, the first scan drive circuit 301 to the third scan drive circuit 303 (in the case of FIG. 12, the screen 1B has three layers so that there are three) are the scan electrodes of each screen. It is connected to the. The circuit configuration is the same as in FIG. 10 (however, there are three scan drive circuits).

 図12及び図13に示した構成の場合も、スクリーン毎に散乱状態と透過状態とを切り替えることができる。そして、図11のような駆動波形で動作させることで、映像光が照射される一つのスクリーンについてのみ映像状態に維持され、他のスクリーンは映像光を透過する非映像情報に制御される。よって、散乱状態にするスクリーンを順次切り替えることを繰り返すことで、奥行きを持たせる立体的な表示が可能となる。 12 and 13 can also be switched between a scattering state and a transmission state for each screen. Then, by operating with the driving waveform as shown in FIG. 11, only one screen irradiated with the image light is maintained in the image state, and the other screens are controlled to non-image information that transmits the image light. Therefore, a three-dimensional display with depth can be achieved by repeatedly switching the screens in the scattering state sequentially.

 本実施例によれば、複数のスキャン駆動回路を備えており、各スキャン駆動回路は、プッシュプル回路に対応した時定数回路が設けられている。このようにすることにより、1つのスクリーンを複数に分割して、それぞれ個別に散乱状態と透過状態とを変化させたり、複数のスクリーンを積層して、それぞれ個別に散乱状態と透過状態とを変化させたりすることが可能となる。また、そのような場合においても放射ノイズを低減させることができる。 According to this embodiment, a plurality of scan drive circuits are provided, and each scan drive circuit is provided with a time constant circuit corresponding to a push-pull circuit. By doing this, one screen is divided into a plurality of parts, and the scattering state and the transmission state are individually changed, or a plurality of screens are laminated, and the scattering state and the transmission state are individually changed. It is possible to make it. Also in such a case, radiation noise can be reduced.

 なお、上述した実施例では、リバースモードの液晶スクリーンで説明したが、ノーマルモードであってもよい。ノーマルモードの場合の回路図を図14に示す。図14においては、スキャン駆動回路3のFETのチャネルが変更になっている。つまり、PチャネルFETであったFET31はNチャネルFET31Nに、NチャネルFETであったFET32はPチャネルFET32Nとなる。そして、FET31Nは、ドレインが電源Vbに接続され、ソースがFET32Nのソースに接続される。FET32Nは、ドレインが接地され、ソースがFET31Nのソースに接続される。 In the above-described embodiment, the reverse mode liquid crystal screen has been described. However, the normal mode may be used. A circuit diagram in the normal mode is shown in FIG. In FIG. 14, the channel of the FET of the scan drive circuit 3 is changed. That is, the FET 31 that is a P-channel FET becomes an N-channel FET 31N, and the FET 32 that is an N-channel FET becomes a P-channel FET 32N. The FET 31N has a drain connected to the power supply Vb and a source connected to the source of the FET 32N. The FET 32N has a drain grounded and a source connected to the source of the FET 31N.

 図15に、図14の回路における駆動波形例を示す。ノーマルモードの場合、コモン電極13とスキャン電極14との間に電位差が無いときに散乱状態となるので、散乱状態にするタイミングで図15に示したようなパルス状の波形をスキャン電極14に印加する。 FIG. 15 shows an example of drive waveforms in the circuit of FIG. In the normal mode, since there is a scattering state when there is no potential difference between the common electrode 13 and the scan electrode 14, a pulsed waveform as shown in FIG. To do.

 また、上述した実施例で説明したスクリーンにタッチパネルを設ける場合は、コモン電極13側に設けるのが好ましい。図16は、コモン電極13側にタッチパネル18を設けた例である。コモン電極は、上述したように、常に駆動波形が緩やかに変化するので、放射ノイズが少なく、タッチパネル18がノイズの影響を受けにくい。スキャン電極14は、コモン反転時の駆動波形は緩やかに変化するものの、スクリーンを散乱状態に変化させる際には急峻に変化するので、放射ノイズが発生する場合がある。よって、コモン電極13側に設けるのが好ましい。 Further, when a touch panel is provided on the screen described in the above-described embodiment, it is preferably provided on the common electrode 13 side. FIG. 16 shows an example in which a touch panel 18 is provided on the common electrode 13 side. As described above, since the drive waveform of the common electrode always changes gently, there is little radiation noise, and the touch panel 18 is not easily affected by the noise. Although the drive waveform at the time of the common inversion of the scan electrode 14 changes gently, the scan electrode 14 changes abruptly when the screen is changed to the scattering state, so that radiation noise may occur. Therefore, it is preferably provided on the common electrode 13 side.

 また、上述した実施例では、コンデンサを独立した素子として説明したが、トランジスタの寄生容量を利用してもよい。更には、コモン駆動回路2は、図示したようなコンデンサと抵抗からなる時定数回路ではなく、特許文献2に記載されているような構成であってもよい。要するに、コモン電極13を緩やかに変化させるような構成であればよい。 In the above-described embodiments, the capacitor is described as an independent element, but the parasitic capacitance of the transistor may be used. Furthermore, the common drive circuit 2 may be configured as described in Patent Document 2 instead of the time constant circuit including a capacitor and a resistor as illustrated. In short, any configuration may be used as long as the common electrode 13 is gradually changed.

 また、本発明は上記実施例に限定されるものではない。即ち、当業者は、従来公知の知見に従い、本発明の骨子を逸脱しない範囲で種々変形して実施することができる。かかる変形によってもなお本発明の駆動装置の構成を具備する限り、勿論、本発明の範疇に含まれるものである。 Further, the present invention is not limited to the above embodiment. That is, those skilled in the art can implement various modifications in accordance with conventionally known knowledge without departing from the scope of the present invention. Of course, such modifications are included in the scope of the present invention as long as the configuration of the drive device of the present invention is provided.

  1、1A、1B          スクリーン
  2                      コモン駆動回路
  3、3A                スキャン駆動回路
  10、10A            駆動装置
  13                    コモン電極
  13a、13b、13c  コモン電極
  14                    スキャン電極
  14a、14b、14c  スキャン電極
  21、22       FET
  23、24       抵抗
  25、26       コンデンサ
  27                    ゲートドライバ
  31、32       FET
  31N、32N          FET
  33、34       抵抗
  35、36       コンデンサ
  37                    ゲートドライバ
1, 1A, 1B Screen 2 Common drive circuit 3, 3A Scan drive circuit 10, 10A Drive device 13 Common electrode 13a, 13b, 13c Common electrode 14 Scan electrode 14a, 14b, 14c Scan electrode 21, 22 FET
23, 24 Resistor 25, 26 Capacitor 27 Gate driver 31, 32 FET
31N, 32N FET
33, 34 Resistor 35, 36 Capacitor 37 Gate driver

Claims (6)

 表示部の第1電極に印加する電圧を制御する第1制御回路と、
 前記表示部の第2電極に印加する電圧を周期的に変化させるとともに、前記変化時の出力インピーダンスが前記変化前後よりも大きくなる第2制御回路と、
 前記第1制御回路を駆動する第1ドライブ回路と前記第1制御回路との間に接続される第1時定数回路と、を備え、
 前記第1時定数回路と前記第2電極とが配線により接続されていることを特徴とする駆動装置。
A first control circuit for controlling a voltage applied to the first electrode of the display unit;
A second control circuit that periodically changes a voltage applied to the second electrode of the display unit, and in which an output impedance at the time of the change is larger than before and after the change;
A first time constant circuit connected between the first drive circuit for driving the first control circuit and the first control circuit;
The drive device, wherein the first time constant circuit and the second electrode are connected by wiring.
 前記第1制御回路は、2つのトランジスタで構成されるプッシュプル回路であって、
 前記第1時定数回路は、前記トランジスタのゲートと前記第2電極との間に接続されたコンデンサ及び該コンデンサと前記第1ドライブ回路との間に接続された抵抗で構成されている、
ことを特徴とする請求項1に記載の駆動装置。
The first control circuit is a push-pull circuit composed of two transistors,
The first time constant circuit includes a capacitor connected between the gate of the transistor and the second electrode, and a resistor connected between the capacitor and the first drive circuit.
The drive device according to claim 1.
 前記第2制御回路を駆動する第2ドライブ回路と、該第2制御回路と前記第2ドライブ回路との間に接続される第2時定数回路と、を備えることを特徴とする請求項1または2に記載の駆動装置。 2. A second drive circuit for driving the second control circuit, and a second time constant circuit connected between the second control circuit and the second drive circuit. 2. The drive device according to 2.  前記第2制御回路は、2つのトランジスタで構成されるプッシュプル回路を含み、
 前記第2時定数回路は、一方側が前記第2電極及び前記トランジスタのドレイン又はソースと接続され、他方側が前記トランジスタのゲートに接続されたコンデンサと、前記ゲートと前記第2ドライブ回路との間に接続された抵抗と、で構成されている、
ことを特徴とする請求項3に記載の駆動装置。
The second control circuit includes a push-pull circuit composed of two transistors,
The second time constant circuit includes a capacitor having one side connected to the second electrode and the drain or source of the transistor and the other side connected to the gate of the transistor, and between the gate and the second drive circuit. Consisting of connected resistors,
The drive device according to claim 3.
 前記第1制御回路を複数備えるとともに、前記第1時定数回路も前記第1制御回路に対応して複数備えていることを特徴とする請求項1乃至4のうちいずれか一項に記載の駆動装置。 5. The drive according to claim 1, further comprising a plurality of the first control circuits and a plurality of the first time constant circuits corresponding to the first control circuits. 6. apparatus.  複数の前記第1時定数回路は共通の配線により前記第2電極と接続されていることを特徴とする請求項5に記載の駆動装置。 6. The driving apparatus according to claim 5, wherein the plurality of first time constant circuits are connected to the second electrode by a common wiring.
PCT/JP2016/057076 2016-03-08 2016-03-08 Drive device Ceased WO2017154089A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10239662A (en) * 1997-03-03 1998-09-11 Toshiba Corp Liquid crystal display
WO2015045067A1 (en) * 2013-09-26 2015-04-02 パイオニア株式会社 Display device and control method for display device
WO2015132908A1 (en) * 2014-03-05 2015-09-11 パイオニア株式会社 Display control device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10239662A (en) * 1997-03-03 1998-09-11 Toshiba Corp Liquid crystal display
WO2015045067A1 (en) * 2013-09-26 2015-04-02 パイオニア株式会社 Display device and control method for display device
WO2015132908A1 (en) * 2014-03-05 2015-09-11 パイオニア株式会社 Display control device

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