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WO2017030091A1 - Dispositif à semi-conducteur, amplificateur opérationnel et dispositif électronique - Google Patents

Dispositif à semi-conducteur, amplificateur opérationnel et dispositif électronique Download PDF

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Publication number
WO2017030091A1
WO2017030091A1 PCT/JP2016/073759 JP2016073759W WO2017030091A1 WO 2017030091 A1 WO2017030091 A1 WO 2017030091A1 JP 2016073759 W JP2016073759 W JP 2016073759W WO 2017030091 A1 WO2017030091 A1 WO 2017030091A1
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Prior art keywords
resistor
transistor element
line
current
source
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English (en)
Japanese (ja)
Inventor
井手大介
片倉雅幸
田上浩康
有馬茉莉
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • This technology relates to semiconductor devices, operational amplifiers, and electronic devices.
  • FIG. 13 is a diagram showing a basic configuration of a conventional transconductance circuit.
  • the transconductance circuit shown in FIG. 1 includes a PMOS 1 serving as a load MOS provided on a line L1 connecting between the high potential side power supply VDD and the low potential side power supply Gnd, and the high potential side power supply VDD and the low potential side.
  • the common-source differential circuit has a common-mode feedback circuit 5 for setting an output common-mode potential and an NMOS 6 as a current source.
  • the common-mode feedback circuit 5 connects the drain of the PMOS 1 and the drain of the PMOS 2 with the resistors Rfb1 and Rfb2 connected in series, and connects the connection points of the resistors Rfb1 and Rfb2 to the gates of the PMOS1 and PMOS2, respectively. It is.
  • the resistance values of the resistors Rfb1 and Rfb2 are the same. As a result, the common-mode potential of the output of a transconductance circuit that generally receives a differential signal can be set.
  • the resistors Rfb1 and Rfb2 detect the common-mode potential and feed back to the gates of the PMOS1 and PMOS2. Thereby, the output common-mode potential is set.
  • the range of the output common-mode potential is the voltage (VDD ⁇ Vdpsat) obtained by subtracting the voltage Vdpsat necessary for the saturation region operation of the PMOSs 1 and 2 from the high potential side power supply VDD, and the voltage necessary for the saturation region operation of the NMOS 3 or NMOS 4. It is between Vdnsat and a voltage (2Vdnsat) obtained by adding a voltage Vdnsat necessary for the operation of the NMOS 6 in the saturation region.
  • the resistors Rfb1 and Rfb2 do not feed back differential components, but become loads between the differential outputs, so they must be set to a sufficiently high value so as not to reduce the voltage gain of the transconductance circuit.
  • Vgsp which is the gate-source potential of PMOS 1 and 2
  • Vgsn which is the gate-source potential of NMOS 3 and 4
  • the drain of NMOS 6 When the source-source potential is 150 mV, the operating lower limit voltage is 1.05 V, and the minimum operating voltage as a specification is about 1.2 to 1.3 V.
  • FIG. 14 there is a configuration shown in FIG. 14, for example, as a configuration in which the input / output operating point is set to such an extent that VDD does not drop to Vgsp (for example, VDD ⁇ 200 mV).
  • Vgsp for example, VDD ⁇ 200 mV.
  • the current branch increases and the low current consumption characteristics deteriorate.
  • the transconductance circuit should have a characteristic that the output impedance is extremely high, and the transconductance Gm should be a certain value and the voltage gain should be extremely large.
  • the following equation (1) is an equation representing the output impedance Zout of the transconductance circuit shown in FIG.
  • R FB is the resistance value of the resistors Rfb1 and Rfb2
  • R DSN is the drain-source resistance of the NMOS 3 and 4
  • R DSP is the drain-source resistance of the PMOS 1 and 2.
  • the output impedances of the PMOS 1, 2 and NMOS 3 and 4 are dominant, and the resistors Rfb1 and Rfb2 of the common-mode feedback circuit further lower the output impedance.
  • the present technology has been made in view of the above problems, and aims to increase the output impedance of the semiconductor device, and more desirably to further reduce the operating voltage and / or power consumption of the semiconductor device. With the goal.
  • One aspect of the present technology includes a first transistor element of a first conductivity type interposed on a first line connecting a high potential side power source and a low potential side power source, the high potential side power source, A second transistor element of a first conductivity type interposed on a second line connecting between the low potential side power supplies and a second transistor interposed on the first line and constituting one of the differential pairs.
  • a conductive third transistor element A conductive third transistor element; a second conductive fourth transistor element interposed on the second line and constituting the other of the differential pair; the first transistor element and the third transistor element; A first output connected to the first line between, a second output connected to the second line between the second transistor element and the fourth transistor element, and A first connecting the control terminal and the first output unit; A resistor, a second resistor connecting the control terminal of the second transistor element and the second output unit, and a connection between the control terminal of the first transistor element and the control terminal of the second transistor element; And a third resistor.
  • Another aspect of the present technology includes a first transistor element of a first conductivity type interposed on a first line connecting a high potential side power source and a low potential side power source, and the high potential side
  • a second transistor element of a first conductivity type interposed on a second line connecting between a power source and the low potential side power source, and constitutes one of a differential pair interposed on the first line.
  • Another aspect of the present technology includes a first transistor element of a first conductivity type interposed on a first line connecting a high potential side power source and a low potential side power source, and the high potential side
  • a second transistor element of a first conductivity type interposed on a second line connecting between a power source and the low potential side power source, and constitutes one of a differential pair interposed on the first line.
  • semiconductor device operational amplifier, and electronic device described above include various modes such as being implemented in another device or being implemented together with another method.
  • the present technology it is possible to increase the output impedance of the semiconductor device, and it is also possible to reduce the operating voltage and / or power consumption of the semiconductor device. Note that the effects described in the present specification are merely examples and are not limited, and may have additional effects.
  • FIG. 1 is a diagram showing a configuration of a transconductance circuit 100 as a semiconductor device according to the present embodiment.
  • the transconductance circuit 100 is a transconductance circuit based on a common source-common differential circuit, and includes a pair of transistor elements 10 serving as a load, a differential pair 20, a first output unit 30, a second output unit 40, and a current source. 50, a first resistor 60, a second resistor 70, and a third resistor 80.
  • a pair of transistor elements 10 serving as a load is configured by a PMOS 11 as a first transistor element of a first conductivity type and a PMOS 12 as a second transistor of a first conductivity type.
  • the PMOS 11 is interposed on the line L1 as the first line
  • the PMOS 12 is interposed on the line L2 as the second line.
  • the first line and the second line are lines respectively connecting a constant voltage source VDD as a high potential side power source and a ground GND as a low potential side power source.
  • the differential pair 20 includes an NMOS 21 as a second conductivity type third transistor element and an NMOS 22 as a second conductivity type fourth transistor element.
  • the NMOS 21 is interposed downstream of the PMOS 11 on the line L1
  • the NMOS 22 is interposed downstream of the PMOS 12 on the line L2.
  • the voltage Vinp constituting one of the differential input voltages is input to the gate as the control terminal of the NMOS 21, and the voltage Vinn constituting the other of the differential input voltages is input to the gate as the control terminal of the NMOS 22. .
  • the current source 50 is constituted by an NMOS 51 which is a transistor element of the second conductivity type that connects between the NMOS 21 and NMOS 22 constituting the differential pair and the ground GND.
  • a constant voltage Vgsn is applied to the gate of the NMOS 51.
  • the current flowing through the NMOS 51 is set to 2 ⁇ I0.
  • the PMOS 11 and 12 and the NMOSs 21 and 22 described above each have an on-resistance.
  • Rdsp is indicated as the on-resistance of the PMOSs 11 and 12
  • Rdsn is indicated as the on-resistance of the NMOSs 21 and 22. .
  • the first output unit 30 is connected to a line L1 between the PMOS 11 and the NMOS 21, and the voltage of the first output unit 30 constitutes a voltage Voutp that constitutes one of the differential output voltages.
  • the second output unit 40 is connected to a line L2 between the PMOS 12 and the NMOS 22, and the voltage of the second output unit 40 constitutes a voltage Voutn that constitutes the other of the differential output voltages.
  • the first resistor 60 connects between the gate of the PMOS 11 and the first output unit 30, and the second resistor 70 connects between the gate of the PMOS 12 and the second output unit 40.
  • the first resistor 60 applies positive feedback to the gate of the PMOS 11
  • the second resistor 70 applies positive feedback to the gate of the PMOS 12.
  • the third resistor 80 is connected between the gate of the PMOS 11 and the gate of the PMOS 12. That is, the third resistor 80 connects between the terminal of the first resistor 60 on the side connected to the gate of the PMOS 11 and the terminal of the second resistor 70 on the side connected to the gate of the PMOS 12.
  • FIG. 2 is a small signal equivalent circuit of the current source load of the transconductance circuit 100 provided with the third resistor 80 as described above.
  • Rfb indicates the resistance value of the first resistor 60 and the second resistor 70
  • Rx indicates half of the resistance value of the third resistor 80
  • Gm indicates transconductance.
  • the output impedance between the first output unit 30 and the second output unit 40 can be expressed by the following equation (2).
  • (k ⁇ Gm) / 2 indicates a negative resistance.
  • the transconductance circuit 100 described above may be configured to directly connect the source terminals of the NMOSs 21 and 22 to the ground GND without providing the current source 50, as shown in FIG. Thus, even in the transconductance circuit 100 in which the current source 50 is not provided, a high low-frequency gain can be realized.
  • FIG. 4 is a diagram showing a configuration of a transconductance circuit 200 as a semiconductor device according to the present embodiment.
  • the transconductance circuit 200 has the same configuration as that of the transconductance circuit 100 according to the first embodiment except that a resistor 81 and a resistor 82 are provided in series instead of the third resistor 80 and a current source 210 is provided. Therefore, the common configuration is denoted by the same reference numeral as that of the transconductance circuit 100, and detailed description of each component is omitted.
  • resistance values of the resistor 81 and the resistor 82 will be described as Rx in order to correspond to the resistance value of the third resistor 80 according to the first embodiment described above in the calculation formula of the output impedance.
  • the current source 210 is connected between the connection point C of the resistor 81 and the resistor 82 which is the middle point of the third resistor 80 and the ground GND, and the current 2 ⁇ Ib is drawn from the connection point C.
  • the current Ib flows through each of the resistors 81 and 82, and the current Ib also flows through the first resistor 60 and the second resistor 70, so that the outputs Voutp and Voutn can be increased by Rfb ⁇ Ib.
  • a high output impedance can be realized. Thereby, it is possible to realize a transconductance circuit that can achieve both low voltage, low current consumption, and high output impedance.
  • the transconductance circuit 200 described above may have a configuration in which the current source 50 is not provided and the source terminals of the NMOSs 21 and 22 are directly connected to the ground GND as shown in FIG. Even in the transconductance circuit 200 in which the current source 50 is not provided, it is possible to realize low voltage, low current consumption, high output impedance, and high low frequency gain.
  • FIG. 6 is a diagram showing a specific example of the current source 210.
  • the current source 210 shown in the figure includes a resistor 211, a current source 212, a PMOS 213, a resistor 214, a current source 215, an operational amplifier 216, and NMOSs 217, 218, and 219.
  • the resistor 211 and the current source 212 are circuits that generate a desired constant voltage V1.
  • the resistor 211 and the current source 212 are connected in series, and the resistor 211 is connected to the constant voltage source VDD side, the current source 212 is connected to the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. .
  • a desired constant voltage V1 corresponding to the current values of the resistor 211 and the current source 212 is generated.
  • the PMOS 213, the resistor 214, and the current source 215 are replicas simulating the PMOS 11, the current source 50, and the first resistor 60 (or the PMOS 12, the current source 50, and the second resistor 70) as either one of the left and right sides of the transconductance circuit 200.
  • This is a circuit for generating a current source Ib that is a source of the current value of the current source 210 in the NMOS 217 having a configuration corresponding to the current source 210.
  • the PMOS 213 and the current source 215 are also connected in series.
  • the source terminal of the PMOS 213 is the constant voltage source VDD side
  • the current source 215 is the ground Gnd side
  • the constant voltage source VDD and the ground Gnd are connected. Yes.
  • the gate and drain of the PMOS 213 are connected by a resistor 214 having the same resistance value as the first resistor 60 and the second resistor 70.
  • An NMOS 217 is connected between the gate of the PMOS 213 and the ground GND.
  • the current source 215 is set to a current value half that of the current source 50.
  • a voltage V2 is generated between the drain of the PMOS 213 and the current source 215, and a current corresponding to the voltage V2 flows to the NMOS 217.
  • the operational amplifier 216 receives the voltage V2 and the constant voltage V1, and applies a voltage at which the potential difference between the constant voltage V1 and the voltage V2 becomes zero to the gate of the NMOS 217.
  • the current Ib flowing through the NMOS 217 has a current value corresponding to the constant voltage V1.
  • the current Ib generated in the NMOS 217 is current mirrored in the NMOSs 218 and 219.
  • the NMOSs 218 and 219 are configured to generate a current twice that of the NMOS 217 by, for example, doubling the transistor size.
  • a current 2 ⁇ Ib generated in the NMOSs 218 and 219 corresponding to the current source 210 of FIG. 5 is generated as a current supplied from the current source 210 to the transconductance circuit 200.
  • VDD ⁇ Vgs + Rfb ⁇ Ib which is the input / output common-mode voltage.
  • FIG. 7 is a diagram showing a configuration of a transconductance circuit 300 as a semiconductor device according to the present embodiment.
  • the transconductance circuit 300 has the same configuration as that of the transconductance circuit 200 according to the second embodiment except that the current source 210 is not provided and the resistor 310 is provided instead.
  • one terminal is connected to a connection point C between the resistor 81 and the resistor 82 which is the middle point of the third resistor 80, and the voltage Vcm is input to the other terminal.
  • the current flowing through the resistor 310 acts on the transconductance circuit 300 as the above-described current 2 ⁇ Ib.
  • the common-mode voltage Ib of the transconductance circuit 300 can be set with higher accuracy by generating the common-mode current Ib with the resistor 310 having higher current accuracy than the transistor without using a current source including a transistor element. .
  • the transconductance circuit 300 described above may be configured to directly connect the source terminals of the NMOSs 21 and 22 to the ground GND without providing the current source 50 as shown in FIG. Thus, even in the transconductance circuit 300 without the current source 50, the same current accuracy and high low frequency gain can be realized.
  • FIG. 9 is a diagram showing a specific example of a Vcm generation circuit that generates the voltage Vcm.
  • the Vcm generation circuit 310 shown in the figure includes a resistor 311, a current source 312, a PMOS 313, a resistor 314, a current source 315, a resistor 316, and an operational amplifier 317.
  • the resistor 311 and the current source 312 are circuits that generate a desired constant voltage V1.
  • the resistor 311 and the current source 312 are connected in series, and the resistor 311 is connected to the constant voltage source VDD side, the current source 312 is connected to the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. .
  • a desired constant voltage V1 corresponding to the current values of the resistor 311 and the current source 312 is generated.
  • the PMOS 313, the resistor 314, the current source 315, the resistor 316, and the operational amplifier 317 are the PMOS 11, the current source 50, and the first resistor 60 (or the PMOS 12, the current source 50, and the second one as the left or right of the transconductance circuit 300).
  • This is a replica circuit simulating the resistor 70), and is a circuit for generating the voltage Vcm at one terminal of the resistor 316 having a configuration corresponding to the resistor 310.
  • the PMOS 313 and the current source 315 are also connected in series.
  • the source terminal of the PMOS 313 is the constant voltage source VDD side
  • the current source 315 is the ground Gnd side
  • the constant voltage source VDD and the ground Gnd are connected. Yes.
  • the gate and drain of the PMOS 313 are connected by a resistor 314 having the same resistance value as the first resistor 60 and the second resistor 70.
  • the other terminal of the resistor 316 is connected to the gate of the PMOS 313.
  • the resistance value of the resistor 316 is twice that of the resistor 310.
  • the current source 315 is set to a current value half that of the current source 50. As a result, a voltage V 2 is generated between the drain of the PMOS 313 and the current source 315.
  • the operational amplifier 317 receives the voltage V2 and the constant voltage V1, has an output terminal connected to the gate of the PMOS 313 via the resistor 316, and an output terminal of the operational amplifier 317 via the resistors 314 and 316 connected in series. And the inverting input terminal are connected to each other.
  • the Vcm generation circuit 310 can supply a voltage Vcm through which a positive current or a negative current flows to the resistor 310 by adjusting the value of the voltage Vcm.
  • VDD ⁇ Vgs + Rfb ⁇ Ib which is the input / output common-mode voltage.
  • FIG. 10 is a diagram showing a configuration of a transconductance circuit 400 as a semiconductor device according to the present embodiment.
  • the transconductance circuit 400 has the same configuration as that of the transconductance circuit 100 according to the first embodiment except that a resistor 81 and a resistor 82 are provided in series instead of the third resistor 80 and a current source 410 is provided. Therefore, the common components are denoted by the same reference numerals as those of the transconductance circuit 100, and detailed description of each component is omitted.
  • resistance values of the resistor 81 and the resistor 82 will be described as Rx in order to correspond to the resistance value of the third resistor 80 according to the first embodiment described above in the calculation formula of the output impedance.
  • the current source 410 is connected between the connection point C of the resistors 81 and 82, which is the middle point of the third resistor 80, and the constant voltage source VDD, and the current 2 ⁇ Ib flows into the connection point C.
  • the current Ib flows through each of the resistors 81 and 82, and the current Ib also flows through the first resistor 60 and the second resistor 70, so that the constant voltage source VDD can be lowered by Rfb ⁇ Ib.
  • a high output impedance can be realized. Thereby, it is possible to realize a transconductance circuit that can achieve both low voltage, low current consumption, and high output impedance.
  • the transconductance circuit 400 described above may be configured to directly connect the source terminals of the NMOSs 21 and 22 to the ground GND without providing the current source 50 as shown in FIG. Even in the transconductance circuit 400 in which the current source 50 is not provided, a low voltage, a low current consumption, a high output impedance, and a high low frequency gain can be realized.
  • FIG. 12 is a diagram showing a specific example of the current source 410.
  • the current source 410 shown in the figure includes a resistor 411, a current source 412, a PMOS 413, a resistor 414, a current source 415, an operational amplifier 416, and PMOSs 417, 418, and 419.
  • the resistor 411 and the current source 412 are circuits that generate a desired constant voltage V1 corresponding to the current 2 ⁇ I0 generated by the current source 50.
  • the resistor 411 and the current source 412 are connected in series, and the resistor 411 is connected to the constant voltage source VDD side, the current source 412 is connected to the ground Gnd side, and the constant voltage source VDD and the ground Gnd are connected. .
  • a desired constant voltage V1 corresponding to the current values of the resistor 411 and the current source 412 is generated.
  • the PMOS 413, the resistor 414, and the current source 415 are replicas simulating the PMOS 11, the current source 50, and the first resistor 60 (or the PMOS 12, the current source 50, and the second resistor 70) as either one of the left and right sides of the transconductance circuit 400.
  • This is a circuit that generates a current source Ib that is a source of the current value of the current source 410 in a PMOS 417 that has a configuration corresponding to the current source 410.
  • the PMOS 413 and the current source 415 are also connected in series.
  • the source terminal of the PMOS 413 is the constant voltage source VDD side
  • the current source 415 is the ground Gnd side
  • the constant voltage source VDD and the ground Gnd are connected. Yes.
  • the gate and drain of the PMOS 413 are connected by a resistor 414 having the same resistance value as that of the first resistor 60 and the second resistor 70.
  • An NMOS 417 is connected between the gate of the PMOS 413 and the ground GND.
  • the current source 415 has a current value that is half that of the current source 50. As a result, a voltage V2 is generated between the drain of the PMOS 413 and the current source 415, and a current corresponding to the voltage V2 flows to the NMOS 417.
  • the operational amplifier 416 receives the voltage V2 and the constant voltage V1, and applies a voltage at which the potential difference between the constant voltage V1 and the voltage V2 becomes zero to the gate of the NMOS 417. Thereby, the current Ib flowing through the NMOS 417 becomes a current value corresponding to the constant voltage V1.
  • the current Ib generated in the NMOS 417 in this way is current mirrored in the NMOSs 418 and 419.
  • the NMOSs 418 and 419 are configured to generate a current twice that of the NMOS 417 by, for example, doubling the transistor size. As a result, a current 2 ⁇ Ib generated in the NMOSs 418 and 419 corresponding to the current source 410 in FIG. 11 is generated as a current supplied from the current source 410 to the transconductance circuit 400.
  • VDD ⁇ Vgs + Rfb ⁇ Ib which is the input / output common-mode voltage.
  • the transconductance circuits 100 to 400 according to the present technology described above are implemented in various modes such as being implemented as an operational amplifier with an output stage or being incorporated in a circuit of an electronic device.
  • Examples of suitable electronic circuits incorporating the transconductance circuit according to the present technology include those having digital circuits and analog circuits that are required to be miniaturized, low power supply voltage, and low power consumption.
  • the present technology is not limited to the above-described embodiments, and the configurations disclosed in the above-described embodiments are replaced with each other or the combination thereof is changed, disclosed in the known technology, and in the above-described embodiments. A configuration in which each configuration is mutually replaced or a combination is changed is also included.
  • the technical scope of the present technology is not limited to the above-described embodiment, but extends to the matters described in the claims and equivalents thereof.
  • An electronic apparatus comprising the semiconductor device according to any one of (1) to (4).
  • DESCRIPTION OF SYMBOLS 10 ... A pair of transistor element used as load, 20 ... Differential pair, 30 ... 1st output part, 40 ... 2nd output part, 50 ... Current source, 60 ... 1st resistance, 70 ... 2nd resistance, 80 ... 1st 3 resistors, 81... Resistors, 82. Resistors, 100 .. transconductance circuit, 200... Transconductance circuit, 210... Current source, 300... Transconductance circuit, 310.

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Abstract

La présente invention a pour but d'augmenter l'impédance de sortie d'un dispositif à semi-conducteur. Le dispositif à semi-conducteur est pourvu : d'un premier élément transistor (Tr) d'un premier type de conduction, interposé dans une première ligne connectant une alimentation électrique d'un côté à potentiel élevé à une alimentation électrique d'un côté à potentiel faible ; d'un deuxième élément Tr du premier type de conduction, interposé dans une seconde ligne connectant l'alimentation électrique d'un côté à potentiel élevé à l'alimentation électrique d'un côté à potentiel faible ; d'un troisième élément Tr d'un second type de conduction, interposé dans la première ligne et formant l'un d'une paire différentielle ; d'un quatrième élément Tr du second type de conduction, interposé dans la seconde ligne et formant l'autre de la paire différentielle ; d'une première partie de sortie connectée à la première ligne entre le premier élément Tr et le troisième élément Tr ; d'une seconde partie de sortie connectée à la seconde ligne entre le deuxième élément Tr et le quatrième élément Tr ; d'une première résistance connectant la borne de commande du premier élément Tr à la première partie de sortie ; d'une deuxième résistance connectant la borne de commande du deuxième élément Tr à la deuxième partie de sortie ; d'une troisième résistance connectant la borne de commande du premier élément Tr à la borne de commande du deuxième élément Tr.
PCT/JP2016/073759 2015-08-19 2016-08-12 Dispositif à semi-conducteur, amplificateur opérationnel et dispositif électronique Ceased WO2017030091A1 (fr)

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JP2015162234A JP2018157238A (ja) 2015-08-19 2015-08-19 半導体装置、オペアンプ及び電子機器
JP2015-162234 2015-08-19

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102048150B1 (ko) * 2018-06-28 2019-11-22 주식회사 에프램 출력 Level Detection 회로 장치
KR102064081B1 (ko) * 2018-07-29 2020-01-08 주식회사 에프램 전류 제한 저항 제어 증폭 회로 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5073365U (fr) * 1973-11-07 1975-06-27
JPH09147573A (ja) * 1995-11-21 1997-06-06 Seiko Epson Corp 半導体記憶装置
JPH11506580A (ja) * 1995-05-30 1999-06-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 中間周波増幅器／リミッタ
JP2009049585A (ja) * 2007-08-16 2009-03-05 Renesas Technology Corp 差動増幅回路、ミキサ回路および受信装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5073365U (fr) * 1973-11-07 1975-06-27
JPH11506580A (ja) * 1995-05-30 1999-06-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 中間周波増幅器／リミッタ
JPH09147573A (ja) * 1995-11-21 1997-06-06 Seiko Epson Corp 半導体記憶装置
JP2009049585A (ja) * 2007-08-16 2009-03-05 Renesas Technology Corp 差動増幅回路、ミキサ回路および受信装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102048150B1 (ko) * 2018-06-28 2019-11-22 주식회사 에프램 출력 Level Detection 회로 장치
KR102064081B1 (ko) * 2018-07-29 2020-01-08 주식회사 에프램 전류 제한 저항 제어 증폭 회로 장치

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