WO2016033949A1 - L2 cache and implementation method of consistency thereof, system and storage medium - Google Patents

Abstract

Disclosed are an L2 Cache and an implementation method of consistency thereof, a data processing system and a storage medium. The L2 Cache comprises a Slave interface, a controller, a Master interface and a RAM; the Slave interface is used for receiving a consistency access indication signal and access, determining that the access is a consistency access when receiving the consistency access indication signal, classifying the access according to the consistency access indication signal and access, and forming indication information according to a classification result; the controller is used for receiving the indication information, querying operation data in the RAM according to the indication information, and executing a consistency operation according to the indication information after the operation data is queried; and the Master interface is used for outputting the consistency access indication signal and the consistency access to a peripheral according to the indication information when the operation data is not queried in the RAM, and outputting the operation data to an external memory according to the indication information after the operation data is queried.

Description

L2Cache and its consistency implementation method, system and storage medium Technical field

The present invention relates to a cache technology in the field of data processing, and in particular, to a L2Cache and a consistent implementation method, system and storage medium thereof.

Background technique

In a shared-core multi-core processor, the cache Cache can cache data in the shared storage space locally, speeding up the process of multi-core acquisition of data. Since the storage views seen by each processor are obtained through the local cache, different processors may obtain different data values for data in the same storage location.

In the current multi-core system, the cache integrated with the central processing unit CPU on the same circuit board or on the main board is called a first-level L1Cache, and the cache independent of the CPU is called a second-level L2Cache. In the prior art, the Cache consistency with the L1Cache is implemented under the control of the processor; however, in order to improve the performance such as the system processing rate, multiple CPUs in a cluster cluster usually share an L2Cache; The L2Cache set by the CPU does not support consistent access. This will result in Cache consistency between L1Cache and L2Cache. L2Cache cannot implement Cache consistency.

Obviously, the Cache consistency cannot be well maintained, which will lead to many problems such as high processing error rate and low processing efficiency caused by data inconsistency.

Summary of the invention

In view of the above, the embodiment of the present invention is to provide an L2Cache, a data processing system, and a storage medium, which are capable of receiving consistent access and achieve Cache consistency. The embodiment of the present invention also provides the L2Cache consistency implementation method.

The technical solution of the present invention is implemented as follows:

A first aspect of the embodiment of the present invention provides a two-level independent cache L2Cache, where the L2Cache includes a Slave interface, a controller, a Master interface, and a RAM.

The slave interface is configured to receive a consistent access indication signal and access, and when the consistent access indication signal is received, determine that the access is a consistent access, and according to the consistent access indication signal and the access Access to classify and form indication information according to the classification result;

The controller is configured to receive the indication information, query operation data in the RAM according to the indication information, and perform a consistency operation according to the indication information after querying the operation data;

The master interface is configured to output the consistent access indication signal and the consistent access to the peripheral device according to the indication information when the operation data is not queried in the RAM, and query the operation The data is then output to the external memory in accordance with the indication information.

Based on the above scheme,

The consistent access indication signal includes a consistent access type indication signal;

The slave interface is configured to receive the consistent access type indication signal, and determine, according to the consistent access type indication signal, that the access is a consistent access.

Based on the above scheme,

The consistent access indication signal further includes the consistent access global signal;

The slave interface includes a first read address channel, a first read data channel, and a first write address channel;

The Slave interface is configured to receive the consistent access global signal, generate a slave interface control signal according to the consistent access global signal, and drive each of the channel receiving stations in the Slave interface according to the Slave interface control signal. Consistent access

The first read address channel is configured to receive the consistent access type indication signal;

The first read data channel is configured to send a read response signal to the request source according to the query result;

The first write address channel is configured to receive an external memory update signal for consistent access.

Based on the above scheme,

The consistent access global signal includes a query status of the consistently accessed operational data in other Caches and a request source for the consistent access.

Based on the above scheme,

The master interface includes a second read address channel, a second read data channel, and a second write address channel;

The second read address channel is configured to output the consistent access indication signal when the operation data is not queried in the RAM;

The second read data channel is configured to receive a read response signal and a listening response signal;

The second write address channel is configured to output an indication signal that writes the operation data to an external memory and invalidates the operation data in the cache.

Based on the above scheme,

The L2Cache also includes:

The first buffer is configured to store the access type, the query status in the other Cache, the query status in the L2Cache, and the request source of the consistent access, and provide a basis for querying the operation data and implementing Cache consistency. information.

Based on the above scheme,

The first buffer is further configured to store invalid failure information, and notify the request source according to the invalid failure information.

Based on the above scheme,

The RAM includes a Data RAM and a Tag RAM; the Data RAM is configured to store operation data; the Data RAM includes a plurality of the cache storage units; the Tag RAM a storage address configured to store operation data and status information of the cache storage unit;

The controller is configured to follow the indication information,

Read the Tag RAM and update the Tag RAM according to the result of the Tag RAM.

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and updating the Tag RAM.

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor.

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and writing the operation data to the external memory,

or

Read the Tag RAM,

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and writing the queried operation data to the external memory and updating the Tag RAM;

The updating the Tag RAM includes at least one of an update operation address and the status information.

Based on the above scheme,

The controller is further configured to: according to the indication information,

When the data RAM queries the operation data and the status of the operation data is dirty, the operation data is output to the external memory through the master interface.

Based on the above scheme,

The controller includes:

a Tag Access fifo queue, configured to store, after querying the operation data, whether to update information of the Tag RAM and an indication of accessing the Data RAM;

a Tag Write fifo queue, configured to store operation information that needs to update the Tag RAM after querying the operation data and determining that the Tag RAM needs to be updated;

a data read fifo queue, configured to store, after querying the operation data, operation information that needs to update the Tag RAM and read the Data RAM;

The control unit is configured to perform the consistency operation according to the Tag Access fifo queue, the Tag Write fifo queue, and the Data read fifo queue.

Based on the above scheme,

The controller includes a control unit;

The control unit is configured to perform an access collision detection, and when the conflicting access is detected, the blocking mechanism is used to process the access conflict.

A second aspect of the embodiments of the present invention provides a data processing system, where the system includes at least one cluster;

The cluster includes at least two processors, an intra-cluster frame listening controller, and the L2Cache according to any one of claims 1 to 9; wherein each of the processors is integrally provided with an L1Cache;

The in-cluster frame listening controller is respectively connected to the L1Cache and the L2Cache, configured to listen for consistent access, and assist any two of the L1Caches and the L1Cache to implement Cache consistency between the L1Cache and the L2Cache. .

Based on the above scheme,

The system also includes an inter-cluster frame listening controller;

The inter-cluster frame listening controller is connected to the L2Cache and configured to listen for consistent access, and assists in implementing Cache consistency between the clusters.

Based on the above scheme,

The L1Cache is configured to query, in the L1Cache, the operation data corresponding to the consistent access when receiving the consistent access; when the L1Cache queries the operation data, respond to the consistent access while in the cluster The Cache consistency of the cluster where the L1Cache is located is implemented with the assistance of the internal cache frame listening controller, and the consistency of the Cache between the clusters is realized with the assistance of the inter-cluster cache frame listening controller.

The in-cluster cache frame listening controller is configured to send the consistent access to the L2Cache when the operation data is not queried in the L1Cache in the cluster;

The L2Cache is configured to receive the consistent access and the consistent access sent by other clusters when the operation data corresponding to the consistent access is not queried in the L1Cache of the cluster, and query whether the L2Cache stores the The operating data, when the L2Cache does not query the operation data corresponding to the consistent access, querying the operation data by using the inter-cluster cache frame listening controller to other clusters other than the cluster where the L2Cache is located, in the query Responding to the consistent access after the operation data, and implementing Cache consistency between the clusters with the assistance of the inter-cluster cache frame listening controller.

A third aspect of the embodiments of the present invention provides a method for implementing L2Cache consistency, where the method includes:

Receiving a consistent access indication signal and access, and determining that the access is a consistent access when receiving the consistent access indication signal;

And classifying the access according to the consistent access indication signal and the access, and forming indication information according to the classification result;

Querying the operation data according to the indication information, performing a consistency operation according to the indication information after querying the operation data; and when the operation data is not queried, outputting the consistency access to the peripheral device according to the indication information Indication signal and the consistent access;

When the access needs to output the operation data to the external memory, after the operation data is queried, the operation data is output to the external memory according to the indication information.

Based on the above scheme,

The consistent access indication signal includes a consistent access type indication signal;

Receiving the consistent access indication signal and the access, when the consistent access indication signal is received, determining that the access is a consistent access, including:

Receiving the consistent access type indication signal, and determining, according to the consistency type indication signal, that the access is a consistent access.

Based on the above scheme,

The L2Cache includes a Slave interface; the Slave interface includes a first read address channel, a first read data channel, and a first write address channel;

The consistent access indication signal further includes the consistent access global signal;

Receiving the consistent access indication signal and the access, when the consistent access indication signal is received, determining that the access is a consistent access, including:

Receiving the consistent access global signal, and forming a slave interface control signal according to the consistent access global signal, and driving each of the channels in the Slave interface to receive the consistent access according to the slave interface control signal;

Receiving, by the first read address channel, the consistent access type indication signal;

Receiving the consistent access indication signal and the access, when the consistent access indication signal is received, determining that the access is a consistent access, and further comprising at least one of the following:

Receiving, by the first read address channel, the consistent access type indication signal;

Transmitting, by the first read data channel, a read response signal to the request source according to the query result;

An external memory update signal for consistent access is received through the first write address channel.

Based on the above scheme,

The consistent access global signal includes a query status of the consistently accessed operational data in other Caches and a request source for the consistent access.

Based on the above scheme,

The L2Cache includes a master interface, and the master interface includes a second read address channel, a second read data channel, and a second write address channel.

And outputting the consistent access indication signal and the consistent access to the peripheral device according to the indication information, when the operation data is not queried, including:

Outputting the consistent access indication signal when the operation data is not queried in the RAM through the second read address channel;

The method further includes:

Receiving a read response signal and a sounding response signal through the second read data channel;

And outputting, by the second write address channel, the operation data to the external memory and invalidating the indication signal of the operation data in the Cache.

Based on the above scheme,

After receiving the consistent access indication signal, the method further includes:

The storage access type, the query status in other Caches, the query status in the L2Cache, and the request source of the consistent access are used to provide basis information for querying the operation data and implementing Cache consistency.

Based on the above scheme,

The method further includes:

When the operation data is not queried in the L2Cache, invalid failure information is formed and stored, and the request source is notified according to the invalid failure information.

Based on the above scheme,

The slave interface includes a control module; the RAM includes a data RAM and a Tag RAM; the data RAM is used to store operation data; the Tag RAM is used to store a storage address of the operation data and state information of a cache storage unit;

The querying the operation data according to the indication information, after querying the operation data, The indicating information performing the consistency operation includes at least one of the following:

Reading, by the control module, the Tag RAM according to the indication information, and querying and updating the status information according to the result of the Tag RAM;

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and updating the status information;

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor;

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and writing the operation data to the external memory;

Read Tag RAM; and

The Tag RAM is read and the Data RAM is queried according to the result of the Tag RAM and the queried operation data is written to the external memory and the status information is updated.

Based on the above scheme,

When the access needs to output the operation data to the external memory, after the operation data is queried, the operation data is output to the external memory according to the indication information, including:

And according to the indication information, when the data RAM queries the operation data and the status of the operation data is dirty, the operation data is output to the external memory through the master interface.

Based on the above scheme,

The method further includes:

The access conflict detection is performed by the control unit, and when the conflicting access is detected, the blocking mechanism is used to process the access conflict.

A fourth aspect of the embodiments of the present invention further provides a computer storage medium, where the computer storage medium stores computer executable instructions, and the computer executable instructions are used to execute the present invention. At least one of the methods of the third aspect of the embodiments.

The L2Cache and the consistency implementation method and the data processing system of the embodiments of the present invention can achieve consistency with other Caches according to the consistent access indication signal by using the consistent access indication signal; the CPU independent L2Cache The ability to perform consistent access operations enables consistency between L1Cache and L2Cache in the data processing system and Cache consistency between clusters and clusters, which expands the scope of Cache consistency and reduces the inability of L2Cache to be realized during data processing. The resulting data handles the chance of errors and reduces the cost of maintaining Cache coherency.

DRAWINGS

FIG. 1 is a schematic structural diagram of an L2Cache according to an embodiment of the present invention;

2 is a schematic structural diagram of a data processing system according to an embodiment of the present invention;

3 is a second schematic structural diagram of a data processing system according to an embodiment of the present invention;

FIG. 4 is a schematic flowchart of a method for implementing L2Cache consistency according to an embodiment of the present disclosure.

detailed description

The present invention is further described in detail with reference to the accompanying drawings and specific embodiments.

Embodiment 1:

As shown in FIG. 1 , a L2Cache is included in the embodiment, and the L2Cache includes a Slave interface 110, a controller 120, a Master interface 130, and a RAM 140. The RAM 140 is generally further divided into a Tag RAM and a Data RAM.

The slave interface 110 is configured to receive a consistent access indication signal and access, and when the consistent access indication signal is received, determine that the access is a consistent access, according to the consistent access indication signal and the access Access to classify and form indication information according to the classification result;

The controller 120 is configured to receive the indication information, query operation data in the RAM 140 according to the indication information, and perform a consistency operation according to the indication information after querying the operation data;

The master interface 130 is configured to output the consistent access indication signal and the consistent access to the peripheral device according to the indication information when the operation data is not queried in the RAM 140, and query the The operation data is output to the external memory according to the indication information after the operation data.

The L2Cache described in this embodiment is an independent Cache with respect to the L1Cache integrated on the same motherboard as the CPU.

The slave interface 110 in the embodiment receives the consistent access indication signal with respect to the existing L2Cache when receiving the access, and determines the access according to the consistent access indication signal; It is divided into consistent access and non-uniform access; generally, when the slave interface receives the consistent access indication signal while receiving the access, it is considered that the access is received as a consistent access. The consistent access is an access operation that needs to maintain data consistency between the Caches. The data consistency between the Caches may also be referred to as Cache consistency. If the access is consistent, the indication information corresponding to the consistent access is generated, so that the L2Cache performs a corresponding consistency operation according to the indication information, such as an invalid data operation.

The classifying the access according to the consistent access indication signal and the access, including dividing the access type into a consistent access and a non-uniform access, and the operation in response to the access may include performing a read operation, a write operation, or The query operation, in order to simplify the controller's processing of data, the Slave interface will also be re-classified according to the specific operations required to facilitate the controller to quickly respond to the access with the indication information.

Optionally, the consistent access indication signal includes a consistent access type indication signal, and the slave interface 110 is configured to receive the consistent access type indication signal according to the one The causal access type indication signal determines that the access is a consistent access.

In this embodiment, the consistent access is specifically defined with respect to the non-uniform access. When receiving the consistent access, the slave interface also receives the consistent access type indication signal, so that the current access can be confirmed as a consistent access.

Optionally, the consistent access indication signal further includes the consistent access global signal;

The slave interface includes a first read address channel, a first read data channel, and a first write address channel;

The Slave interface is configured to receive the consistent access global signal, generate a slave interface control signal according to the consistent access global signal, and drive each of the channel receiving stations in the Slave interface according to the Slave interface control signal. Consistent access

The first read address channel is configured to receive the consistent access type indication signal;

The first read data channel is configured to send a read response signal to the request source according to the query result;

The first write address channel is configured to receive an external memory update signal for consistent access.

The slave interface of the embodiment is preferably an interface including five channels. In a specific implementation process, the slave interface further includes the first three channels, and further includes a first read data channel and a first write response channel. .

When the access is a consistent access, the slave interface may receive an access (the access may be a read access or a write access, etc.); and how to receive access and which channels receive access to the Slave interface described in the prior art The receiving access is consistent; in order to indicate that the access is a consistent access, the slave interface will also receive the consistent access type indication signal; in order to determine the status of the consistent access in other Caches, the consistency The access will also receive the consistent access global signal; the salve interface will synthesize the access and the information carried in the consistent access global signal, determine the operation that the L2Cache needs to perform, and form the indication information. The controller controls the slave interface, the master interface, and the RAM to perform corresponding operations according to the indication information. Consistent operation. Specifically, the method sends a read response signal to the request source according to the query result, and is a consistent access Read response added in the L2Cache.

Optionally, the consistent access global signal includes a query status of the consistently accessed operational data in other Caches and a request source of the consistent access.

The other Cache may be an L1Cache or other L2Cache. The specific request source may be a CPU integrated with the L1Cache, an AXI master device, an AXI slave device, and the like.

When the query status in the other Cache is stored, the corresponding data may be queried in the L2Cache, and the data is obtained by the other Cache, and the corresponding operation is performed in the L2Cache, and the read operation or the write operation control is performed according to whether the operation is performed. The other Cache performs a consistency operation, for example, when the L2Cache performs a write operation, the controller will output control information according to the consistent access global signal to invalidate other caches to internally stored data.

Correspondingly, in order to enable the L2Cache to support the consistent access, in this embodiment, not only the Slave interface is improved, but also the Master interface is improved, as follows: The Master interface 130 includes a second read address channel and a second read data. Channel and second write address channel;

The second read address channel is configured to output the consistent access indication signal when the operation data is not queried in the RAM; the consistent access indication signal specifically includes the consistent access type indication signal;

The second read data channel is configured to receive a read response signal and a sounding response signal; the read response signal is generally a signal outputted by the downstream processing structure of the L2Cache when the operation data is returned; the downstream processing structure is specifically an external memory memory .

The second write address channel is configured to output an indication signal that writes the operation data to an external memory and invalidates the operation data in the cache. The external memory may be various types of registers or the like. In the embodiment, the master interface 130 is also preferably a 5-channel interface, and further includes a second write data channel and a second write response channel; the second write data channel is used for outputting and receiving data write operations. Signal; the second write response channel for receiving and outputting Write a response signal.

Optionally, the L2Cache further includes: a first buffer, configured to store an access type, a query status in another Cache, a query status in the L2Cache, and a request source of the consistent access, for Query the operation data and implement Cache consistency to provide basis information.

The first buffer may be a specially configured buffer; the access type includes whether the access type is an execution access or a non-uniform access; the other cache includes an L1Cache and other L2Caches. Storing the query status in the L2Cache, so that other Caches maintain consistency with the Cache of the L2Cache when performing consistent access.

The first buffer may be configured to store the foregoing information obtained from the consistent access global signal and the interception signal to assist the L2Cache to achieve consistency with other caches.

The first buffer may be further configured to store invalid failure information, and notify the request source according to the invalid failure information.

Optionally, the RAM includes a Data RAM and a Tag RAM; the Data RAM is configured to store operational data. The Tag RAM is configured to store a storage address of the operation data and status information of a cache storage unit. The data RAM includes a plurality of the cache storage units; the cache storage unit may be a cache line or the like, and is a minimum unit for performing a cache read and write operation.

The controller 120 is configured to follow the indication information,

Read the Tag RAM and update the Tag RAM according to the result of the Tag RAM.

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and updating the Tag RAM.

Or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor.

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and writing the operation data to the external memory,

or

Read the Tag RAM,

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and writing the queried operation data to the external memory and updating the Tag RAM;

The updating the Tag RAM includes at least one of an update operation address and the status information.

The control logic of the controller in the existing L2Cache is relatively simple, and the update of the Tag RAM only occurs when the replacement by the write operation or the read-write allocation occurs, and in the present embodiment, the update of the Tag RAM is also performed. Other operations for consistent access, such as manipulating data queries. For example, when other Caches perform write operations in the consistent access, it may be necessary to invalidate the copy of the operation data in the L2Cache, and may need to invalidate the corresponding Cache unit, and the controller may execute the read Tag RAM. And according to the result of the Tag RAM query to update the control logic of the Tag RAM.

The specific controller 120 uses which control logic responds to the current access, based on information such as the operation pointed to by the access and the type of access and the status of the query in other Caches.

The controller can implement an increase in control logic by adding a control chip or a logic control circuit or the like.

Optionally, the controller 120 is further configured to: according to the indication information,

When the data RAM reads the operation data and the state of the operation data is dirty, the operation data is output to the external memory through the master interface.

The state of the operation data is dirty, indicating that the operation data in the current time Cache has been updated, but the operation data in the external memory has not been updated.

Optionally, the controller 120 includes:

a Tag Access fifo queue, configured to store, after querying the operation data, whether to update information of the Tag RAM and an indication of accessing the Data RAM;

a Tag Write fifo queue, configured to: after the querying the operation data and determining that the Tag RAM needs to be updated, storing operation information that needs to update the Tag RAM; so as to ensure that the consistent access of the Tag RAM is updated, and pressing Return in order;

a data read fifo queue, after querying the operation data, storing operation information that needs to update the Tag RAM and read the Data RAM; so as to ensure that the data update of the Tag RAM is performed after the data is read;

The control unit is configured to perform the consistency operation according to the Tag Access fifo queue, the Tag Write fifo queue, and the Data read fifo queue.

The fifo queue described in this embodiment is a first-in first-out queue; the controller 120 in this embodiment has three new queues to assist in implementing the new control logic with respect to the existing L2 cache.

Optionally, the controller 120 includes a control unit;

The control unit is configured to perform an access collision detection, and when the conflicting access is detected, the blocking mechanism is used to process the access conflict.

The above fifo queue may be located inside the control unit, and is respectively connected to the Slave interface, the Master interface, the Tag RAM and the Data RAM.

When the L2 cache needs to implement consistent access, different CPUs may perform read and write operations on the same Cache storage unit, which may cause conflicts. In this case, the control unit needs to perform access collision detection and access using the blocking mechanism. Conflict handling; the access A conflict can be all of the access violations involved in an existing Cache consistent access.

The blocking mechanism can be as follows:

If the access request needs to modify the state of a cache thread Cache, the access request for the same Cache may not be received during the state of modifying the Tag RAM, otherwise the state of the Tag RAM will not be updated; and then the subsequent from the Tag RAM The query result obtained by the query will be inaccurate, causing problems in the access of the subsequent Cache. Therefore, for all requests, the controller needs to perform collision detection with the address in the Tag Write fifo queue, and block the access request of the same index.

In summary, the present embodiment provides an L2Cache that uses five channels to implement consistent access. The specific L2Cache includes an L2Cache that does not support consistent access supported by the AXI protocol. The L2Cache Slave interface that supports the AXI protocol. Generally, the L2Cache in this embodiment may be an L2Cache improved on the L2Cache supporting the AXI protocol, and the control logic is added to the controller through multiplexing of each channel in the Slave interface and the Master interface. (The added control logic can be implemented by specifically adding new logic circuits or adding new control chips) to enable the L2Cache to support consistent access. When the L2Cache is applied to the data processing system, it can be used to implement Cache consistency with the L1Cache and the L2Cache; and the L2Cache and the existing L1Cache and the listening controller are provided in the embodiment. Very good compatibility.

Embodiment 2:

As shown in FIG. 2, this embodiment provides a data processing system, where the system includes at least one cluster;

The cluster includes at least two processors, an intra-cluster frame listening controller, and an L2Cache as described in the first embodiment; wherein each of the processors is integrally provided with an L1Cache;

The in-cluster frame listening controller L1Cache Snoop Controller is respectively connected to the L1Cache and the L2Cache, and is configured to listen for consistent access and assist any two of the L1Caches. And implementing Cache consistency between the L1Cache and the L2Cache.

Generally, when the CPU initiates an access, the L1Cache integrated in the CPU first queries whether there is corresponding operation data. When the corresponding operation data is not queried, the intra-cluster listening controller queries the other L1Caches. When the operation data is queried in the other Cache, the operation data of the query is returned to the corresponding L1Cache and the CPU with the assistance of the intra-cluster listening controller; if there is no query, the intra-cluster listening control is performed. The device queries the L2Cache; the L2Cache responds to the consistency operation.

The L2Cache described in this embodiment supports consistent access, so that the Cache consistency with the L1Cache can be implemented, and the data access efficiency and the data processing inconsistency can be improved.

As shown in FIG. 3, the system further includes an inter-cluster frame listening controller; the inter-cluster frame listening controller is connected to the L2Cache for listening for consistent access, and assists in implementing Cache coherency between clusters.

When the corresponding operation data in the consistency access does not query the corresponding data in the L1Cache and the L2Cache in a cluster, the inter-cluster frame listen controller to the other clusters to query the corresponding operation data, and the same The L2Cache and the L1Cache also receive operations such as data query operations of consistency operations sent by other clusters through the inter-cluster frame listening controller.

The system shown in FIG. 3 includes a plurality of clusters Cluster; Cluster 0 and Cluster N are shown in the figure; wherein N is an integer not less than 1. Each of the clusters includes an L1Cache, an L2Cache, and an intra-cluster cache frame listen controller.

The L1Cache is configured to query, in the L1Cache, the operation data corresponding to the consistent access when receiving the consistent access; when the L1Cache queries the operation data, respond to the consistent access while in the cluster The Cache consistency of the cluster where the L1Cache is located is implemented with the assistance of the internal cache frame listening controller, and the consistency of the Cache between the clusters is realized with the assistance of the inter-cluster cache frame listening controller.

The intra-cluster cache frame listening controller is configured to not be queried in the L1Cache in the cluster. Sending the consistent access to the L2Cache when the data is operated;

The L2Cache is configured to receive the consistent access and the consistent access sent by other clusters when the operation data corresponding to the consistent access is not queried in the L1Cache of the cluster, and query whether the secondary cache is stored in the L2Cache. The operating data, when the L2Cache does not query the operation data corresponding to the consistent access, querying the operation data by using the inter-cluster cache frame listening controller to other clusters other than the cluster where the L2Cache is located, Responding to the consistent access after querying the operation data, and implementing Cache consistency between clusters with the assistance of the inter-cluster cache frame listening controller.

After receiving the consistent access (such as the consistent access sent by the CPU), the operation data corresponding to the consistent access is first queried in the L1Cache; usually, one operation data includes multiple copies; in the L1Cache corresponding to the CPU, A copy of the operational data may or may not be stored. After the CPU queries the corresponding operation data in its corresponding L1Cache, it can directly respond to the consistent access; if it is not found in the L1Cache, it needs to go to the L2Cache to search; if the L2Cache in the cluster If not, go to other clusters to query.

For example, when the operation data B stores two copies in the Cluster 0, it is located in the L1Cache corresponding to the CPU 0 and the L2Cache of the cluster in which it is located, and when the consistency access is performed, the L1Cache corresponding to the CPU 0 is stored. The operation data B is used to perform a write operation on the operation data B, and at the same time, the L2Cache invalidates the stored operation data with the assistance of the cluster frame frame listening controller. Specifically, how to invalidate the controller that can use the Cache by updating the status information of the storage address in the Tag RAM from the valid state to the invalid state. This achieves Cache consistency within the cluster. The Cache consistency is that the information content of the same operation data stored by different Caches is consistent.

When the operation data B stores one copy in each of the Cluster 0 and the Cluster N, it is stored in the L1Cache corresponding to the CPU 0 in the Cluster 0 and the L1Cache corresponding to the CPU N corresponding to the Cluster N. Query to store the L1Cache corresponding to CPU 0 in Cluster 0. The operation data B is written to the operation data B, and the L1Cache corresponding to the CPU N in the Cluster N is invalidated with the assistance of the intra-cluster frame frame listening controller and the inter-cluster buffer listening controller. Its stored operational data. Specifically, how to invalidate the controller that can use the Cache by invalidating the storage address in the Tag RAM, such as erasing the address and the like. This achieves Cache coherency between clusters.

For example, when the operation data B is stored in the Cluster 0, there are two copies, which are respectively located in the L1Cache corresponding to the CPU0 and the L1Cache corresponding to the CPU N, wherein the N is an integer that is not less than one; The operating data B is stored in the L1Cache corresponding to the CPU 0, and the operation data B is written, and the CPU N is correspondingly assisted by the buffered frame listening controller in the cluster. L1Cache invalidates its stored operational data. Specifically, how to invalidate the controller that can use the Cache by invalidating the storage address in the Tag RAM, such as erasing the address and the like. This achieves Cache consistency within the cluster.

Similarly, when the secondary cache finds the operation data B itself, in response to the write request, the operation data B in the other clusters will be invalidated with the assistance of the inter-cluster cache listening controller.

How to trigger the Cache to invalidate the copy of the internal operation data in the embodiment can be omitted from the prior art.

The write access includes an operation of deleting operation data, adding new content to the operation data, and performing replacement modification on the content in the operation data.

When performing the consistent access response, the system described in the present embodiment first performs query processing by the primary cache, and responds according to the query result, and then has a secondary cache to perform query and response, and maintains the cluster without modifying the prior art. On the basis of the internal cache consistency, the Cache consistency between the clusters is realized, and the compatibility with the prior art is strong.

When the consistent access is a read access, the primary cache is configured to query the Performing a read operation on the operation data after operating the data;

When the consistent access is a write access, the secondary cache is configured to perform a read operation on the operational data after querying the operational data.

Since the consistent access is a read access, the operation data corresponding to the consistent access is not modified, added, and deleted, and new operation data is not generated, so that the action of invalidating the data is not required.

In this embodiment, the L2Cache and the inter-cluster cache snooping controller that can implement consistent access can implement the consistency of the Cache between the cluster and the cluster in the system, and avoid the data inconsistency between the cluster and the cluster. The probability of data processing errors.

Embodiment 3:

As shown in FIG. 4, this embodiment provides a method for implementing L2Cache consistency, where the method includes:

Step S110: Receive a consistent access indication signal and access, and determine that the access is a consistent access when receiving the consistent access indication signal;

Step S120: classify the access according to the consistent access indication signal and the access, and form indication information according to the classification result;

Step S130: Query operation data according to the indication information, perform a consistency operation according to the indication information after querying the operation data, and output the foregoing to the peripheral device according to the indication information when the operation data is not queried The consistent access indication signal and the consistent access; the peripherals herein are relative to the L2Cache, and the peripherals may be a three-level cache or RAM.

Step S140: When the access needs to output the operation data to the external memory, after the operation data is queried, the operation data is output to the external memory according to the indication information.

The method described in this embodiment is applied to the L2Cache described in Embodiment 1, and is specifically provided. L2Cache has the advantage of simple implementation, such as the implementation method of responding to consistent access.

Optionally, the consistent access indication signal includes a consistent access type indication signal;

The step S110 includes: receiving the consistent access type indication signal, and determining, according to the consistency type indication signal, that the access is a consistent access. It is further defined herein how to determine that the access is a consistent access.

Optionally, the L2Cache includes a Slave interface; the Slave interface includes a first read address channel, a first read data channel, and a first write address channel;

The consistent access indication signal further includes the consistent access global signal;

The step S110 includes:

Receiving the consistent access global signal, and forming a slave interface control signal according to the consistent access global signal, and driving each of the channels in the Slave interface to receive the consistent access according to the slave interface control signal;

Receiving, by the first read address channel, the consistent access type indication signal;

The step S110 further includes at least one of the following:

Receiving, by the first read address channel, the consistent access type indication signal;

Transmitting, by the first read data channel, a read response signal to the request source according to the query result;

An external memory update signal for consistent access is received through the first write address channel.

This embodiment further defines how each channel in the slave responds to the consistent access. The slave interface is a 5-channel interface. In a specific implementation process, the slave interface further includes a first write response channel and a first write data channel.

Optionally, the consistent access global signal includes a query status of the consistently accessed operational data in other Caches and a request source of the consistent access.

The step S110 includes the received consistent access global signal, and the step S120 includes performing classification according to the consistent access global signal to form indication information.

Optionally, the L2Cache includes a master interface, and the master interface includes a second read address channel, a second read data channel, and a second write address channel.

The step S130 specifically includes: outputting the consistent access indication signal when the operation data is not queried in the RAM through the second read address channel;

The method further includes:

Receiving a read response signal and a sounding response signal through the second read data channel;

And outputting, by the second write address channel, the operation data to the external memory and invalidating the indication signal of the operation data in the Cache.

The read response signal is typically a signal from a downstream processing structure; the downstream processing structure is such as memory or the like. The intercept response signal is from the inter-cluster listening controller or the intra-cluster listening controller described in the second embodiment.

Optionally, after the consistent access indication signal is received in step S110, the method further includes:

The storage access type, the query status in other Caches, the query status in the L2Cache, and the request source of the consistent access are used to provide basis information for querying the operation data and implementing Cache consistency.

The access type, the query status in other Caches, the query status in the L2Cache, and the request source of the consistent access may all be obtained in the access and the consistent access indication signal. In a specific implementation process, the slave interface parses the access and the consistent access indication signal, and stores the information in a buffer, so that the controller performs the consistent access operation according to the information. .

Optionally, the method further includes:

When the operation data is not queried in the L2Cache, invalid failure information is formed and stored, and the request source is notified according to the invalid failure information.

This embodiment further specifies how the L2Cache feeds back the invalidation failure letter to the request source. In order to facilitate the subsequent processing operations of the request source.

Optionally, the slave interface includes a control module; the RAM includes a data RAM and a Tag RAM; the data RAM is used to store operation data; the data RAM includes a plurality of the cache storage units; and the Tag RAM is used. And storing a storage address of the operation data and status information of the cache storage unit.

The step S130 includes at least one of the following:

Reading, by the controller, the Tag RAM according to the indication information, and updating the status information according to the result of the Tag RAM, reading the Tag RAM, and querying the Data RAM according to the result of the Tag RAM and querying the operation data. Returning to the processor and updating the status information, reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor, reading the Tag RAM and querying the result according to the result of the Tag RAM Data RAM and return the queried operation data to the processor and write the operation data to the external memory, read the Tag RAM, and read the Tag RAM and query the Data RAM according to the result of the Tag RAM and query the operation data. Write to the external memory and update the status information.

In this embodiment, the controller adds a controller to the existing L2Cache, and specifically provides control logic for how the L2Cache implements consistent access, which has the advantages of simple implementation.

Optionally, the step S140 includes:

And according to the indication information, when the data RAM queries the operation data and the status of the operation data is dirty, the operation data is output to the external memory through the master interface.

Specifically, the controller includes: a Tag Access fifo queue, configured to store, after querying the operation data, an update information of the Tag RAM and an indication of accessing the Data RAM; a Tag Write fifo queue, After the operation data is queried and it is determined that the Tag RAM needs to be updated, the operation information of the Tag RAM needs to be updated to ensure that the consistent access of the updated Tag RAM is returned in the order in which the access is initiated; the Data read fifo queue For After querying the operation data, storing operation information that needs to update the Tag RAM and reading the Data RAM to ensure that the update of the Tag RAM is performed after the data is read; the control unit is configured to use the Tag Access according to the Tag Access The fifo queue, the Tag Write fifo queue, and the Data read fifo queue perform the consistency operation.

The controller specifically uses the above-mentioned first-in-first-out fifo to control the L2Cache to implement consistent access.

Optionally, the method further includes:

The access conflict detection is performed by the control unit, and when the conflicting access is detected, the blocking mechanism is used to process the access conflict. The conflicting access includes, for example, a read operation and a write operation to the same cache storage unit.

The method in this embodiment is based on the L2Cache described in the first embodiment, and can implement the Cache consistency between the L2Cache and other Caches, including the consistency of the Cache in the cluster and the consistency of the Cache between the clusters.

Embodiment 4:

The embodiment further provides a computer storage medium, wherein the computer storage medium stores computer executable instructions, where the computer executable instructions are used to perform at least one of the methods described in the third embodiment, specifically as shown in FIG. The method shown. The computer storage medium may be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program code. In some embodiments, the computer storage medium is a non-transitory storage medium.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, such as: multiple units or components may be combined, or Can be integrated into another system, or some features can be ignored or not executed. In addition, each shown or discussed The coupling, or direct coupling, or communication connection of the components to each other may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or other.

The units described above as separate components may or may not be physically separated, and the components displayed as the unit may or may not be physical units, that is, may be located in one place or distributed to multiple network units; Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the above integration The unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to the program instructions. The foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing storage device includes the following steps: the foregoing storage medium includes: a mobile storage device, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk. A medium that can store program code.

The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Modifications made in accordance with the principles of the invention are understood to fall within the scope of the invention.

Claims (25)

A two-level independent cache L2 Cache, the L2 Cache includes a Slave interface, a controller, a Master interface, and a RAM; The slave interface is configured to receive a consistent access indication signal and access, and when the consistent access indication signal is received, determine that the access is a consistent access, and according to the consistent access indication signal and the access Access to classify and form indication information according to the classification result; The controller is configured to receive the indication information, query operation data in the RAM according to the indication information, and perform a consistency operation according to the indication information after querying the operation data; The master interface is configured to output the consistent access indication signal and the consistent access to the peripheral device according to the indication information when the operation data is not queried in the RAM, and query the operation The data is then output to the external memory in accordance with the indication information. The L2 Cache according to claim 1, wherein The consistent access indication signal includes a consistent access type indication signal; The slave interface is configured to receive the consistent access type indication signal, and determine, according to the consistent access type indication signal, that the access is a consistent access. The L2 Cache according to claim 2, wherein The consistent access indication signal further includes the consistent access global signal; The slave interface includes a first read address channel, a first read data channel, and a first write address channel; The Slave interface is configured to receive the consistent access global signal, generate a slave interface control signal according to the consistent access global signal, and drive each of the channel receiving stations in the Slave interface according to the Slave interface control signal. Consistent access The first read address channel is configured to receive the consistent access type indication signal; The first read data channel is configured to send a read response signal to the request source according to the query result; The first write address channel is configured to receive an external memory update signal for consistent access. The L2 Cache according to claim 3, wherein The consistent access global signal includes a query status of the consistently accessed operational data in other Caches and a request source for the consistent access. The L2 Cache according to claim 1, wherein The master interface includes a second read address channel, a second read data channel, and a second write address channel; The second read address channel is configured to output the consistent access indication signal when the operation data is not queried in the RAM; The second read data channel is configured to receive a read response signal and a listening response signal; The second write address channel is configured to output an indication signal that writes the operation data to an external memory and invalidates the operation data in the cache. The L2 Cache according to claim 1, wherein The L2 Cache further includes: The first buffer is configured to store an access type, a query status in another Cache, a query status in the L2 Cache, and a request source of the consistent access, to query the operation data and implement Cache consistency. Based on information. The L2 Cache according to claim 6, wherein The first buffer is further configured to store invalid failure information, and notify the request source according to the invalid failure information. The L2 Cache according to claim 1, wherein The RAM includes a Data RAM and a Tag RAM; the Data RAM is configured to be stored Operating data; the Data RAM includes a plurality of the cache storage units; the Tag RAM is configured to store a storage address of the operation data and status information of the cache storage unit; The controller is configured to follow the indication information, Read the Tag RAM and update the Tag RAM according to the result of the Tag RAM. or Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and updating the Tag RAM. or Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor. or Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and writing the operation data to the external memory, or Read the Tag RAM, or Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and writing the queried operation data to the external memory and updating the Tag RAM; The updating the Tag RAM includes at least one of an update operation address and the status information. The L2 Cache according to claim 8, wherein The controller is further configured to: according to the indication information, When the data RAM queries the operation data and the status of the operation data is dirty, the operation data is output to the external memory through the master interface. The L2 Cache according to claim 8, wherein The controller includes: a Tag Access fifo queue, configured to store, after querying the operation data, whether to update information of the Tag RAM and an indication of accessing the Data RAM; a Tag Write fifo queue, configured to store operation information that needs to update the Tag RAM after querying the operation data and determining that the Tag RAM needs to be updated; a data read fifo queue, configured to store, after querying the operation data, operation information that needs to update the Tag RAM and read the Data RAM; The control unit is configured to perform the consistency operation according to the Tag Access fifo queue, the Tag Write fifo queue, and the Data read fifo queue. The L2 Cache according to claim 1, wherein The controller includes a control unit; The control unit is configured to perform an access collision detection, and when the conflicting access is detected, the blocking mechanism is used to process the access conflict. A data processing system, wherein The system includes at least one cluster; The cluster includes at least two processors, an intra-cluster frame listening controller, and the L2 Cache according to any one of claims 1 to 9; wherein each of the processors is integrally provided with an L1Cache; The in-cluster frame listening controller is respectively connected to the L1Cache and the L2 Cache, configured to listen for consistent access, and assist any two of the L1Cache and the L1Cache and the L2 Cache to implement a Cache consistency. The system of claim 12, wherein The system also includes an inter-cluster frame listening controller; The inter-cluster frame listening controller is connected to the L2 Cache and configured to listen for consistent access, and assists in implementing Cache consistency between the clusters. The system of claim 13 wherein The L1Cache is configured to query, in the L1Cache, the operation data corresponding to the consistent access when receiving the consistent access; when the L1Cache queries the operation data, respond to the consistent access while in the cluster The Cache consistency of the cluster where the L1Cache is located is implemented with the assistance of the internal cache frame listening controller, and the consistency of the Cache between the clusters is realized with the assistance of the inter-cluster cache frame listening controller. The in-cluster cache frame listening controller is configured to send the consistent access to the L2 Cache when the operation data is not queried in the L1Cache in the cluster; The L2 Cache is configured to receive the consistent access and the consistent access sent by other clusters when the operation data corresponding to the consistent access is not queried in the L1Cache of the cluster, and query whether the L2 Cache stores the L2 Cache. The operating data, when the L2 Cache does not query the operation data corresponding to the consistent access, querying the operation data by using the inter-cluster cache frame listening controller to other clusters other than the cluster where the L2Cache is located. And responding to the consistent access after querying the operation data, and implementing Cache consistency between the clusters with the assistance of the inter-cluster cache frame listening controller. An L2 Cache consistency implementation method, the method comprising: Receiving a consistent access indication signal and access, and determining that the access is a consistent access when receiving the consistent access indication signal; And classifying the access according to the consistent access indication signal and the access, and forming indication information according to the classification result; Querying the operation data according to the indication information, performing a consistency operation according to the indication information after querying the operation data; and when the operation data is not queried, outputting the consistency access to the peripheral device according to the indication information Indication signal and the consistent access; When the access needs to output the operation data to the external memory, after the operation data is queried, the operation data is output to the external memory according to the indication information. The method of claim 15 wherein The consistent access indication signal includes a consistent access type indication signal; Receiving the consistent access indication signal and the access, when the consistent access indication signal is received, determining that the access is a consistent access, including: Receiving the consistent access type indication signal, and determining, according to the consistency type indication signal, that the access is a consistent access. The method of claim 15 wherein The L2 Cache includes a Slave interface; the Slave interface includes a first read address channel, a first read data channel, and a first write address channel; The consistent access indication signal further includes the consistent access global signal; Receiving the consistent access indication signal and the access, when the consistent access indication signal is received, determining that the access is a consistent access, including: Receiving the consistent access global signal, and forming a slave interface control signal according to the consistent access global signal, and driving each of the channels in the Slave interface to receive the consistent access according to the slave interface control signal; Receiving, by the first read address channel, the consistent access type indication signal; Receiving the consistent access indication signal and the access, when the consistent access indication signal is received, determining that the access is a consistent access, and further comprising at least one of the following: Receiving, by the first read address channel, the consistent access type indication signal; Transmitting, by the first read data channel, a read response signal to the request source according to the query result; An external memory update signal for consistent access is received through the first write address channel. The method of claim 17, wherein The consistent access global signal includes a query status of the consistently accessed operational data in other Caches and a request source for the consistent access. The method of claim 15 wherein The L2 Cache includes a Master interface, and the Master interface includes a second read address channel, a second read data channel, and a second write address channel. And outputting the consistent access indication signal and the consistent access to the peripheral device according to the indication information, when the operation data is not queried, including: Outputting the consistent access indication signal when the operation data is not queried in the RAM through the second read address channel; The method further includes: Receiving a read response signal and a sounding response signal through the second read data channel; And outputting, by the second write address channel, the operation data to the external memory and invalidating the indication signal of the operation data in the Cache. The method of claim 15 wherein After receiving the consistent access indication signal, the method further includes: The storage access type, the query status in other Caches, the query status in the L2 Cache, and the request source of the consistent access are used to provide basis information for querying the operation data and implementing Cache consistency. The method of claim 20, wherein The method further includes: When the operation data is not queried in the L2 Cache, invalid failure information is formed and stored, and the request source is notified according to the invalid failure information. The method of claim 15 wherein The slave interface includes a control module; the RAM includes a data RAM and a Tag RAM; the data RAM is used to store operation data; the Tag RAM is used to store a storage address of the operation data and state information of a cache storage unit; The querying the operation data according to the indication information, after querying the operation data, The indicating information performing the consistency operation includes at least one of the following: Reading, by the control module, the Tag RAM according to the indication information, and querying and updating the status information according to the result of the Tag RAM; Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and updating the status information; Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor; Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the queried operation data to the processor and writing the operation data to the external memory; Read Tag RAM; and The Tag RAM is read and the Data RAM is queried according to the result of the Tag RAM and the queried operation data is written to the external memory and the status information is updated. The method of claim 22, wherein When the access needs to output the operation data to the external memory, after the operation data is queried, the operation data is output to the external memory according to the indication information, including: And according to the indication information, when the data RAM queries the operation data and the status of the operation data is dirty, the operation data is output to the external memory through the master interface. The method of claim 15 wherein The method further includes: The access conflict detection is performed by the control unit, and when the conflicting access is detected, the blocking mechanism is used to process the access conflict. A computer storage medium having stored therein computer executable instructions for performing the method of claims 15-24 One of them is less.

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