CN105468540B - L2 Cache and its consistency implementation method and data processing system - Google Patents

Abstract

The invention discloses an L2 Cache and its consistency realization method and data processing system. The L2 Cache includes a Slave interface, a controller, a Master interface and a RAM; the Slave interface is used for receiving consistent access indication signals and accessing, when When the consistent access indication signal is received, it is determined that the access is a consistent access, and the access is classified according to the consistent access indication signal and the access, and the indication information is formed according to the classification result; the controller is used to receive the indication information, and store the indication information in the RAM Query the operation data in the RAM, and execute consistent operations according to the instruction information after the operation data is queried; the Master interface is used to output consistent access indication signals and consistent access and After the operation data is queried, the operation data is output to the external memory according to the instruction information.

Description

L2 Cache and its consistency implementation method and data processing system

technical field

The present invention relates to cache technology in the field of data processing, in particular to an L2 Cache and its consistent implementation method and data processing system.

Background technique

In a multi-core processor with shared storage, the cache memory Cache can cache data in the shared storage space locally, speeding up the process of obtaining data by the multi-core. Since the storage view seen by each processor is obtained through the local cache, different processors may obtain different data values for the data in the same storage location.

In the current multi-core system, the cache integrated with the central processing unit CPU on the same circuit board or motherboard is called the first-level L1 cache, and the cache independent of the CPU is called the second-level L2 cache. In the prior art, the Cache coherence between the L1 Cache and the L1 Cache is realized under the control of the processor; however, in order to improve performance such as system processing speed, multiple CPUs in a cluster usually share an L2 Cache; however, the existing The L2 Cache set separately from the CPU does not support consistent access, which will cause the L1 Cache and L2 Cache to fail to achieve Cache consistency; the L2 Cache cannot achieve Cache consistency.

Obviously, failing to maintain Cache consistency well will lead to many problems such as high processing error rate and low processing efficiency caused by data inconsistency.

Contents of the invention

In view of this, the embodiment of the present invention expects to provide an L2 Cache and data processing system capable of receiving consistent access to achieve Cache consistency; the embodiment of the present invention also provides the method for implementing the L2 Cache consistency.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

The first aspect of the embodiment of the present invention provides a second-level independent high-speed cache L2 Cache, the L2 Cache includes a Slave interface, a controller, a Master interface, and a RAM;

The Slave interface is used to receive a consistent access indication signal and access, determine that the access is a consistent access when receiving the consistent access indication signal, and perform a consistent access to the access according to the consistent access indication signal and the access Classify the visits, and form instruction information according to the classification results;

The controller is configured to receive the instruction information, query operation data in the RAM according to the instruction information, and perform a consistent operation according to the instruction information after querying the operation data;

The Master interface is used to output the consistent access indication signal and the consistent access to peripherals according to the indication information when the operation data is not queried in the RAM, and when the operation data is queried, Then output the operation data to the external memory according to the indication information.

Preferably,

The consistent access indication signal includes a consistent access type indication signal;

The slave interface is configured to receive the consistent access type indication signal, and determine that the access is consistent access according to the consistent access type indication signal.

Preferably,

The consistent access indication signal also includes the consistent access global signal;

The Slave interface includes a first read address channel, a first read data channel and a first write address channel;

The Slave interface is used to receive the consistent access global signal, drive and form a Slave interface control signal according to the consistent access global signal, and drive each of the channels in the Slave interface to receive the received signal according to the Slave interface control signal. consistent access described above;

The first read address channel is used to receive the consistent access type indication signal;

The first read data channel is used to send a read response signal to the request source according to the query result;

The first write address channel is used to receive an external memory update signal for consistent access.

Preferably,

The coherent access global signal includes the query status of the coherent access operation data in other caches and the coherent access request source.

Preferably,

The Master interface includes a second read address channel, a second read data channel and a second write address channel;

The second read address channel is used to output the consistent access indication signal when the operation data is not queried in the RAM;

The second read data channel is used to receive a read response signal and listen to a response signal;

The second write address channel is used to output an indication signal for writing the operation data to the external memory and invalidating the operation data in the Cache.

Preferably,

The L2 Cache also includes:

The first buffer is used to store the access type, the query status in other Cache, the query status in the L2 Cache and the request source of the consistent access, and is used for querying the operation data and realizing Cache consistency provide evidence based information.

Preferably,

The first buffer is also used to store invalid failure information, and notify the request source according to the invalid failure information.

Preferably,

The RAM includes Data RAM and Tag RAM; the Data RAM is used to store operation data; the DataRAM includes several cache storage units; the Tag RAM is used to store storage addresses of operation data and the cache storage units status information;

The controller is specifically configured to, according to the indication information,

Read the Tag RAM and query and update the Tag RAM according to the result of the Tag RAM,

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and updating the Tag RAM,

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor,

or

reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and writing the operation data to the external memory,

or

Read Tag RAM,

or

Read the Tag RAM and query the Data RAM according to the result of the Tag RAM and write the query operation data to the external memory and update the Tag RAM;

Wherein, updating the Tag RAM includes updating at least one of an operation address and the state information.

Preferably,

The controller is further specifically configured to, according to the indication information,

When the Data RAM finds the operation data and the state of the operation data is dirty, output the operation data to the external memory through the master interface.

Preferably,

The controller includes:

The Tag Access fifo queue is used to store information about whether to update the TagRAM and an instruction to access the Data RAM after the operation data is queried;

The Tag Write fifo queue is used to store the operation information that needs to be updated to the Tag RAM when the operation data is queried and the TagRAM needs to be updated;

Data read fifo queue, used for storing operation information that needs to update the Tag RAM and read the Data RAM after the operation data is queried;

A control unit, configured to execute the consistency operation according to the Tag Access fifo queue, Tag Write fifo queue and Dataread fifo queue.

Preferably,

The controller includes a control unit;

The control unit is configured to perform access conflict detection, and when a conflict access is detected, a blocking mechanism is used to process the access conflict.

The second aspect of the embodiment of the present invention provides a data processing system, the system includes at least one cluster;

The cluster includes at least two processors, an intra-cluster frame listener controller, and the L2 Cache according to any one of claims 1 to 9; wherein, each of the processors is integrated with an L1 Cache;

The intra-cluster frame monitoring controller is connected to the L1 Cache and the L2 Cache respectively, and is used for monitoring consistent access, assisting any two of the L1 Cache and the connection between the L1 Cache and the L2 Cache To achieve cache coherency.

Preferably,

The system also includes an inter-cluster frame listening controller;

The inter-cluster frame monitoring controller is connected to the L2 Cache for monitoring consistent access, and assists in realizing Cache consistency between clusters.

Preferably,

The L1 Cache is specifically used to query the operation data corresponding to the consistency access in the L1 Cache when receiving the consistency access; when the L1 Cache queries the operation data, respond to the consistency access, and at the same time Realize the Cache consistency of the cluster where the L1 Cache is located with the assistance of the intra-cluster cache frame controller, and realize the inter-cluster Cache consistency with the assistance of the inter-cluster cache frame controller;

The intra-cluster cache frame controller is configured to send the consistent access to the L2 Cache when the operation data is not found in the L1 Cache in the cluster;

The L2 Cache is used to receive the consistent access and the consistent access sent by other clusters when the operation data corresponding to the consistent access is not queried in the L1 Cache of the cluster, and query whether the L2 Cache stores any For the operation data, when the L2 Cache does not query the operation data corresponding to the consistent access, query the operation data in a cluster other than the cluster where the L2 Cache is located through the inter-cluster cache frame controller data, responding to the consistent access after querying the operation data, and realizing inter-cluster Cache consistency with the assistance of the inter-cluster cache frame controller.

A third aspect of the embodiments of the present invention provides a method for implementing L2 Cache consistency, the method comprising:

Receiving a consistent access indication signal and an access, and determining that the access is a consistent access when receiving the consistent access indication signal;

Classify the access according to the consistent access indication signal and the access, and form indication information according to the classification result;

Querying the operation data according to the instruction information, and performing a consistent operation according to the instruction information after the operation data is queried; when the operation data is not queried, output the consistent access to the peripheral device according to the instruction information indication signal and said coherent access;

When the access needs to output the operation data to the external memory, output the operation data to the external memory according to the indication information after the operation data is queried.

Preferably,

The consistent access indication signal includes a consistent access type indication signal;

The receiving consistent access indication signal and access, determining that the access is consistent access when receiving the consistent access indication signal, includes:

receiving the consistent access type indication signal, and determining that the access is a consistent access according to the consistency type indication signal.

Preferably,

The L2 Cache includes a Slave interface; the Slave interface includes a first read address channel, a first read data channel and a first write address channel;

The consistent access indication signal also includes the consistent access global signal;

The receiving consistent access indication signal and access, determining that the access is consistent access when receiving the consistent access indication signal, includes:

receiving the consistent access global signal, driving to form a slave interface control signal according to the consistent access global signal, and driving each of the channels in the slave interface to receive the consistent access according to the slave interface control signal;

receiving the consistent access type indication signal through the first read address channel;

The receiving consistent access indication signal and access, determining that the access is consistent access when receiving the consistent access indication signal, also includes at least one of the following:

receiving the consistent access type indication signal through the first read address channel;

sending a read response signal to the request source through the first read data channel according to the query result;

An external memory update signal for consistent access is received through the first write address channel.

Preferably,

The coherent access global signal includes the query status of the coherent access operation data in other caches and the coherent access request source.

Preferably,

The L2 Cache includes a Master interface; the Master interface includes a second read address channel, a second read data channel, and a second write address channel;

The step of outputting the consistent access indication signal and the consistent access to peripherals according to the indication information when the operation data is not inquired includes:

Outputting the consistent access indication signal when the operation data is not queried in the RAM through the second read address channel;

The method also includes:

receiving a read response signal and a listen response signal through the second read data channel;

Outputting an indication signal for writing the operation data to the external memory and invalidating the operation data in the Cache through the second write address channel.

Preferably,

After receiving the consistent access indication signal, the method further includes:

Store access type, query status in other Cache, query status in L2 Cache and the request source of the consistent access, which is used to provide basis information for querying the operation data and realizing Cache consistency.

Preferably,

The method also includes:

When the operation data is not found in the L2 Cache, the invalid failure information is formed and stored, and the request source is notified according to the invalid failure information.

Preferably,

The Slave interface includes a controller; the RAM includes Data RAM and Tag RAM; the Data RAM is used to store operation data; the Tag RAM is used to store the storage address of the operation data and the state information of the cache storage unit;

The querying of the operation data according to the instruction information, and performing a consistent operation according to the instruction information after querying the operation data includes at least one of the following:

Through the controller, read the Tag RAM according to the instruction information, and query and update the state information according to the result of the Tag RAM;

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and updating the state information;

Read the Tag RAM and query the Data RAM according to the result of the Tag RAM and return the query operation data to the processor;

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and writing the operation data to the external memory;

Read Tag RAM; and

Read the Tag RAM and query the Data RAM according to the result of the Tag RAM and write the query operation data to the external memory and update the state information.

Preferably,

When the access needs to output the operation data to the external memory, output the operation data to the external memory according to the instruction information after querying the operation data, including:

According to the indication information, when the Data RAM finds the operation data and the state of the operation data is dirty, output the operation data to the external memory through the master interface.

Preferably,

The method also includes:

Access conflict detection is performed by the control unit, and when conflict access is detected, a blocking mechanism is used to process the access conflict. The L2 Cache and its consistency implementation method and data processing system described in the embodiments of the present invention can achieve consistency with other Caches according to the consistency access indication signal through the reception of the consistency access indication signal; independent of the CPU L2 Cache can perform consistent access operations, and can realize the consistency between L1 Cache and L2Cache in the data processing system and the Cache consistency between clusters, which expands the scope of Cache consistency and reduces the data processing process. Data processing error probability caused by L2 Cache failure.

Description of drawings

FIG. 1 is a schematic structural diagram of an L2 Cache according to an embodiment of the present invention;

Fig. 2 is one of the structural diagrams of the data processing system described in the embodiment of the present invention;

Fig. 3 is the second structural diagram of the data processing system described in the embodiment of the present invention;

FIG. 4 is a schematic flowchart of the method for implementing L2 Cache consistency described in the embodiment of this method.

Detailed ways

The technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Embodiment one:

As shown in 1, the present embodiment is a kind of secondary high-speed cache device L2 Cache, and described L2 Cache comprises Slave interface 110, controller 120, Master interface 130 and RAM 140; Described RAM 140 is usually divided into Tag RAM and DataRAM again .

The Slave interface 110 is configured to receive a consistent access indication signal and access, determine that the access is a consistent access when receiving the consistent access indication signal, and determine the access according to the consistent access indication signal and the access. Classify the visits, and form instruction information according to the classification results;

The controller 120 is configured to receive the instruction information, query operation data in the RAM 140 according to the instruction information, and perform a consistent operation according to the instruction information after querying the operation data;

The Master interface 130 is configured to output the consistent access indication signal and the consistent access to peripherals according to the indication information when the operation data is not queried in the RAM 140, and when the operation data is queried, the After operating the data, output the operation data to the external memory according to the indication information.

The L2 Cache described in this embodiment is an independent Cache relative to the L1 Cache integrated with the CPU on the same motherboard.

In this embodiment, the Slave interface 110, when receiving access, will also receive the consistent access indication signal relative to the existing L2Cache, and judge the access according to the consistent access indication signal; It is divided into consistent access and non-uniform access; usually when the Slave interface receives the access and receives the consistent access indication signal at the same time, it is considered that the received access is consistent access. The consistent access is an access operation that needs to maintain data consistency between caches, and this kind of data consistency between caches may also be called cache consistency. If it is a consistent access, indication information corresponding to the consistent access will be generated, so that the L2 Cache can perform corresponding consistent operations according to the indication information, specifically operations such as invalid data.

Classifying the access according to the consistent access indication signal and the access includes classifying the access type into consistent access and non-uniform access, and the operation in response to the access may include performing a read operation, a write operation, or a write operation on the RAM. For query operations, in order to simplify data processing by the controller, the Slave interface will also classify again according to the specific operations to be performed, so that the controller can quickly respond to the access with the instruction information.

Preferably, the consistent access indication signal includes a consistent access type indication signal; the Slave interface 110 is configured to receive the consistent access type indication signal, and determine that the access is consistent access.

In this embodiment, it is specifically defined that consistent access is relative to non-consistent access. When the Slave interface receives consistent access, it will also receive the consistent access type indication signal, so that the current access can be confirmed as consistent access.

Preferably,

The consistent access indication signal also includes the consistent access global signal;

The Slave interface includes a first read address channel, a first read data channel and a first write address channel;

The Slave interface is used to receive the consistent access global signal, drive and form a Slave interface control signal according to the consistent access global signal, and drive each of the channels in the Slave interface to receive the received signal according to the Slave interface control signal. consistent access described above;

The first read address channel is used to receive the consistent access type indication signal;

The first read data channel is used to send a read response signal to the request source according to the query result;

The first write address channel is used to receive an external memory update signal for consistent access.

The Slave interface described in this embodiment is preferably an interface comprising 5 channels; in a specific implementation process, the Slave interface will also include the first read data channel and the first write response channel in addition to the above-mentioned 3 channels .

When the access is a consistent access, the Slave interface will receive access, such as read access or write access; how to receive access and which channels receive access is the same as that of the Slave interface in the prior art. Consistent; in order to indicate that the access is a consistent access, the Slave interface will also receive the consistent access type indication signal; in order to determine the status of the consistent access in other Cache and other information, the consistent access will also Receive the consistent access global signal; the salve interface will synthesize the access and the information carried in the consistent access global signal, determine the operation to be performed by the L2 Cache, and then form instruction information. The controller will control the Slave interface, the Master interface and the RAM to perform corresponding consistent operations according to the instruction information. Specifically, sending a read response signal to the request source according to the query result is a consistent access Read response added in the L2 Cache.

Preferably, the coherent access global signal includes the query status of the coherent access operation data in other caches and the coherent access request source.

The other Cache may be L1 Cache or other L2 Cache. Specifically, the request source may be a CPU integrated with L1Cache, an AXI master device, an AXI slave device, and the like.

When storing the query status in the other Cache, if the corresponding data cannot be queried in this L2 Cache, go to other Cache to obtain the data, copy it to this L2 Cache to perform the corresponding operation, and at the same time, according to whether the operation is a read operation or a write operation The operation controls other Caches to perform consistent operations. Specifically, when the current L2 Cache performs a write operation, the controller will output control information according to the consistent access global signal so that other Caches invalidate their internally stored data.

Correspondingly, in order to make the L2 Cache support consistent access, not only the Slave interface has been improved in this embodiment, but also the Master interface has been improved, as follows: the Master interface 130 includes a second read address channel, a second read address channel, and a second read address channel. A data channel and a second write address channel;

The second read address channel is used to output the consistent access indication signal when the operation data is not queried in the RAM; the consistent access indication signal specifically includes the consistent access type indication signal;

The second read data channel is used to receive a read response signal and listen for a response signal; the read response signal is usually a signal output when the downstream processing structure of the L2 Cache returns operation data; the downstream processing structure is specifically such as an external memory memory.

The second write address channel is used to output an indication signal for writing the operation data to the external memory and invalidating the operation data in the Cache. The external memory may be various types of registers and the like. In this embodiment, the Master interface 130 is also preferably a 5-channel interface, and also includes a second write data channel and a second write response channel; the second write data channel is used to output and receive data related to the write operation signal; the second write response channel is used for receiving and outputting a write response signal.

Preferably, the L2 Cache also includes:

The first buffer is used to store the access type, the query status in other Cache, the query status in the L2 Cache and the request source of the consistent access, and is used for querying the operation data and realizing Cache consistency provide evidence based information.

The first buffer may be a specially set buffer; the access type includes whether the access type is one-execution access or non-uniform access; the other Cache includes L1 Cache and other L2 Cache, etc. Storing the query state in the L2 Cache is convenient for other Caches to maintain consistency with the Cache of the L2 Cache when performing consistent access.

The first buffer is specifically used to store the above information obtained from the coherent access global signal and the listening signal, so as to assist the L2 Cache to achieve consistency with other Cache.

The first buffer is also used to store invalid failure information, and notify the request source according to the invalid failure information.

Preferably, the RAM includes Data RAM and Tag RAM; the Data RAM is used to store operation data and the Tag RAM is used to store the storage address of the operation data and the state information of the cache storage unit; the Data RAM includes several The cache storage unit; the cache storage unit may specifically be a cache row, etc., and is the smallest unit for performing cache read and write operations.

The controller 120 is specifically configured to, according to the indication information,

Read the Tag RAM and query and update the Tag RAM according to the result of the Tag RAM,

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and updating the Tag RAM,

or

Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor,

or

reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and writing the operation data to the external memory,

or

Read Tag RAM,

or

Read the Tag RAM and query the Data RAM according to the result of the Tag RAM and write the query operation data to the external memory and update the Tag RAM;

Wherein, updating the Tag RAM includes updating at least one of an operation address and the status information.

The control logic of the controller in the existing L2 Cache is relatively simple, and the update to the Tag RAM only occurs when the replacement caused by the write operation or read-write allocation, but in this embodiment, the update to the Tag RAM also occurs When performing other operations for consistent access, such as operating data queries. Specifically, when other Cache is performing a write operation in consistent access, it may need to invalidate the copy of the operation data in this L2 Cache, and may need to invalidate the corresponding Cache unit, then the controller may execute the read Tag The RAM queries and updates the control logic of the Tag RAM according to the result of the Tag RAM.

The specific control logic adopted by the controller 120 to respond to the current access is determined according to the operation pointed to by the access, the type of the access, and the query status in other caches.

The controller can increase the control logic by adding a control chip or a logic control circuit.

Preferably, the controller 120 is also specifically configured to, according to the indication information,

When the Data RAM finds the operation data and the state of the operation data is dirty, output the operation data to the external memory through the master interface.

The state of the operation data is dirty, which means that the operation data in the Cache has been updated at the current moment, but the operation data in the external memory has not been updated.

Preferably, the controller 120 includes:

The Tag Access fifo queue is used to store information about whether to update the TagRAM and an instruction to access the Data RAM after the operation data is queried;

The Tag Write fifo queue is used to store the operation information that needs to be updated to the Tag RAM when the operation data is queried and the TagRAM needs to be updated;

Data read fifo queue, used for storing operation information that needs to update the Tag RAM and read the Data RAM after the operation data is queried;

A control unit, configured to execute the consistency operation according to the Tag Access fifo queue, Tag Write fifo queue and Dataread fifo queue.

The fifo queue described in this embodiment is a first-in-first-out queue; compared with the existing L2 cache, the controller 120 described in this embodiment has 4 new queues to assist in implementing the newly added control logic.

Preferably, the controller 120 includes a control unit;

The control unit is configured to perform access conflict detection, and when a conflict access is detected, a blocking mechanism is used to process the access conflict.

The specific structure of the control unit may be a processing chip, which is respectively connected to the above-mentioned fifo, the Slave interface, the Master interface and RAM.

When the L2 cache needs to implement consistent access, there may be different CPUs performing read and write operations on the same Cache storage unit, which will cause conflicts. At this time, the control unit needs to perform access conflict detection and use a blocking mechanism to The access conflicts are coordinated and processed; the access conflicts may be all access conflicts involved in the existing Cache consistent access; the blocking mechanism may also adopt the existing blocking mechanism.

Based on the above, this embodiment provides an L2 Cache that uses 5 channels to achieve consistent access. The specific existing L2 Cache includes an L2 Cache that supports the AXI protocol and does not support consistent access; this L2 Cache that supports the AXI protocol The Slave interface of Cache is usually 5 channels, and the L2 Cache described in this embodiment can be the L2 Cache improved on the L2 Cache of described support AXI agreement, through the multiplexing of each channel in the Slave interface and the Master interface, in the Adding control logic to the controller (the added control logic can be realized by adding a new logic circuit or a new control chip) makes the L2 Cache support consistent access. When the L2 Cache is applied to a data processing system, it can be used to achieve Cache consistency with L1 Cache and or L2 Cache; and practice has proved that the L2 Cache described in this embodiment is compatible with the existing L1 Cache and intercept Devices such as controllers have good compatibility.

Embodiment two:

As shown in Figure 2, this embodiment provides a data processing system, the system includes at least one cluster;

The cluster includes at least two processors, an intra-cluster frame listener controller, and an L2Cache as described in Embodiment 1; wherein, each of the processors is integrated with an L1 Cache;

The intra-cluster frame snooping controller L1 Cache Snoop Controller is connected to the L1 Cache and the L2 Cache respectively, and is used for snooping consistent access, assisting any two of the L1 Cache and the L1 Cache with all Cache coherence is achieved between the above L2 caches.

Usually, when a CPU initiates an access, it first inquires whether there is corresponding operation data in the L1 Cache integrated with the CPU. Query, when the operation data is found in other Cache, with the assistance of the in-cluster interception controller, the inquired operation data is returned to the corresponding L1Cache and CPU; The listening controller queries the L2 Cache; the L2 Cache responds to the consistency operation.

The L2 Cache described in this embodiment supports consistent access, thereby achieving Cache consistency with the L1 Cache, improving data access efficiency and reducing data processing inconsistencies.

As shown in FIG. 3 , the system further includes an inter-cluster frame snoop controller; the inter-cluster frame snoop controller is connected to the L2Cache for snooping coherent access, and assists in realizing inter-cluster Cache coherency.

When the corresponding operation data in the consistent access is not queried in the L1 Cache and L2 Cache in a cluster, the inter-cluster frame listener controller goes to other clusters to query the corresponding operation data, and the same The L2 Cache and the L1 Cache also receive operations such as data query operations sent by other clusters through the inter-cluster frame monitoring controller.

The system shown in FIG. 3 includes multiple clusters; Cluster 0 and Cluster N are shown in the diagram; wherein, N is an integer not less than 1. Each of the clusters includes L1 Cache, L2 Cache and an intra-cluster cache frame controller.

The L1 Cache is specifically used to query the operation data corresponding to the consistency access in the L1 Cache when receiving the consistency access; when the L1 Cache queries the operation data, respond to the consistency access, and at the same time Realize the Cache consistency of the cluster where the L1 Cache is located with the assistance of the intra-cluster cache frame controller, and realize the inter-cluster Cache consistency with the assistance of the inter-cluster cache frame controller;

The intra-cluster cache frame controller is configured to send the consistent access to the L2 Cache when the operation data is not found in the L1 Cache in the cluster;

The L2 Cache is used to receive the consistent access and the consistent access sent by other clusters when the operation data corresponding to the consistent access is not found in the L1 Cache of the cluster, and query whether the secondary cache stores With the operation data, when the operation data corresponding to the consistent access is not queried by the L2 Cache, the inter-cluster cache frame listener controller queries the L2 Cache in a cluster other than the cluster where the L2 Cache is located. Operating data, responding to the consistent access after querying the operating data, and realizing inter-cluster Cache consistency with the assistance of the inter-cluster cache frame controller.

After receiving consistent access (such as the consistent access issued by the CPU), the operation data corresponding to the consistent access will first be queried in the L1 Cache; usually an operation data will include multiple copies; in the L1 Cache corresponding to the CPU There may or may not be a copy of the operational data stored in the . When the CPU finds the corresponding operation data in its corresponding L1 Cache, it can directly respond to the consistent access; if it is not found in the L1Cache, it needs to search in the L2Cache; if the L2 in the cluster If there is no cache, go to other clusters to query.

Specifically, when the operation data B has two copies stored in Cluster 0, which are located in the L1 Cache corresponding to CPU 0 and the L2 Cache of the cluster where it is located, when performing consistent access, the L1 Cache corresponding to CPU 0 is queried. The operation data B is stored in the L2 Cache, and the operation data B is written, and at the same time, with the assistance of the intra-cluster cache frame controller, the L2 Cache invalidates the stored operation data. Specifically, how to invalidate can use the controller of the Cache to update the state information of the storage address in the Tag RAM from a valid state to an invalid state. This achieves cache consistency within the cluster. The cache consistency means that the information content of the same operation data stored in different caches is consistent.

When the operation data B stores one copy in each of Cluster 0 and Cluster N, it is specifically stored in the L1 Cache corresponding to CPU 0 in Cluster 0 and in the L1 Cache corresponding to CPU N in Cluster N. Querying that the operation data B is stored in the L1 Cache corresponding to CPU 0 in Cluster 0, performing a write operation on the operation data B, and simultaneously caching the frame listener controller and the inter-cluster cache listener control in the cluster With the assistance of the controller, the L1Cache corresponding to CPU N in Cluster N is invalidated to delete the operation data stored therein. Specifically, how to invalidate can use the controller of the Cache to invalidate the storage address in the Tag RAM, such as erasing the address and similar operations. This achieves cache consistency between clusters.

For another example, when the operation data B has two copies stored in Cluster 0, they are respectively located in the L1 Cache corresponding to CPU 0 and the L1 Cache corresponding to CPU N, where N is an integer not less than 1; During a permanent access, it is found that the operation data B is stored in the L1 Cache corresponding to CPU 0, and the operation data B is written, and at the same time, with the assistance of the cache frame controller in the cluster, the CPU The L1 Cache corresponding to N invalidates the stored operation data. Specifically, how to invalidate can use the controller of the Cache to invalidate the storage address in the Tag RAM, such as erasing the address and similar operations. This achieves cache consistency within the cluster.

The same secondary cache finds the operation data B by itself, and when responding to the write request, it will also invalidate the operation data B in other clusters with the assistance of the inter-cluster cache snooping controller.

In this embodiment, how to trigger the Cache to invalidate the copy of its internal operation data can be referred to the prior art and will not be elaborated here one by one.

The write access includes operations of deleting operation data, adding new content in the operation data, and replacing and modifying content in the operation data.

When the system described in this implementation performs consistent access response, the first-level Cache performs query processing, and responds according to the query results, and then the second-level Cache performs query and response, and maintains the cluster without modifying the existing technology. On the basis of intra-cache consistency, inter-cluster cache consistency is realized, which is highly compatible with existing technologies.

When the consistent access is a read access, the first-level Cache is specifically used to perform a read operation on the operation data after the operation data is queried;

When the consistent access is a write access, the secondary cache is specifically configured to perform a read operation on the operation data after the operation data is queried.

Since the consistent access is a read access, the operation data corresponding to the consistent access will not be modified, added, or deleted, and no new operation data will be generated, so there is no need to invalidate the operation data.

In this embodiment, the L2 Cache that can realize consistent access and the introduction of the inter-cluster cache interception controller can realize the consistency of the Cache between the clusters in the system, and avoid the data inconsistency between the clusters. Chances of data processing errors.

Embodiment three:

As shown in Figure 4, this embodiment provides a method for implementing L2 Cache consistency, the method comprising:

Step S110: receiving a consistent access indication signal and an access, and determining that the access is a consistent access when the consistent access indication signal is received;

Step S120: Classify the access according to the consistent access indication signal and the access, and form indication information according to the classification result;

Step S130: Query the operation data according to the instruction information, and perform a consistent operation according to the instruction information after the operation data is queried; when the operation data is not queried, output the operation data to the peripheral device according to the instruction information consistent access indication signal and the consistent access;

Step S140: When the access needs to output the operation data to the external memory, output the operation data to the external memory according to the instruction information after the operation data is queried.

The method described in this embodiment is applied to the L2 Cache described in Embodiment 1, and specifically provides an implementation method of the L2 Cache such as response consistent access, which has the advantage of simple implementation.

Preferably,

The consistent access indication signal includes a consistent access type indication signal;

The step S110 includes: receiving the consistent access type indication signal, and determining that the access is a consistent access according to the consistent type indication signal. How to determine that the access is a consistent access is further defined here.

Preferably, the L2 Cache includes a Slave interface; the Slave interface includes a first read address channel, a first read data channel and a first write address channel;

The consistent access indication signal also includes the consistent access global signal;

The step S110 includes:

receiving the consistent access global signal, driving to form a slave interface control signal according to the consistent access global signal, and driving each of the channels in the slave interface to receive the consistent access according to the slave interface control signal;

receiving the consistent access type indication signal through the first read address channel;

The step S110 also includes at least one of the following:

receiving the consistent access type indication signal through the first read address channel;

sending a read response signal to the request source through the first read data channel according to the query result;

An external memory update signal for consistent access is received through the first write address channel.

This embodiment further defines how each channel in the slave responds to the consistent access. The Slave interface is a 5-channel interface. In a specific implementation process, the Slave interface also includes a first write response channel and a first write data channel.

Preferably, the coherent access global signal includes the query status of the coherent access operation data in other caches and the coherent access request source.

The step S110 includes receiving the consistent access global signal, and the step S120 includes classifying the consistent access global signal to form indication information.

Preferably, the L2 Cache includes a Master interface; the Master interface includes a second read address channel, a second read data channel, and a second write address channel;

The step S130 specifically includes: outputting the consistent access indication signal when the operation data is not queried in the RAM through the second read address channel;

The method also includes:

receiving a read response signal and a listen response signal through the second read data channel;

Outputting an indication signal for writing the operation data to the external memory and invalidating the operation data in the Cache through the second write address channel.

The read response signal is usually a signal from a downstream processing structure; the downstream processing structure is such as memory and the like. The intercept response signal comes from the inter-cluster intercept controller or the intra-cluster intercept controller described in the second embodiment.

Preferably, after receiving the consistent access indication signal in step S110, the method further includes:

Store access type, query status in other Cache, query status in L2 Cache and the request source of the consistent access, which is used to provide basis information for querying the operation data and realizing Cache consistency.

The access type, the query status in other Cache, the query status in the L2 Cache, and the request source of the consistent access may all be obtained from the access and the consistent access indication signal. In a specific implementation process, the Slave interface parses the access and the consistent access indication signal, and stores the information in a buffer, so that the controller can perform the consistent access operation according to the information .

Further, the method also includes:

When the operation data is not found in the L2 Cache, the invalid failure information is formed and stored, and the request source is notified according to the invalid failure information.

This embodiment further specifies how the L2 Cache feeds back storage invalidation failure information to the request source, so that the request source can perform subsequent processing operations.

Preferably, the Slave interface includes a controller; the RAM includes Data RAM and Tag RAM; the Data RAM is used to store operation data; the Data RAM includes several cache storage units; the Tag RAM is used for storing the storage address of the operation data and the state information of the cache storage unit;

The step S130 includes at least one of the following:

Through the controller, according to the instruction information, read the Tag RAM and query and update the state information according to the result of the Tag RAM, read the Tag RAM and query the Data RAM according to the result of the Tag RAM and query the operation data Return to the processor and update the state information, read the Tag RAM and query the DataRAM according to the result of the Tag RAM and return the query operation data to the processor, read the Tag RAM and query the DataRAM according to the result of the Tag RAM and return the query operation data to the processor and write the operation data to the external memory, read the Tag RAM, and read the Tag RAM and query the Data RAM according to the result of the Tag RAM and write the query operation data to external memory and update the state information.

Compared with the existing L2 Cache, the controller in this embodiment adds a new controller, and specifically provides control logic for how the L2 Cache implements consistent access, which has the advantage of simple implementation.

Preferably,

The step S140 includes:

According to the indication information, when the Data RAM finds the operation data and the state of the operation data is dirty, output the operation data to the external memory through the master interface.

Specifically, the controller includes: a Tag Access fifo queue, used to store the update information of the Tag RAM and an indication of access to the Data RAM after the operation data is queried; a Tag Write fifo queue, used After the operation data is queried and it is determined that the Tag RAM needs to be updated, the operation information of the Tag RAM that needs to be updated is stored; the Data read fifo queue is used to store the operation information that needs to be updated after the operation data is queried. The TagRAM and read the operation information of the Data RAM; the control unit is used to execute the consistency operation according to the Tag Access fifo queue, the TagWrite fifo queue and the Data read fifo queue.

The controller specifically utilizes the above-mentioned first-in-first-out fifo to control the L2 Cache to implement consistent access.

Further, the method also includes:

Access conflict detection is performed by the control unit, and when conflict access is detected, a blocking mechanism is used to process the access conflict. The conflicting access includes, for example, a read operation and a write operation to the same cache storage unit

The method described in this embodiment is a method proposed on the basis of the L2 Cache described in Embodiment 1, which can realize the Cache consistency between the L2 Cache and other Cache, including intra-cluster Cache consistency and inter-cluster Cache consistency.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or May be integrated into another system, or some features may be ignored, or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention can be integrated into one processing module, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration The unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

Those of ordinary skill in the art can understand that all or part of the steps for realizing the above-mentioned method embodiments can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the Including the steps of the foregoing method embodiments; and the foregoing storage medium includes: a removable storage device, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, etc. A medium on which program code can be stored.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (24)

1. A secondary independent high-speed register L2 Cache, it is characterized in that, Described L2 Cache comprises Slave interface, controller, Master interface and RAM; The Slave interface is used to receive a consistent access indication signal and access, the access includes consistent access and non-uniform access, and when the consistent access indication signal is received, it is determined that the access is a consistent access, and Classify the access according to the consistent access indication signal and the access, and form indication information according to the classification result; The controller is configured to receive the indication information, query operation data in the RAM according to the indication information, and perform a consistent operation according to the indication information after the operation data is queried in the RAM; The Master interface is used to output the consistent access indication signal and the consistent access to peripherals according to the indication information when the operation data is not queried in the RAM, and when the operation data is queried, Then output the operation data to the external memory according to the indication information. 2. The L2 Cache according to claim 1, characterized in that, The consistent access indication signal includes a consistent access type indication signal; The slave interface is configured to receive the consistent access type indication signal, and determine that the access is consistent access according to the consistent access type indication signal. 3. The L2 Cache according to claim 2, characterized in that, The consistent access indication signal also includes a consistent access global signal; The Slave interface includes a first read address channel, a first read data channel and a first write address channel; The Slave interface is used to receive the consistent access global signal, drive and form a Slave interface control signal according to the consistent access global signal, and drive each of the channels in the Slave interface to receive the received signal according to the Slave interface control signal. consistent access described above; The first read address channel is used to receive the consistent access type indication signal; The first read data channel is used to send a read response signal to the request source according to the query result; The first write address channel is used to receive an external memory update signal for consistent access. 4. The L2 Cache according to claim 3, characterized in that, The coherent access global signal includes the query status of the coherent access operation data in other caches and the coherent access request source. 5. The L2 Cache according to claim 1, characterized in that, The Master interface includes a second read address channel, a second read data channel and a second write address channel; The second read address channel is used to output the consistent access indication signal when the operation data is not queried in the RAM; The second read data channel is used to receive a read response signal and listen to a response signal; The second write address channel is used to output an indication signal for writing the operation data to the external memory and invalidating the operation data in the Cache. 6. The L2 Cache according to claim 1, characterized in that, The L2 Cache also includes: The first buffer is used to store the access type, the query status in other Cache, the query status in the L2Cache and the request source of the consistent access, and is used for querying the operation data and realizing Cache consistency Provide supporting information. 7. The L2 Cache according to claim 6, characterized in that, The first buffer is also used to store invalid failure information, and notify the request source according to the invalid failure information. 8. The L2 Cache according to claim 1, characterized in that, The RAM includes Data RAM and Tag RAM; the Data RAM is used to store operation data; the Data RAM includes several cache storage units; the Tag RAM is used to store the storage address of the operation data and the state information of the cache storage unit ; The controller is specifically configured to, according to the indication information, Read the Tag RAM and query and update the Tag RAM according to the result of the Tag RAM, or Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and updating the Tag RAM, or Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor, or reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and writing the operation data to the external memory, or Read Tag RAM, or Read the Tag RAM and query the Data RAM according to the result of the Tag RAM and write the query operation data to the external memory and update the Tag RAM; Wherein, updating the Tag RAM includes updating at least one of an operation address and the status information. 9. The L2 Cache according to claim 8, characterized in that, The controller is further specifically configured to, according to the indication information, When the Data RAM finds the operation data and the state of the operation data is dirty, output the operation data to the external memory through the Master interface. 10. The L2 Cache according to claim 8, characterized in that, The controller includes: The Tag Access fifo queue is used to store information about whether to update the Tag RAM and an instruction to access the Data RAM after the operation data is queried; The Tag Write fifo queue is used to store the operation information that needs to be updated in the Tag RAM when the operation data is queried and it is determined that the Tag RAM needs to be updated; Data read fifo queue, used for storing operation information that needs to update the Tag RAM and read the Data RAM after the operation data is queried; A control unit, configured to execute the consistency operation according to the Tag Access fifo queue, Tag Write fifo queue and Data readfifo queue. 11. The L2 Cache according to claim 1, characterized in that, The controller includes a control unit; The control unit is configured to perform access conflict detection, and when a conflict access is detected, a blocking mechanism is used to process the access conflict. 12. A data processing system, characterized in that, The system includes at least one cluster; The cluster includes at least two processors, an intra-cluster frame listener controller, and the L2Cache according to any one of claims 1 to 9; wherein, each of the processors is integrated with an L1 Cache; The intra-cluster frame monitoring controller is connected to the L1 Cache and the L2 Cache respectively, and is used to monitor consistent access and assist any two of the L1 Cache and between the L1 Cache and the L2 Cache Achieve Cache consistency. 13. The system of claim 12, wherein: The system also includes an inter-cluster frame listening controller; The inter-cluster frame monitoring controller is connected to the L2 Cache for monitoring consistent access, and assists in realizing Cache consistency between clusters. 14. The system of claim 13, wherein: The L1 Cache is specifically used to query the operation data corresponding to the consistency access in the L1 Cache when receiving the consistency access; when the L1 Cache queries the operation data, respond to the consistency access, and at the same time Realize the Cache consistency of the cluster where the L1 Cache is located with the assistance of the intra-cluster cache frame controller, and realize the inter-cluster Cache consistency with the assistance of the inter-cluster cache frame controller; The intra-cluster cache frame controller is configured to send the consistent access to the L2 Cache when the operation data is not found in the L1 Cache in the cluster; The L2 Cache is used to receive the consistent access and the consistent access sent by other clusters when the operation data corresponding to the consistent access is not queried in the L1 Cache of the cluster, and query whether the L2 Cache stores any For the operation data, when the L2 Cache does not query the operation data corresponding to the consistent access, query the operation data in a cluster other than the cluster where the L2 Cache is located through the inter-cluster cache frame controller data, responding to the consistent access after querying the operation data, and realizing inter-cluster Cache consistency with the assistance of the inter-cluster cache frame controller. 15. A method for implementing L2 Cache consistency, characterized in that said method comprises: receiving a consistent access indication signal and access, the access including consistent access and non-uniform access, and determining that the access is a consistent access when the consistent access indication signal is received; Classify the access according to the consistent access indication signal and the access, and form indication information according to the classification result; Querying the operation data according to the instruction information, and performing a consistent operation according to the instruction information after the operation data is queried; when the operation data is not queried, output the consistent access to the peripheral device according to the instruction information indication signal and said coherent access; When the access needs to output the operation data to the external memory, output the operation data to the external memory according to the indication information after the operation data is queried. 16. The method of claim 15, wherein, The consistent access indication signal includes a consistent access type indication signal; The receiving consistent access indication signal and access, determining that the access is consistent access when receiving the consistent access indication signal, includes: receiving the consistent access type indication signal, and determining that the access is a consistent access according to the consistent access type indication signal. 17. The method of claim 15, wherein, The L2 Cache includes a Slave interface; the Slave interface includes a first read address channel, a first read data channel and a first write address channel; The consistent access indication signal also includes a consistent access global signal; The receiving consistent access indication signal and access, determining that the access is consistent access when receiving the consistent access indication signal, includes: receiving the consistent access global signal, driving to form a slave interface control signal according to the consistent access global signal, and driving each of the channels in the slave interface to receive the consistent access according to the slave interface control signal; receiving a consistent access type indication signal through the first read address channel; The receiving consistent access indication signal and access, determining that the access is consistent access when receiving the consistent access indication signal, also includes at least one of the following: receiving the consistent access type indication signal through the first read address channel; sending a read response signal to the request source through the first read data channel according to the query result; An external memory update signal for consistent access is received through the first write address channel. 18. The method of claim 17, wherein, The coherent access global signal includes the query status of the coherent access operation data in other caches and the coherent access request source. 19. The method of claim 15, wherein, The L2 Cache includes a Master interface; the Master interface includes a second read address channel, a second read data channel, and a second write address channel; The step of outputting the consistent access indication signal and the consistent access to peripherals according to the indication information when the operation data is not inquired includes: Outputting the consistent access indication signal when the operation data is not queried in the RAM through the second read address channel; The method also includes: receiving a read response signal and a listen response signal through the second read data channel; Outputting an indication signal for writing the operation data to the external memory and invalidating the operation data in the Cache through the second write address channel. 20. The method of claim 15, wherein, After receiving the consistent access indication signal, the method further includes: Store access type, query status in other Cache, query status in L2 Cache and the request source of the consistent access, which is used to provide basis information for querying the operation data and realizing Cache consistency. 21. The method of claim 20, wherein, The method also includes: When the operation data is not found in the L2 Cache, the invalid failure information is formed and stored, and the request source is notified according to the invalid failure information. 22. The method of claim 15, wherein, Slave interface comprises controller; RAM comprises Data RAM and Tag RAM; Described Data RAM is used for storing operation data; Described Tag RAM is used for storing the storage address of described operation data and the state information of cache storage unit; The querying of the operation data according to the instruction information, and performing a consistent operation according to the instruction information after querying the operation data includes at least one of the following: Through the controller, read the Tag RAM according to the instruction information, and query and update the state information according to the result of the Tag RAM; Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and updating the state information; Read the Tag RAM and query the Data RAM according to the result of the Tag RAM and return the query operation data to the processor; Reading the Tag RAM and querying the Data RAM according to the result of the Tag RAM and returning the query operation data to the processor and writing the operation data to the external memory; Read Tag RAM; and Read the Tag RAM and query the Data RAM according to the result of the Tag RAM and write the query operation data to the external memory and update the state information. 23. The method of claim 22, wherein, When the access needs to output the operation data to the external memory, output the operation data to the external memory according to the instruction information after querying the operation data, including: According to the indication information, when the Data RAM finds the operation data and the state of the operation data is dirty, output the operation data to the external memory through the Master interface. 24. The method of claim 15, wherein, The method also includes: Access conflict detection is performed by the control unit, and when conflict access is detected, a blocking mechanism is used to process the access conflict.