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WO2016026177A1 - Tft基板的制作方法及其结构 - Google Patents

Tft基板的制作方法及其结构 Download PDF

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Publication number
WO2016026177A1
WO2016026177A1 PCT/CN2014/086258 CN2014086258W WO2016026177A1 WO 2016026177 A1 WO2016026177 A1 WO 2016026177A1 CN 2014086258 W CN2014086258 W CN 2014086258W WO 2016026177 A1 WO2016026177 A1 WO 2016026177A1
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layer
island
pixel electrode
shaped
oxide semiconductor
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French (fr)
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王俊
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/427,631 priority Critical patent/US9793298B2/en
Publication of WO2016026177A1 publication Critical patent/WO2016026177A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a structure thereof.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • OLED display-based OLED display technology Compared with mature LCD, OLED is an active light-emitting display with self-luminous, high contrast, wide viewing angle (up to 170°), fast response, high luminous efficiency, low operating voltage (3 ⁇ ) 10V), ultra-thin (thickness less than 2mm) and other advantages, with superior color display quality, wider viewing range and greater design flexibility.
  • TFTs Thin Film Transistors
  • LCDs LCDs, OLEDs, and electrophoretic display devices (EPDs).
  • EPDs electrophoretic display devices
  • Oxide semiconductor TFT technology is currently a popular technology. Since the carrier mobility of the oxide semiconductor is 20-30 times that of the amorphous silicon semiconductor, and having a high electron mobility, the charge and discharge rate of the TFT electrode can be greatly improved, the response speed of the pixel can be improved, and the pixel can be realized faster. The refresh rate and the ability to increase the line scan rate of pixels make it possible to produce ultra-high resolution flat panel display devices. Compared with low-temperature polysilicon (LTPS), oxide semiconductors are simple in process and highly compatible with amorphous silicon processes. They can be applied to LCD, OLED, flexible display, etc., and are compatible with high-generation production lines. Large, medium and small size display, with good application development prospects.
  • LTPS low-temperature polysilicon
  • the conventional TFT substrate structure generally includes a substrate, a gate, a gate insulating layer, an oxide semiconductor layer, an etch barrier layer, a source/drain, a pixel electrode layer, and the like.
  • each layer structure needs to be formed through a photolithography process, and each photolithography process includes film formation, yellow light, etching, stripping, etc., wherein the yellow light process includes Coating photoresist, exposure, development, and each ray process needs to make a reticle, resulting in longer process flow, more complicated production process, lower production efficiency; more reticle required, higher production cost
  • the more processes, the more prominent the cumulative yield problem the more processes, the more prominent the cumulative yield problem.
  • the object of the present invention is to provide a method for fabricating a TFT substrate, which can significantly reduce the process steps, simplify the process flow, shorten the process time, improve the production efficiency, reduce the number of masks, reduce the production cost, and improve the product yield.
  • Another object of the present invention is to provide a TFT substrate structure which has a short process flow, high production efficiency, and low production cost.
  • the present invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to form a gate;
  • Step 2 depositing a gate insulating layer on the gate and the substrate;
  • Step 3 sequentially depositing an oxide semiconductor layer and the first photoresist layer on the gate insulating layer;
  • Step 4 using the gate as a photomask, performing backside exposure on the first photoresist layer to form an island-shaped first photoresist layer directly above the gate;
  • Step 5 etching the oxide semiconductor layer according to the pattern of the island-shaped first photoresist layer, forming an island-shaped oxide semiconductor layer directly above the gate, and then removing the island-shaped first photoresist layer;
  • Step 6 Depositing and patterning an etch barrier layer on the island-shaped oxide semiconductor layer and the gate insulating layer to form an island-shaped etch barrier layer on the oxide semiconductor layer;
  • the island-shaped etch barrier layer has a width smaller than a width of the island-shaped oxide semiconductor layer; the island-shaped etch barrier layer covers an intermediate portion of the island-shaped oxide semiconductor layer to expose both sides of the island-shaped oxide semiconductor layer unit;
  • Step 7 depositing and patterning a second metal layer on the island-shaped etch barrier layer and the gate insulating layer to form a source/drain;
  • the source/drain are in contact with both side portions of the island-shaped oxide semiconductor layer to form an electrical connection
  • Step 8 sequentially deposit a protective layer and a second photoresist layer on the source/drain and island etching barrier layer, and perform gray scale exposure and development on the second photoresist layer, and correspondingly form a pixel electrode.
  • the position of the hole forms a full exposure area, and a gray scale exposure area is formed at a position corresponding to the pixel electrode to be formed;
  • Step 9 removing the protective layer under the full exposed area to form a pixel electrode via, and then performing ashing treatment on the second photoresist layer to remove the gray scale exposure area;
  • Step 10 depositing a pixel electrode layer on the remaining second photoresist layer and the protective layer;
  • Step 11 removing the remaining second photoresist layer and a portion of the pixel electrode layer deposited thereon to form a pixel electrode;
  • the pixel electrode fills the pixel electrode via and contacts the source/drain to form an electrical connection
  • step 12 the substrate of step 11 is annealed.
  • the patterning is achieved by a yellow light and etching process.
  • the island-shaped oxide semiconductor layer is an IGZO semiconductor layer.
  • the material of the protective layer is SiO 2 or SiON.
  • the protective layer under the fully exposed region is removed by dry etching to form a pixel electrode via; the second photoresist layer is ashed by dry etching to remove the gray Order exposure area.
  • the material of the pixel electrode is ITO or IZO.
  • the remaining second photoresist layer and a part of the pixel electrode layer deposited thereon are removed by a lift-off process by using a difference in thickness between the remaining second photoresist layer and the protective layer.
  • the substrate is a glass substrate.
  • the invention also provides a TFT substrate structure, comprising: a substrate, a gate on the substrate, a gate insulating layer on the gate and the substrate, and an island oxide on the gate insulating layer directly above the gate; a peninsula body layer, an island-shaped etch barrier layer on the island-shaped oxide semiconductor layer, a source/drain on the island-shaped etch barrier layer and the gate insulating layer, on the source/drain and the etch barrier layer a protective layer and a pixel electrode on the protective layer;
  • the island-shaped oxide peninsula layer includes an intermediate portion and two side portions; the width of the island-shaped etching barrier layer is smaller than a width of the island-shaped oxide semiconductor layer, Covering only the intermediate portion; the source/drain are in contact with the two side portions to form an electrical connection;
  • the protective layer has a pixel electrode via located on a side of the island-shaped oxide semiconductor layer, A pixel electrode fills the pixel electrode via to contact the source/drain to form an electrical connection.
  • the substrate is a glass substrate
  • the island-shaped oxide semiconductor layer is an IGZO semiconductor layer
  • the material of the protective layer is SiO 2 or SiON
  • the material of the pixel electrode is ITO or IZO.
  • the fabrication of the TFT substrate is completed by using only four masks, which can significantly reduce the process steps, simplify the process flow, shorten the processing time, improve the production efficiency, reduce the number of masks, and reduce the production cost. , to improve product yield, and because of the self-aligned process technology, the alignment accuracy is improved, and the aperture ratio and luminous efficiency of the display device can be improved.
  • the TFT substrate structure of the invention has a short process flow, high production efficiency and low production cost.
  • FIG. 1 is a flow chart of a method of fabricating a TFT substrate of the present invention
  • FIGS. 2 and 3 are schematic views of step 1 of a method for fabricating a TFT substrate according to the present invention
  • step 2 is a schematic view of step 2 of a method for fabricating a TFT substrate of the present invention
  • step 3 is a schematic view of step 3 of a method for fabricating a TFT substrate of the present invention.
  • FIG. 6 is a schematic view showing a step 4 of a method for fabricating a TFT substrate of the present invention
  • FIG. 7 is a schematic view showing a step 5 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a step 6 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 7 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a step 8 of a method for fabricating a TFT substrate of the present invention.
  • FIG. 11 is a schematic view showing a step 9 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 12 is a schematic view showing a step 10 of a method of fabricating a TFT substrate of the present invention
  • FIG. 13 is a schematic view showing the step 11 of the method for fabricating the TFT substrate of the present invention and a schematic view of the structure of the TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 please refer to FIG. 2 and FIG. 3, a substrate 1 is provided, a first metal layer 2 is deposited on the substrate 1, and the first metal layer 2 is patterned by a yellow light and an etching process using a common mask. Gate 21.
  • the substrate 2 is a transparent substrate.
  • the substrate 1 is a glass substrate.
  • Step 2 referring to FIG. 4, a gate insulating layer 3 is deposited on the gate 21 and the substrate 1.
  • the gate insulating layer 3 completely covers the substrate 1.
  • Step 3 Referring to FIG. 5, an oxide semiconductor layer 4 and a first photoresist layer 5 are sequentially deposited on the gate insulating layer 3.
  • the oxide semiconductor layer 4 is an indium gallium zinc oxide (IGZO) semiconductor layer.
  • IGZO indium gallium zinc oxide
  • Step 4 referring to FIG. 6, the gate electrode 21 is used as a photomask, and the first photoresist layer 5 is back-exposed to form an island-shaped first photoresist layer 51 directly above the gate electrode 21.
  • step 4 light is irradiated from the bottom surface of the substrate 1 toward the photoresist layer 5, Exposing the photoresist layer 5 with the gate electrode 21 as a mask saves a mask, simplifies the process flow, shortens the processing time, reduces the production cost, and realizes the gate 21 as a mask.
  • the alignment process can improve the alignment accuracy and improve the aperture ratio and luminous efficiency of the display device.
  • Step 5 referring to FIG. 7, the oxide semiconductor layer 4 is etched according to the pattern of the island-shaped first photoresist layer 51, and the island-shaped oxide semiconductor layer 41 located directly above the gate electrode 21 is formed, and then passed through a lift-off process.
  • the island-shaped first photoresist layer 51 is removed.
  • the oxide semiconductor layer 41 is an IGZO semiconductor layer.
  • Step 6 referring to FIG. 8, depositing on the island-shaped oxide semiconductor layer 41 and the gate insulating layer 3 and performing a yellow light and etching process patterning etching barrier layer using a common mask to form the oxide layer An island-shaped etch barrier layer 6 on the semiconductor layer 41.
  • the width of the island-shaped etch barrier layer 6 is smaller than the width of the island-shaped oxide semiconductor layer 41; the island-shaped etch barrier layer 6 covers the intermediate portion 411 of the island-shaped oxide semiconductor layer 41 to expose the island Both side portions 413 of the oxide semiconductor layer 41.
  • Step 7 referring to FIG. 9, depositing on the island etching barrier layer 6 and the gate insulating layer 3 and performing a yellow light and etching process to pattern the second metal layer using a common mask to form the source/drain electrodes 7 .
  • the source/drain electrodes 7 are in contact with both side portions 413 of the island-shaped oxide semiconductor layer 41 to form an electrical connection.
  • Step 8 referring to FIG. 10, a protective layer 8 and a second photoresist layer 9 are sequentially deposited on the source/drain 7 and the island-shaped etch barrier layer 6, and the second photoresist layer 9 is performed using a photomask.
  • the gray scale exposure and development forms a full exposure region 91 at a position corresponding to the pixel electrode via hole to be formed, and a gray scale exposure region 93 is formed at a position corresponding to the pixel electrode to be formed.
  • the material of the protective layer 8 is SiO 2 or SiON.
  • this step 8 by performing gray scale exposure on the second photoresist layer 9, the pixel electrode via of the protective layer and the pattern of the pixel electrode are defined, thereby saving the mask, simplifying the process flow, and shortening the process. Time increases production efficiency while reducing the number of masks and reducing production costs.
  • Step 9 referring to FIG. 11, the protective layer 8 under the fully exposed region 91 is removed by dry etching to form a pixel electrode via 81 to expose the surface of the source/drain 7;
  • the second photoresist layer 9 is subjected to ashing treatment by dry etching to remove the gray scale exposure region 93.
  • Step 10 Referring to Figure 12, the pixel electrode layer 10 is deposited on the remaining second photoresist layer 9' and the protective layer 8.
  • the material of the pixel electrode layer 10 is indium tin oxide (ITO) or indium tin oxide (IZO).
  • Step 11 please refer to FIG. 13, using the remaining second photoresist layer 9' and the protective layer 8.
  • the difference in thickness is obtained by removing the remaining second photoresist layer 9' and a portion of the pixel electrode layer 10 deposited thereon by a lift-off process to form a pixel electrode 10'.
  • the pixel electrode 10' fills the pixel electrode via 81 and is in contact with the source/drain 7 to form an electrical connection.
  • the material of the pixel electrode 10' is ITO or IZO.
  • Step 12 Annealing the substrate 1 of the step 11 to complete the fabrication of the TFT substrate.
  • the present invention further provides a TFT substrate structure including a substrate 1 , a gate 21 on the substrate 1 , and a gate on the gate 21 and the substrate 1 .
  • the pole insulating layer 3 the island-shaped oxide peninsula body layer 41 located on the gate insulating layer 3 directly above the gate electrode 21, the island-shaped etching barrier layer 6 on the island-shaped oxide semiconductor layer 41, and the island-shaped etching barrier.
  • the island-shaped oxide peninsula body layer 41 includes an intermediate portion 411 and two side portions 413; the island-shaped etching barrier layer 6 has a width smaller than a width of the island-shaped oxide semiconductor layer 41, and covers only the intermediate portion 411 .
  • the source/drain electrodes 7 are in contact with the two side portions 413 to form an electrical connection.
  • the protective layer 8 has a pixel electrode via 81 on a side of the island-shaped oxide semiconductor layer 41, and the pixel electrode 10' fills the pixel electrode via 81 to contact the source/drain 7 to form Electrical connection.
  • the substrate 1 is a glass substrate, the island-shaped oxide semiconductor layer 41 is an IGZO semiconductor layer, the material of the protective layer 8 is SiO 2 or SiON, and the material of the pixel electrode 10 ′ is ITO or IZO.
  • the first photoresist layer is back-exposed with the gate as a mask to form an island-shaped oxide semiconductor layer, and the second photoresist layer is subjected to gray scale exposure.
  • Forming the pixel electrode via and the pixel electrode, the TFT substrate is completed by using only four masks, which can significantly reduce the process steps, simplify the process flow, shorten the processing time, improve the production efficiency, reduce the number of masks, and reduce the production cost. Improve product yield, and because of the self-aligned process technology, the alignment accuracy is improved, and the aperture ratio and luminous efficiency of the display device can be improved.
  • the TFT substrate structure of the invention has a short process flow, high production efficiency and low production cost.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种TFT基板的制作方法及其结构。该方法包括如下步骤：1、在基板（1）上形成栅极（21）；2、沉积栅极绝缘层（3）；3、沉积氧化物半导体层（4）与第一光阻层（5）；4、以栅极（21）为光罩，对第一光阻层（5）进行背面曝光，形成岛状第一光阻层（51）；5、形成岛状氧化物半导体层（41），去除岛状第一光阻层（51）；6、形成岛状蚀刻阻挡层（6）；7、形成源/漏极（7）；8、沉积保护层（8）、第二光阻层（9），并对第二光阻层（9）进行灰阶曝光、显影；9、形成像素电极过孔（81），对第二光阻层（9）进行灰化处理；10、沉积像素电极层（10）；11、去除剩余的第二光阻层（9'），形成像素电极（10'）；12、退火处理。

Description

TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及其结构。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。
基于有机发光二极管的OLED显示技术同成熟的LCD相比，OLED是主动发光的显示器，具有自发光、高对比度、宽视角(达170°)、快速响应、高发光效率、低操作电压(3～10V)、超轻薄(厚度小于2mm)等优势，具有更优异的彩色显示画质、更宽广的观看范围和更大的设计灵活性。
薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED、电泳显示装置(EPD)上。
氧化物半导体TFT技术是当前的热门技术。由于氧化物半导体的载流子迁移率是非晶硅半导体的20-30倍，具有较高的电子迁移率，可以大大提高TFT对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，并能够提高像素的行扫描速率，使得制作超高分辨率的平板显示装置成为可能。相比低温多晶硅(LTPS)，氧化物半导体制程简单，与非晶硅制程相容性较高，可以应用于LCD、OLED、柔性显示(Flexible)等领域，且与高世代生产线兼容，可应用于大中小尺寸显示，具有良好的应用发展前景。
现有的TFT基板结构，一般包括基板、栅极、栅极绝缘层、氧化物半导体层、蚀刻阻挡层、源/漏极、像素电极层等。在其制作过程中，除基板外，每一层结构的形成均需要通过一道光刻制程，而每一道光刻制程包括成膜、黄光、蚀刻、剥离等制程工序，其中黄光制程又包括涂布光阻、曝光、显影，且每一道黄光制程需要制作一光罩，造成工序流程较长，制作工艺较复杂，生产效率较低；所需的光罩数量较多，生产成本较高；同时工序越多，累积的良率问题也越凸显。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，能显著的减少制程步骤，简化工艺流程，缩短制程时间，提高生产效率，同时减少光罩数量，降低生产成本，提升产品良率。
本发明的另一目的在于提供一种TFT基板结构，其工艺流程较短，生产效率较高，生产成本较低。
为实现上述目的，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积第一金属层，并图案化该第一金属层，形成栅极；
步骤2、在所述栅极与基板上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上依次沉积氧化物半导体层、与第一光阻层；
步骤4、以所述栅极作为光罩，对所述第一光阻层进行背面曝光，形成位于所述栅极正上方的岛状第一光阻层；
步骤5、根据岛状第一光阻层的图案蚀刻所述氧化物半导体层，形成位于所述栅极正上方的岛状氧化物半导体层，再去除所述岛状第一光阻层；
步骤6、在所述岛状氧化物半导体层与栅极绝缘层上沉积并图案化蚀刻阻挡层，形成位于所述氧化物半导体层上的岛状蚀刻阻挡层；
所述岛状蚀刻阻挡层的宽度小于所述岛状氧化物半导体层的宽度；所述岛状蚀刻阻挡层覆盖岛状氧化物半导体层的中间部而暴露出岛状氧化物半导体层的两侧部；
步骤7、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积并图案化第二金属层，形成源/漏极；
所述源/漏极与所述岛状氧化物半导体层的两侧部接触，形成电性连接；
步骤8、在所述源/漏极与岛状蚀刻阻挡层上依次沉积保护层、第二光阻层，并对该第二光阻层进行灰阶曝光、显影，在对应欲形成像素电极过孔的位置形成全曝光区域，在对应欲形成像素电极的位置形成灰阶曝光区域；
步骤9、去除位于所述全曝光区域下方的保护层，形成像素电极过孔，再对所述第二光阻层进行灰化处理，去除所述灰阶曝光区域；
步骤10、在剩余的第二光阻层与保护层上沉积像素电极层；
步骤11、去除所述剩余的第二光阻层及沉积于其上的部分像素电极层，形成像素电极；
所述像素电极填充所述像素电极过孔，与所述源/漏极接触，形成电性 连接；
步骤12、对步骤11的基板进行退火处理。
所述图案化通过黄光与蚀刻制程实现。
所述岛状氧化物半导体层为IGZO半导体层。
所述保护层的材料为SiO2或SiON。
所述步骤9中，通过干法蚀刻去除位于所述全曝光区域下方的保护层，形成像素电极过孔；再通过干法蚀刻对所述第二光阻层进行灰化处理，去除所述灰阶曝光区域。
所述像素电极的材料为ITO或IZO。
所述步骤11中，利用所述剩余的第二光阻层与保护层之间的厚度差，通过剥离工艺去除所述剩余的第二光阻层及沉积于其上的部分像素电极层。
所述基板为玻璃基板。
本发明还提供一种TFT基板结构，包括：一基板、位于基板上的栅极、位于栅极与基板上的栅极绝缘层、于栅极正上方位于栅极绝缘层上的岛状氧化物半岛体层、位于岛状氧化物半导体层上的岛状蚀刻阻挡层、位于岛状蚀刻阻挡层与栅极绝缘层上的源/漏极，位于所述源/漏极与蚀刻阻挡层上的保护层、及位于保护层上的像素电极；所述岛状氧化物半岛体层包括中间部与两侧部；所述岛状蚀刻阻挡层的宽度小于所述岛状氧化物半导体层的宽度，仅覆盖所述中间部；所述源/漏极与所述两侧部接触，形成电性连接；所述保护层具有位于所述岛状氧化物半导体层一侧的像素电极过孔，所述像素电极填充所述像素电极过孔与所述源/漏极接触，形成电性连接。
所述基板为玻璃基板，所述岛状氧化物半导体层为IGZO半导体层，所述保护层的材料为SiO2或SiON，所述像素电极的材料为ITO或IZO。
本发明的有益效果：本发明的TFT基板的制作方法，通过以栅极作为光罩对第一光阻层进行背面曝光以形成岛状氧化物半导体层，对第二光阻层进行灰阶曝光以形成像素电极过孔与像素电极，仅使用四道光罩即完成TFT基板的制作，能显著的减少制程步骤，简化工艺流程，缩短制程时间，提高生产效率，同时减少光罩数量，降低生产成本，提升产品良率，且由于采用自对位的制程工艺，提高了对位精度，还能提高显示装置的开口率与发光效率。本发明的TFT基板结构，工艺流程较短，生产效率较高，生产成本较低。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明TFT基板的制作方法的流程图；
图2、图3为本发明TFT基板的制作方法的步骤1的示意图；
图4为本发明TFT基板的制作方法的步骤2的示意图；
图5为本发明TFT基板的制作方法的步骤3的示意图；
图6为本发明TFT基板的制作方法的步骤4的示意图；
图7为本发明TFT基板的制作方法的步骤5的示意图；
图8为本发明TFT基板的制作方法的步骤6的示意图；
图9为本发明TFT基板的制作方法的步骤7的示意图；
图10为本发明TFT基板的制作方法的步骤8的示意图；
图11为本发明TFT基板的制作方法的步骤9的示意图；
图12为本发明TFT基板的制作方法的步骤10的示意图；
图13为本发明TFT基板的制作方法的步骤11的示意图暨本发明TFT基板结构的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其技术效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、请参阅图2、图3，提供一基板1，在该基板1上沉积第一金属层2，并使用一道普通光罩进行黄光与蚀刻制程图案化该第一金属层2，形成栅极21。
所述基板2为透明基板，优选的，所述基板1为玻璃基板。
步骤2、请参阅图4，在所述栅极21与基板1上沉积栅极绝缘层3。
该栅极绝缘层3完全覆盖所述基板1。
步骤3、请参阅图5，在所述栅极绝缘层3上依次沉积氧化物半导体层4、与第一光阻层5。
所述氧化物半导体层4为铟镓锌氧化物(IGZO)半导体层。
步骤4、请参阅图6，以所述栅极21作为光罩，对所述第一光阻层5进行背面曝光，形成位于所述栅极21正上方的岛状第一光阻层51。
在该步骤4中，光线由所述基板1的底面朝向所述光阻层5进行照射， 以所述栅极21作为光罩对光阻层5进行曝光，节省了一道光罩，简化了工艺流程，缩短了制程时间，降低了生产成本，同时将栅极21作为光罩，实现了自对位制程，能够提高对位精度，提高显示装置的开口率与发光效率。
步骤5、请参阅图7，根据岛状第一光阻层51的图案蚀刻所述氧化物半导体层4，形成位于所述栅极21正上方的岛状氧化物半导体层41，再通过剥离工艺去除所述岛状第一光阻层51。
所述氧化物半导体层41为IGZO半导体层。
步骤6、请参阅图8，在所述岛状氧化物半导体层41与栅极绝缘层3上沉积并使用一道普通光罩进行黄光与蚀刻制程图案化蚀刻阻挡层，形成位于所述氧化物半导体层41上的岛状蚀刻阻挡层6。
进一步的，所述岛状蚀刻阻挡层6的宽度小于所述岛状氧化物半导体层41的宽度；所述岛状蚀刻阻挡层6覆盖岛状氧化物半导体层41的中间部411而暴露出岛状氧化物半导体层41的两侧部413。
步骤7、请参阅图9，在所述岛状蚀刻阻挡层6与栅极绝缘层3上沉积并使用一道普通光罩进行黄光与蚀刻制程图案化第二金属层，形成源/漏极7。
所述源/漏极7与所述岛状氧化物半导体层41的两侧部413接触，形成电性连接。
步骤8、请参阅图10，在所述源/漏极7与岛状蚀刻阻挡层6上依次沉积保护层8、第二光阻层9，并使用光罩对该第二光阻层9进行灰阶曝光、显影，在对应欲形成像素电极过孔的位置形成全曝光区域91，在对应欲形成像素电极的位置形成灰阶曝光区域93。
所述保护层8材料为SiO2或SiON。
在该步骤8中，通过对第二光阻层9进行灰阶曝光，同时定义出了保护层的像素电极过孔、及像素电极的图案，节省了光罩，简化了工艺流程，缩短了制程时间，提高了生产效率，同时减少光罩数量，降低了生产成本。
步骤9、请参阅图11，通过干法蚀刻去除位于所述全曝光区域91下方的保护层8，形成像素电极过孔81，以暴露出所述源/漏极7的表面；再通入氧气，通过干法蚀刻对所述第二光阻层9进行灰化处理，去除所述灰阶曝光区域93。
步骤10、请参阅图12，在剩余的第二光阻层9’与保护层8上沉积像素电极层10。
所述像素电极层10的材料为氧化铟锡(ITO)或氧化铟锡(IZO)。
步骤11、请参阅图13，利用所述剩余的第二光阻层9’与保护层8之间 的厚度差，通过剥离工艺去除所述剩余的第二光阻层9’及沉积于其上的部分像素电极层10，形成像素电极10’。
进一步的，所述像素电极10’填充所述像素电极过孔81，与所述源/漏极7接触，形成电性连接。
所述像素电极10’的材料为ITO或IZO。
步骤12、对步骤11的基板1进行退火处理，完成TFT基板的制作。
请参阅图13，在上述TFT基板的制作方法的基础上，本发明还提供一种TFT基板结构，包括一基板1、位于基板1上的栅极21、位于栅极21与基板1上的栅极绝缘层3、于栅极21正上方位于栅极绝缘层3上的岛状氧化物半岛体层41、位于岛状氧化物半导体层41上的岛状蚀刻阻挡层6、位于岛状蚀刻阻挡层6与栅极绝缘层3上的源/漏极7，位于所述源/漏极7与蚀刻阻挡层6上的保护层8、及位于保护层8上的像素电极10’。
所述岛状氧化物半岛体层41包括中间部411与两侧部413；所述岛状蚀刻阻挡层6的宽度小于所述岛状氧化物半导体层41的宽度，仅覆盖所述中间部411。所述源/漏极7与所述两侧部413接触，形成电性连接。所述保护层8具有位于所述岛状氧化物半导体层41一侧的像素电极过孔81，所述像素电极10’填充所述像素电极过孔81与所述源/漏极7接触，形成电性连接。
所述基板1为玻璃基板，所述岛状氧化物半导体层41为IGZO半导体层，所述保护层8的材料为SiO2或SiON，所述像素电极10’的材料为ITO或IZO。
综上所述，本发明的TFT基板的制作方法，通过以栅极作为光罩对第一光阻层进行背面曝光以形成岛状氧化物半导体层，对第二光阻层进行灰阶曝光以形成像素电极过孔与像素电极，仅使用四道光罩即完成TFT基板的制作，能显著的减少制程步骤，简化工艺流程，缩短制程时间，提高生产效率，同时减少光罩数量，降低生产成本，提升产品良率，且由于采用自对位的制程工艺，提高了对位精度，还能提高显示装置的开口率与发光效率。本发明的TFT基板结构，工艺流程较短，生产效率较高，生产成本较低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积第一金属层，并图案化该第一金属层，形成栅极；
    步骤2、在所述栅极与基板上沉积栅极绝缘层；
    步骤3、在所述栅极绝缘层上依次沉积氧化物半导体层、与第一光阻层；
    步骤4、以所述栅极作为光罩，对所述第一光阻层进行背面曝光，形成位于所述栅极正上方的岛状第一光阻层；
    步骤5、根据岛状第一光阻层的图案蚀刻所述氧化物半导体层，形成位于所述栅极正上方的岛状氧化物半导体层，再去除所述岛状第一光阻层；
    步骤6、在所述岛状氧化物半导体层与栅极绝缘层上沉积并图案化蚀刻阻挡层，形成位于所述氧化物半导体层上的岛状蚀刻阻挡层；
    所述岛状蚀刻阻挡层的宽度小于所述岛状氧化物半导体层的宽度；所述岛状蚀刻阻挡层覆盖岛状氧化物半导体层的中间部而暴露出岛状氧化物半导体层的两侧部；
    步骤7、在所述岛状蚀刻阻挡层与栅极绝缘层上沉积并图案化第二金属层，形成源/漏极；
    所述源/漏极与所述岛状氧化物半导体层的两侧部接触，形成电性连接；
    步骤8、在所述源/漏极与岛状蚀刻阻挡层上依次沉积保护层、第二光阻层，并对该第二光阻层进行灰阶曝光、显影，在对应欲形成像素电极过孔的位置形成全曝光区域，在对应欲形成像素电极的位置形成灰阶曝光区域；
    步骤9、去除位于所述全曝光区域下方的保护层，形成像素电极过孔，再对所述第二光阻层进行灰化处理，去除所述灰阶曝光区域；
    步骤10、在剩余的第二光阻层与保护层上沉积像素电极层；
    步骤11、去除所述剩余的第二光阻层及沉积于其上的部分像素电极层，形成像素电极；
    所述像素电极填充所述像素电极过孔，与所述源/漏极接触，形成电性连接；
    步骤12、对步骤11的基板进行退火处理。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述图案化通过黄光与蚀刻制程实现。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述岛状氧化物半导体层为IGZO半导体层。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述保护层的材料为SiO2或SiON。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤9中，通过干法蚀刻去除位于所述全曝光区域下方的保护层，形成像素电极过孔；再通过干法蚀刻对所述第二光阻层进行灰化处理，去除所述灰阶曝光区域。
  6. 如权利要求1所述的TFT基板的制作方法，其特征在于，所述像素电极的材料为ITO或IZO。
  7. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤11中，利用所述剩余的第二光阻层与保护层之间的厚度差，通过剥离工艺去除所述剩余的第二光阻层及沉积于其上的部分像素电极层。
  8. 如权利要求1所述的TFT基板的制作方法，其中，所述基板为玻璃基板。
  9. 一种TFT基板结构，包括一基板、位于基板上的栅极、位于栅极与基板上的栅极绝缘层、于栅极正上方位于栅极绝缘层上的岛状氧化物半岛体层、位于岛状氧化物半导体层上的岛状蚀刻阻挡层、位于岛状蚀刻阻挡层与栅极绝缘层上的源/漏极，位于所述源/漏极与蚀刻阻挡层上的保护层、及位于保护层上的像素电极；所述岛状氧化物半岛体层包括中间部与两侧部；所述岛状蚀刻阻挡层的宽度小于所述岛状氧化物半导体层的宽度，仅覆盖所述中间部；所述源/漏极与所述两侧部接触，形成电性连接；所述保护层具有位于所述岛状氧化物半导体层一侧的像素电极过孔，所述像素电极填充所述像素电极过孔与所述源/漏极接触，形成电性连接。
  10. 如权利要求9所述的TFT基板结构，其中，所述基板为玻璃基板，所述岛状氧化物半导体层为IGZO半导体层，所述保护层的材料为SiO2或SiON，所述像素电极的材料为ITO或IZO。
  11. 一种TFT基板结构，包括一基板、位于基板上的栅极、位于栅极与基板上的栅极绝缘层、于栅极正上方位于栅极绝缘层上的岛状氧化物半岛体层、位于岛状氧化物半导体层上的岛状蚀刻阻挡层、位于岛状蚀刻阻挡层与栅极绝缘层上的源/漏极，位于所述源/漏极与蚀刻阻挡层上的保护层、及位于保护层上的像素电极；所述岛状氧化物半岛体层包括中间部与两侧部；所述岛状蚀刻阻挡层的宽度小于所述岛状氧化物半导体层的宽度，仅覆盖所述中间部；所述源/漏极与所述两侧部接触，形成电性连接；所述保护层具有位于所述岛状氧化物半导体层一侧的像素电极过孔，所述像素 电极填充所述像素电极过孔与所述源/漏极接触，形成电性连接；
    其中，所述基板为玻璃基板，所述岛状氧化物半导体层为IGZO半导体层，所述保护层的材料为SiO2或SiON，所述像素电极的材料为ITO或IZO。
PCT/CN2014/086258 2014-08-20 2014-09-11 Tft基板的制作方法及其结构 Ceased WO2016026177A1 (zh)

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