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WO2016006510A1 - Condensateur à empilement de céramique semi-conductrice doté d'une fonction de varistance - Google Patents

Condensateur à empilement de céramique semi-conductrice doté d'une fonction de varistance Download PDF

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Publication number
WO2016006510A1
WO2016006510A1 PCT/JP2015/068974 JP2015068974W WO2016006510A1 WO 2016006510 A1 WO2016006510 A1 WO 2016006510A1 JP 2015068974 W JP2015068974 W JP 2015068974W WO 2016006510 A1 WO2016006510 A1 WO 2016006510A1
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semiconductor ceramic
internal electrode
ceramic capacitor
mol
capacitor
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Japanese (ja)
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光俊 川本
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

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  • the present invention relates to a multilayer semiconductor ceramic capacitor having a varistor function, and more particularly to a multilayer semiconductor ceramic capacitor having a varistor function using an SrTiO 3 -based grain boundary insulating semiconductor ceramic.
  • semiconductor elements such as various ICs and LSIs are increasingly used in order to realize downsizing and multi-functionalization of electronic devices, and accordingly, noise resistance of electronic devices is decreasing.
  • a film capacitor, a multilayer ceramic capacitor, a multilayer semiconductor ceramic capacitor, and the like are arranged as a bypass capacitor in the power line of the semiconductor element, thereby ensuring noise resistance of electronic equipment.
  • a Zener diode 105 is connected in parallel to a capacitor 104 connected to a power supply line 103 that connects an external terminal 101 and a semiconductor element (IC) 102.
  • ESD countermeasures are taken by connecting a varistor 106 in parallel to the capacitor 104.
  • SrTiO 3 -based grain boundary insulation type multilayer semiconductor ceramic capacitors are known to have varistor characteristics, and a large current flows when a voltage exceeding a certain voltage is applied. Is also attracting attention.
  • this type of multilayer semiconductor ceramic capacitor has resistance to ESD and can also protect the semiconductor element 102, as shown in FIG. 5, instead of the Zener diode 105 and the varistor 106 of FIG. It can be covered with only one multilayer semiconductor ceramic capacitor 107. As a result, the number of parts and the cost can be reduced, the design can be easily standardized, and a capacitor having added value can be provided.
  • the laminated body which is formed along the interface between the several semiconductor ceramic layer laminated
  • the semiconductor ceramic layer has a specific surface area of 4.0 m 2 / g or more.
  • SrTiO 3 -based grain boundary insulation type semiconductor ceramic capacitors formed by sintering ceramic powders having a 90% cumulative particle size D90 of 1.2 ⁇ m or less and no greater than 0 m 2 / g have been proposed.
  • Patent Document 1 has a problem that even if the initial insulating property is good, when ESD repeatedly occurs, the insulating property may be remarkably deteriorated and the reliability is lacking.
  • the inventor has investigated the cause, and it has been found that when the distance between the end face and side face of the semiconductor ceramic layer and the end face and side face of the internal electrode layer becomes extremely narrow, the ESD resistance is lowered.
  • this type of multilayer semiconductor ceramic capacitor is usually manufactured as follows by a so-called multi-cavity method.
  • a conductive film having a predetermined pattern and a ceramic green sheet are alternately laminated on a large ceramic green sheet to prepare a large laminate, and then the large film is formed so that one end of the conductive film has a lead portion.
  • the laminate is cut into a predetermined size and separated into individual pieces to produce a green laminate.
  • the green laminate is subjected to primary firing and secondary firing to produce a component body in which a semiconductor ceramic layer and an internal electrode layer having one end having an extraction portion are alternately laminated, and then the component body External electrodes are formed at both ends.
  • the multilayer semiconductor ceramic capacitor is manufactured by a multi-cavity method, when obtaining a green multilayer body by dividing a large-sized multilayer body into individual pieces, the end surfaces and side surfaces of the semiconductor ceramic layer and the internal electrode layers are formed. A dimensional error may occur in the distance between the end face and the side face, and the distance may be extremely narrow.
  • the present invention has been made in view of such circumstances, and is a multilayer semiconductor ceramic capacitor with a varistor function that can suppress a decrease in insulation even when repeated ESD occurs and can secure desired electrical characteristics.
  • the purpose is to provide.
  • the present inventor conducted earnest research to achieve the above object, and as a result, the distance between the end surface of the internal electrode layer opposite to the lead portion and the end surface of the component body (hereinafter, this distance is referred to as “end surface distance”).
  • layer thickness the thickness of the semiconductor ceramic layer
  • multilayer semiconductor ceramic capacitor with a varistor function according to the present invention
  • multilayer semiconductor ceramic capacitor is an SrTiO 3 -based grain boundary insulation.
  • the internal electrode layer has a lead-out portion that is led out to one of the one end face and the other end face of the component element body, and An interval (end surface interval) a between an end surface opposite to the lead portion and an end surface of the component element body, an interval (side interval) b between the internal electrode layer and the side surface of the component element body,
  • the thickness (layer thickness) t of the semiconductor ceramic layer is characterized in that the relations 2 ⁇ a / t ⁇ 10 and 2 ⁇ b
  • the semiconductor ceramic has a compounding molar ratio m of Sr sites to Ti sites of 0.990 ⁇ m ⁇ 1.010, and the donor element is dissolved in the crystal particles.
  • the acceptor element is preferably present in the grain boundary layer in a range of 0.7 mol or less (excluding 0 mol) with respect to 100 mol of the Ti element.
  • the acceptor element is at least one element of Mn, Co, Ni, and Cr.
  • the donor element is at least one element selected from La, Nd, Sm, Dy, Nb, and Ta.
  • the low melting point oxide is contained in a range of 0.1 mol or less with respect to 100 mol of the Ti element.
  • the low melting point oxide is SiO 2 .
  • the internal electrode has Ni as a main component.
  • the multilayer semiconductor ceramic capacitor a component element body in which a plurality of semiconductor ceramic layers and a plurality of internal electrode layers formed with SrTiO 3 -based grain boundary insulation type semiconductor ceramics are alternately laminated, and the component element In a multilayer semiconductor ceramic capacitor having a pair of external electrodes electrically connected to the internal electrode layer at both ends of the body, the internal electrode layer is one of the one end surface and the other end surface of the component body. And a relationship of 2 ⁇ a / t ⁇ 10 and 2 ⁇ b / t ⁇ 5 between the end surface interval a, the side surface interval b, and the layer thickness t.
  • the functions of the capacitor and the Zener diode can be realized by a single multilayer semiconductor ceramic capacitor, the number of parts can be reduced, the cost can be reduced, the design can be easily standardized, and the ESD resistance can be improved. It is possible to realize a laminated semiconductor ceramic capacitor having good added value with excellent reliability.
  • FIG. 1 is a perspective view schematically showing an embodiment of a multilayer semiconductor ceramic capacitor according to the present invention.
  • FIG. 2 is a cross-sectional view taken along line AA in FIG. 1.
  • FIG. 3 is a cross-sectional view taken along the line BB in FIG. It is an electric circuit diagram when a Zener diode or a varistor is connected in parallel to a bypass capacitor arranged on a power supply line.
  • FIG. 5 is an electric circuit diagram when a multilayer semiconductor ceramic capacitor having a varistor function is connected to a power supply line.
  • FIG. 1 is a perspective view schematically showing an embodiment of a multilayer semiconductor ceramic capacitor according to the present invention
  • FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1, and FIG. It is arrow sectional drawing.
  • the multilayer semiconductor ceramic capacitor includes a component body 1 and external electrodes 2a and 2b formed at both ends of the component body 1.
  • Component body 1 length L, a width W, has a rectangular shape having a thickness T, a plurality of semiconductor ceramic layers made of a semiconductor ceramic 3 -based grain boundary insulation type SrTiO 3 and a plurality of internal electrode layers 4 ( 4a and 4b) are alternately laminated and sintered.
  • the internal electrode layer 4 a has a lead portion 7 drawn to one end face 5 of the component element body 1, and the lead portion 7 is electrically connected to the external electrode 2 a.
  • the internal electrode layer 4b has a lead portion 8 drawn to the other end face 6 of the component element body 1, and the lead portion 8 is electrically connected to the external electrode 2b.
  • the main component of the semiconductor ceramic layer 3 is an SrTiO 3 -based material, the donor element is dissolved in the crystal grains, and the acceptor element is present in the grain boundary layer. That is, microscopically, the semiconductor ceramic layer 3 is composed of a plurality of crystal grains made of semiconductor ceramic and a grain boundary layer formed around the crystal grains (not shown). Capacitance is formed via A desired capacitance is obtained as a whole by connecting in series or in parallel between the opposing surfaces of the internal electrode layers 4 facing each other through the semiconductor ceramic layer 3.
  • the internal electrode material used for the internal electrode layer 4 is not particularly limited, but a base metal material mainly composed of Ni having good conductivity at a low cost is preferably used.
  • the external electrode material used for the external electrodes 2a and 2b is not particularly limited, and Ni, Cr, Cu, Ga, In, and alloys containing them can be used.
  • the external electrodes 2a and 2b can be formed into a single layer structure or a multilayer structure using these external electrode materials, and it is also preferable to form an Ag layer on them, and further to form an underlying electrode.
  • a plating film made of Ni, Sn, or the like may be formed as the external electrodes 2a and 2b.
  • the multilayer semiconductor ceramic capacitor has an end face interval a (the distance between the end face 9 on the opposite side of the lead portion 7 and the end face 6 of the component body 1, the end face 10 on the opposite side of the lead portion 8 and the part body 1.
  • the relationship of mathematical formulas (1) and (2) is established.
  • the end face spacing a, the side face spacing b, and the layer thickness t satisfy the formulas (1) and (2), so that insulation can be secured even if ESD repeatedly occurs.
  • a multilayer semiconductor ceramic capacitor excellent in durability and reliability can be obtained.
  • a multilayer semiconductor ceramic capacitor is usually manufactured by a so-called multi-cavity method. That is, a conductive film having a predetermined pattern is formed on a large-sized ceramic green sheet, and a large-sized laminate is manufactured by stacking the ceramic green sheets on which the conductive film is formed. After the large-sized laminate is cut into pieces so as to have dimensions, firing processing (primary firing and secondary firing) is performed.
  • the ratio a / t between the end face spacing a and the layer thickness t exceeds 10
  • the end face spacing a becomes too large, and the facing area between the internal electrode 4a and the internal electrode 4b is reduced, resulting in the capacitance. If it is attempted to secure a desired capacitance, it may lead to an increase in size of the component.
  • the ratio a / t between the end face spacing a and the layer thickness t is set to 2 to 10.
  • Ratio b / t between side face distance b and layer thickness t The ratio b / t between the side face distance b and the layer thickness t is also important for obtaining good ESD resistance.
  • the ratio b / t is less than 2
  • the side face distance b is excessively smaller than the layer thickness t, and therefore, the current to be discharged between the internal electrode layers 4a and 4b is similar to the above.
  • the ratio a / t between the side surface distance b and the layer thickness t is set to 2 to 5.
  • the end face distance a, the side face distance b, and the layer thickness t satisfy Formulas (1) and (2).
  • b does not cause a discharge, and can be discharged between the internal electrode 4a and the internal electrode 4b. This makes it possible to suppress a decrease in insulation, and has excellent durability with desired electrical characteristics.
  • a laminated semiconductor ceramic capacitor can be obtained.
  • an insulation resistance IR of 1.0 ⁇ 10 8 ⁇ or more can be secured even if a voltage of 30 kV is repeatedly applied 1000 times in the forward and reverse directions, and a decrease in insulation can be suppressed. It becomes possible.
  • the functions of the capacitor and the Zener diode can be realized by a single multilayer semiconductor ceramic capacitor, the number of parts can be reduced, the cost can be reduced, the design can be easily standardized, and the ESD resistance can be improved. It is possible to realize a laminated semiconductor ceramic capacitor having good added value with excellent reliability.
  • the blending molar ratio m between the Sr site and the Ti site is 0.990 ⁇ m ⁇ 1.010.
  • the blending molar ratio m exceeds 1.010, the precipitation of Sr not dissolved in the crystal particles to the crystal grain boundary increases, the thickness of the grain boundary insulating layer becomes excessively thick, and the capacitance is increased. There is a risk of excessive degradation.
  • the blending molar ratio m is less than 0.990, the molar content of Ti becomes excessive, and the crystal grains tend to be coarsened, which may cause a decrease in insulation.
  • the blending molar ratio m is 0.990 ⁇ m ⁇ 1.010.
  • the donor element is solid-solved in the crystal particles in order to convert the ceramic into a semiconductor by performing a firing process in a reducing atmosphere, but the content thereof is not particularly limited.
  • the donor element is less than 0.2 mol with respect to 100 mol of Ti element, there is a risk of causing an excessive decrease in capacitance.
  • the donor element exceeds 1.2 mol with respect to 100 mol of Ti element, the allowable temperature range of the firing temperature may be narrowed.
  • the molar amount of the donor element is 0.2 to 1.2 mol, preferably 0.4 to 1.0 mol, per 100 mol of Ti element.
  • donor element it is not specifically limited, For example, La, Nd, Sm, Dy, Nb, Ta etc. can be used, for example.
  • the acceptor element is present in the grain boundary insulating layer as described above.
  • the grain boundary insulating layer is an stacked layer type that has an electrically active energy level (grain boundary level) to promote the formation of a Schottky barrier, thereby improving insulation resistance and good insulation.
  • a semiconductor ceramic capacitor can be obtained.
  • the molar amount of the acceptor element exceeds 0.7 mol with respect to 100 mol of Ti element, the ESD withstand voltage is lowered, which is not preferable.
  • the molar content of the acceptor element is 0.7 mol or less (excluding 0 mol) with respect to 100 mol of Ti element, preferably 0.3 to 0.5 mol.
  • Mn Mn, Co, Ni, Cr etc.
  • Mn Mn, Co, Ni, Cr etc.
  • a low melting point oxide in the semiconductor ceramic layer 3 in a range of 0.1 mol or less with respect to 100 moles of Ti element.
  • the crystallinity of the acceptor element can be promoted and the segregation of the acceptor element can be promoted.
  • the content of the low melting point oxide is within the above range because when the content exceeds 0.1 mol with respect to 100 mol of Ti element, the electrostatic capacity is excessively lowered, and the desired electrical properties are reduced. This is because characteristics may not be obtained.
  • the low-melting-point oxide is not particularly limited, SiO 2, B and alkali metal element (K, Li, Na, etc.) glass ceramic containing copper - may be used tungsten salt However, SiO 2 is preferably used.
  • an Sr compound such as SrCO 3 as a ceramic raw material, a donor compound containing a donor element such as La or Sm, and TiO having a specific surface area of 10 m 2 / g or more (average particle size: about 0.1 ⁇ m or less), for example.
  • a fine Ti compound such as 2 and weigh a predetermined amount.
  • a dispersant is added to 100 parts by weight of the weighed product, and the mixture is put into a ball mill together with a grinding medium such as PSZ (Partially Stabilized Zirconia) balls and pure water. Then, the slurry is sufficiently wet-mixed in the ball mill.
  • a grinding medium such as PSZ (Partially Stabilized Zirconia) balls and pure water.
  • this slurry is evaporated to dryness, and then calcined at a predetermined temperature (eg, 1350 ° C. to 1450 ° C.) for about 2 hours in an air atmosphere to produce a calcined powder in which the donor element is dissolved. .
  • a predetermined temperature eg, 1350 ° C. to 1450 ° C.
  • an acceptor compound containing an acceptor element such as Mn or Co is weighed, and a predetermined amount of a low melting point oxide such as SiO 2 is weighed if necessary.
  • the acceptor compound and the low melting point oxide are mixed with the calcined powder, and further, a predetermined amount of a dispersant and pure water are added, and the mixture is again put into the ball mill together with the grinding medium. Mix to obtain a mixture.
  • the dispersant is added to avoid agglomeration of crystal particles in the mixture, and the type of the dispersant is not particularly limited, but usually organic such as ammonium polycarboxylate.
  • a system dispersant can be preferably used.
  • the mixture is evaporated and dried, and then heat-treated at a predetermined temperature (for example, 500 to 700 ° C.) for about 5 hours in an air atmosphere to produce heat-treated powder.
  • a predetermined temperature for example, 500 to 700 ° C.
  • an organic solvent such as toluene and alcohol, an organic binder, a plasticizer, a surfactant, and the like are appropriately added to the heat-treated powder, and mixed sufficiently wet, thereby obtaining a ceramic slurry.
  • the ceramic slurry is formed using a forming method such as a doctor blade method, a lip coater method, or a die coater method to produce a large ceramic green sheet.
  • a forming method such as a doctor blade method, a lip coater method, or a die coater method to produce a large ceramic green sheet.
  • the ceramic paste is subjected to transfer using a screen printing method, a gravure printing method, a vacuum deposition method, a sputtering method or the like on a ceramic green sheet using a conductive paste for internal electrodes mainly composed of Ni or the like, and the ceramic A conductive film having a predetermined pattern is formed on the surface of the green sheet.
  • a plurality of ceramic green sheets having conductive films formed thereon are laminated in a predetermined direction, and a ceramic green sheet for exterior use without a conductive film is laminated and subjected to thermocompression bonding, and then end face spacing a and side spacing b After the firing, the layer thickness t is cut into a predetermined size so as to satisfy the above (1) and (2), so that a green laminate is produced.
  • the body is made into a semiconductor to produce a laminated sintered body.
  • the firing temperature (1200 to 1250 ° C.) in the primary firing treatment lower than the calcining temperature (1350 to 1450 ° C.) in the calcining treatment, grain growth of crystal grains is promoted in the primary firing treatment. It is possible to suppress the coarsening of the crystal particles, and the average particle diameter Dave of the crystal particles can be easily reduced to 1.0 ⁇ m or less in combination with the mixing molar ratio m of Sr and Ti.
  • the semiconductor ceramic layer 3 can be thinned.
  • the laminated sintered body is subjected to secondary firing at a low temperature of 600 to 900 ° C. for about 1 hour in an air atmosphere to re-oxidize the semiconductor ceramic, thereby diffusing oxygen to the crystal grain boundaries.
  • the crystal grain boundary becomes an insulating layer (grain boundary insulating layer)
  • a Schottky barrier is formed at the crystal grain boundary, the insulation can be improved, and the component body 1 in which the internal electrode 4 is embedded. Is produced.
  • a conductive paste for external electrodes is applied to both ends of the component element body 1 and subjected to a baking treatment to form external electrodes 2a and 2b, whereby a multilayer semiconductor ceramic capacitor is manufactured.
  • the present invention is not limited to the above embodiment.
  • the solid solution is produced by the solid phase method, but the production method of the solid solution is not particularly limited.
  • hydrothermal synthesis method, sol-gel method, hydrolysis method, coprecipitation Any method such as a method can be used.
  • this slurry was evaporated to dryness, and then calcined in an air atmosphere at a calcining temperature of 1400 ° C. for 2 hours to obtain a calcined powder in which La was dissolved in crystal particles.
  • MnCO 3 is weighed so that the content of Mn element as an acceptor element is 0.3 mol with respect to 100 mol of Ti element, and the content mol of Si is 0.1 with respect to 100 mol of Ti element.
  • SiO 2 is weighed so as to have a mole, and these weighed products are added to the calcined powder, and the polycarboxylic acid ammonium salt as a dispersant is 3 parts by weight with respect to 100 parts by weight of the calcined powder. And added to the calcined powder.
  • MnCO 3 is added to the calcined powder, but a MnCl 2 solution or a Mn sol solution may be added.
  • the mixture was evaporated to dryness, and heat treatment was performed at 600 ° C. for 5 hours in an air atmosphere to remove organic components such as a dispersant to obtain heat treated powder.
  • an organic solvent such as toluene and alcohol, and an appropriate amount of a dispersant were added to the heat-treated powder, and again put into a ball mill together with a PSZ ball having a diameter of 2 mm, and wet mixed in the ball mill for 16 hours.
  • a dispersant such as toluene and alcohol
  • PVB polyvinyl butyral
  • DOP dioctyl phthalate
  • a cationic surfactant are added in an appropriate amount, followed by a wet mixing process for 1.5 hours. A rally was made.
  • a lip coater method was used to form the ceramic slurry, and a large ceramic green sheet was prepared so that the thickness after firing was 25 ⁇ m.
  • the conductive film was formed in various patterns such that the ratio a / t between the end face spacing a and the layer thickness t after firing and the ratio b / t between the side face spacing b and the layer thickness t were as shown in Table 1.
  • this large laminate was cut into a predetermined size and separated into individual pieces to obtain a green laminate, and then the binder was treated in a nitrogen atmosphere at a temperature of 375 ° C. for 2 hours. .
  • re-oxidation is performed by performing secondary firing at 700 ° C. for 1 hour in an air atmosphere, thereby dispersing oxygen at the grain boundaries to form a grain boundary insulating layer, and then polishing the end faces.
  • a component body was produced.
  • samples Nos. 1 to 11 were obtained.
  • the outer diameter dimensions of the samples were length L: 1.0 mm, width W: 0.5 mm, and thickness T: 0.5 mm.
  • sample evaluation Six samples of sample numbers 1 to 11 were prepared.
  • the remaining three samples are held in such a posture that the length (L) direction is along the vertical direction, the periphery of the sample is hardened with resin, and is defined by the width W and thickness T of the sample.
  • the WT surface was exposed from the resin. Thereafter, the WT surface of each sample is polished by a polishing machine, each sample is polished to a depth of about 1 ⁇ 2 of the length (L) direction, and further, the polishing surface is ion milled to prevent the internal electrode from extending. Thus, a cross section of each sample was obtained.
  • ⁇ Measurement of layer thickness t> For each of the three samples Nos. 1 to 11 with the LT section exposed, a center line C perpendicular to the semiconductor ceramic layer was drawn at a substantially central portion of the LT section. Then, using a scanning electron microscope (SEM), the layer thickness t of the semiconductor ceramic layer on the center line C was measured for all 10 layers of each of the three samples, and the average value was calculated. The average value of the layer thickness t was 25.0 ⁇ m.
  • Table 1 shows the ratio a / t, the ratio b / t, the capacitance, the initial insulation resistance IR 0 , and the insulation resistance IR after contact discharge in the samples of sample numbers 1 to 11.
  • the insulation resistance IR is indicated by a common logarithm (logIR).
  • the ratio a / t is as small as 1.5 and the facing area between the internal electrode layers is large. Therefore, although the capacitance is as large as 1.65 nF, the initial value of the insulation resistance logIR is 8.5.
  • the insulation resistance logIR was lowered to 5.8 by one forward and reverse contact discharge. This is because the end face spacing a is excessively small compared to the layer thickness t, and therefore, when a voltage of 30 kV is applied, discharge occurs between the end face spacings a, without discharging between the internal electrode layers. It seems that fine cracks were generated in the semiconductor ceramic layer at the time of discharge, which caused a decrease in the insulation resistance logIR.
  • Sample No. 7 has a small ratio b / t of 1.5, and in this case as well, since the facing area between the internal electrode layers is large, the capacitance is as large as 1.71 nF, but the initial value of the insulation resistance logIR is 8.4. In contrast, when the voltage of 30 kV was applied, the insulation resistance logIR was reduced to 5.9 after one forward and reverse contact discharge. This is because the side face distance b is excessively small compared to the layer thickness t, and when a voltage of 30 kV is applied, the discharge occurs between the side face distances b without discharging between the internal electrode layers. It is considered that fine cracks were generated in the semiconductor ceramic layer at the time of carrying out the process, leading to a decrease in the insulation resistance logIR.
  • Sample No. 8 had a large ratio a / t of 15, and the facing area between the internal electrode layers was small, so the capacitance was reduced to 0.51 nF.
  • Sample No. 9 has a large ratio b / t of 8 and, like Sample No. 8, the facing area between the internal electrode layers was reduced, so the capacitance was reduced to 0.42 nF.
  • Sample Nos. 8 and 9 are not preferable because the facing area between the internal electrode layers is small, and thus the capacitance decreases, and the size of the parts is increased in order to obtain a desired capacitance.
  • the ratios a / t and b / t are as small as 1.75, respectively, and also in this case, the facing area between the internal electrode layers is large, so that the capacitances are 2.05 nF and 2.13 nF, respectively. large.
  • the insulation resistance logIR is 8.2 and 8.3 in the forward and reverse contact discharges when the voltage of 30 kV is applied, whereas the insulation resistance logIR is 5. 7 and 5.4. This is because the end face interval a or the side face interval b is not sufficiently larger than the layer thickness t, and when a 30 kV voltage is applied, when contact discharge is performed 100 times forward and reverse, the end face is not discharged between the internal electrode layers. It seems that discharge occurred between the intervals a or between the side intervals b, and fine cracks were generated in the semiconductor ceramic layer, which caused a decrease in the insulation resistance logIR.
  • Sample Nos. 1 to 5 have a ratio a / t of 2 to 10 and a ratio b / t of 2 to 5, both within the scope of the present invention. Therefore, the capacitance was 0.75 to 1.83 nF. Even if the contact discharge is performed 1000 times forward and backward by applying a voltage of 30 kV while maintaining a good value, the insulation resistance logIR is 8.4 to 9.0, which is comparable to the initial insulation resistance value, It was found to have good ESD resistance.
  • the desired insulation can be secured, the desired electrical characteristics and good durability, and a highly reliable multilayer semiconductor ceramic capacitor with a varistor function can be realized. It can be carried by one element.

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Abstract

La présente invention comprend : un élément de composant (1) obtenu en empilant alternativement des couches de céramique semi-conductrice (3) faites d'une céramique semi-conductrice à isolation interganulaire à base de SrTiO3 et des couches d'électrodes internes (4a, 4b) ; et des électrodes externes (2a, 2b) qui sont électriquement connectées, au deux extrémités de l'élément de composant (1), aux couches d'électrodes internes (4a, 4b). Les couches d'électrodes internes (4a, 4b) sont pourvues de sections de sortie (7, 8) qui sont acheminées en sortie vers une surface d'extrémité (5) ou une autre surface d'extrémité (6) de l'élément de composant (1). L'intervalle (a) séparant les surfaces d'extrémité (9, 10) des couches d'électrodes internes (4a, 4b) des surfaces d'extrémité (5, 6) de l'élément de composant (1), l'intervalle (b) séparant les surfaces latérales (13, 14) des couches d'électrodes internes (4a, 4b) des surfaces latérales (15, 16) de l'élément de composant (1), et l'épaisseur (t) de chacune des couches de céramiques semi-conductrice (3) satisfont aux relations 2 ≤ a/t ≤ 10 et 2 ≤ b/t ≤ 5. Le condensateur à empilement de céramique semi-conductrice doté d'une fonction de varistance ainsi formé présente une excellente fiabilité, il est capable d'inhiber une réduction des propriétés d'isolation, même en cas de pointes de tension répétées, et il est capable d'assurer les caractéristiques électriques voulues.
PCT/JP2015/068974 2014-07-08 2015-07-01 Condensateur à empilement de céramique semi-conductrice doté d'une fonction de varistance Ceased WO2016006510A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005303160A (ja) * 2004-04-15 2005-10-27 Murata Mfg Co Ltd 積層型半導体セラミック電子部品
WO2012176714A1 (fr) * 2011-06-22 2012-12-27 株式会社村田製作所 Poudre céramique, condensateur céramique semi-conducteur et procédé de fabrication de celui-ci

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