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WO2016000363A1 - 低温多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 - Google Patents

低温多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2016000363A1
WO2016000363A1 PCT/CN2014/089661 CN2014089661W WO2016000363A1 WO 2016000363 A1 WO2016000363 A1 WO 2016000363A1 CN 2014089661 W CN2014089661 W CN 2014089661W WO 2016000363 A1 WO2016000363 A1 WO 2016000363A1
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Prior art keywords
insulating layer
array substrate
substrate
layer
gate
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PCT/CN2014/089661
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English (en)
French (fr)
Inventor
张家祥
姜晓辉
阎长江
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/443,777 priority Critical patent/US10002889B2/en
Priority to EP14861140.3A priority patent/EP3163620B1/en
Publication of WO2016000363A1 publication Critical patent/WO2016000363A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method of manufacturing the same, and a display device.
  • amorphous silicon ( ⁇ -Si) technology and low temperature poly-silicon (LTPS) technology are widely used.
  • LTPS technology has been widely used due to its high performance and high definition.
  • the magnitude of the leakage current is an important indicator. If the leakage current is too large, the driving voltage cannot be maintained, and display defects may occur.
  • the method of reducing the leakage current of the LTPS structure is to use a double gate or multi-gate structure, such as the double gate structure including two gates 7 shown in FIG.
  • the gate electrode 7 is generally made of a metal material having good conductivity, such as molybdenum or molybdenum aluminum alloy. These materials are themselves opaque, such as the grid 7 in Figure 1, which obscures the light. Therefore, in the prior art, the technical solution of using an array substrate of a double gate or a multi-gate structure is disadvantageous for an increase in aperture ratio.
  • Embodiments of the present invention provide a low-temperature polysilicon thin film transistor array substrate, a manufacturing method thereof, and a display device, which not only reduce the generation of leakage current, but also improve the aperture ratio of the panel.
  • Embodiments of the present invention provide a low temperature polysilicon thin film transistor array substrate, including: a substrate; a polysilicon active layer disposed on the substrate; a first insulating layer on the layer; a plurality of gates and gate lines disposed on the first insulating layer; a second insulating layer disposed on the gate; a source disposed on the second insulating layer a pole, a drain and a data line, and a pixel electrode electrically connected to the drain, the source covering the plurality of gates.
  • the array substrate may further include a buffer layer disposed under the active layer.
  • the number of the plurality of gates of the array substrate may be 2 to 5.
  • the array substrate may further include a common electrode disposed in the same layer as the pixel electrode.
  • the array substrate may further include a third insulating layer disposed over the pixel electrode, and a slit-shaped common electrode disposed on the third insulating layer.
  • the array substrate may further include a common electrode disposed in the same layer as the gate.
  • the second insulating layer of the array substrate may include a resin material.
  • the resin material may include polymethyl methacrylate and a sensitizer.
  • the second insulating layer may have a thickness of 1.5 to 2.0 ⁇ m.
  • Another embodiment of the present invention provides a method for fabricating a low temperature polysilicon thin film transistor array substrate, comprising the steps of: sequentially forming an active layer, a first insulating layer, and a plurality of gates on a substrate; Forming a second insulating layer including a first via and a second via on the substrate of the first insulating layer and the gate; forming a source and a drain on the substrate forming the second insulating layer a pattern, the source covering the plurality of gates; and forming a pattern including a pixel electrode on the substrate forming a pattern including the source and the drain, the pixel electrode being connected to the drain.
  • the step of sequentially forming an active layer, a first insulating layer, and a plurality of gate electrodes on the substrate may include: depositing a buffer layer and an amorphous silicon film on the substrate, converting the amorphous silicon into low-temperature polysilicon, and patterning Forming a pattern including an active layer; forming a pattern of the first insulating layer on the substrate on which the active layer is formed; and depositing a gate metal film on the substrate on which the first insulating layer is formed, formed by a patterning process A pattern comprising a plurality of gates.
  • the manufacturing method of the low temperature polysilicon thin film transistor array substrate may further include a step of: forming a third insulating layer on the substrate on which the pattern of the pixel electrode is formed; and depositing a transparent conductive film on the substrate on which the third insulating layer is formed, and forming a pattern including the common electrode by a patterning process.
  • the method of manufacturing the low temperature polysilicon thin film transistor array substrate may further include the step of forming a pattern including a common electrode when forming a pattern including a plurality of gate electrodes.
  • the second insulating layer is a resin layer formed by spin coating.
  • Another embodiment of the present invention provides a display device including the above low temperature polysilicon thin film transistor array substrate.
  • the multi-gate structure is arranged directly under the source, which not only increases the aperture ratio of the panel, but also reduces the leakage current.
  • a resin layer having a small dielectric constant is disposed between the gate and the source and drain, thereby avoiding a coupling capacitance due to overlap of the gate and the source, thereby reducing generation of leakage current.
  • FIG. 1 is a plan view of a prior art double gate structure array substrate.
  • FIG. 2A is a plan view of an array substrate according to Embodiment 1 of the present invention.
  • Fig. 2B is a cross-sectional view taken along line A-B of Fig. 2A.
  • 3A is a plan view showing a structure formed in a first patterning process in a method of fabricating an array substrate according to a second embodiment of the present invention.
  • Fig. 3B is a cross-sectional view taken along line A-B of Fig. 3A.
  • 4A is a plan view showing a structure formed in a second patterning process in the method of fabricating the array substrate of the second embodiment of the present invention.
  • Fig. 4B is a cross-sectional view taken along line A-B of Fig. 4A.
  • Fig. 5A is a plan view showing a structure formed in a third patterning process in the method of fabricating the array substrate of the second embodiment of the present invention.
  • Fig. 5B is a cross-sectional view taken along line A-B of Fig. 5A.
  • Fig. 6A is a plan view showing a structure formed in a fourth patterning process in the method of fabricating the array substrate of the second embodiment of the present invention.
  • Fig. 6B is a cross-sectional view taken along line A-B of Fig. 5A.
  • Fig. 7A is a plan view showing the structure formed in the fifth patterning process in the method of manufacturing the array substrate of the second embodiment of the present invention.
  • Fig. 7B is a cross-sectional view taken along line A-B in Fig. 7A.
  • Fig. 8A is a plan view showing a structure formed in a sixth patterning process in the method of manufacturing the array substrate of the second embodiment of the present invention.
  • Fig. 8B is a cross-sectional view taken along line A-B of Fig. 7A.
  • Fig. 9A is a plan view showing a structure formed in a seventh patterning process in the method of manufacturing the array substrate of the second embodiment of the present invention.
  • Fig. 9B is a cross-sectional view taken along line A-B of Fig. 9A.
  • Embodiment 1 provides a low temperature polysilicon thin film transistor array substrate. 2A and 2B, FIG. 2A is a plan view of the array substrate of the first embodiment, and FIG. 2B is a cross-sectional view taken along line A-B of FIG. 2A.
  • the array substrate of the first embodiment includes: a substrate 1; a polysilicon active layer 2 disposed on the substrate 1; a first insulating layer 3 disposed on the active layer 2; and a plurality of gates disposed on the first insulating layer 3. a gate line 70; a second insulating layer 4 disposed on the gate electrode 7; a source 5, a drain electrode 6 and a data line disposed on the second insulating layer 4, and a pixel electrode electrically connected to the drain electrode 6 8.
  • the source 5 covers the plurality of gates 7.
  • the number of the plurality of gates is three.
  • a multi-gate structure is disposed directly under the source 5, and in a top view of the array substrate, a plurality of gates 7 are covered by the source 5.
  • the metal is shielded from light, which increases the aperture ratio of the panel.
  • the array substrate of this embodiment further includes a pixel electrode disposed at the pixel A third insulating layer 9 above the 8 and a slit-shaped common electrode 10 disposed on the third insulating layer 9.
  • Each of the pixel electrode 8 and the common electrode 10 is formed of at least one of indium gallium zinc oxide, indium zinc oxide (IZO), indium tin oxide (ITO), and indium gallium tin oxide.
  • the first insulating layer 3, the second insulating layer 4, and the third insulating layer 9 may be formed using at least one of silicon oxide, silicon nitride, tantalum oxide, or aluminum oxide.
  • the gate electrode 7, the source electrode 5, and the drain electrode 6 may each be formed using at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium, or copper.
  • the active layer 2 may be formed using a low temperature polysilicon material.
  • the number of the plurality of gate electrodes 7 may be two.
  • those skilled in the art may also choose to use 4 gates or 5 gates as needed.
  • a buffer layer may be disposed under the active layer 2.
  • the common electrode and the pixel electrode may be disposed in the same layer to form an IPS (In-Plane Switching) structure.
  • the common electrode can also be disposed in the same layer as the gate.
  • the second insulating layer 4 may include a resin material.
  • the resin material may include polymethyl methacrylate and a sensitizer.
  • the thickness of the second insulating layer 4 ranges from 1.5 to 2.0 ⁇ m.
  • the second embodiment provides a method for preparing a low temperature polysilicon thin film transistor array substrate.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • step S1 an amorphous silicon film is deposited on the substrate, amorphous silicon is converted into low temperature polycrystalline silicon, and a pattern including the active layer 2 is formed by a patterning process.
  • an amorphous silicon layer is deposited on the substrate 1 using a chemical vapor deposition (CVD) method.
  • CVD chemical vapor deposition
  • amorphous silicon is crystallized into low temperature polycrystalline silicon by an excimer laser annealing (ELA) method.
  • ELA excimer laser annealing
  • step S2 a pattern of the first insulating layer 3 is formed on the substrate on which step S1 is completed.
  • a first insulating layer 3 is formed on the substrate 1 on which the step S1 is completed by a chemical vapor deposition (CVD) method, and the thickness of the first insulating layer 3 is in the range of
  • the first insulating layer 3 is generally formed of a transparent material (silicon oxide, silicon nitride, tantalum oxide or aluminum oxide).
  • step S3 a gate metal film is deposited on the substrate on which step S2 is completed, and a pattern including the gate electrode 7 and the gate line is formed by a patterning process.
  • a gate metal film is formed on the substrate 1 completing step S2, and the gate metal film may be made of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium or copper. At least one is formed, and then a pattern including the gate electrode 7 and the gate line is formed by a patterning process, and the gate electrode 7 is connected to the gate line.
  • the active layer is doped with the gate electrode 7 as a mask layer.
  • the gate is a three-gate or multi-gate pattern, distributed in a comb shape, and the multi-gate structure is disposed directly under the source.
  • the gate metal film can be formed by a deposition method, a sputtering method or a thermal evaporation method, and the thickness of the gate metal film is in the range of
  • a photoresist is first coated on the gate metal film, and then the photoresist is exposed, developed, etched, and stripped using a mask to form a gate electrode 7 and The pattern of the grid lines.
  • Arranging the multi-gate structure directly under the source not only reduces the generation of leakage current, but also increases the aperture ratio of the panel.
  • step S4 a layer of about 3 ⁇ m is spin-coated on the substrate on which step S3 is completed.
  • a thick resin layer is formed to form the second insulating layer 4. Via holes are formed in the first insulating layer 3 and the second insulating layer 4 by a patterning process.
  • a resin layer is applied by spin coating on the substrate 1 on which the step S3 is completed to form the second insulating layer 4. Via holes are formed in the first insulating layer 3 and the second insulating layer 4 by a patterning process.
  • a resin layer having a small dielectric constant is disposed between the gate electrode 7 and the source and drain electrodes, thereby avoiding a coupling capacitance due to overlap of the gate and the source.
  • step S5 a source/drain metal film is deposited on the substrate on which step S4 is completed, and a pattern including the source 5 and the drain 6 is formed by a patterning process.
  • a source/drain metal film is formed on the substrate 1 on which the step S4 is completed, and a pattern including the source 5, the drain 6 and the data line is formed by a patterning process, the source 5 And the drain electrode 6 is located on both sides of the second insulating layer 4, and is connected to the doped region of the active layer 2 through the via holes in the second insulating layer 4 and the first insulating layer 3, respectively.
  • the source/drain metal film may be formed by a deposition method, a sputtering method, or a thermal evaporation method. In the patterning process, a layer of photoresist is first coated on the source/drain metal film, and then the photoresist is exposed, developed, etched, and stripped using a mask to form a source 5, Graph of drain 6 and data lines.
  • the source/drain metal film may be formed using at least one of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium or copper.
  • step S6 a transparent conductive film is deposited on the substrate on which step S5 is completed, and a pattern including the pixel electrode 8 is formed by a patterning process, and the pixel electrode 8 is electrically connected to the drain 6.
  • a pixel electrode film is formed on the substrate on which the step S5 is completed, and a pattern including the pixel electrode 8 is formed by a patterning process.
  • the pixel electrode 8 is located above the drain electrode 6 and the second insulating layer 4, and the pixel electrode 8 is electrically connected to the drain electrode 6.
  • the pixel electrode film may be formed by chemical vapor deposition, sputtering or thermal evaporation, and the thickness of the pixel electrode film is In the patterning process, a photoresist is first coated on the pixel electrode film, and the photoresist is exposed, developed, etched, and stripped using a mask to form a pattern of the pixel electrode 8.
  • step S7 a third insulating layer 9 is deposited on the substrate on which step S6 is completed, and via holes are formed by a patterning process.
  • a passivation layer film is formed on the substrate 1 on which the step S6 is completed, and a pattern of the third insulating layer 9 (PVX) is formed by a patterning process, the third insulating layer 9 A pattern covers the source 5, the drain 6, and the pixel electrode 8.
  • the passivation layer film may be formed by a deposition method, a sputtering method or a thermal evaporation method, and the thickness of the passivation layer film is In the patterning process, a photoresist is coated on the passivation layer film, and the photoresist is exposed, developed, etched, and stripped using a mask to form a third insulating layer. And the pattern of the vias. Similar to the first insulating layer 3, the third insulating layer 9 is generally formed of a transparent material (silicon oxide, silicon nitride, tantalum oxide or aluminum oxide).
  • the third insulating layer 9 is formed over the data line, the source 5 and the drain 6 and extends to the peripheral lead region of the array substrate, and the peripheral lead region of the array substrate is provided with the data line driving signal introducing electrode, and the third The insulating layer 9 is provided with a via hole at a position corresponding to the data line driving signal introducing electrode, and the data line is electrically connected to the data line driving signal introducing electrode through the via hole.
  • step S8 a transparent conductive film is deposited on the substrate on which step S7 is completed, and a pattern including the common electrode 10 is formed by a patterning process.
  • a common electrode film is formed on the substrate 1 on which the step S7 is completed, and a pattern including the common electrode 10 is formed over the third insulating layer 9 by a patterning process.
  • the formation of the common electrode film may be performed by a deposition method, a sputtering method, or a thermal evaporation method.
  • a photoresist is first coated on the common electrode film, and the photoresist is exposed, developed, etched, and stripped using a mask to form a pattern including the common electrode 10.
  • the common electrode 10 is a slit electrode distributed in a comb shape.
  • the number of patterning processes can be reduced by using a halftone or gray tone mask or the like in forming the respective layer structures, which is not limited in this embodiment.
  • a plurality of gate electrodes are formed at the source Directly below, not only reduces the leakage current, but also increases the aperture ratio of the panel. Further, a resin layer having a small dielectric constant is formed between the gate and the source and drain, thereby avoiding a coupling capacitance due to overlap of the gate and the source.
  • the embodiment of the invention further provides a display device comprising any one of the above array substrates.
  • the display device can be applied to any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种低温多晶硅薄膜晶体管阵列基板及其制造方法和显示装置。该阵列基板，包括：基板（1）；设置在基板上的多晶硅有源层（2）；设置在有源层上的第一绝缘层（3）；设置在第一绝缘层上的多个栅极（7）和栅线；设置在栅极上的第二绝缘层（4）；设置在第二绝缘层上的源极（5）、漏极（6）和数据线；以及与漏极电连接的像素电极（8）；该源极覆盖多个栅极。将多个栅极布置在源极正下方，不但减小了漏电流，还提高了面板的开口率。

Description

低温多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 技术领域
本发明涉及显示技术领域，特别涉及阵列基板及其制造方法、和显示装置。
背景技术
在显示技术领域，非晶硅(α-Si)技术和低温多晶硅(Low Temperature Poly-silicon，简称：LTPS)技术应用较为广泛。随着显示技术的发展，LTPS技术凭借其能实现高效能和高清晰的特点，得到了越来越广泛的应用。
对于LTPS结构，漏电流的大小是一个重要指标。漏电流过大则造成驱动电压无法保持，会出现显示方面的不良。目前，减小LTPS结构的漏电流的方法是采用双栅或多栅结构，例如图1所示的包括两个栅极7的双栅结构。虽然通过采用多个栅极，能够有效降低沟道中的电场分布，减少热载流子效应并抑制泄漏电流，但是栅极7一般采用导电性能较好的金属材料，例如钼或钼铝合金等，这些材料本身不透光，如图1中的栅极7，其对光有所遮挡。因此，在现有技术中，采用双栅或多栅结构的阵列基板的技术方案不利于开口率的提高。
发明内容
本发明实施例提供一种低温多晶硅薄膜晶体管阵列基板及其制造方法、显示装置，其不但降低了漏电流的产生，还提高了面板的开口率。
本发明实施例提供一种低温多晶硅薄膜晶体管阵列基板，包括：基板；设置在所述基板上的多晶硅有源层；设置在所述有源 层上的第一绝缘层；设置在所述第一绝缘层上的多个栅极和栅线；设置在所述栅极上的第二绝缘层；设置在所述第二绝缘层上的源极、漏极和数据线以及与所述漏极电连接的像素电极，所述源极覆盖所述多个栅极。
所述阵列基板还可以包括设置在所述有源层下方的缓冲层。
所述阵列基板的多个栅极的数量可以为2至5个。
所述阵列基板还可以包括与所述像素电极同层设置的公共电极。
可替代地，所述阵列基板还可以包括设置在所述像素电极上方的第三绝缘层、以及设置在所述第三绝缘层上的狭缝状公共电极。
可替代地，所述阵列基板还可以包括与所述栅极同层设置的公共电极。
所述阵列基板的第二绝缘层可以包括树脂材料。
所述树脂材料可以包括聚甲基丙烯酸甲酯和感光剂。
所述第二绝缘层的厚度可以为1.5-2.0μm。
本发明另一实施例提供一种低温多晶硅薄膜晶体管阵列基板的制造方法，包括步骤：在衬底基板上依次形成有源层、第一绝缘层、多个栅极；在形成有所述有源层、所述第一绝缘层、所述栅极的基板上形成包括第一过孔和第二过孔的第二绝缘层；在形成第二绝缘层的基板上形成包括源极和漏极的图形，所述源极覆盖所述多个栅极；以及在形成包括所述源极和所述漏极的图形的基板上形成包括像素电极的图形，所述像素电极与所述漏极连接。
所述在衬底基板上依次形成有源层、第一绝缘层、多个栅极的步骤可以包括：在基板上沉积缓冲层和非晶硅薄膜，将非晶硅转化成低温多晶硅，通过构图工艺形成包括有源层的图形；在形成有所述有源层的基板上形成第一绝缘层的图形；以及在形成有所述第一绝缘层的基板上沉积栅金属薄膜，通过构图工艺形成包括多个栅极的图形。
所述低温多晶硅薄膜晶体管阵列基板的制造方法还可以包括 步骤：在形成有所述像素电极的图形的基板上形成第三绝缘层；以及在形成第三绝缘层的基板上沉积透明导电薄膜，通过构图工艺形成包括公共电极的图形。
可替代地，所述低温多晶硅薄膜晶体管阵列基板的制造方法还可以包括步骤：在形成包括多个栅极的图形时，还形成包括公共电极的图形。
所述第二绝缘层为通过旋转涂覆形成的树脂层。
本发明另一实施例提供一种显示装置，包括上述的低温多晶硅薄膜晶体管阵列基板。
在本发明实施例提供的阵列基板中，将多栅结构布置在源极正下方，不但提高了面板的开口率，还减小了漏电流。此外，在栅极和源漏极之间布置介电常数小的树脂层，避免了因栅极与源极重叠产生的耦合电容，从而降低了漏电流的产生。
附图说明
图1是现有技术中的双栅结构阵列基板的平面图。
图2A是本发明实施例一的阵列基板的平面图。
图2B是沿图2A中的线A-B截取的剖面图。
图3A是本发明实施例二的阵列基板的制造方法中第一次构图工艺中形成的结构的平面图。
图3B是沿图3A中的线A-B截取的剖面图。
图4A是本发明实施例二的阵列基板的制造方法中第二次构图工艺中形成的结构的平面图。
图4B是沿图4A中的线A-B截取的剖面图。
图5A是本发明实施例二的阵列基板的制造方法中第三次构图工艺中形成的结构的平面图。
图5B是沿图5A中的线A-B截取的剖面图。
图6A是本发明实施例二的阵列基板的制造方法中第四次构图工艺中形成的结构的平面图。
图6B是沿图5A中的线A-B截取的剖面图。
图7A是本发明实施例二的阵列基板的制造方法中第五次构图工艺中形成的结构的平面图。
图7B是沿图7A中的线A-B截取的剖面图。
图8A是本发明实施例二的阵列基板的制造方法中第六次构图工艺中形成的结构的平面图。
图8B是沿图7A中的线A-B截取的剖面图。
图9A是本发明实施例二的阵列基板的制造方法中第七次构图工艺中形成的结构的平面图。
图9B是沿图9A中的线A-B截取的剖面图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的阵列基板及其制造方法和显示装置进行详细描述。
[实施例一]
实施例一提供了一种低温多晶硅薄膜晶体管阵列基板。参照图2A和图2B，图2A为实施例一的阵列基板的俯视图，图2B为沿图2A中的线A-B截取的剖面图。实施例一的阵列基板包括：基板1；设置在基板1上的多晶硅有源层2；设置在有源层2上的第一绝缘层3；设置在第一绝缘层3上的多个栅极7和栅线70；设置在栅极7上的第二绝缘层4；设置在第二绝缘层4上的源极5、漏极6和数据线以及与所述漏极6电连接的像素电极8，所述源极5覆盖所述多个栅极7。
如图2B所示，所述多个栅极的数量为3个。参照图2A和图2B，将多栅结构布置在源极5的正下方，在该阵列基板的俯视图中，多个栅极7被源极5覆盖。与在俯视图中未被源极覆盖的多个栅极额外地对光有所遮挡的现有技术中的阵列基板相比，在本实施例的阵列基板中，通过将多个栅极布置在源极的正下方，减少了金属对光的遮挡，从而提高了面板的开口率。
参照图2B，本实施例的阵列基板还包括设置在所述像素电极 8上方的第三绝缘层9、以及设置在所述第三绝缘层9上的狭缝状公共电极10。
像素电极8和公共电极10均采用氧化铟镓锌、氧化铟锌(Indium Zinc Oxide，简称IZO)、氧化铟锡(Indium Tin Oxide，简称ITO)、氧化铟镓锡中的至少一种形成。
第一绝缘层3、第二绝缘层4、第三绝缘层9可以采用硅氧化物、硅氮化物、铪氧化物或铝氧化物中的至少一种形成。栅极7、源极5和漏极6可以均采用钼、钼铌合金、铝、铝钕合金、钛或铜中的至少一种形成。有源层2可以采用低温多晶硅材料形成。
可替代地，本实施例的阵列基板中，多个栅极7的数量可以为2个。当然，本领域技术人员根据需要也可以选择采用4个栅极或5个栅极。
本实施例提供的低温多晶硅薄膜晶体管阵列基板中，有源层2下方还可以设置有缓冲层。
可替代地，本实施例的阵列基板中，公共电极与像素电极可以设置在同一层，以形成IPS(In-Plane Switching，平面转换)的结构。此外，公共电极还可以与栅极同层设置。
可替代地，本实施例的阵列基板中，第二绝缘层4可以包括树脂材料。树脂材料可以包括聚甲基丙烯酸甲酯和感光剂。第二绝缘层4的厚度范围为1.5-2.0μm。
[实施例二]
实施例二提供了低温多晶硅薄膜晶体管阵列基板的制备方法。在阐述具体制备方法之前，应该理解，在本发明中，构图工艺可只包括光刻工艺，或者包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩膜板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
实施例二提供的低温多晶硅薄膜晶体管阵列基板的制备方法 具体包括如下步骤S1至S8。
步骤S1中，在基板上沉积非晶硅薄膜，将非晶硅转变成低温多晶硅，通过构图工艺形成包括有源层2的图形。
在本步骤中，如图3A和3B所示，在所述基板1上使用化学气相沉积(CVD)方法沉积非晶硅层。例如，采用准分子激光退火(ELA)方法将非晶硅晶化为低温多晶硅。然后，进行光刻及刻蚀步骤以形成所需要的图形化的低温多晶硅层。
步骤S2中，在完成步骤S1的基板上形成第一绝缘层3的图形。
在本步骤中，如图4A和4B所示，在完成步骤S1的基板1上采用化学气相沉积(Chemical Vapor Deposition，简称CVD)法形成第一绝缘层3，第一绝缘层3的厚度范围为
Figure PCTCN2014089661-appb-000001
第一绝缘层3一般采用透明材料(硅氧化物、硅氮化物、铪氧化物或铝氧化物)形成。
步骤S3中，在完成步骤S2的基板上沉积栅金属薄膜，通过构图工艺形成包括栅极7和栅线的图形。
在本步骤中，如图4A和4B所示，在完成步骤S2的基板1上形成栅极金属薄膜，栅极金属薄膜可采用钼、钼铌合金、铝、铝钕合金、钛或铜中的至少一种形成，然后通过构图工艺形成包括栅极7和栅线的图形，所述栅极7和所述栅线相连。以栅极7为掩膜层，对有源层进行掺杂。所述栅极为三栅极或多栅极图案，呈梳状分布，多栅结构布置在源极正下方。
形成栅极金属薄膜可以采用沉积法、溅射法或热蒸发法，栅极金属薄膜的厚度范围为
Figure PCTCN2014089661-appb-000002
在所述构图工艺中，先在栅极金属薄膜上涂覆一层光刻胶，然后采用掩膜板对所述光刻胶进行曝光、显影、刻蚀、剥离，以形成包括栅极7和栅线的图形。
将多栅结构布置在源极正下方，不但降低了漏电流的产生，还提高了面板的开口率。
步骤S4中，在完成步骤S3的基板上旋转涂覆一层大概3μm 厚的树脂层，以形成第二绝缘层4。通过构图工艺在第一绝缘层3和第二绝缘层4中形成过孔。
在本步骤中，如图5A和5B所示，在完成步骤S3的基板1上采用旋转涂覆的方法涂覆一层树脂层，以形成第二绝缘层4。通过构图工艺在第一绝缘层3和第二绝缘层4中形成过孔。
在栅极7和源漏极之间布置介电常数小的树脂层，从而避免了因栅极与源极重叠产生的耦合电容。
步骤S5中，在完成步骤S4的基板上沉积源漏金属薄膜，通过构图工艺形成包括源极5和漏极6的图形。
在本步骤中，如图6A和6B所示，在完成步骤S4的基板1上形成源漏金属薄膜，通过构图工艺形成包括源极5、漏极6和数据线的图形，所述源极5和漏极6位于第二绝缘层4的上方两侧，并且通过第二绝缘层4和第一绝缘层3中的过孔分别与有源层2的掺杂区相连。
形成源漏金属薄膜可以采用沉积法、溅射法或热蒸发法。在所述构图工艺中，先在源漏金属薄膜上涂覆一层光刻胶，然后采用掩膜板对所述光刻胶进行曝光、显影、刻蚀、剥离，以形成包括源极5、漏极6和数据线的图形。源漏金属薄膜可采用钼、钼铌合金、铝、铝钕合金、钛或铜中的至少一种形成。
步骤S6中，在完成步骤S5的基板上沉积透明导电薄膜，通过构图工艺形成包括像素电极8的图形，所述像素电极8与所述漏极6电连接。
在本步骤中，如图7A和7B所示，在完成步骤S5的基板上形成像素电极膜，通过构图工艺形成包括像素电极8的图形。所述像素电极8位于漏极6和第二绝缘层4的上方，所述像素电极8与所述漏极6电连接。
形成像素电极薄膜可以采用化学气相沉积法、溅射法或热蒸发法，像素电极薄膜的厚度范围为
Figure PCTCN2014089661-appb-000003
在所述构图工艺中，先在像素电极薄膜上涂覆一层光刻胶，采用掩膜板对所述光刻胶进行曝光、显影、刻蚀、剥离，以形成像素电极8的图形。
步骤S7中，在完成步骤S6的基板上沉积第三绝缘层9，通过构图工艺形成过孔。
在本步骤中，如图8A和8B所示，在完成步骤S6的基板1上形成钝化层薄膜，通过构图工艺形成第三绝缘层9(PVX)的图形，所述第三绝缘层9的图形覆盖所述源极5、漏极6和像素电极8。
形成钝化层薄膜可以采用沉积法、溅射法或热蒸发法，钝化层薄膜的厚度范围为
Figure PCTCN2014089661-appb-000004
在所述构图工艺中，先在钝化层薄膜上涂覆一层光刻胶，采用掩膜板对所述光刻胶进行曝光、显影、刻蚀、剥离，以形成包括第三绝缘层9和过孔的图形。与第一绝缘层3类似，第三绝缘层9一般采用透明材料(硅氧化物、硅氮化物、铪氧化物或铝氧化物)形成。
此时，第三绝缘层9形成在数据线、源极5和漏极6的上方并延伸至阵列基板的外围引线区域，在阵列基板的外围引线区域设置有数据线驱动信号引入电极，第三绝缘层9在对应数据线驱动信号引入电极的位置开设有过孔，所述数据线通过过孔与数据线驱动信号引入电极电连接。
步骤S8中，在完成步骤S7的基板上沉积透明导电薄膜，通过构图工艺形成包括公共电极10的图形。
在本步骤中，如图9A和9B所示，在完成步骤S7的基板1上形成公共电极薄膜，通过构图工艺在第三绝缘层9上方形成包括公共电极10的图形。
形成公共电极薄膜可以采用沉积法、溅射法或热蒸发法。在所述构图工艺中，先在公共电极薄膜上涂覆一层光刻胶，采用掩膜板对所述光刻胶进行曝光、显影、刻蚀、剥离，以形成包括公共电极10的图形。公共电极10为呈梳状分布的狭缝电极。
在上述阵列基板的制备方法中，在形成各层结构时，还可以通过使用半色调或灰色调掩膜板等方式来减少构图工艺的次数，对此本实施例并不限定。
本实施例的阵列基板的制备方法中，将多个栅极形成在源极 正下方，不但降低了漏电流的产生，还提高了面板的开口率。此外，在栅极与源漏极之间形成介电常数小的树脂层，避免了因栅极与源极重叠产生的耦合电容。
本发明实施例还提供了一种显示装置，其包括上述任意一种阵列基板。所述显示装置可以应用于：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (15)

  1. 一种低温多晶硅薄膜晶体管阵列基板，包括：
    基板；
    设置在所述基板上的多晶硅有源层；
    设置在所述有源层上的第一绝缘层；
    设置在所述第一绝缘层上的多个栅极和栅线；
    设置在所述栅极上的第二绝缘层；
    设置在所述第二绝缘层上的源极、漏极和数据线以及与所述漏极电连接的像素电极，
    其中，所述源极覆盖所述多个栅极。
  2. 根据权利要求1所述的阵列基板，还包括设置在所述有源层下方的缓冲层。
  3. 根据权利要求1或2所述的阵列基板，其中，所述多个栅极的数量为2至5个。
  4. 根据权利要求1所述的阵列基板，还包括与所述像素电极同层设置的公共电极。
  5. 根据权利要求1所述的阵列基板，还包括：
    设置在所述像素电极上方的第三绝缘层；以及
    设置在所述第三绝缘层上的狭缝状公共电极。
  6. 根据权利要求1所述的阵列基板，还包括与所述栅极同层设置的公共电极。
  7. 根据权利要求1所述的阵列基板，其中，所述第二绝缘层包括树脂材料。
  8. 根据权利要求7所述的阵列基板，其中，所述树脂材料包括聚甲基丙烯酸甲酯和感光剂。
  9. 根据权利要求7所述的阵列基板，其中，所述第二绝缘层的厚度为1.5-2.0μm。
  10. 一种低温多晶硅薄膜晶体管阵列基板的制造方法，包括步骤：
    在衬底基板上依次形成有源层、第一绝缘层、多个栅极；
    在形成有所述有源层、所述第一绝缘层、所述栅极的基板上形成包括第一过孔和第二过孔的第二绝缘层；
    在形成第二绝缘层的基板上形成包括源极和漏极的图形，所述源极覆盖所述多个栅极；以及
    在形成包括所述源极和所述漏极的图形的基板上形成包括像素电极的图形，所述像素电极与所述漏极连接。
  11. 根据权利要求10所述的阵列基板的制造方法，其中，所述在衬底基板上依次形成有源层、第一绝缘层、多个栅极的步骤包括：
    在基板上沉积缓冲层和非晶硅薄膜，将非晶硅转化成低温多晶硅，通过构图工艺形成包括有源层的图形；
    在形成有所述有源层的基板上形成第一绝缘层的图形；以及
    在形成有所述第一绝缘层的基板上沉积栅金属薄膜，通过构图工艺形成包括多个栅极的图形。
  12. 根据权利要求10所述的阵列基板的制造方法，还包括步骤：
    在形成有所述像素电极的图形的基板上形成第三绝缘层；以及
    在形成有所述第三绝缘层的基板上沉积透明导电薄膜，通过构图工艺形成包括公共电极的图形。
  13. 根据权利要求11所述的阵列基板的制造方法，还包括步骤：
    在形成包括多个栅极的图形时，还形成包括公共电极的图形。
  14. 根据权利要求10所述的阵列基板的制造方法，其中，所述第二绝缘层为通过旋转涂覆形成的树脂层。
  15. 一种显示装置，包括权利要求1至9中任一项所述的阵列基板。
PCT/CN2014/089661 2014-06-30 2014-10-28 低温多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 Ceased WO2016000363A1 (zh)

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