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WO2015021720A1 - 一种阵列基板及其制备方法及显示装置 - Google Patents

一种阵列基板及其制备方法及显示装置 Download PDF

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Publication number
WO2015021720A1
WO2015021720A1 PCT/CN2013/089765 CN2013089765W WO2015021720A1 WO 2015021720 A1 WO2015021720 A1 WO 2015021720A1 CN 2013089765 W CN2013089765 W CN 2013089765W WO 2015021720 A1 WO2015021720 A1 WO 2015021720A1
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Prior art keywords
layer
protective layer
gate
slit structure
pattern
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PCT/CN2013/089765
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English (en)
French (fr)
Inventor
崔承镇
金熙哲
宋泳锡
刘圣烈
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US14/388,699 priority Critical patent/US9690146B2/en
Publication of WO2015021720A1 publication Critical patent/WO2015021720A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present invention relates to the field of display technology, and in particular to an array substrate, a preparation method thereof and a display device. Background technique
  • a TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • a complete liquid crystal display panel must have a backlight module group, a polarizer, an upper substrate (usually a color filter substrate), and a lower substrate (usually an array substrate) and a box composed of two substrates thereof.
  • the liquid crystal molecular layer is composed.
  • the array substrate is formed with horizontally and vertically intersecting data lines and gate lines, and the data lines and the gate lines are arranged to form pixel units arranged in a matrix form.
  • Each of the pixel units includes a TFT switch and a pixel electrode; wherein the TFT switch includes a gate electrode, a source electrode, a drain electrode, and an active layer; a gate electrode is connected to the gate line, a source electrode is connected to the data line, a drain electrode is connected to the pixel electrode, and an active layer Formed between the source and drain electrodes and the gate electrode.
  • a common electrode is also formed on the array substrate for forming an electric field with the pixel electrode, and a change in electric field intensity between the common electrode and the pixel electrode controls the degree of rotation of the liquid crystal molecules.
  • ADS-DS (ADvanced Super Dimension Switch), referred to as ADS, is an advanced super-dimensional field conversion technology.
  • the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field.
  • the rotation of all the liquid crystal molecules in the liquid crystal cell between the slit electrodes and the electrodes directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the storage capacitance (Cst) between the common electrode 111 and the pixel electrode 112 of the TFT array substrate 110 in the ADS mode is very large, and it occupies almost the entire pixel area, especially a large-sized product, due to a change in pixel area.
  • the storage capacitor will become bigger, usually to adapt to this Large storage capacitors need to be designed with larger thin film transistors for filling. Larger thin film transistors will occupy the pixel area.
  • the coupling capacitances Cgd and Cgs of the thin film transistors will also become larger, thus affecting the display of the screen. There are many limitations in design.
  • one of the most straightforward methods for solving such a problem is that the ADS type pixel electrode 112 and the common electrode 111 are formed in a state as shown in FIG. 2, but the current process cannot be directly realized.
  • the reason is that the pixel electrode 112 and the common electrode 111 are both transparent electrodes. In the process of exposure, development, etc. by the process equipment, the alignment effect of the transparent film is limited, and the device cannot achieve the true one as shown in FIG. 2 .
  • the technical problem to be solved by the present invention is to provide an array substrate, a preparation method thereof and a display device, which can make the pixel electrode of the array substrate and the common electrode zero overlap, reduce the storage capacitance between the common electrode and the pixel electrode, and ensure the picture. quality.
  • an embodiment of the present invention provides a method for preparing an array substrate, including:
  • a common electrode having a slit structure is formed on the substrate, and a pixel electrode having a slit structure that overlaps with the common electrode.
  • the step of forming a common electrode of the slit structure on the substrate, and the pixel electrode of the slit structure having zero overlap with the common electrode includes:
  • a gate, a gate line, a gate insulating layer, a semiconductor layer, a data line, a source/drain on the substrate and forming a substrate having a gate, a gate line, a gate insulating layer, a semiconductor layer, a data line, and a source/drain a pattern of a protective layer and a passivation layer on which a slit structure is formed;
  • a transparent conductive film on the substrate on which the pattern of the protective layer and the passivation layer is formed, the transparent conductive film being used to form a common electrode of the slit structure on the protective layer, and a bit a pixel electrode in a slit region in the slit structure of the protective layer and the passivation layer, wherein the pixel electrode and the drain directly overlap.
  • the step of forming a pattern of the protective layer and the passivation layer of the slit structure on the substrate on which the gate, the gate line, the gate insulating layer, the semiconductor layer, the data line, and the source/drain are formed includes:
  • the protective layer and the passivation layer are patterned to obtain a pattern of a protective layer and a passivation layer having a slit structure.
  • the step of patterning the protective layer and the passivation layer to obtain a pattern of a protective layer and a passivation layer having a slit structure includes:
  • the protective layer and the passivation layer are sequentially etched by a common patterning process to obtain a pattern of a protective layer and a passivation layer having a slit structure.
  • the step of patterning the protective layer and the passivation layer to obtain a pattern of a protective layer and a passivation layer having a slit structure includes:
  • the passivation layer exposed by the slit structure is directly etched to obtain a pattern of a protective layer and a passivation layer having a slit structure.
  • the step of forming a common electrode having a slit structure on the substrate, and the pixel electrode of the slit structure having zero overlap with the common electrode includes:
  • the transparent conductive film Forming a transparent conductive film on a substrate on which a pattern of the protective layer and the gate insulating layer is formed, the transparent conductive film being used to form a common electrode of a slit structure on the protective layer, and being located on the protective layer And a pixel electrode of a slit region in a slit structure of the gate insulating layer, wherein said The pixel electrode is directly overlapped with the drain.
  • the method further comprises:
  • the semiconductor layer and the transparent conductive film over the source/drain are removed by a patterning process to obtain a pattern of the final common electrode and the pixel electrode.
  • An embodiment of the present invention further provides an array substrate, including:
  • a common electrode of a slit structure formed on the substrate and a pixel electrode of a slit structure that overlaps with the common electrode.
  • the array substrate comprises a thin film transistor of a bottom gate structure or a thin film transistor of a top gate structure.
  • the thin film transistor of the bottom gate structure includes: a gate electrode, a gate line, a gate insulating layer formed on the substrate, and a semiconductor layer, a data line, a source/drain formed on the gate insulating layer; A pattern of a protective layer and a passivation layer of the slit structure over the semiconductor layer, the source/drain is further formed on the substrate, and the protective layer and the passivation layer are laminated structures.
  • the width of the cross section of the protective layer is wider than that of the passivation layer.
  • the thin film transistor of the top gate structure includes: a semiconductor layer formed on the substrate, a data line, a source/drain, and a gate insulating film and a gate sequentially formed on the source/drain electrodes and the data lines And grid lines;
  • the common electrode of the slit structure is located on the protective layer pattern; the pixel electrode of the slit structure is formed in a slit region of the slit structure of the protective layer and the passivation layer, wherein The pixel electrode is directly overlapped with the drain.
  • the common electrode of the slit structure is located on the protective layer pattern; the pixel electrode of the slit structure is formed in a slit region of the slit structure of the protective layer and the gate insulating layer, wherein The pixel electrode is directly overlapped with the drain.
  • the protective layer is made of an inorganic insulating resin material or an organic photosensitive resin material.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the common electrode of the slit structure is formed on the substrate, and the pixel electrode of the slit structure having zero overlap with the common electrode, thereby reducing the storage capacitance of the common electrode and the pixel electrode, thereby ensuring picture quality.
  • FIG. 1 is a schematic diagram of a common electrode and a pixel electrode of a conventional array substrate
  • FIG. 2 is a schematic view showing a pixel electrode of a slit structure of a desired array substrate and a common electrode of a slit structure;
  • 3 to 8 are schematic views showing an implementation process of a specific embodiment of a method of fabricating an array substrate of the present invention. Concrete implementation
  • Embodiments of the present invention provide a method for fabricating an array substrate, including:
  • a common electrode having a slit structure is formed on the substrate, and a pixel electrode having a slit structure that overlaps with the common electrode.
  • This embodiment can reduce the storage capacitance between the common electrode and the pixel electrode by forming a common electrode having a slit structure on the substrate and a pixel electrode of a slit structure overlapping the common electrode, thereby ensuring a picture quality.
  • the specific implementation process of the pixel electrode having the slit structure formed on the substrate and the slit structure having zero overlap with the common electrode is as follows:
  • a substrate 11 is provided, and a gate electrode 12, a gate line (not shown), a gate insulating layer 13, a semiconductor layer 14, and a data line (not shown) are formed on the substrate 11.
  • the source 15 and the drain 16; specifically, the step may include:
  • Step 31 forming a gate metal layer on the substrate, and forming a pattern of the gate line and the gate by a patterning process;
  • Step 32 forming a gate insulating layer on the substrate on which the gate line and the gate pattern are formed;
  • Step 33 forming a semiconductor layer film on the gate insulating layer formed thereon, and forming a pattern of the semiconductor layer by a patterning process;
  • Step 34 forming a source/drain metal layer film on the formed semiconductor layer; forming a pattern of a source, a drain, and a data line by a communication process;
  • the formation of the semiconductor layer and the source/drain may be specifically achieved by the following steps: Step 34', sequentially forming a semiconductor layer film and a source/drain metal layer film on the substrate on which the gate insulating layer is formed, by using a patterning process Processing the source/drain metal layer film and the semiconductor layer film to obtain a pattern of the semiconductor active layer 14, the data lines (not shown), the source 15 and the drain 16; wherein, step 34' is specific
  • the implementation process can include:
  • Step 341 coating a photoresist on the thin film on which the source/drain metal layer is formed;
  • Step 342 exposing the photoresist by using a halftone mask or a gray tone mask, and forming a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist completely removed region after development;
  • the photoresist completely reserved region corresponds to a source region, a drain region and a data line region
  • the photoresist semi-reserved region corresponds to a gap region between the source and the drain
  • other regions correspond to a photoresist completely removed region ;
  • Step 343 removing a source/drain metal layer film and a semiconductor layer film in the completely removed region of the photoresist by an etching process to expose a gate insulating layer of the region;
  • Step 344 removing a photoresist of the semi-reserved region of the photoresist by a plasma ashing process, exposing a source/drain metal layer film of the region;
  • Step 345 etching the exposed source/drain metal layer film by an etching process to expose the semiconductor layer, and forming a pattern of the slit region between the source and the drain of the thin film transistor in the region;
  • Step 346 removing the photoresist in the completely remaining region of the photoresist by a plasma ashing process or a photoresist stripping process, and forming a narrow line between the data line, the source, the drain, and the source and the drain. Stitched graphics.
  • the foregoing steps are only one specific implementation example of the foregoing solution of the present invention, but the embodiments of the present invention are not limited to the foregoing implementation steps, and those skilled in the art may know that different modes, such as a top gate mode or a bottom gate mode,
  • the above-mentioned pattern formation process may be slightly different, such as by step sequence adjustment; or the sequence adjustment of the above-mentioned mask process steps, the above array can be realized
  • the structure of the thin film transistor on the substrate. 3 is only a schematic diagram of a bottom gate structure, specifically including: a gate electrode 12, a gate line (not shown), a gate insulating layer 13, a semiconductor layer 14, a data line (not shown), a source 15, Drain 16.
  • a gate electrode 12, a gate line (not shown), a gate insulating layer 13, a semiconductor layer 14, a data line (not shown), a source 15, and a drain 16 are formed.
  • a passivation layer 17 continues to be formed on the substrate.
  • the protective layer pattern 18 of the slit structure is formed on the substrate 11 on which the passivation layer 17 is formed.
  • the specific implementation process of the protective layer pattern of the slit structure may include:
  • Step 51 forming a protective layer on the passivation layer
  • the protective layer may be a resin material, and the resin material is an inorganic insulating resin material; the film forming density of the inorganic insulating resin material may be higher than the density of the passivation layer 17, so that in the subsequent patterning process
  • the etching rate of the protective layer can be made lower than the etching rate of the passivation layer, thereby ensuring etching chamfering of the passivation layer and the protective layer in the cross section.
  • the protective layer 18 may also be formed of a photosensitive resin material. This saves subsequent etching of the protective layer.
  • Step 52 patterning the protective layer and the passivation layer to obtain a pattern of a protective layer having a slit structure and a passivation layer as shown in FIG.
  • the slit region in the slit structure corresponds to a region of the pixel electrode, and the protective layer in the slit structure corresponds to a region of the common electrode.
  • the specific implementation process of the foregoing step 52 may include the following two methods:
  • Method 1 forming a photoresist on the protective layer; using a common patterning process, sequentially etching the protective layer 18 and the passivation layer 17 to form a slit pattern as shown in FIG. 6, in order to make subsequent pixel electrodes
  • the common electrode can smoothly realize the fault.
  • an etching solution with different etching rates of the passivation layer and the protective layer is selected to ensure that the etching rate of the passivation layer is faster than that of the protective layer, so that the passivation layer is finally
  • the contact portion of the protective layer is etched and chamfered, that is, in the region of the passivation layer and the protective layer, the cross-sectional width of the protective layer is wider than that of the passivation layer.
  • a slit structure of the protective layer can be formed by an exposure and development process, and the exposed passivation layer is directly etched by using a pattern of the protective layer.
  • the etching time or the etching rate is controlled by an etching process.
  • 6 shows the pattern of the protective layer and the passivation layer having the slit structure, and in the laminated structure of the passivation layer and the protective layer, the cross-sectional width of the passivation layer is narrower than that of the protective layer to facilitate subsequent pixel electrodes and common When the electrodes are formed, a good break can be produced to ensure the fault of the common electrode and the pixel electrode.
  • a pattern of a semiconductor layer, a source/drain electrode, and a data line may be sequentially formed on the array substrate; and then sequentially formed on the substrate on which the active/drain electrodes and the data lines are formed.
  • a pattern of the gate insulating film and the gate and the gate lines forming a protective layer on the pattern on which the gate and the gate lines are formed, patterning the protective layer and the gate insulating layer film by a patterning process, forming a protective layer of the slit structure and a gate insulating layer (the passivation layer is formed by a gate insulating layer), wherein the slit in the slit structure corresponds to a region of the pixel electrode, and the protective layer pattern in the slit structure corresponds to a pattern of the common electrode .
  • a transparent conductive film is formed on a substrate on which a protective layer and a passivation layer pattern are formed; the transparent conductive film is used to form a common electrode and a pixel electrode; and the transparent conductive film is subjected to a film forming process.
  • a common electrode 20 on the protective layer and a pixel electrode 19 located in the slit region in the slit structure Obtaining a common electrode 20 on the protective layer and a pixel electrode 19 located in the slit region in the slit structure; and since the bottom of the protective layer pattern covers the top of the passivation layer, and the passivation layer and the protective layer form an etching chamfer That is, the width of the cross section of the protective layer is wider than the width of the cross section of the passivation layer, and therefore, when the transparent conductive film is formed, the common electrode 20 on the protective layer and the pixel located in the slit region of the slit structure
  • the electrodes 19 do not overlap and are staggered in a horizontal position, so that a zero overlap between the common electrode and the pixel electrode can minimize the storage capacitance, thereby ensuring picture quality;
  • the fabrication of the pixel electrode and the common electrode is performed separately from the fabrication process of the conventional array substrate.
  • the fabrication process is reduced, the fabrication process is shortened, and the fabrication efficiency of the array substrate is improved.
  • the method further includes:
  • the transparent conductive film belongs to a part of the common electrode and exists above the thin film transistor, which causes signal interference to the thin film transistor to increase the load of the thin film transistor, and generates some unnecessary parasitic capacitance, such as increasing Cdc, etc., and removing The adverse effects of thin film transistors are minimized.
  • the above embodiments of the present invention can be applied to a TFT array substrate of an ADS mode, simultaneously forming a metal layer of a common electrode and a pixel electrode by a single film forming process, and forming a pixel electrode and a common electrode having a slit structure to make a common
  • the electrode and the pixel electrode overlap at zero, thereby avoiding the storage capacitance between the common electrode and the pixel electrode, thereby ensuring picture quality;
  • the fabrication of the pixel electrode and the common electrode is performed separately from the fabrication process of the conventional array substrate.
  • the fabrication process is reduced, the fabrication process is shortened, and the fabrication efficiency of the array substrate is improved.
  • an embodiment of the present invention further provides an array substrate, which is fabricated by using the method embodiment as described above, and the array substrate includes:
  • a substrate 11 a substrate 11; and a common electrode 20 of a slit structure formed on the substrate, and a pixel electrode 19 of a slit structure that overlaps with the common electrode 20.
  • the array substrate includes a thin film transistor of a bottom gate structure or a thin film transistor of a top gate structure; wherein the bottom gate structure thin film transistor includes: a gate electrode 12 formed on the substrate 11, a gate line, a gate insulating layer 13, and a formation a semiconductor layer 14, a data line, a source 15 and a drain 16 on the gate insulating layer 13; the substrate further has: a narrow region formed on the semiconductor layer 14, the source 15 and the drain 16. a pattern of the protective layer and the passivation layer of the slit structure;
  • the thin film transistor of the top gate structure includes: a semiconductor layer formed on the substrate, a data line, a source/drain, and a gate insulating film, a gate, and a gate line sequentially formed on the source/drain electrodes and the data lines.
  • the protective layer and the gate insulating layer are a stacked structure;
  • the width of the cross section of the protective layer is wider than that of the passivation layer; thus, the transparent conductive film for forming the common electrode and the pixel electrode can be deposited once,
  • the common electrode 20 located above the protective layer and the pixel electrode 19 located in the slit region are obtained; and the etching of the common electrode and the etching process of the pixel electrode are omitted, and the bottom of the protective layer pattern covers the passivation layer
  • the top therefore, is located in the protective layer when depositing the transparent conductive film
  • the upper common electrode 20 does not overlap with the pixel electrode 19 on the gate insulating layer, and therefore, the storage capacitance between the common electrode and the pixel electrode is avoided, and the picture quality is ensured.
  • the passivation layer of the slit structure is formed by a gate insulating layer, and the gate is between the gate insulating layer and the protective layer; in the stacked structure of the protective layer and the gate insulating layer, the cross section of the protective layer The width is wider than that of the gate insulating layer; the transparent conductive film for forming the common electrode and the pixel electrode can also be used to form a common electrode 20 located above the protective layer and the pixel electrode 19 located in the slit region; The etching of the common electrode and the patterning process of the pixel electrode are omitted, and since the bottom of the protective layer pattern covers the top of the gate insulating layer, the common electrode 20 on the protective layer is insulated from the gate when the transparent conductive film is prepared.
  • the pixel electrodes 19 on the layer do not overlap, and therefore, the storage capacitance between the common electrode and the pixel electrode is avoided, and the picture quality is ensured.
  • the pixel electrode and the drain are directly overlapped in the bottom gate structure or the top gate structure.
  • a common electrode 20 of the slit structure is located on the protective layer pattern;
  • a pixel electrode 19 of the slit structure is formed in a slit region in the slit structure; that is, the pixel electrode and the A passivation layer (or gate insulating layer) and a protective layer are formed between the common electrodes.
  • the transparent conductive film for forming the common electrode and the pixel electrode can be deposited once to obtain the common electrode 20 above the protective layer and the pixel electrode 19 located in the slit region;
  • the etching of the common electrode and the etching process of the pixel electrode are removed, and since the bottom of the protective layer pattern covers the top of the passivation layer (or the gate insulating layer), the public layer on the protective layer is deposited when the transparent conductive film is deposited.
  • the electrode 20 does not overlap with the pixel electrode 19 located in the slit region, and therefore, the storage capacitance between the common electrode and the pixel electrode is avoided, and the picture quality is ensured.
  • the material of the protective layer may be an organic photosensitive resin material or an inorganic insulating resin material.
  • the common electrode 20 and the pixel electrode 19 are made of the same metal material.
  • the embodiment of the array substrate also forms a pixel electrode having a slit structure and a common electrode so that the common electrode and the pixel electrode are zero-overlapped, thereby avoiding the storage capacitance between the common electrode and the pixel electrode, thereby ensuring picture quality.
  • the thin film for the formation process of the thin film, there are common methods for semiconductor film formation such as chemical vapor deposition, vapor deposition, magnetron sputtering, etc.
  • spin coating and spraying may be performed in the formation process of the photoresist. , transfer, etc., the above specific film forming method or photoresist forming method Domain engineers can choose freely based on specific equipment or product designs.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display device uses any one of the array substrates as described in the above embodiments.
  • the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.

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Abstract

一种阵列基板及其制备方法及显示装置，其中，阵列基板的制备方法包括：在基板（11）上形成有狭缝结构的公共电极（20），以及与公共电极（20）零交叠的狭缝结构的像素电极（19）。采用这种方法制备的阵列基板和显示装置能够减小公共电极（20）和像素电极（19）的存储电容，保证画面品质。

Description

一种阵列基板及其制备方法及显示装置 技术领域
本发明涉及显示技术领域， 特别是指一种阵列基板及其制备方法及显示 装置。 背景技术
TFT-LCD (Thin Film Transistor-Liquid Crystal Display, 薄膜场效应晶体管 液晶显示器） 是利用设置在液晶层上电场强度的变化， 改变液晶分子的旋转 的程度， 从而控制透光的强弱来显示图像的。 一般来讲， 一块完整的液晶显 示面板必须具有由背光模块组、偏光片、上基板（通常是彩膜基板） 和下基板 (通常是阵列基板） 以及由它们两块基板组成的盒中填充的液晶分子层构成。
阵列基板上形成有横纵交叉的数据线和栅线， 数据线和栅线围设形成矩 阵形式排列的像素单元。每个像素单元包括 TFT 开关和像素电极；其中， TFT 开关包括栅电极、 源电极、 漏电极和有源层； 栅电极连接栅线， 源电极连接 数据线， 漏电极连接像素电极， 有源层形成在源、 漏电极与栅电极之间。
阵列基板上一般还形成有公共电极， 用于和像素电极形成电场， 公共电 极与像素电极之间的电场强度变化控制着液晶分子的旋转的程度。
ADS-DS (ADvanced Super Dimension Switch), 简称 ADS， 即高级超维 场转换技术， 通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与 板状电极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上 方所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了透 光效率。 高级超维场转换技术可以提高 TFT-LCD 产品的画面品质， 具有高 分辨率、高透过率、低功耗、 宽视角、高开口率、低色差、无挤压水波紋 (push Mura) 等优点。
如图 1所示， 在 ADS 模式的 TFT 阵列基板 110的公共电极 111与像素 电极 112之间的存储电容 （Cst) 非常大， 几乎占到整个像素区域， 特别是大 尺寸产品， 由于像素面积变大后， 存储电容会变得更大， 通常为了适应这么 大的存储电容， 需要设计更大的薄膜晶体管进行充满， 较大的薄膜晶体管一 是会占用像素面积， 二是薄膜晶体管本身的耦合电容 Cgd， Cgs等也会变大， 从而影响画面显示， 从而在设计上受到很多限制， 一般情况下， 解决这样的 问题最直接的方法之一是 ADS型像素电极 112和公共电极 111形成为如图 2 所示的状态， 但目前的工艺是无法直接实现的， 原因是像素电极 112和公共 电极 111均是透明电极， 在通过工艺设备进行曝光、 显影等过程中， 透明薄 膜的对位效果是有限的， 设备根本无法做到真正的如图 2所示的结构， 如果 因为工艺对位偏差导致像素电极与公共电极在一个有效显示区域内相对位移 不均匀， 比如一部分区域像素电极 112相对于公共电极 111 向左偏， 而另一 部分区域像素电极 112相对于公共电极 111 向右偏， 则会出现 Cst区域间不 均， 反映到画面中， 则会出现一个显示器上各个区域之间的显示灰度不均匀， 人眼感觉到的就是画面区域间显示亮度不均导致画面失真， 是非常致命的显 示缺陷， 而现有技术中没有很好的解决方案。 发明内容
本发明要解决的技术问题是提供一种阵列基板及其制备方法及显示装置, 可以使阵列基板的像素电极与公共电极零交叠， 减小公共电极与像素电极之 间的存储电容， 保证画面品质。
为解决上述技术问题， 本发明的实施例提供一种阵列基板的制备方法， 包括：
在基板上形成有狭缝结构的公共电极， 以及与所述公共电极零交叠的狭 缝结构的像素电极。
其中， 在基板上形成狭缝结构的公共电极， 以及与所述公共电极零交叠 的狭缝结构的像素电极的步骤包括：
在基板上形成栅极、 栅线、 栅绝缘层、 半导体层、 数据线、 源 /漏极； 在形成有栅极、 栅线、 栅绝缘层、 半导体层、 数据线、 源 /漏极的基板上 形成狭缝结构的保护层和钝化层的图形；
在形成有所述保护层和钝化层的图形的基板上， 形成透明导电薄膜， 所 述透明导电薄膜用于形成位于所述保护层上的狭缝结构的公共电极， 以及位 于所述保护层和钝化层的狭缝结构中的狭缝区域的像素电极， 其中所述像素 电极与漏极直接搭接。
其中， 在形成有栅极、 栅线、 栅绝缘层、 半导体层、 数据线、 源 /漏极的 基板上形成狭缝结构的保护层和钝化层的图形的步骤包括：
形成钝化层；
在所述钝化层上形成保护层；
对所述保护层以及所述钝化层进行构图， 得到具有狭缝结构的保护层和 钝化层的图形。
其中， 对所述保护层以及所述钝化层进行构图， 得到具有狭缝结构的保 护层和钝化层的图形的步骤包括：
在所述保护层上形成光刻胶；
利用普通构图工艺， 依次对所述保护层和钝化层进行刻蚀， 得到具有狭 缝结构的保护层和钝化层的图形。
其中， 对所述保护层以及所述钝化层进行构图， 得到具有狭缝结构的保 护层和钝化层的图形的步骤包括：
通过曝光、 显影工艺形成狭缝结构的保护层；
直接对狭缝结构暴露出的钝化层进行刻蚀， 得到具有狭缝结构的保护层 和钝化层的图形。
其中， 在基板上形成有狭缝结构的公共电极， 以及与所述公共电极零交 叠的狭缝结构的像素电极的步骤包括：
在基板上依次形成半导体层、 源 /漏极和数据线的图形；
在形成有半导体层、 源 /漏电极和数据线的图形的基板上， 依次形成栅绝 缘层薄膜以及栅极和栅线的图形；
在形成有栅绝缘层薄膜、 栅极和栅线的图形的基板上形成保护层； 利用构图工艺对保护层和栅绝缘层薄膜进行构图， 形成狭缝结构的保护 层和栅绝缘层的图形；
在形成有所述保护层和栅绝缘层的图形的基板上， 形成透明导电薄膜， 所述透明导电薄膜用于形成位于所述保护层上的狭缝结构的公共电极， 以及 位于所述保护层和栅绝缘层的狭缝结构中的狭缝区域的像素电极， 其中所述 像素电极与漏极直接搭接。
其中， 形成透明导电薄膜后还包括：
通过构图工艺对所述半导体层、 源 /漏极上方的透明导电薄膜去除， 得到 最终的公共电极和像素电极的图形。
本发明的实施例还提供一种阵列基板， 其特征在于， 包括：
基板； 以及
形成于所述基板上的狭缝结构的公共电极， 以及与所述公共电极零交叠 的狭缝结构的像素电极。
其中， 所述阵列基板包括底栅结构的薄膜晶体管或者顶栅结构的薄膜晶 体管。
其中， 所述底栅结构的薄膜晶体管包括： 形成于所述基板上的栅极、 栅 线、 栅绝缘层， 以及形成于所述栅绝缘层上的半导体层、 数据线、 源 /漏极； 所述基板上还形成有位于所述半导体层、 源 /漏极之上的狭缝结构的保护 层和钝化层的图形， 且所述保护层和钝化层为叠层结构。
其中， 在保护层和钝化层的叠层结构中， 保护层横截面的宽度比钝化层 宽。
其中， 所述顶栅结构的薄膜晶体管包括： 形成于所述基板上的半导体层、 数据线、 源 /漏极， 以及依次形成于源 /漏电极和数据线上的栅绝缘层薄膜、栅 极和栅线；
所述基板上还形成有位于所述栅极、 栅线上的保护层， 利用构图工艺对 保护层和栅绝缘层薄膜进行构图以形成狭缝结构的保护层和栅绝缘层的图 形， 且所述保护层和栅绝缘层为叠层结构。
其中， 所述狭缝结构的公共电极位于所述保护层图形上； 所述狭缝结构 的像素电极形成于所述保护层和钝化层的所述狭缝结构中的狭缝区域， 其中 所述像素电极与漏极直接搭接。
其中， 所述狭缝结构的公共电极位于所述保护层图形上； 所述狭缝结构 的像素电极形成于所述保护层和栅绝缘层的所述狭缝结构中的狭缝区域， 其 中所述像素电极与漏极直接搭接。
其中， 所述保护层采用无机绝缘树脂材料或者有机感光树脂材料制成。 本发明的实施例还提供一种显示装置， 包括如上所述的阵列基板。
本发明的上述技术方案的有益效果如下：
上述方案中， 通过在基板上形成有狭缝结构的公共电极， 以及与所述公 共电极零交叠的狭缝结构的像素电极， 从而可以减小公共电极与像素电极的 存储电容， 保证画面品质。 附图说明
图 1为现有的阵列基板的公共电极与像素电极的图形示意图；
图 2为期望的阵列基板的狭缝结构的像素电极以及狭缝结构的公共电极 的图形示意图；
图 3—图 8为本发明的阵列基板的制备方法的具体实施例的实现过程示 意图。 具体实舫式
为使本发明要解决的技术问题、 技术方案和优点更加清楚， 下面将结合 附图及具体实施例进行详细描述。
本发明的实施例提供一种阵列基板的制备方法， 包括：
在基板上形成有狭缝结构的公共电极， 以及与所述公共电极零交叠的狭 缝结构的像素电极。
该实施例通过在基板上形成有狭缝结构的公共电极， 以及与所述公共电 极零交叠的狭缝结构的像素电极， 从而可以减小公共电极与像素电极之间的 存储电容， 保证画面品质。
如图 3—图 8所示， 为上述在基板上形成有狭缝结构的公共电极， 以及 与所述公共电极零交叠的狭缝结构的像素电极的具体实现过程：
如图 3所示， 首先， 提供一基板 11， 在基板 11上形成栅极 12、栅线（图 中未示出）、 栅绝缘层 13、 半导体层 14、 数据线 （图中未示出）、 源极 15、 漏极 16; 具体的， 该步骤可以包括：
步骤 31， 在基板上形成栅金属层， 采用构图工艺形成栅线以及栅极的图 形； 步骤 32， 在形成有栅线以及栅极图形的基板上形成栅绝缘层； 步骤 33， 在形成有栅绝缘层上形成半导体层薄膜， 通过构图工艺形成半 导体层的图形；
步骤 34， 在形成有半导体层上形成源漏金属层薄膜； 通过沟通工艺形成 源极、 漏极和数据线的图形；
另外， 对于半导体层和源 /漏极的形成还可以具体通过以下步骤实现： 步骤 34'， 在形成有栅绝缘层的基板上， 依次形成半导体层薄膜和源 /漏 金属层薄膜， 利用构图工艺对所述源 /漏金属层薄膜以及半导体层薄膜进行处 理， 得到半导体有源层 14、数据线（图中未示出）、源极 15、漏极 16的图形; 其中， 步骤 34'具体的实现过程可以包括：
步骤 341， 在形成有所述源 /漏金属层薄膜上涂布光刻胶；
步骤 342， 利用半色调掩膜板或灰色调掩膜板对所述光刻胶进行曝光， 显影后形成光刻胶完全保留区域、 光刻胶部分保留区域和光刻胶完全去除区 域； 其中， 所述光刻胶完全保留区域对应源极区域、 漏极区域和数据线区域， 所述光刻胶半保留区域对应源极和漏极之间的缝隙区域， 其他区域对应光刻 胶完全去除区域；
步骤 343， 利用刻蚀工艺去除掉所述光刻胶完全去除区域的源漏金属层 薄膜、 半导体层薄膜， 暴露出该区域的栅绝缘层；
步骤 344， 利用等离子体灰化工艺去除掉所述光刻胶半保留区域的光刻 胶， 暴露出该区域的源漏金属层薄膜；
步骤 345， 利用刻蚀工艺对暴露出的源漏金属层薄膜进行刻蚀， 暴露出 半导体层， 在该区域形成薄膜晶体管源极和漏极之间的狭缝区域图形；
步骤 346， 利用等离子体灰化工艺或光刻胶剥离工艺去除掉所述光刻胶 完全保留区域的光刻胶， 形成包括数据线、 源极、 漏极和源极与漏极之间的 狭缝的图形。
上述步骤仅为本发明的上述方案的一个具体实现实例， 但本发明的实施 例中， 并不限于上述实现步骤， 本领域技术人员可以知道， 不同模式下， 例 如顶栅模式或者底栅模式下上述图形的形成过程可以稍微有差别， 如通过步 骤顺序的调整； 或者上述掩膜工艺的步骤的顺序调整， 都可以实现上述阵列 基板上薄膜晶体管的结构。 图 3仅是底栅结构的示意图， 具体包括： 栅极 12、 栅线 （图中未示出）、 栅绝缘层 13、 半导体层 14、 数据线 （图中未示出）、 源 极 15、 漏极 16。
如图 4所示， 在形成有栅级 12、 栅线 （图中未示出）、 栅绝缘层 13、 半 导体层 14、 数据线 （图中未示出）、 源极 15、 漏极 16的基板上继续形成钝化 层 17。
如图 5所示， 在形成有钝化层 17的基板 11上继续形成狭缝结构的保护 层图形 18; 其中， 该狭缝结构的保护层图形的具体实现过程可以包括：
步骤 51， 在所述钝化层上形成保护层；
其中， 所述保护层可以为树脂材料， 且该树脂材料为无机绝缘树脂材料; 所述无机绝缘树脂材料的成膜致密度比钝化层 17的致密度高即可，这样 在后续构图工艺中可以使保护层的刻蚀速率比钝化层的刻蚀速率低， 从而可 保证在截面上钝化层与保护层出现刻蚀倒角。
进一步的， 所述保护层 18还可以选用感光树脂材料形成。这样可以节省 后续对保护层的刻蚀工序。
步骤 52， 对所述保护层以及所述钝化层进行构图， 得到如图 5所示， 具 有狭缝结构的保护层以及钝化层的图形。
其中， 所述狭缝结构中的狭缝区域对应像素电极的区域， 所述狭缝结构 中的保护层对应公共电极的区域。
其中， 上述步骤 52的具体实现过程可以包括以下两种方法：
方法一， 在所述保护层上形成光刻胶； 利用普通的构图工艺， 依次对保 护层 18和钝化层 17刻蚀后形成如图 6所示的狭缝图形， 为了使后续像素电 极与公共电极可以很顺利的实现断层， 一般会选用对钝化层和保护层刻蚀速 率不同的刻蚀液， 以确保钝化层的刻蚀速率比保护层快， 这样最终会使钝化 层与保护层的接触部分实现刻蚀倒角， 即在钝化层与保护层叠层的区域， 保 护层的横截面宽度要比钝化层宽。
方法二， 所述保护层的材料可以使用有机感光树脂材料时， 首先， 通过 曝光、 显影工艺可以形成保护层的狭缝结构， 利用保护层的图案直接对暴露 出的钝化层进行刻蚀， 通过刻蚀工艺， 控制刻蚀时间或者刻蚀速率得到如图 6 所示的具有狭缝结构的保护层和钝化层的图形， 并且钝化层与保护层的叠 层结构中， 钝化层的横截面宽度比保护层窄， 以利于后续像素电极与公共电 极形成时， 可以产生很好的断差以确保公共电极和像素电极的断层。
上述步骤仅为本发明的上述方案的一个具体实现实例， 但本发明的实施 例中， 并不限于上述实现步骤， 本领域技术人员可以知道， 不同模式下， 上 述图形的形成过程可以稍微有差别， 如步骤的顺序调整； 或者上述刻蚀工艺 的步骤的合并， 都可以实现具有狭缝结构的保护层以及钝化层的图形。
进一步的， 例如， 薄膜晶体管采用顶栅结构时， 可以在阵列基板上依次 形成半导体层、源 /漏电极和数据线的图形； 然后再在形成有源 /漏电极和数据 线的基板上依次形成栅绝缘层薄膜以及栅极和栅线的图形； 在形成有栅极和 栅线的图形上形成保护层，利用构图工艺对保护层和栅绝缘层薄膜进行构图， 形成狭缝结构的保护层和栅绝缘层（该顶栅结构中，钝化层由栅绝缘层形成 )， 所述狭缝结构中的狭缝对应像素电极的区域， 所述狭缝结构中的保护层图形 对应公共电极的图形。
如图 7所示，在形成有保护层和钝化层图形的基板上形成透明导电薄膜; 所述透明导电薄膜用于形成公共电极和像素电极； 该透明导电薄膜经过一次 成膜工艺，就可得到位于保护层上的公共电极 20以及位于狭缝结构中的狭缝 区域的像素电极 19; 且由于保护层图形的底部覆盖钝化层的顶部， 且钝化层 与保护层形成刻蚀倒角， 即保护层的横截面的宽度比钝化层的横截面的宽度 要宽， 因此， 在形成透明导电薄膜时， 位于保护层上的公共电极 20与位于狭 缝结构的狭缝区域中的像素电极 19 不会产生交叠， 且在水平位置是交错分 布， 因此， 公共电极与像素电极之间的零交叠可以使存储电容最小化， 从而 保证画面品质；
且相对于传统的阵列基板的制作工艺， 分别进行像素电极以及公共电极 的制作， 本发明的实施例中减少了制作工艺， 缩短了制作过程， 提高阵列基 板的制作效率。
如图 8所示， 在形成像素电极和公共电极之后， 还可以包括：
通过构图工艺对所述薄膜晶体管 （半导体层、 源极、 漏极） 上方的透明 导电薄膜去除， 以得到最终的公共电极和像素电极的图形， 这样半导体上方 的透明导电薄膜属于公共电极的一部分， 存在于薄膜晶体管上方， 会对薄膜 晶体管产生信号干扰增加薄膜晶体管的负载， 且会产生一些不需要的寄生电 容， 例如增大 Cdc等， 去除后可以将对薄膜晶体管的不良影响降至最低。
综上， 本发明的上述实施例可以应用于 ADS模式的 TFT阵列基板， 通 过一次成膜工艺同时制作公共电极和像素电极的金属层， 并形成具有狭缝结 构的像素电极和公共电极， 使公共电极与像素电极为零交叠， 从而避免了公 共电极与像素电极之间的存储电容， 保证画面品质；
且相对于传统的阵列基板的制作工艺， 分别进行像素电极以及公共电极 的制作， 本发明的实施例中减小了制作工艺， 缩短了制作过程， 提高阵列基 板的制作效率。
另外， 如图 8所示， 本发明的实施例还提供一种阵列基板， 该阵列基板 采用如上述方法实施例制作得到， 该阵列基板包括：
基板 11 ; 以及形成于所述基板上的狭缝结构的公共电极 20， 以及与所述 公共电极 20零交叠的狭缝结构的像素电极 19。
所述阵列基板包括底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管； 其中， 底栅结构薄膜晶体管包括： 形成于所述基板 11 上的栅极 12、 栅 线、 栅绝缘层 13， 以及形成于所述栅绝缘层 13上的半导体层 14、 数据线、 源极 15、 漏极 16; 所述基板上还具有： 形成于所述半导体层 14、 源极 15、 漏极 16之上的狭缝结构的保护层和钝化层的图形；
而顶栅结构的薄膜晶体管包括： 形成于所述基板上的半导体层、数据线、 源 /漏极，以及依次形成于源 /漏电极和数据线上的栅绝缘层薄膜、栅极和栅线； 所述基板上还形成有位于所述栅极、 栅线上的保护层， 利用构图工艺对 保护层和栅绝缘层薄膜进行构图以形成狭缝结构的保护层和栅绝缘层的图 形， 且所述保护层和栅绝缘层为叠层结构；
如图 8所示， 在保护层和钝化层的叠层结构中， 保护层的横截面的宽度 比钝化层宽； 这样可以使用于制作公共电极和像素电极的透明导电薄膜经过 一次沉积，就可得到位于保护层上方的公共电极 20以及位于狭缝区域的像素 电极 19; 且省去了公共电极的刻蚀以及像素电极的刻蚀工艺， 且由于保护层 图形的底部覆盖钝化层的顶部， 因此， 在沉积透明导电薄膜时， 位于保护层 上的公共电极 20与位于栅绝缘层上的像素电极 19不会产生交叠， 因此， 避 免了公共电极与像素电极之间的存储电容， 保证画面品质。
在顶栅结构中， 狭缝结构的钝化层由栅绝缘层形成， 栅极处于栅绝缘层 和保护层之间； 在保护层和栅绝缘层的叠层结构中， 保护层的横截面的宽度 要比栅绝缘层的宽； 也可以使用于制作公共电极和像素电极的透明导电薄膜 经过一次成膜，就可得到位于保护层上方的公共电极 20以及位于狭缝区域的 像素电极 19; 且省去了公共电极的刻蚀以及像素电极的构图工艺， 且由于保 护层图形的底部覆盖栅绝缘层的顶部， 因此， 在制备透明导电薄膜时， 位于 保护层上的公共电极 20与位于栅绝缘层上的像素电极 19不会产生交叠， 因 此， 避免了公共电极与像素电极之间的存储电容， 保证画面品质。
上述阵列基板的实施例中， 无论上述底栅结构还是顶栅结构中， 像素电 极与漏极直接搭接。所述狭缝结构的公共电极 20位于所述保护层图形上； 所 述狭缝结构的像素电极 19形成于所述狭缝结构中的狭缝区域； 也就是说， 所 述像素电极与所述公共电极之间形成有钝化层 （或栅绝缘层） 和保护层。 另 外， 公共电极和像素电极在制作时， 可以将制作公共电极和像素电极的透明 导电薄膜经过一次沉积，就可得到位于保护层上方的公共电极 20以及位于狭 缝区域的像素电极 19; 且省去了公共电极的刻蚀以及像素电极的刻蚀工艺， 且由于保护层图形的底部覆盖钝化层 （或栅绝缘层） 的顶部， 因此， 在沉积 透明导电薄膜时， 位于保护层上的公共电极 20 与位于狭缝区域的像素电极 19不会产生交叠， 因此， 避免了公共电极与像素电极之间的存储电容， 保证 画面品质。
在上述阵列基板的实施例中， 所述保护层的材料可以选用有机感光树脂 材料或者无机绝缘树脂材料。 所述公共电极 20与所述像素电极 19采用相同 的金属材料制成。 该阵列基板的实施例同样通过形成具有狭缝结构的像素电 极和公共电极， 使公共电极与像素电极为零交叠， 从而避免了公共电极与像 素电极之间的存储电容， 保证画面品质。
在本发明实施例中， 对于所述薄膜的形成工艺， 有化学气相沉积、 蒸镀、 磁控溅射等半导体成膜的常用方法， 另外， 在光刻胶的形成过程中可以旋涂、 喷涂、 转印等方法进行， 上述具体薄膜成膜方法或者光刻胶形成方法为本领 域工程师可以根据具体的设备或者产品设计进行自由选择。
本发明的实施例还提供一种显示装置， 包括如上所述的阵列基板。其中， 该显示装置使用了如上述实施例所述的任意一种阵列基板。 所述显示装置可 以为： 液晶面板、 电子纸、 OLED面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
以上所述是本发明的优选实施方式， 应当指出， 对于本技术领域的普通 技术人员来说， 在不脱离本发明所述原理的前提下， 还可以作出若干改进和 润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

权利要求书
1 . 一种阵列基板的制备方法， 其特征在于， 包括：
在基板上形成狭缝结构的公共电极， 以及与所述公共电极零交叠的狭缝 结构的像素电极。
2. 根据权利要求 1所述的阵列基板的制备方法， 其特征在于， 在基板上 形成狭缝结构的公共电极， 以及与所述公共电极零交叠的狭缝结构的像素电 极的步骤包括：
在基板上形成栅极、 栅线、 栅绝缘层、 半导体层、 数据线、 源 /漏极； 在形成有栅极、 栅线、 栅绝缘层、 半导体层、 数据线、 源 /漏极的基板上 形成狭缝结构的保护层和钝化层的图形；
在形成有所述保护层和钝化层的图形的基板上， 形成透明导电薄膜， 所 述透明导电薄膜用于形成位于所述保护层上的狭缝结构的公共电极， 以及位 于所述保护层和钝化层的狭缝结构中的狭缝区域的像素电极， 其中所述像素 电极与漏极直接搭接。
3. 根据权利要求 2所述的阵列基板的制备方法， 其特征在于， 在形成有 栅极、 栅线、 栅绝缘层、 半导体层、 数据线、 源 /漏极的基板上形成狭缝结构 的保护层和钝化层的图形的步骤包括：
形成钝化层；
在所述钝化层上形成保护层；
对所述保护层以及所述钝化层进行构图， 得到具有狭缝结构的保护层和 钝化层的图形。
4. 根据权利要求 3所述的阵列基板的制备方法， 其特征在于， 对所述保 护层以及所述钝化层进行构图， 得到具有狭缝结构的保护层和钝化层的图形 的步骤包括：
在所述保护层上形成光刻胶；
利用普通构图工艺， 依次对所述保护层和钝化层进行刻蚀， 得到具有狭 缝结构的保护层和钝化层的图形。
5. 根据权利要求 4所述的阵列基板的制备方法， 其特征在于， 所述保 护层为无机绝缘树脂材料。
6. 根据权利要求 3所述的阵列基板的制备方法， 其特征在于， 对所述保 护层以及所述钝化层进行构图， 得到具有狭缝结构的保护层和钝化层的图形 的步骤包括：
通过曝光、 显影工艺形成狭缝结构的保护层；
直接对狭缝结构暴露出的钝化层进行刻蚀， 得到具有狭缝结构的保护层 和钝化层的图形。
7. 根据权利要求 6所述的阵列基板的制备方法， 其特征在于， 所述保 护层为有机感光树脂材料。
8. 根据权利要求 1所述阵列基板的制备方法， 其特征在于， 在基板上形 成有狭缝结构的公共电极， 以及与所述公共电极零交叠的狭缝结构的像素电 极的步骤包括：
在基板上依次形成半导体层、 源 /漏极和数据线的图形；
在形成有半导体层、 源 /漏电极和数据线的图形的基板上， 依次形成栅绝 缘层薄膜以及栅极和栅线的图形；
在形成有栅绝缘层薄膜、 栅极和栅线的图形的基板上形成保护层； 利用构图工艺对保护层和栅绝缘层薄膜进行构图， 形成狭缝结构的保护 层和栅绝缘层的图形；
在形成有所述保护层和栅绝缘层的图形的基板上， 形成透明导电薄膜， 所述透明导电薄膜用于形成位于所述保护层上的狭缝结构的公共电极， 以及 位于所述保护层和栅绝缘层的狭缝结构中的狭缝区域的像素电极， 其中所述 像素电极与漏极直接搭接。
9. 根据权利要求 2或 8所述的阵列基板的制备方法， 其特征在于， 形成 透明导电薄膜后还包括：
通过构图工艺对所述半导体层、 源 /漏极上方的透明导电薄膜去除， 得到 最终的公共电极和像素电极的图形。
10. 一种阵列基板， 其特征在于， 包括：
基板； 以及
形成于所述基板上的狭缝结构的公共电极， 以及与所述公共电极零交叠 的狭缝结构的像素电极。
11 . 根据权利要求 10所述的阵列基板， 其特征在于， 所述阵列基板包括 底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管。
12. 根据权利要求 11所述的阵列基板， 其特征在于， 所述底栅结构的薄 膜晶体管包括： 形成于所述基板上的栅极、 栅线、 栅绝缘层， 以及形成于所 述栅绝缘层上的半导体层、 数据线、 源 /漏极；
所述基板上还形成有位于所述半导体层、 源 /漏极之上的狭缝结构的保护 层和钝化层的图形， 且所述保护层和钝化层为叠层结构。
13. 根据权利要求 12所述的阵列基板， 其特征在于， 在保护层和钝化层 的叠层结构中， 保护层横截面的宽度比钝化层宽。
14. 根据权利要求 11所述的阵列基板， 其特征在于， 所述顶栅结构的薄 膜晶体管包括： 形成于所述基板上的半导体层、 数据线、 源 /漏极， 以及依次 形成于源 /漏电极和数据线上的栅绝缘层薄膜、 栅极和栅线；
所述基板上还形成有位于所述栅极、 栅线上的保护层， 利用构图工艺对 保护层和栅绝缘层薄膜进行构图以形成狭缝结构的保护层和栅绝缘层的图 形， 且所述保护层和栅绝缘层为叠层结构。
15. 根据权利要求 14所述的阵列基板， 其特征在于， 在保护层和栅绝缘 层的叠层结构中， 保护层的横截面的宽度比栅绝缘层宽。
16. 根据权利要求 12或 13所述的阵列基板， 其特征在于， 所述狭缝结 构的公共电极位于所述保护层图形上； 所述狭缝结构的像素电极形成于所述 保护层和钝化层的所述狭缝结构中的狭缝区域， 其中所述像素电极与漏极直 接搭接。
17. 根据权利要求 14或 15所述的阵列基板， 其特征在于， 所述狭缝结 构的公共电极位于所述保护层图形上； 所述狭缝结构的像素电极形成于所述 保护层和栅绝缘层的所述狭缝结构中的狭缝区域， 其中所述像素电极与漏极 直接搭接。
18. 根据权利要求 12-17 中任一项所述的阵列基板， 其特征在于， 所述 保护层采用无机绝缘树脂材料或者有机感光树脂材料制成。
19. 一种显示装置， 其特征在于， 包括如权利要求 10— 18任一项所述的 阵列基板。
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