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WO2014201730A1 - 掩膜板和阵列基板的制作方法 - Google Patents

掩膜板和阵列基板的制作方法 Download PDF

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Publication number
WO2014201730A1
WO2014201730A1 PCT/CN2013/078589 CN2013078589W WO2014201730A1 WO 2014201730 A1 WO2014201730 A1 WO 2014201730A1 CN 2013078589 W CN2013078589 W CN 2013078589W WO 2014201730 A1 WO2014201730 A1 WO 2014201730A1
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WO
WIPO (PCT)
Prior art keywords
fan
line width
lines
predetermined line
impression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/078589
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English (en)
French (fr)
Inventor
郑华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to JP2016520232A priority Critical patent/JP6246916B2/ja
Priority to GB1522338.1A priority patent/GB2529790B/en
Priority to RU2016101271A priority patent/RU2619817C1/ru
Priority to US13/985,286 priority patent/US9110375B2/en
Priority to KR1020167000363A priority patent/KR101708158B1/ko
Publication of WO2014201730A1 publication Critical patent/WO2014201730A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • H10W20/01—
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0005—Production of optical devices or components in so far as characterised by the lithographic processes or materials used therefor
    • G03F7/0007—Filters, e.g. additive colour filters; Components for display devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks

Definitions

  • the present invention relates to the field of display manufacturing, and in particular to a mask, and to a method of fabricating an array substrate.
  • Display panel for manufacturing displays including LCD (Liquid Crystal) Display, liquid crystal display panels and OLED (Organic Light-Emitting Diode) panels all require a photolithography process to form a circuit.
  • LCD Liquid Crystal
  • OLED Organic Light-Emitting Diode
  • the photolithography process mainly includes four steps of photoresist coating, exposure, photoresist development and etching. After forming a metal layer on the glass substrate, photoresist coating is started, and a photoresist layer is formed on the metal layer; then the photoresist layer is exposed; after the exposed photoresist layer is developed, the photoresist layer is formed in advance.
  • the circuit pattern is designed; finally, the metal layer is etched, the metal without photoresist protection is etched away, and the remaining metal forms the circuit.
  • the display panel includes a valid display area (AA, Active) Area) and the non-effective display area surrounding the effective display area.
  • the effective display area has various signal traces, such as scan lines and data lines.
  • the non-effective county has fan-out leads, and the fan-out leads are connected to the above signals. The other end is connected to the peripheral driver chip.
  • FIG. 1 it is a schematic structural view of a display panel of the prior art, and the fan-out leads are also enlarged in the figure. Since the fan-out lead corresponds to the connection signal trace, when the signal is transmitted, the fan-out lead will act as a signal load.
  • the effective length of the peripheral fan-out lead is greater than the intermediate fan-out lead, and the peripheral fan
  • the resistance of the lead wire will be larger than the middle fan lead wire, so that different signal wires have different loads, which will affect the signal transmission, resulting in uneven display of the image of the display. This phenomenon is called display unevenness (Fanout). Mura) phenomenon.
  • the fan-out leads in the middle are bent, which in turn increases the effective length of the intermediate fan-out leads and reduces the difference in resistance from the peripheral fan-out leads.
  • Part (a) is a desired shape in which the fan-out lead forms a front curved portion, and the line width of the curved portion is equal to the line width elsewhere.
  • Part (b) is the actual shape of the bent portion after the fan-out lead is formed under the existing photolithography process, and the line width of the curved portion is larger than the line width elsewhere.
  • the reason for this is that in the exposure step, the optical path is difficult to achieve complete collimation, there will be a small amount of lateral light, and the exposed area will simultaneously illuminate the collimated light and the lateral light, but the part (b) of the A
  • the A area is surrounded by three sides, that is, the A area has three sides that are not irradiated with the lateral light, and the other exposed areas can illuminate the collimated light and the lateral light, so
  • the photosensitive intensity of the A region is weaker than that of the other exposed regions, and the chemical reaction of the photoresist is slow, which causes the development speed and etching speed of the A region to be slower than other exposed regions during the subsequent development and etching steps, and finally the curved portion of the fan lead is bent.
  • the area of the A region is increased, the line width of the curved portion of the fan-out lead is increased, and the resistance is correspondingly small, causing the resistance difference to further increase.
  • a primary object of the present invention is to provide a mask and an array substrate manufacturing method capable of reducing a difference in resistance between fan-out leads.
  • a technical solution adopted by the present invention is to provide a mask for fabricating fan-out leads in an ineffective display area on an array substrate, the mask comprising a fan-out lead pattern and a fan-out lead
  • the pattern has a plurality of fan-out impression lines, the effective lengths of the plurality of fan-out impression lines are equal, each fan-out impression line has a predetermined line width, and at least a part of the fan-out impression lines of the plurality of fan-out impression lines have at least A curved portion, the plurality of curved portions are continuously arranged in an S shape, and a line width of the curved portion of the same fan-out impression line is smaller than the predetermined line width of the fan-out impression line.
  • the predetermined line widths of the fan-out impression lines are equal.
  • the predetermined line width of the fan-out impression line in the middle of the fan-out lead pattern is smaller than the predetermined line width of the fan-out impression line at the edge of the fan-out lead pattern.
  • the predetermined line width of the plurality of fan-out impression lines gradually increases in the direction from the middle to the edge of the fan-out lead pattern.
  • another technical solution adopted by the present invention is to provide a mask for fabricating fan-out leads in an ineffective display area on an array substrate, the mask comprising a fan-out lead pattern, fan-out
  • the lead pattern has a plurality of fan-out impression lines, each of the fan-out impression lines has a predetermined line width, and at least a portion of the plurality of fan-out impression lines have at least one curved portion and the same fan-out impression line
  • the line width of the curved portion is smaller than the predetermined line width of the fan-out impression line.
  • the plurality of curved portions are arranged in an S-shape in a continuous manner.
  • the predetermined line widths of the fan-out impression lines are equal.
  • the predetermined line width of the fan-out impression line in the middle of the fan-out lead pattern is smaller than the predetermined line width of the fan-out impression line at the edge of the fan-out lead pattern.
  • the predetermined line width of the plurality of fan-out impression lines gradually increases in the direction from the middle to the edge of the fan-out lead pattern.
  • the effective lengths of the plurality of fan-out impression lines are equal.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: providing a glass substrate, sequentially forming a metal layer and a photoresist layer on the glass substrate; providing any of the above The mask plate is used to expose the glass substrate by using a mask plate, wherein the exposure speed of the photoresist layer corresponding to the position of the curved portion is smaller than the exposure speed of the other position; the glass substrate is developed and transferred on the photoresist layer.
  • a development speed of the position of the photoresist layer corresponding to the curved portion is smaller than a development speed of the other position; etching the metal layer to form a fan-out lead on the glass substrate, wherein the metal layer corresponds to the position of the curved portion
  • the etching speed is lower than the etching speed at other positions such that the line width of the fan-out lead corresponding to the curved portion is less than or equal to a predetermined line width.
  • the photoresist layer is formed by a positive photoresist, and the fan-out lead pattern is a non-hollow pattern.
  • the photoresist layer is formed by a negative photoresist, and the fan-out lead pattern is a hollow pattern.
  • the line width of the curved portion of the fan-out impression line is smaller than the predetermined line width of the fan-out impression line, and the photosensitive strength of the position of the photoresist layer corresponding to the curved portion is obtained. Further, the exposure intensity is smaller than that of other positions, and after development and etching, the line width of the corresponding curved portion of the fan-out lead can be made smaller than or equal to a predetermined line width, which can reduce the difference in resistance between the fan-out leads and eliminate display unevenness. .
  • FIG. 1 is a schematic structural view of a display panel of the prior art, and the fan-out leads are also enlarged in the figure;
  • FIG. 3 is a schematic structural view of an embodiment of a mask according to the present invention.
  • Figure 4 is an enlarged schematic view showing a fan-out stamp line on the mask shown in Figure 3;
  • FIG. 5 is a schematic flow chart of an embodiment of a method for fabricating an array substrate of the present invention.
  • Fig. 6 is a view showing the effect of performing an exposure step and a developing step on the photoresist layer on the glass substrate in the manufacturing method shown in Fig. 5.
  • FIG. 3 is a schematic structural view of an embodiment of a mask according to the present invention.
  • 4 is an enlarged schematic view showing a fan-out stamp line on the mask shown in FIG.
  • the mask 30 is used to fabricate fan-out leads in the ineffective display area on the array substrate.
  • the masking plate 30 includes a fan-out lead pattern 31 corresponding to the fan-out lead in the non-effective display area, that is, the exposure is performed by the mask 31, and the fan-out lead pattern 31 can be turned into a fan-out lead. pattern.
  • the fan-out lead pattern 31 has a fan shape, and the formed fan-out leads are also fan-shaped.
  • the fan-out lead pattern 31 has a plurality of fan-out stamp lines 310, each fan-out stamp line 310 has a predetermined line width L1, and the predetermined line width L1 refers to a line width conforming to a design value. At least a portion of the fan-out impression lines 310 of the plurality of fan-out impression lines 310 have at least one curved portion 311. Since the fan-out impression lines 310 correspond to the fan-out leads, the length of the fan-out impression lines 310 determines the fan-out. The length of the lead, if the effective length of each of the fan-out stamp lines 310 is inconsistent, the effective length of each of the fan-out leads is inconsistent, resulting in an increase in the resistance difference between the fan-out leads.
  • the curved portion 311 can increase the effective length of the fan-out impression line 310. In the present embodiment, the effective lengths of the plurality of fan-out impression lines 310 are equal.
  • the line width L2 of the curved portion 311 of the same fan-out stamp line 310 is smaller than the predetermined line width L1 of the fan-out stamp line 310.
  • the line width of each position thereof is a predetermined line width L1.
  • the plurality of curved portions 311 are continuously arranged in an S shape (as shown in FIG. 4).
  • the predetermined line width L1 of each fan-out stamp line 310 may take the same value or may take a different value. In the present embodiment, the predetermined line widths L1 of the respective fan-out stamp lines 310 are equal. In other embodiments, the predetermined line width L1 of the fan-out impression line 310 in the middle of the fan-out lead pattern 31 is smaller than the predetermined line width L1 of the fan-out impression line 310 at the edge of the fan-out lead pattern 31. Specifically, the predetermined line width L1 of the plurality of fan-out stamp lines 310 gradually increases in the direction toward the edge of the fan-out lead pattern 31.
  • the effective length of the fan-out stamp line 310 in the middle of the fan-out lead pattern 31 is smaller than the effective length of the fan-out stamp line 310 at the edge of the fan-out lead pattern 31, if the fan-out stamp in the middle of the lead pattern 31 is fanned out
  • the predetermined line width L1 of the line 310 is smaller than the predetermined line width L1 of the fan-out stamp line 310 at the edge of the fan-out lead pattern 31, and the formed fan-out lead has a unit length resistance in the middle portion larger than the unit length resistance at the edge, which can be reduced. The difference in resistance between the fan-out leads.
  • FIG. 5 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention.
  • the production method includes the following steps:
  • Step S51 providing a glass substrate, and sequentially forming a metal layer and a photoresist layer on the glass substrate.
  • the metal layer may be formed by a deposition process or the like, and the photoresist layer may be formed by a coating process or the like.
  • Step S52 providing a mask for exposing the glass substrate by using a mask, wherein the exposure speed of the photoresist layer corresponding to the position of the curved portion is smaller than the exposure speed of the other positions.
  • the mask is the mask 30 of the above embodiment.
  • the photoresist layer is formed of a positive photoresist
  • the fan-out wiring pattern 31 is a non-hollow pattern. That is to say, the photoresist that needs to form the fan-out lead does not need to be irradiated with light.
  • the photosensitive layer corresponding to the curved portion 311 is weak in intensity, so that a part of the photoresist inside the curved portion 311 is chemically weak.
  • FIG. 6 is a comparison view of the effect of the exposure step and the development step of the photoresist layer on the glass substrate in the manufacturing method shown in FIG. 5.
  • Part (a) of the figure is a schematic diagram showing the effect of the exposure step of the photoresist layer.
  • the position of the corresponding curved portion 311 on the photoresist layer that is, the B region, is surrounded by the three-sided photoresist, and the lateral light cannot be irradiated, the photosensitive intensity is weak, and the photoresist of the B region is chemically weak.
  • the reaction is slow and the exposure speed is less than the exposure speed at other locations.
  • Step S53 developing the glass substrate, and transferring a fan-out lead pattern on the photoresist layer, wherein the development speed of the position of the photoresist layer corresponding to the curved portion is smaller than the development speed of the other position.
  • part (b) of Fig. 6 is a schematic view showing the effect of the development step of the photoresist layer. Since the photoresist chemical reaction in the region B in (a) is very slow, the chemical properties thereof are substantially unchanged, and the development speed is slow in development and is not washed away by the developer, and this portion of the photoresist is retained. Thereby, the photoresist of the portion (b) corresponds to an increase in the line width of the curved portion 311.
  • Step S54 etching the metal layer to form a fan-out lead on the glass substrate, wherein the etching speed of the metal layer corresponding to the position of the curved portion is smaller than the etching speed of the other position, so that the line width of the fan-out lead corresponding to the curved portion is less than or Equal to the predetermined line width.
  • the etching of the metal protected by the B region is slow at the time of etching, and the pattern of the remaining metal is the same as that of the fan-out lead pattern 31, and
  • the line width of the fan-out lead corresponding to the curved portion 311 is less than or equal to the predetermined line width L1, so that the difference in resistance between the fan-out leads will be reduced, and display unevenness can be eliminated.
  • the photoresist layer may be formed of a negative photoresist and the fan-out lead pattern 31 is a hollow pattern. Regardless of whether it is a positive photoresist or a negative photoresist, the photoresist of the B region is retained, so that the line widths of the respective portions of the fan-out leads on the array substrate are equal, and even the line width of the fan-out lead corresponding to the curved portion 311 is smaller than The line width is reserved.
  • the line width of the curved portion of the fan-out impression line is smaller than the predetermined line width of the fan-out impression line, and the photosensitive strength of the position of the photoresist layer corresponding to the curved portion is
  • the exposure light intensity smaller than other positions can make the line width of the corresponding curved portion of the fan-out lead less than or equal to the predetermined line width after development and etching, and can reduce the difference in resistance between the fan-out leads and eliminate display unevenness.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Engineering & Computer Science (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Lead Frames For Integrated Circuits (AREA)

Abstract

一种掩膜板和阵列基板的制作方法被公开。掩膜板（30）用于制作阵列基板上非有效显示区内的扇出引线，其包括扇出引线图案（31），扇出引线图案（31）具有多条扇出印模线（310）。各扇出印模线（310）具有预定线宽（L1），多条扇出印模线（310）中至少部分扇出印模线（310）具有至少一个弯曲部分（311），并且同一扇出印模线（310）的弯曲部分（311）的线宽（L2）小于扇出印模线（310）的预定线宽（L1）。利用这种掩膜板制作阵列基板，能够减小扇出引线之间的电阻差，消除显示不均匀现象。

Description

掩膜板和阵列基板的制作方法
【技术领域】
本发明涉及显示器制造领域，特别是涉及一种掩膜板，还涉及一种阵列基板的制作方法。
【背景技术】
用于制造显示器的显示面板，包括LCD（Liquid Crystal Display，液晶显示）面板和OLED（Organic Light-Emitting Diode，有机发光二极管）面板，都需要通过光刻工艺形成电路。
光刻工艺主要包括光阻涂布、曝光、光阻显影和蚀刻四个步骤。在玻璃基板上形成金属层后，开始光阻涂布，在金属层上形成光阻层；然后对光阻层进行曝光；对曝光后的光阻层进行显影后，光阻层就形成了预先设计的电路图案；最后对金属层进行蚀刻，没有光阻保护的金属被蚀刻掉，剩下的金属就形成了电路。
众所周知，显示面板包括有效显示区（AA，Active Area）和环绕有效显示区的非有效显示区，有效显示区内具有各种信号走线，例如扫描线和数据线，非有效县市区内具有扇出引线，这些扇出引线一端连接上述信号走线，另一端连接外围的驱动芯片。如图1所示，是现有技术一种显示面板的结构示意图，图中还放大示意了扇出引线。由于扇出引线对应连接信号走线，传输信号时，扇出引线将作为信号的负载，如果扇出引线全部为直线，那么外围的扇出引线的有效长度大于中间的扇出引线，外围的扇出引线的电阻就将大于中间的扇出引线，使得不同的信号走线有不同的负载，给信号传输带来影响，造成显示器的图像显示不均匀，这种现象被叫做显示不均匀（Fanout Mura）现象。为了克服这一困难，图中将中间的扇出引线弯曲，也就变相增加了中间的扇出引线的有效长度，减小与外围的扇出引线之间的电阻差。
然而，现有技术在进行光刻工艺时，由于制程能力有限，弯曲的扇出引线往往难以达到预先设计的线宽，造成电阻差进一步增大。请参见图2，是现有技术显示面板上的扇出引线形成前和形成后的效果对比图。（a）部分是扇出引线形成前弯曲部分的期望形状，其弯曲部分的线宽与其他地方的线宽相等。（b）部分是在现有的光刻工艺下扇出引线形成后弯曲部分的实际形状，其弯曲部分的线宽大于其他地方的线宽。造成这样的原因是：在曝光步骤中，光路难以做到完全准直，会有少量的侧向光存在，曝光区域会同时照射到准直光和侧向光，但是对（b）部分的A区域而言，由于扇形引线的图案没有照射光，所以A区域三面被包围，也就是说A区域有三面照射不到侧向光，而其它曝光区域能够照射到准直光和侧向光，所以A区域的感光强度较其它曝光区域弱，光阻的化学反应较慢，这就造成后续进行显影和蚀刻步骤时，A区域的显影速度和蚀刻速度较其它曝光区域慢，最后扇出引线弯曲部分就多出A区域部分，扇出引线弯曲部分线宽增大，电阻就相应变小，造成电阻差进一步增大。
【发明内容】
本发明的主要目的是提供一种掩膜板和阵列基板的制作方法，能够减小扇出引线之间的电阻差。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种掩膜板，用于制作阵列基板上非有效显示区内的扇出引线，掩膜板包括扇出引线图案，扇出引线图案具有多条扇出印模线，多条扇出印模线的有效长度相等，各扇出印模线具有预定线宽，多条扇出印模线中至少部分扇出印模线具有至少一个弯曲部分，多个弯曲部分呈S形连续排布，并且同一扇出印模线的弯曲部分的线宽小于扇出印模线的所述预定线宽。
其中，各扇出印模线的预定线宽相等。
其中，扇出引线图案中部的扇出印模线的预定线宽小于扇出引线图案边缘的扇出印模线的预定线宽。
其中，多条扇出印模线的预定线宽沿扇出引线图案的中部向边缘的方向逐渐增大。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种掩膜板，用于制作阵列基板上非有效显示区内的扇出引线，掩膜板包括扇出引线图案，扇出引线图案具有多条扇出印模线，各扇出印模线具有预定线宽，多条扇出印模线中至少部分扇出印模线具有至少一个弯曲部分，并且同一扇出印模线的弯曲部分的线宽小于扇出印模线的预定线宽。
其中，多个弯曲部分呈S形连续排布。
其中，各扇出印模线的预定线宽相等。
其中，扇出引线图案中部的扇出印模线的预定线宽小于扇出引线图案边缘的扇出印模线的预定线宽。
其中，多条扇出印模线的预定线宽沿扇出引线图案的中部向边缘的方向逐渐增大。
其中，多条扇出印模线的有效长度相等。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制作方法，制作方法包括：提供一玻璃基板，在玻璃基板上依次形成金属层和光阻层；提供上述任一种的掩膜板，利用掩膜板对玻璃基板进行曝光，其中，光阻层对应弯曲部分的位置的曝光速度小于其它位置的曝光速度；对玻璃基板进行显影，在光阻层上转印出扇出引线图案，其中，光阻层对应弯曲部分的位置的显影速度小于其它位置的显影速度；对金属层进行蚀刻，在玻璃基板上形成扇出引线，其中，金属层对应弯曲部分的位置的蚀刻速度小于其它位置的蚀刻速度，以使得扇出引线对应弯曲部分的线宽小于或等于预定线宽。
其中，光阻层由正性光阻形成，扇出引线图案为非镂空图案。
其中，光阻层由负性光阻形成，扇出引线图案为镂空图案。
综上所述，本发明的掩膜板和阵列基板的制作方法中扇出印模线弯曲部分的线宽小于扇出印模线的预定线宽，光阻层对应弯曲部分的位置的感光强度又小于其它位置的曝感光强度，在显影和蚀刻后，能够使扇出引线对应弯曲部分的线宽小于或等于预定线宽，能够减小扇出引线之间的电阻差，消除显示不均匀现象。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
【附图说明】
图1是现有技术一种显示面板的结构示意图，图中还放大示意了扇出引线；
图2是现有技术显示面板上的扇出引线形成前和形成后的效果对比图；
图3是本发明掩膜板一实施例的结构示意图；
图4是图3所示的掩膜板上一条扇出印模线的放大示意图；
图5是本发明阵列基板的制作方法一实施例的流程示意图；
图6是图5所示的制作方法中玻璃基板上的光阻层进行曝光步骤和显影步骤的效果对比图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本发明保护的范围。
请一并参阅图3和图4，图3是本发明掩膜板一实施例的结构示意图。图4是图3所示的掩膜板上一条扇出印模线的放大示意图。
掩膜板30用于制作阵列基板上非有效显示区内的扇出引线。掩膜板30包括扇出引线图案31，扇出引线图案31对应非有效显示区内扇出引线，也就是说，利用掩膜板31进行曝光，扇出引线图案31可以变为扇出引线的图案。扇出引线图案31呈扇形，形成的扇出引线也就呈扇形分布。
扇出引线图案31具有多条扇出印模线310，各扇出印模线310具有预定线宽L1，预定线宽L1是指符合设计值的线宽。多条扇出印模线310中至少部分扇出印模线310具有至少一个弯曲部分311，由于扇出印模线310对应扇出引线，那么扇出印模线310的长度就决定了扇出引线的长度，如果每条扇出印模线310的有效长度不一致，那么每条扇出引线的有效长度就不一致，结果就会导致各扇出引线之间的电阻差增大。而弯曲部分311可以增加扇出印模线310的有效长度。在本实施例中，多条扇出印模线310的有效长度相等。
同一条扇出印模线310的弯曲部分311的线宽L2小于扇出印模线310的预定线宽L1。对于不具有弯曲部分311的扇出印模线310而言，其各个位置的线宽均为预定线宽L1。对于具有两个以上弯曲部分311的扇出印模线310而言，多个弯曲部分311呈S形连续排布（如图4所示）。
每条扇出印模线310的预定线宽L1可以取相同的值，也可取不同的值。在本实施例中，各扇出印模线310的预定线宽L1相等。在其它实施例中，扇出引线图案31中部的扇出印模线310的预定线宽L1小于扇出引线图案31边缘的扇出印模线310的预定线宽L1。特别的，多条扇出印模线310的预定线宽L1沿扇出引线图案31的中部向边缘的方向逐渐增大。在扇出引线图案31中部的扇出印模线310的有效长度小于扇出引线图案31边缘的扇出印模线310的有效长度的情况下，若扇出引线图案31中部的扇出印模线310的预定线宽L1小于扇出引线图案31边缘的扇出印模线310的预定线宽L1，则形成的扇出引线在中部的单位长度电阻大于在边缘的单位长度电阻，可以减小扇出引线之间的电阻差。
请参阅图5，是本发明阵列基板的制作方法一实施例的流程示意图。制作方法包括以下步骤：
步骤S51：提供一玻璃基板，在玻璃基板上依次形成金属层和光阻层。
其中，金属层可以采用沉积等工艺形成，光阻层可采用涂覆等工艺形成。
步骤S52：提供一掩膜板，利用掩膜板对玻璃基板进行曝光，其中，光阻层对应弯曲部分的位置的曝光速度小于其它位置的曝光速度。
其中，掩膜板为上述实施例的掩膜板30。在本实施例中，光阻层由正性光阻形成，扇出引线图案31为非镂空图案。也就是说，需要形成扇出引线的光阻是不需要照射光的。
由于扇出印模线310弯曲部分311的线宽L2小于预定线宽L1，则弯曲部分311对应的光阻层的感光强度较弱，使得弯曲部分311内侧的一部分光阻产生化学反应较弱。例如，请一并参阅图6，是图5所示的制作方法中玻璃基板上的光阻层进行曝光步骤和显影步骤的效果对比图。图中（a）部分为光阻层进行曝光步骤的效果示意图。经过掩膜板30曝光后，光阻层上对应弯曲部分311的位置，即B区域，由于受到三面光阻的包围，不能照射到侧向光，感光强度较弱，B区域的光阻的化学反应缓慢，曝光速度就小于其它位置的曝光速度。
步骤S53：对玻璃基板进行显影，在光阻层上转印出扇出引线图案，其中，光阻层对应弯曲部分的位置的显影速度小于其它位置的显影速度。
其中，进行显影后的光阻如图6中（b）部分所示，（b）部分为光阻层进行显影步骤的效果示意图。由于（a）部分中B区域的光阻化学反应很慢，其化学性质基本没有产生变化，在显影时显影速度很慢，不会被显影液洗去，这部分光阻得以保留。从而（b）部分的光阻对应弯曲部分311的线宽增大。
步骤S54：对金属层进行蚀刻，在玻璃基板上形成扇出引线，其中，金属层对应弯曲部分的位置的蚀刻速度小于其它位置的蚀刻速度，以使得扇出引线对应弯曲部分的线宽小于或等于预定线宽。
其中，由于金属层上剩余的光阻的图案与扇出引线图案31相同，在蚀刻时，被B区域保护的金属蚀刻速度很慢，剩余的金属的图案就与扇出引线图案31相同，并且扇出引线对应弯曲部分311的线宽小于或等于预定线宽L1，从而各扇出引线之间的电阻差将减小，能够消除显示不均匀现象。
在其它实施例中，光阻层可由负性光阻形成，扇出引线图案31为镂空图案。无论为正性光阻还是负性光阻，B区域的光阻都将得以保留，从而阵列基板上的扇出引线各部分的线宽相等，甚至于扇出引线对应弯曲部分311的线宽小于预定线宽。
通过上述方式，本发明的掩膜板和阵列基板的制作方法中扇出印模线弯曲部分的线宽小于扇出印模线的预定线宽，光阻层对应弯曲部分的位置的感光强度又小于其它位置的曝感光强度，在显影和蚀刻后，能够使扇出引线对应弯曲部分的线宽小于或等于预定线宽，能够减小扇出引线之间的电阻差，消除显示不均匀现象。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种掩膜板，用于制作阵列基板上非有效显示区内的扇出引线，其中，所述掩膜板包括扇出引线图案，所述扇出引线图案具有多条扇出印模线，所述多条扇出印模线的有效长度相等，各所述扇出印模线具有预定线宽，所述多条扇出印模线中至少部分所述扇出印模线具有至少一个弯曲部分，多个所述弯曲部分呈S形连续排布，并且同一扇出印模线的所述弯曲部分的线宽小于所述扇出印模线的所述预定线宽。
  2. 根据权利要求1所述的掩膜板，其中，各所述扇出印模线的预定线宽相等。
  3. 根据权利要求1所述的掩膜板，其中，所述扇出引线图案中部的扇出印模线的预定线宽小于所述扇出引线图案边缘的扇出印模线的预定线宽。
  4. 根据权利要求3所述的掩膜板，其中，所述多条扇出印模线的所述预定线宽沿所述扇出引线图案的中部向边缘的方向逐渐增大。
  5. 一种掩膜板，用于制作阵列基板上非有效显示区内的扇出引线，其中，所述掩膜板包括扇出引线图案，所述扇出引线图案具有多条扇出印模线，各所述扇出印模线具有预定线宽，所述多条扇出印模线中至少部分所述扇出印模线具有至少一个弯曲部分，并且同一扇出印模线的所述弯曲部分的线宽小于所述扇出印模线的所述预定线宽。
  6. 根据权利要求5所述的掩膜板，其中，多个所述弯曲部分呈S形连续排布。
  7. 根据权利要求5所述的掩膜板，其中，各所述扇出印模线的预定线宽相等。
  8. 根据权利要求5所述的掩膜板，其中，所述扇出引线图案中部的扇出印模线的预定线宽小于所述扇出引线图案边缘的扇出印模线的预定线宽。
  9. 根据权利要求8所述的掩膜板，其中，所述多条扇出印模线的所述预定线宽沿所述扇出引线图案的中部向边缘的方向逐渐增大。
  10. 根据权利要求5所述的掩膜板，其中，所述多条扇出印模线的有效长度相等。
  11. 一种阵列基板的制作方法，其中，所述制作方法包括：
    提供一玻璃基板，在所述玻璃基板上依次形成金属层和光阻层；
    提供一掩膜板，利用所述掩膜板对所述玻璃基板进行曝光，其中，所述光阻层对应所述弯曲部分的位置的曝光速度小于其它位置的曝光速度，所述掩膜板包括扇出引线图案，所述扇出引线图案具有多条扇出印模线，各所述扇出印模线具有预定线宽，所述多条扇出印模线中至少部分所述扇出印模线具有至少一个弯曲部分，并且同一扇出印模线的所述弯曲部分的线宽小于所述扇出印模线的所述预定线宽；
    对所述玻璃基板进行显影，在所述光阻层上转印出所述扇出引线图案，其中，所述光阻层对应所述弯曲部分的位置的显影速度小于其它位置的显影速度；
    对所述金属层进行蚀刻，在所述玻璃基板上形成所述扇出引线，其中，所述金属层对应所述弯曲部分的位置的蚀刻速度小于其它位置的蚀刻速度，以使得所述扇出引线对应所述弯曲部分的线宽小于或等于所述预定线宽。
  12. 根据权利要求11所述的制作方法，其中，所述光阻层由正性光阻形成，所述扇出引线图案为非镂空图案。
  13. 根据权利要求11所述的制作方法，其中，所述光阻层由负性光阻形成，所述扇出引线图案为镂空图案。
  14. 根据权利要求11所述的制作方法，其中，多个所述弯曲部分呈S形连续排布。
  15. 根据权利要求11所述的制作方法，其中，各所述扇出印模线的预定线宽相等。
  16. 根据权利要求11所述的制作方法，其中，所述扇出引线图案中部的扇出印模线的预定线宽小于所述扇出引线图案边缘的扇出印模线的预定线宽。
  17. 根据权利要求16所述的制作方法，其中，所述多条扇出印模线的所述预定线宽沿所述扇出引线图案的中部向边缘的方向逐渐增大。
  18. 根据权利要求11所述的制作方法，其中，所述多条扇出印模线的有效长度相等。
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CN104252098B (zh) * 2014-09-18 2019-03-01 京东方科技集团股份有限公司 相移掩膜板及其制作方法、阵列基板及其制作方法
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101442109A (zh) * 2008-08-20 2009-05-27 昆山维信诺显示技术有限公司 一种有机电致发光器件及其引线结构、掩模板、驱动芯片
US20100258820A1 (en) * 2009-04-09 2010-10-14 Dong-Gyu Kim Manufacturing method for contact pads of a thin film transistor array panel, and a thin film transistor array panel having such contact pads
CN102495524A (zh) * 2011-09-05 2012-06-13 友达光电股份有限公司 光罩、平面显示面板的导线的制作方法以及平面显示面板的导线结构
CN102944974A (zh) * 2012-10-26 2013-02-27 北京京东方光电科技有限公司 一种掩膜板及阵列基板的制造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04115254A (ja) * 1990-09-05 1992-04-16 Kyodo Printing Co Ltd サイドエッチの補正方法
JP3286225B2 (ja) * 1997-10-22 2002-05-27 株式会社東芝 パターン設計方法
US6218203B1 (en) * 1999-06-28 2001-04-17 Advantest Corp. Method of producing a contact structure
JP3327394B2 (ja) * 1999-10-25 2002-09-24 日本電気株式会社 光近接効果補正方法
JP2002148780A (ja) * 2000-11-15 2002-05-22 Mitsui Mining & Smelting Co Ltd マスクパターン生成装置、マスクパターン生成方法、その方法をコンピュータに実行させるプログラムを記録したコンピュータ読み取り可能な記録媒体およびフォトマスク
CN100378984C (zh) * 2005-09-23 2008-04-02 中芯国际集成电路制造(上海)有限公司 恒温电迁移测试结构及其圆角光学邻近修正方法
CN100538804C (zh) * 2005-10-21 2009-09-09 友达光电股份有限公司 显示面板
KR20070045751A (ko) * 2005-10-28 2007-05-02 엘지.필립스 엘시디 주식회사 포토 마스크
US20070216845A1 (en) * 2006-03-16 2007-09-20 Chia-Te Liao Uniform impedance conducting lines for a liquid crystal display
US7932470B2 (en) * 2006-09-05 2011-04-26 Mitsui Mining & Smelting Co., Ltd. Printed wiring board
JP2008047904A (ja) * 2007-08-10 2008-02-28 Hitachi Ltd 半導体装置
KR100912804B1 (ko) * 2007-12-05 2009-08-18 삼성에스디아이 주식회사 플라즈마 디스플레이 패널 및 플라즈마 디스플레이 패널의격벽 형성 방법
JP2009140397A (ja) * 2007-12-10 2009-06-25 Shinko Electric Ind Co Ltd 自動配線設計方法およびそのコンピュータプログラム
CN101794558A (zh) * 2009-02-03 2010-08-04 友达光电股份有限公司 有源器件阵列基板及显示面板
KR20100109771A (ko) * 2009-04-01 2010-10-11 삼성전자주식회사 림 영역을 가진 투과율 조절형 위상 반전 포토마스크 및 그 제조 방법
KR101627245B1 (ko) * 2009-05-11 2016-06-07 삼성디스플레이 주식회사 팬아웃 배선을 포함하는 표시장치
CN102243383A (zh) * 2010-05-10 2011-11-16 瀚宇彩晶股份有限公司 扇出信号线结构及显示面板
KR101771562B1 (ko) * 2011-02-14 2017-08-28 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법
US20140103480A1 (en) * 2012-10-17 2014-04-17 Shenzhen China Star Optoelectronics Technology Co Mask, TFT Glass Substrate and the Manufacturing Method Thereof
CN103050379B (zh) * 2012-12-10 2015-03-04 华映视讯（吴江）有限公司 窄间距线路的形成方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101442109A (zh) * 2008-08-20 2009-05-27 昆山维信诺显示技术有限公司 一种有机电致发光器件及其引线结构、掩模板、驱动芯片
US20100258820A1 (en) * 2009-04-09 2010-10-14 Dong-Gyu Kim Manufacturing method for contact pads of a thin film transistor array panel, and a thin film transistor array panel having such contact pads
CN102495524A (zh) * 2011-09-05 2012-06-13 友达光电股份有限公司 光罩、平面显示面板的导线的制作方法以及平面显示面板的导线结构
CN102944974A (zh) * 2012-10-26 2013-02-27 北京京东方光电科技有限公司 一种掩膜板及阵列基板的制造方法

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