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WO2014117443A1 - 氧化物薄膜晶体管阵列基板及其制作方法、显示面板 - Google Patents

氧化物薄膜晶体管阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2014117443A1
WO2014117443A1 PCT/CN2013/074651 CN2013074651W WO2014117443A1 WO 2014117443 A1 WO2014117443 A1 WO 2014117443A1 CN 2013074651 W CN2013074651 W CN 2013074651W WO 2014117443 A1 WO2014117443 A1 WO 2014117443A1
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Prior art keywords
patterning process
oxide
active layer
source electrode
connection structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2013/074651
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English (en)
French (fr)
Inventor
操彬彬
杨成绍
周伯柱
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP13848102.3A priority Critical patent/EP2953165B1/en
Priority to JP2015555539A priority patent/JP6227674B2/ja
Priority to US14/354,215 priority patent/US9502575B2/en
Priority to KR1020147016237A priority patent/KR20140108641A/ko
Publication of WO2014117443A1 publication Critical patent/WO2014117443A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H10P14/3434—

Definitions

  • the present disclosure relates to an oxide thin film transistor, a method of fabricating the same, and a display panel. Background technique
  • An oxide active layer such as indium gallium zinc oxide (IGZO) as an active layer, has a carrier mobility of 20-30 times that of amorphous silicon.
  • the oxide active layer can greatly improve the charging and discharging rate of the TFT electrode to the pixel electrode, improve the response speed of the pixel, and achieve a faster refresh rate, and is used for a new generation of TFT-LCD (Thin Film Transistor Liquid Crystal Display). Effect transistor liquid crystal display) channel layer material in the technology.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the source-drain electrodes and the oxide active layer are in direct contact in the oxide TFT device.
  • the oxide active layer On both sides of the oxide active layer, there is no PN junction between the oxide active layer and the source and drain electrodes, such that holes of the oxide active layer flow into the source and drain, or the source and drain. Electrons flow into the oxide active layer, which causes an increase in leakage current between the oxide active layer and the source-drain electrodes, causing flicker, crosstalk, and afterimage of the display panel.
  • An embodiment of the present disclosure provides an oxide thin film transistor (TFT) array substrate, including: a substrate substrate, an oxide TFT, a gate line, a data line, and a pixel electrode disposed on the substrate substrate, the oxidation a drain of the TFT is connected to the pixel electrode, wherein a connection structure is disposed between a source of the oxide TFT and the data line, and is electrically connected to each other through the connection structure, and a resistance of the connection structure The rate is greater than the resistivity of the source.
  • TFT oxide thin film transistor
  • connection structure is formed using the same transparent conductive material as the pixel electrode.
  • the oxide TFT includes: a gate insulating layer disposed on the gate line; an oxide active layer disposed on the gate insulating layer and above the gate line; disposed on the oxide An etch stop layer on the active layer; the source and the drain disposed on the etch stop layer, wherein the source and the drain are respectively in contact with the oxide active layer, wherein The grid line is located in the oxygen At least a portion of the active layer of the compound serves as a gate of the oxide TFT.
  • the oxide TFT array substrate further includes: a passivation layer disposed on the substrate substrate on which the pixel electrode is formed; and a common electrode disposed on the passivation layer in the pixel region.
  • the oxide active layer is an indium gallium oxide.
  • the etch barrier layer has a via hole exposing the oxide active layer above the active layer, and the source and the drain pass through the via hole and the oxide Active layer contact.
  • Another embodiment of the present disclosure provides a display panel including an oxide TFT array substrate according to any of the embodiments of the present disclosure.
  • a further embodiment of the present disclosure provides a method of fabricating an oxide thin film transistor (TFT) array substrate, comprising: forming a data line and a source of an oxide TFT to separate the data line and the source from each other, and A connection structure is disposed between the source and the data line, wherein the source and the data line are electrically connected to each other through the connection structure, and a resistivity of the connection structure is greater than a resistivity of the source.
  • TFT oxide thin film transistor
  • the connection structure uses the same transparent conductive material as the pixel electrode.
  • the method includes: forming a pattern including a gate line on a substrate of a village by a first patterning process; forming a grid including a gate on a substrate of the first patterning process by a second patterning process a pattern of the insulating layer and the oxide active layer, wherein the pattern of the oxide active layer is located above the gate line; forming a etch stop layer on the substrate of the substrate through the second patterning process by the third patterning process Forming a data line, a source, and a drain formed on the substrate of the substrate through the third patterning process by the fourth patterning process, wherein the data line and the source are formed to be separated from each other;
  • the five-time patterning process forms a pattern including a pixel electrode and a connection structure at a separation of the source and the drain from each other on the substrate of the fourth patterning process.
  • the method further includes: forming, by the sixth patterning process, a pattern including a passivation layer on the substrate of the fifth patterning process;
  • the sub-patterning process forms a pattern including a common electrode on the substrate of the village through the sixth patterning process.
  • the oxide active layer is an indium gallium oxide.
  • connection structure 21 is provided between the source 15 and the data line 17, the connection structure 21 The resistivity is greater than the resistivity of the source 15, which can increase the resistance between the source 15 and the data line 17, thereby reducing the leakage current of the oxide TFT, and improving the flicker, crosstalk, and afterimage of the display panel. Improve display performance.
  • FIG. 1 is a schematic top plan view of an oxide TFT array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of the oxide TFT array substrate along the grid line taken along line A-A of the present disclosure
  • FIG. 3 is a schematic structural view of a method of fabricating an oxide TFT array substrate according to a first embodiment of the present disclosure
  • FIG. 4 is a schematic structural view of a second fabrication process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural view of a method of fabricating an oxide TFT array substrate according to a third embodiment of the present disclosure
  • FIG. 6 is a schematic structural view of a method of fabricating an oxide TFT array substrate according to a fourth embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of a fifth patterning process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present disclosure
  • FIG. 8 is a schematic structural view of a sixth fabrication process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural view of an oxide TFT array substrate according to another embodiment of the present disclosure. detailed description
  • Embodiments of the present disclosure provide an oxide TFT array substrate.
  • the array substrate includes a substrate substrate 10, an oxide thin film transistor (TFT), a gate line 11, a data line 17, and a pixel electrode 18 which are disposed on the substrate substrate 10.
  • the oxide TFT includes a gate insulating layer 12 on the gate line 11, an oxide active layer 13 on the gate insulating layer 12, a source 15 and a drain 16 on the oxide active layer 13. There is a space between the source 15 and the drain 16, and a portion of the oxide active layer 13 below the interval forms a channel region. At least a portion of the gate line 11 below the channel region serves as a gate of the oxide TFT.
  • the gate line 11 is located below the oxide active layer 13, the source 15 and the drain 16, such that the gate line 11 blocks the oxide in the channel between the source 15 and the drain 16.
  • the source layer can effectively reduce the probability of electron-hole pairs generated during illumination, and greatly reduce the leakage current generated by illumination.
  • the gate line 11 and the data line 17 cross each other to define a pixel area.
  • the pixel electrode 18 may be formed in the pixel region and extend to the drain 16 of the oxide TFT and electrically connected to the drain 16.
  • connection structure 21 is provided between the source 15 and the data line 17.
  • the connection structure 21 is connected to the source 15 and the data line 17, respectively, and the source 15 and the data line 17 are electrically connected to each other through the connection structure 21.
  • the resistivity of the connection structure 21 is greater than the resistivity of the source 15.
  • the source 15 is made of metal
  • the connection structure 21 is made of a transparent conductive material. That is, in the present embodiment, the source 15 and the data line 17 are not directly connected to each other, but are electrically connected to each other through the connection structure 21.
  • connection structure 21 Since the connection structure 21 is disposed between the source 15 and the data line 17, the resistivity of the connection structure 21 is greater than the resistivity of the source 15, so that the resistance between the source 15 and the data line 17 can be effectively increased, thereby reducing The leakage current between the small source 15 and the data line 17 can improve the display quality and stability of the TFT.
  • the arrangement of the oxide TFT, the gate line, the data line, and the pixel electrode is not specifically limited, but various suitable arrangements may be adopted according to actual needs.
  • the array substrate according to the present embodiment may further include other components.
  • the following is an ultra-high dimensional field switching with reference to Figures 1 and 2 (Advanced Dimension
  • the structure of the TFT array substrate is described by taking a single sub-pixel of an oxide TFT array substrate of the ADS type.
  • the gate line 11 is disposed on the substrate substrate 10, the gate insulating layer 12 is disposed on the gate line 11, and the oxide active layer 13 is disposed on the gate insulating layer 12 above the gate line.
  • the oxide TFT array substrate may further include a source on the oxide active layer 13.
  • the gate line 11, the gate insulating layer 12, the oxide active layer 13, the source 15, and the drain 16 constitute an oxide TFT. At least a portion of the gate line 11 under the oxide active layer 13 serves as a gate of the oxide TFT.
  • the oxide TFT may further include an etch barrier layer 14 disposed on the oxide active layer 13, the etch barrier layer 14 being used to prevent formation of a source during fabrication of the oxide TFT array substrate.
  • the oxide active layer 13 in the channel formed between the source 15 and the drain 16 at 15 and the drain 16 is etched.
  • the etch stop layer 14 covers at least the channel region between the source 15 and the drain 16.
  • the other regions of the gate line 11 excluding the regions where the source 15, the drain 16 and the oxide active layer 13 are in contact are exemplarily covered with the etch barrier layer 14 in Fig. 4.
  • the source 15 and the drain 16 are in contact with the oxide active layer 13 through the via holes formed in the barrier layer 14 above the oxide active layer 13, respectively.
  • the pattern of the etch barrier layer 14 may be determined according to the actual fabrication process and requirements, which is not specifically limited in the present disclosure.
  • the source 15 and the drain 16 are respectively in contact with the oxide active layer 13, and the space formed between the source 15 and the drain 16 is located on the etch stop layer 14.
  • the oxide TFT array substrate may further include a data line 17 in the same layer as the source 15 and the drain 16, and a connection structure 21 disposed between the source 15 and the data line 17.
  • the connection structure 21 is connected to the source 15 and the data line 17, respectively, and the source 15 and the data line 17 are connected by a connection structure 21.
  • the oxide TFT array substrate may further include a pixel electrode 18 disposed in the pixel region. Specifically, the gate line 11 and the data line 17 cross each other to define a pixel area, and the pixel electrode 18 is located in the pixel area. The pixel electrode 18 extends to the drain 16, and is connected to the drain 16.
  • the oxide TFT array substrate may further include a passivation layer 19 disposed on the substrate substrate 10 on which the pixel electrode 18 is formed, and a common electrode 20 disposed on the passivation layer 19 in the pixel region.
  • the oxide TFTs in the above FIGS. 1 and 2 are disposed on the gate line 11. Since the gate line metal is a non-transparent metal, the channel of the oxide TFT can be blocked at the same time, thereby reducing the oxide TFT array base. The light leakage current of the board.
  • Figs. 1 and 2 are merely illustrative of the bottom gate structure of the ADS-type oxide TFT array substrate, but the present disclosure is not limited to the TFT array substrate in which the present disclosure is applied only to the bottom gate structure.
  • the present disclosure is also applicable to a TFT array substrate in which the source 15 and the drain 16 and the oxide active layer 13 are in direct contact with each other, such as a top gate structure, which is not specifically limited herein.
  • FIG. 1 and 2 are merely exemplified by the ADS type oxide TFT array substrate, but the present disclosure is not limited to the ADS type oxide TFT array substrate.
  • the present disclosure is also applicable to an oxide TFT array substrate in which a source 15 of a twisted nematic (TN) type, a drain 16 and an oxide active layer 13 are in direct contact, and the present disclosure is not specifically limited herein.
  • TN twisted nematic
  • connection structure 21 may specifically adopt the same transparent conductive material as the pixel electrode 18, such as ITO (Indium tin oxide), thereby forming In the patterning process of the pixel electrode 18, the connection structure 21 can be formed together.
  • ITO Indium tin oxide
  • the oxide active layer 13 is indium gallium oxide (IGZO).
  • connection structure 21 is disposed between the source 15 and the data line 17
  • the resistivity of the connection structure 21 is greater than the resistivity of the source 15, thereby reducing the source.
  • the leakage current generated between the 15 and the data line 17 reduces the leakage current of the oxide TFT, thereby improving the phenomenon of picture flicker, crosstalk, and afterimage of the display panel, thereby improving display performance.
  • the embodiment of the present disclosure further provides a method for fabricating an oxide TFT array substrate, the method comprising: setting a connection between the source 15 and the data line 17 by a patterning process
  • the structure 21, the source 15 and the data line 17 are connected by the connection structure 21, and the connection structure 21 has a resistivity greater than that of the source 15.
  • the patterning process mentioned in the embodiments of the present disclosure includes main processes such as exposure, development, etching, ashing and the like.
  • the method can include the following steps.
  • a pattern including the gate lines 11 is formed on the substrate substrate 10 by the first patterning process.
  • a gate metal layer film is first coated on the substrate substrate 10, and then a photoresist is formed on the substrate substrate 10 coated with the gate metal layer film.
  • a photoresist completely retained region and light are formed.
  • the photoresist completely removes the region; wherein the photoresist completely retains the region corresponding to the gate line 11; the photoresist completely removed region corresponds to a region of the pixel unit other than the photoresist completely reserved region.
  • the gate metal film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process. As shown in FIG. 3, the pattern of the gate line 11 is exposed. A gate line 11 is formed.
  • the pattern of the oxide active layer 13 is located above the gate line 11. Since the gate line metal is a non-transparent metal, the channel of the oxide TFT can be blocked at the same time, thereby reducing the light leakage current of the oxide TFT array substrate.
  • a gate insulating film and an oxide active layer film are first coated on the substrate substrate 10 subjected to the first patterning process. Then, a photoresist is formed on the substrate 10 coated with the gate insulating film and the oxide active layer film.
  • a photoresist completely reserved region and a photoresist completely removed region are formed; wherein the photoresist completely reserved region corresponds to the region of the oxide active layer 13; The photoresist completely removed region corresponds to a region of the pixel unit other than the completely retained region of the photoresist.
  • the oxide active layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process, as shown in FIG. 4, the oxide active is exposed.
  • the pattern of the layer 13 forms the gate insulating layer 12 and the oxide active layer 13.
  • an etch barrier film is first coated on the substrate substrate 10 subjected to the second patterning process, and then lithography is formed on the substrate substrate 10 coated with the etch barrier film. gum.
  • a photoresist completely reserved region and a photoresist completely removed region are formed; wherein the photoresist completely reserved region corresponds to a region of the etch barrier layer 14;
  • the engraved complete removal region corresponds to an area of the pixel unit other than the completely retained region of the photoresist.
  • the etch barrier film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process. As shown in FIG. 5, the etch barrier layer 14 is exposed.
  • the pattern forms an etch stop layer 14.
  • a source/drain metal layer film is coated on the substrate substrate 10 after the third patterning process, and then a photolithography is formed on the substrate substrate 10 coated with the active metal leakage film. gum.
  • a photoresist completely reserved region and a photoresist completely removed region are formed; wherein the photoresist completely reserved region corresponds to the source 15, the drain 16 and the data line 17
  • the photoresist completely removed region corresponds to a region of the pixel unit other than the completely remaining region of the photoresist, including a region of the pattern 22 in which the source 15 and the drain 16 are broken.
  • the source/drain metal layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process. As shown in FIG. 6, the source 15 and the drain are formed. The pattern of the pole 16, the data line 17, and the pattern 22 of the source 15 and drain 16 are broken.
  • a pattern including the pixel electrode 18 and the connection structure 21 on the pattern 22 in which the source and drain are disconnected is formed on the substrate substrate 10 subjected to the fourth patterning process.
  • connection structure 21 and the pixel electrode 18 are made of the same transparent conductive material.
  • a transparent conductive layer film is first coated on the substrate substrate 10 subjected to the fourth patterning process, and then a photoresist is formed on the substrate substrate 10 coated with the transparent conductive film.
  • a photoresist completely reserved region and a photoresist completely removed region are formed; wherein the photoresist completely reserved region corresponds to the region of the pixel electrode 18 and the region of the connection structure 21
  • the photoresist completely removed region corresponds to a region of the pixel unit other than the photoresist completely reserved region.
  • the transparent conductive layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process, as shown in FIG. 7, the pixel electrode is exposed. 18 and the connection structure 21.
  • a passivation layer film is first coated on the substrate substrate 10 subjected to the fifth patterning process, and then a photoresist is formed on the substrate substrate 10 coated with the passivation film.
  • a photoresist completely reserved region and a photoresist completely removed region After exposing and developing the photoresist by using the mask, forming a photoresist completely reserved region and a photoresist completely removed region; wherein the photoresist completely retaining region corresponds to a region of the passivation layer 19;
  • the glue completely removed region corresponds to a region of the pixel unit other than the completely reserved region of the photoresist, and the specific photoresist completely removed region includes a gate line lead via and a data line lead via.
  • the passivation layer film on the completely removed region of the photoresist is removed by an etching process, wherein the gate line via hole also needs to etch the gate insulating film, and then the lithography process is used to strip away the photoresist from the completely reserved region.
  • the glue as shown in FIG. 8, forms a passivation layer 19, gate line via vias, and data line lead vias, wherein the gate line vias and the data line leads are vias (not shown).
  • a pattern including the common electrode 20 is formed on the substrate of the village through the sixth patterning process.
  • a transparent conductive layer film is first coated on the substrate substrate 10 subjected to the sixth patterning process, and then a photoresist is formed on the substrate substrate 10 coated with the transparent conductive layer film.
  • the transparent conductive layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process. As shown in FIG. 2, a passivation layer is formed to form a common electrode. 20.
  • connection structure 21 adopts the same transparent conductive material as the pixel electrode 18, and the connection structure 21 and the pixel electrode 18 may be Formed in a patterning process.
  • this does not limit the connection structure 21 in the present disclosure to only use the same transparent conductive material as the pixel electrode 18.
  • the connection structure 21 can also be made of other materials as long as the resistivity of the material is greater than the resistivity of the source 15. In this case, the connection structure 21 and the pixel electrode 18 need to be completed by two patterning processes. .
  • the method of fabricating the oxide TFT array substrate described in the embodiments of the present disclosure is merely described by way of a seven-time patterning process, but it should not be construed that limiting the present disclosure can only be implemented by the seven-time patterning process.
  • the number of other patterning processes, the method of forming the connection structure 21 between the source 15 and the data line 17, is also within the scope of the present disclosure.
  • connection structure 21 is formed between the source 15 and the data line 17
  • the resistivity of the connection structure 21 is greater than the resistivity of the source 15
  • the leakage current generated between the source 15 and the data line 17 is reduced, thereby reducing the leakage current of the oxide TFT, and the phenomenon of picture flicker, crosstalk, and afterimage of the display panel can be improved, and display performance is improved.
  • the embodiment of the present disclosure further provides a display panel including the oxide TFT array substrate provided by the above embodiments.
  • the display panel may be a liquid crystal display panel, or may be an OLED (Organic
  • connection structure 21 is disposed in the same layer as the pixel electrode 18.
  • installation position of the connection structure 21 is not limited to this.
  • a connection structure 21 may be formed on the passivation layer 19 and connected to the source electrode 15 and the data line 17 through via holes in the passivation layer 19 above the source electrode 15 and the data line 17, respectively.
  • steps before the formation of the connection structure 21 may be the same as the steps of fabricating the array substrate as shown in FIG.
  • connection structure 21 is not formed in the process of the pixel electrode 18 (i.e., the fifth patterning process described above).
  • via holes are respectively formed in the passivation layer 19 over the source electrode 15 and the data line 17, respectively (which may be formed in the sixth patterning process described above), and the connection structure 21 is formed over the via holes.

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Abstract

提供一种氧化物薄膜晶体管阵列基板及其制作方法、显示面板。该氧化物阵列基板包括：衬底基板（10），设置于衬底基板（10）上的氧化物TFT、栅线（11）、数据线（17）和像素电极（18）。氧化物TFT的漏极（16）和像素电极（18）相连，氧化物TFT的源极（15）和数据线（17）之间设置有连接结构（21），并通过连接结构（21）彼此点连接，连接结构（21）的电阻率大于源极（15）的电阻率。

Description

氧化物薄膜晶体管阵列基板及其制作方法、 显示面板 技术领域
本公开涉及一种氧化物薄膜晶体管及其制作方法、 显示面板。 背景技术
氧化物有源层， 如铟镓辞氧化物 IGZO ( indium gallium zinc oxide )作为 有源层， 其载流子迁移率是非晶硅的 20-30倍。 这种氧化物有源层可以大大 提高 TFT对像素电极的充放电速率， 提高像素的响应速度， 实现更快的刷新 率 , 是用于新一代 TFT-LCD ( Thin Film Transistor Liquid Crystal Display, 薄 膜场效应晶体管液晶显示）技术中的沟道层材料。
一般地， 氧化物 TFT器件中源漏电极和氧化物有源层直接接触。 在氧 化物有源层的两侧， 氧化物有源层和源漏电极之间没有 PN结， 这样， 氧化 物有源层的空穴流入到源极和漏极， 或源极和漏极的电子流入到氧化物有源 层， 这使得氧化物有源层和源漏电极之间的漏电流增加， 造成显示面板画面 闪烁、 串扰和残像等现象。 发明内容
本公开的一个实施例提供一种氧化物薄膜晶体管 （TFT ) 阵列基板， 包 括： 村底基板， 设置于所述村底基板上的氧化物 TFT、 栅线、 数据线和像素 电极， 所述氧化物 TFT的漏极和所述像素电极相连， 其中， 所述氧化物 TFT 的源极和所述数据线之间设置有连接结构，并通过所述连接结构彼此电连接， 所述连接结构的电阻率大于所述源极的电阻率。
在一个示例中， 所述连接结构与所述像素电极采用相同的透明导电材料 形成。
在一个示例中， 所述氧化物 TFT包括： 设置于所述栅线上的栅绝缘层； 设置于所述栅绝缘层上且位于栅线上方的氧化物有源层； 设置于所述氧化物 有源层上的刻蚀阻挡层； 设置于所述刻蚀阻挡层上的所述源极和所述漏极， 所述源极和漏极分别与所述氧化物有源层接触， 其中所述栅线的位于所述氧 化物有源层的至少一部分用作所述氧化物 TFT的栅极。
在一个示例中， 该氧化物 TFT阵列基板还包括： 设置于形成有所述像素 电极的村底基板上的钝化层； 设置于所述钝化层上的位于像素区域的公共电 极。
在一个示例中， 所述氧化物有源层为铟镓辞氧化物。
在一个示例中， 所述刻蚀阻挡层在所述有源层上方具有露出所述氧化物 有源层的通孔，所述源极和所述漏极通过所述通孔与所述氧化物有源层接触。
本公开的另一个实施例提供一种显示面板， 包括根据本公开任一实施例 的氧化物 TFT阵列基板。
本公开的再一个实施例提供一种氧化物薄膜晶体管 （TFT ) 阵列基板的 制作方法， 包括： 形成数据线和氧化物 TFT的源极以使所述数据线和所述源 极彼此分隔， 并在所述源极和所述数据线之间设置连接结构， 其中所述源极 和数据线通过所述连接结构彼此电连接， 且所述连接结构的电阻率大于所述 源极的电阻率。
在一个示例中，所述连接结构与所述像素电极采用相同的透明导电材料。 在一个示例中， 该方法包括： 通过第一次构图工艺， 在村底基板上形成 包括栅线的图形； 通过第二次构图工艺， 在经过第一次构图工艺的村底基板 上形成包括栅绝缘层和氧化物有源层的图形， 所述氧化物有源层的图形位于 栅线上方； 通过第三次构图工艺， 在经过第二次构图工艺的村底基板上形成 包括刻蚀阻挡层的图形； 通过第四次构图工艺， 在经过第三次构图工艺的村 底基板上形成包括数据线、 源极、 漏极， 其中所述数据线和所述源极形成为 彼此分隔； 通过第五次构图工艺， 在经过第四次构图工艺的村底基板上形成 包括像素电极和在所述源极和漏极的彼此分隔处的连接结构的图形。
在一个示例中， 在所述第五次构图工艺之后， 该方法还包括： 通过第六 次构图工艺， 在经过第五次构图工艺的村底基板上形成包括钝化层的图形； 通过第七次构图工艺， 在经过第六次构图工艺的村底基板上形成包括公共电 极的图形。
在一个示例中， 所述氧化物有源层为铟镓辞氧化物。
本公开实施例提供的一种氧化物 TFT 阵列基板及其制作方法、 显示面 板。 由于在源极 15和数据线 17之间设置有连接结构 21 , 该连接结构 21的 电阻率大于源极 15的电阻率，这样可以增大源极 15和数据线 17之间的电阻， 从而减小氧化物 TFT的漏电流， 可以改善显示面板的画面闪烁、 串扰和残像 等现象， 提高显示性能。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本公开实施例提供的氧化物 TFT阵列基板的俯视结构示意图； 图 2为本公开实施例提供的氧化物 TFT阵列基板沿栅线上的 A-A向剖 视结构示意图；
图 3为本公开实施例提供的氧化物 TFT阵列基板的制作方法的第一次构 图工艺后的结构示意图；
图 4为本公开实施例提供的氧化物 TFT阵列基板的制作方法的第二次构 图工艺后的结构示意图；
图 5为本公开实施例提供的氧化物 TFT阵列基板的制作方法的第三次构 图工艺后的结构示意图；
图 6为本公开实施例提供的氧化物 TFT阵列基板的制作方法的第四次构 图工艺后的结构示意图；
图 7为本公开实施例提供的氧化物 TFT阵列基板的制作方法的第五次构 图工艺后的结构示意图；
图 8为本公开实施例提供的氧化物 TFT阵列基板的制作方法的第六次构 图工艺后的结构示意图；
图 9为根据本公开另一个实施例的氧化物 TFT阵列基板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
需要说明的是： 本公开实施例的 "上" "下" 只是参考附图对本公开实 施例进行说明， 不作为限定用语。
实施例一
本公开实施例提供了一种氧化物 TFT阵列基板。 如图 1和 2所示， 该阵 列基板包括村底基板 10,设置于村底基板 10上的氧化物薄膜晶体管（ TFT )、 栅线 11、 数据线 17和像素电极 18。 氧化物 TFT包括位于栅线 11上的栅绝 缘层 12、位于栅绝缘层 12上的氧化物有源层 13、位于氧化物有源层 13上的 源极 15和漏极 16。 源极 15和漏极 16之间具有一间隔， 且氧化物有源层 13 在该间隔下方的部分形成沟道区域。栅线 11在沟道区域下方的至少一部分用 作氧化物 TFT的栅极。
如图 1所示， 栅线 11位于氧化物有源层 13、 源极 15和漏极 16的下方， 这样栅线 11遮挡住了源极 15和漏极 16之间的沟道内的氧化物有源层，从而 能够有效降低光照时电子空穴对产生的概率， 大大降低光照产生的漏电流。
如图 1所示， 栅线 11和数据线 17彼此交叉以限定处像素区域。 像素电 极 18可以形成在像素区域内， 并延伸到氧化物 TFT的漏极 16并与漏极 16 电连接。
源极 15和数据线 17之间设置有连接结构 21。 连接结构 21分别和源极 15、 数据线 17相连， 源极 15和数据线 17通过该连接结构 21彼此电连接。 连接结构 21的电阻率大于源极 15的电阻率。 例如， 源极 15由金属构成， 连 接结构 21由透明导电材料构成。 也就是说， 在本实施例中， 源极 15和数据 线 17之间并不直接相连， 而是通过连接结构 21彼此电连接。
由于源极 15和数据线 17之间设置有连接结构 21 , 连接结构 21的电阻 率大于源极 15的电阻率，从而能够有效的增大源极 15和数据线 17之间的电 阻， 进而减小源极 15和数据线 17之间的漏电流， 从而能够提升 TFT的显示 品质和稳定性。
本实施例中对氧化物 TFT、 栅线、 数据线、 像素电极的布置方式不作具 体限制，而是根据实际需要可以采用各种合适的布置方式。除了上述部件外， 根据本实施例的阵列基板还可以包括其他部件。
示例性地， 以下参照图 1 和 2 以超高维场切换 ( Advanced Dimension Switch, 筒称 ADS )型的氧化物 TFT阵列基板的单个子像素为例描述该 TFT 阵列基板的结构。
栅线 11设置于村底基板 10上， 栅绝缘层 12设置于栅线 11上， 且氧化 物有源层 13设置于栅绝缘层 12上位于栅线上方。
此外， 氧化物 TFT阵列基板还可以包括位于氧化物有源层 13上的源极
15和漏极 16。 栅线 11、 栅极绝缘层 12、 氧化物有源层 13和源极 15、 漏极 16构成氧化物 TFT。栅线 11位于氧化物有源层 13下方的至少一部分用作氧 化物 TFT的栅极。 在一个示例中， 氧化物 TFT还可包括设置于氧化物有源 层 13上的刻蚀阻挡层 14, 该刻蚀阻挡层 14在制作氧化物 TFT阵列基板的 过程中， 用于防止形成源极 15和漏极 16时源极 15和漏极 16之间形成的沟 道内的氧化物有源层 13被刻蚀。 刻蚀阻挡层 14至少覆盖源极 15和漏极 16 之间的沟道区域。 图 4中示例性的示出除源极 15、 漏极 16和氧化物有源层 13接触的区域外的栅线 11的其它区域都覆盖有刻蚀阻挡层 14。源极 15和漏 极 16通过刻蚀阻挡层 14中形成于氧化物有源层 13上方的通孔分别与氧化物 有源层 13接触。 在实际的制作过程中， 刻蚀阻挡层 14的图形可视实际制作 工艺和要求而定， 本公开对此不作具体限定。 例如， 源极 15和漏极 16分别 与氧化物有源层 13接触，源极 15和漏极 16之间形成的间隔位于所述刻蚀阻 挡层 14上。
氧化物 TFT阵列基板还可包括与源极 15和漏极 16位于同一层的数据线 17, 以及设置于所述源极 15和所述数据线 17之间的连接结构 21。 连接结构 21分别和源极 15、 数据线 17相连， 所述源极 15和数据线 17通过连接结构 21相连。
氧化物 TFT阵列基板还可包括设置于所述像素区域的像素电极 18。 具 体而言，栅线 11和数据线 17彼此交叉以限定出像素区域，像素电极 18位于 像素区域内。 像素电极 18延伸至漏极 16, 与所述漏极 16相连。
此外， 氧化物 TFT阵列基板还可包括设置于形成所述像素电极 18的村 底基板 10上的钝化层 19,以及设置于所述钝化层 19上的位于像素区域的公 共电极 20。
上述图 1、 2中的氧化物 TFT设置在栅线 11上， 由于栅线金属为非透明 金属， 可以同时遮挡氧化物 TFT的沟道， 进而能够减小氧化物 TFT阵列基 板的光照漏电流。
需要说明的是， 上述图 1、 2仅是以 ADS型氧化物 TFT阵列基板的底栅 结构为例进行说明， 但并不限制本公开仅适用于底栅结构的 TFT阵列基板。 本公开同样适用于顶栅结构等源极 15、漏极 16和氧化物有源层 13直接接触 的 TFT阵列基板， 在此本公开不作具体限定。
需要说明的是， 上述图 1、 2仅是以 ADS型氧化物 TFT阵列基板为例进 行了说明， 但并不限制本公开仅适用于 ADS型氧化物 TFT阵列基板。 本公 开同样适用于扭曲向列 （ Twisted Nematic, 筒称 TN )型等源极 15、 漏极 16 和氧化物有源层 13直接接触的氧化物 TFT阵列基板， 本公开在此不作具体 限定。
进一步的， 为了在制作氧化物 TFT阵列基板时， 减少构图工艺的次数， 该连接结构 21 具体可以采用和像素电极 18 同样的透明导电材料， 如 ITO ( Indium tin oxide 氧化铟锡） ， 从而在形成像素电极 18的构图工艺时， 可 以一并形成连接结构 21。
例如， 该氧化物有源层 13为铟镓辞氧化物（IGZO ) 。
本公开实施例提供的氧化物 TFT阵列基板， 由于在源极 15和数据线 17 之间设置有连接结构 21 , 该连接结构 21的电阻率大于源极 15的电阻率， 这 样可以减小源极 15和数据线 17之间产生的漏电流，从而减小氧化物 TFT的 漏电流， 可以改善显示面板的画面闪烁、 串扰和残像等现象，提高显示性能。
基于上述实施例提供的氧化物 TFT阵列基板，本公开实施例还提供了一 种氧化物 TFT 阵列基板的制作方法， 该方法包括： 通过构图工艺， 在源极 15和数据线 17之间设置连接结构 21 , 所述源极 15和数据线 17通过所述连 接结构 21相连， 所述连接结构 21的电阻率大于所述源极 15的电阻率。
下面以 ADS型氧化物 TFT阵列基板的制作方法为例更详细地描述根据 本公开的实施例。 需要说明的是， 本公开实施例提到的构图工艺包括曝光、 显影、 刻蚀、 灰化等主要工艺。 该方法可以包括以下步骤。
501、 通过第一次构图工艺， 在村底基板 10上形成包括栅线 11的图形。 例如，在第一次构图工艺过程中，首先在村底基板 10上涂布栅金属层薄 膜， 然后在涂布有栅金属层薄膜的村底基板 10上形成光刻胶。
利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光 刻胶完全去除区域； 其中， 所述光刻胶完全保留区域对应栅线 11的区域； 所 述光刻胶完全去除区域对应所述像素单元中除所述光刻胶完全保留区域以外 的区域。
利用刻蚀工艺去除掉光刻胶完全去除区域上的栅金属层薄膜， 再利用灰 化工艺剥离掉光刻胶完全保留区域的光刻胶，如图 3所示，露出栅线 11的图 形， 形成栅线 11。
502、 通过第二次构图工艺， 在经过第一次构图工艺的村底基板 10上形 成包括栅绝缘层 12和氧化物有源层 13的图形。
所述氧化物有源层 13的图形位于栅线 11上方， 由于栅线金属为非透明 金属， 可以同时遮挡氧化物 TFT的沟道， 进而能够减小氧化物 TFT阵列基 板的光照漏电流。
例如， 在第二次构图工艺过程中， 首先在经过第一次构图工艺的村底基 板 10上涂布栅绝缘层薄膜和氧化物有源层薄膜。然后在涂布有栅绝缘层薄膜 和氧化物有源层薄膜的村底基板 10上形成光刻胶。
利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光 刻胶完全去除区域； 其中， 所述光刻胶完全保留区域对应氧化物有源层 13 的区域； 所述光刻胶完全去除区域对应所述像素单元中除所述光刻胶完全保 留区域以外的区域。
利用刻蚀工艺去除掉光刻胶完全去除区域上的氧化物有源层薄膜， 再利 用灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 如图 4所示， 露出氧化物 有源层 13的图形， 形成栅绝缘层 12和氧化物有源层 13。
503、 通过第三次构图工艺， 在经过第二次构图工艺的村底基板 10上形 成包括刻蚀阻挡层 14的图形。
在第三次构图工艺过程中， 首先在经过第二次构图工艺的村底基板 10 上涂布刻蚀阻挡层薄膜，然后在涂布有刻蚀阻挡层薄膜的村底基板 10上形成 光刻胶。
利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光 刻胶完全去除区域；其中，所述光刻胶完全保留区域对应刻蚀阻挡层 14的区 域； 所述光刻胶完全去除区域对应所述像素单元中除所述光刻胶完全保留区 域以外的区域。 利用刻蚀工艺去除掉光刻胶完全去除区域上的刻蚀阻挡层薄膜， 再利用 灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 如图 5所示， 露出刻蚀阻挡 层 14的图形， 形成刻蚀阻挡层 14。
504、 通过第四次构图工艺， 在经过第三次构图工艺的村底基板 10上形 成包括数据线 17、 源极 15、 漏极 16, 以及所述源极 15和漏极 16断开的图 形 22。
在第四次构图工艺过程中， 首先在经过第三次构图工艺的村底基板 10 上涂布源漏金属层薄膜，然后在涂布有源漏金属层薄膜的村底基板 10上形成 光刻胶。
利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光 刻胶完全去除区域； 其中， 所述光刻胶完全保留区域对应源极 15、 漏极 16 及数据线 17的区域；所述光刻胶完全去除区域对应所述像素单元中除所述光 刻胶完全保留区域以外的区域， 其中包括源极 15和漏极 16断开的图形 22 的区域。
利用刻蚀工艺去除掉光刻胶完全去除区域上的源漏金属层薄膜， 再利用 灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 如图 6所示， 形成源极 15、 漏极 16、 数据线 17, 以及源极 15和漏极 16断开的图形 22的图形。
505、 通过第五次构图工艺， 在经过第四次构图工艺的村底基板 10上形 成包括像素电极 18和在所述源极和漏极断开的图形 22上的连接结构 21的图 形。
该连接结构 21与像素电极 18采用相同的透明导电材料。
在第五次构图工艺过程中， 首先在经过第四次构图工艺的村底基板 10 上涂布透明导电层薄膜，然后在涂布有透明导电薄膜的村底基板 10上形成光 刻胶。
利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光 刻胶完全去除区域；其中，所述光刻胶完全保留区域对应像素电极 18的区域 和连接结构 21的区域；所述光刻胶完全去除区域对应所述像素单元中除所述 光刻胶完全保留区域以外的区域。
利用刻蚀工艺去除掉光刻胶完全去除区域上的透明导电层薄膜， 再利用 灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 如图 7所示， 露出像素电极 18和连接结构 21。
506、 通过第六次构图工艺， 在经过第五次构图工艺的村底基板 10上形 成包括钝化层 19的图形。
在第六次构图工艺过程中， 首先在经过第五次构图工艺的村底基板 10 上涂布钝化层薄膜， 然后在涂布有钝化层薄膜的村底基板 10上形成光刻胶。
利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光 刻胶完全去除区域； 其中， 所述光刻胶完全保留区域对应钝化层 19的区域； 所述光刻胶完全去除区域对应所述像素单元中除所述光刻胶完全保留区域以 外的区域， 具体的所述光刻胶完全去除区域包括栅线引线过孔和数据线引线 过孔。
利用刻蚀工艺去除掉光刻胶完全去除区域上的钝化层薄膜， 其中栅线引 线过孔还需要刻蚀栅绝缘层薄膜， 再利用灰化工艺剥离掉光刻胶完全保留区 域的光刻胶，如图 8所示，形成钝化层 19、栅线引线过孔和数据线引线过孔， 其中栅线引线过孔和数据线引线过孔（图中未示出） 。
507、通过第七次构图工艺，在经过第六次构图工艺的村底基板上形成包 括公共电极 20的图形。
在第七次构图工艺过程中， 首先在经过第六次构图工艺的村底基板 10 上涂布透明导电层薄膜，然后在涂布有透明导电层薄膜的村底基板 10上形成 光刻胶。
利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光 刻胶完全去除区域；其中，所述光刻胶完全保留区域对应公共电极 20的区域； 所述光刻胶完全去除区域对应所述像素单元中除所述光刻胶完全保留区域以 外的区域。
利用刻蚀工艺去除掉光刻胶完全去除区域上的透明导电层薄膜， 再利用 灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 如图 2所示， 形成钝化层形 成公共电极 20。
需要说明是， 本公开实施例描述的氧化物 TFT阵列基板的制作方法中， 为了减少构图工艺的次数， 连接结构 21采用和像素电极 18相同的透明导电 材料， 则连接结构 21和像素电极 18可以在一次构图工艺中形成。 但是这并 不能限制本公开中连接结构 21仅可以采用和像素电极 18相同的透明导电材 料， 该连接结构 21还可以采用其它的材料， 只要该材料的电阻率大于源极 1 5的电阻率即可， 在这种情况下， 连接结构 21和像素电极 18需要采用两次 构图工艺完成。
进一步， 需要说明的是， 本公开实施例描述的氧化物 TFT阵列基板的制 作方法仅是示例性以七次构图工艺进行描述， 但不能理解为限制本公开仅能 采用七次构图工艺实现。 其它不同构图工艺次数， 能够在源极 15 和数据线 17之间形成连接结构 21的制作方法， 也属于本公开的保护范围。
本公开实施例提供的一种氧化物 TFT阵列基板的制作方法， 由于在源极 15和数据线 17之间形成连接结构 21 , 该连接结构 21的电阻率大于源极 15 的电阻率， 这样可以减小源极 15和数据线 17之间产生的漏电流， 从而减小 氧化物 TFT的漏电流， 可以改善显示面板的画面闪烁、 串扰和残像等现象， 提高显示性能。
本公开实施例还提供了一种显示面板， 包括上述实施例提供的氧化物 TFT阵列基板。
具体的， 该显示面板可以是液晶显示面板， 还可以是 OLED ( Organic
Light-Emitting Diode, 有机发光二极管）显示面板等。
上文描述了本发明的一些实施例， 根据本发明的技术方案并不局限于上 述具体的结构与方法。 例如， 在以上具体实施例中， 连接结构 21与像素电极 18同层设置。 然而， 连接结构 21的设置位置并不局限于此。 如图 9所示， 连接结构 21可以形成在钝化层 19上， 并且通过钝化层 19中的在源电极 15 和数据线 17上方的通孔分别连接到源电极 15和数据线 17。在制作如图 9所 示的阵列基板时，在形成连接结构 21之前的步骤（上述第一至第四次构图工 艺）可以与制作如图 8所示的阵列基板的步骤相同， 然而， 在形成像素电极 18的过程 (即上述第五次构图工艺）中并不形成连接结构 21。在形成钝化层 19之后，在钝化层 19中分别在源电极 15和数据线 17上方分别形成通孔（可 在上述第六次构图工艺中形成）， 连接结构 21形成在这些通孔上方， 以通过 这些通孔分别与源电极 15和数据线 17相连（可在上述第七次构图工艺中与 公共电极同步形成） 。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种氧化物薄膜晶体管（TFT )阵列基板， 包括： 村底基板， 设置于 所述村底基板上的氧化物 TFT、 栅线、 数据线和像素电极， 所述氧化物 TFT 的漏极和所述像素电极相连， 其中，
所述氧化物 TFT的源极和所述数据线之间设置有连接结构，并通过所述 连接结构彼此电连接， 所述连接结构的电阻率大于所述源极的电阻率。
2、根据权利要求 1所述的阵列基板， 其中， 所述连接结构与所述像素电 极采用相同的透明导电材料形成。
3、 根据权利要求 1或 2所述的阵列基板， 其中， 所述氧化物 TFT包括： 设置于所述栅线上的栅绝缘层；
设置于所述栅绝缘层上且位于栅线上方的氧化物有源层；
设置于所述氧化物有源层上的刻蚀阻挡层；
设置于所述刻蚀阻挡层上的所述源极和所述漏极， 所述源极和漏极分别 与所述氧化物有源层接触，
其中所述栅线的位于所述氧化物有源层的至少一部分用作所述氧化物 TFT的栅极。
4、 根据权利要求 1-3中任一项所述的阵列基板， 还包括：
设置于形成有所述像素电极的村底基板上的钝化层；
设置于所述钝化层上的位于像素区域的公共电极。
5、根据权利要求 3所述的阵列基板， 其中， 所述氧化物有源层为铟镓辞 氧化物。
6、根据权利要求 3所述的阵列基板， 其中， 所述刻蚀阻挡层在所述有源 层上方具有露出所述氧化物有源层的通孔， 所述源极和所述漏极通过所述通 孔与所述氧化物有源层接触。
7、 根据权利要求 1所述的阵列基板， 其中， 所述氧化物 TFT包括： 设置于所述栅线上的栅绝缘层；
设置于所述栅绝缘层上且位于栅线上方的氧化物有源层；
设置于所述氧化物有源层上的刻蚀阻挡层；
设置于所述刻蚀阻挡层上的所述源极和所述漏极， 所述源极和漏极分别 与所述氧化物有源层接触，
其中所述栅线的位于所述氧化物有源层的至少一部分用作所述氧化物
TFT的栅极，
所述阵列基板还包括：
设置于形成有所述像素电极的村底基板上的钝化层；
设置于所述钝化层上的位于像素区域的公共电极， 接结构形成在所述通孔的上方， 并且通过所述通孔分别与所述源极和所述数 据线相连。
8、 一种显示面板， 包括权利要求 1-7中任一项所述的氧化物 TFT阵列 基板。
9、 一种氧化物薄膜晶体管 （TFT ) 阵列基板的制作方法， 包括： 形成数据线和氧化物 TFT的源极以使所述数据线和所述源极彼此分隔， 并在所述源极和所述数据线之间设置连接结构，
其中所述源极和数据线通过所述连接结构彼此电连接， 且所述连接结构 的电阻率大于所述源极的电阻率。
10、 根据权利要求 9所述的方法， 其中， 所述连接结构与所述像素电极 采用相同的透明导电材料。
11、 根据权利要求 9或 10所述的方法， 包括：
通过第一次构图工艺， 在村底基板上形成包括栅线的图形；
通过第二次构图工艺， 在经过第一次构图工艺的村底基板上形成包括栅 绝缘层和氧化物有源层的图形， 所述氧化物有源层的图形位于栅线上方； 通过第三次构图工艺， 在经过第二次构图工艺的村底基板上形成包括刻 蚀阻挡层的图形；
通过第四次构图工艺， 在经过第三次构图工艺的村底基板上形成包括数 据线、 源极、 漏极， 其中所述数据线和所述源极形成为彼此分隔；
通过第五次构图工艺， 在经过第四次构图工艺的村底基板上形成包括像 素电极和在所述源极和漏极的彼此分隔处的连接结构的图形。
12、根据权利要求 11所述的方法， 在所述第五次构图工艺之后， 该方法 还包括： 通过第六次构图工艺， 在经过第五次构图工艺的村底基板上形成包括钝 化层的图形；
通过第七次构图工艺， 在经过第六次构图工艺的村底基板上形成包括公 共电极的图形。
13、根据权利要求 11所述的方法， 其中， 所述氧化物有源层为铟镓辞氧 化物。
14、 根据权利要求 9所述的方法， 包括：
通过第一次构图工艺， 在村底基板上形成包括栅线的图形；
通过第二次构图工艺， 在经过第一次构图工艺的村底基板上形成包括栅 绝缘层和氧化物有源层的图形， 所述氧化物有源层的图形位于栅线上方； 通过第三次构图工艺， 在经过第二次构图工艺的村底基板上形成包括刻 蚀阻挡层的图形；
通过第四次构图工艺， 在经过第三次构图工艺的村底基板上形成包括数 据线、 源极、 漏极， 其中所述数据线和所述源极形成为彼此分隔；
通过第五次构图工艺， 在经过第四次构图工艺的村底基板上形成像素电 极的图形；
通过第六次构图工艺， 在经过第五次构图工艺的村底基板上形成包括钝 化层的图形， 并且在该钝化层中所述源极和所述数据线的上方形成通孔； 以 及
通过第七次构图工艺， 在经过第六次构图工艺的村底基板上形成包括公 共电极以及连接结构的图形， 所述连接结构通过所述通孔分别与所述源极和 所述数据线相连。
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