WO2014168104A1 - Semiconductor device and method for producing same - Google Patents

Abstract

Provided is a semiconductor device that can prevent an increase in bit line contact resistance. Each of a plurality of bit line contact plugs at which the upper surface of a plurality of bit line contact regions and the bottom surface of a bit line extending in a first direction contact is configured from: a first plug that contacts the upper surface of the bit line contact region; and a second plug that contacts the upper surface of the first plug. The first plug has a first lateral surface and second lateral surface that oppose each other in the first direction. The second plug has a first end section and second end section that oppose each other in the first direction. The gap between the first end sections and second end sections is wider than the gap between the first lateral surfaces and second lateral surfaces.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor device and a manufacturing method thereof.

DRAM (Dynamic Random Access Memory), one of the semiconductor memory devices, is installed in various electronic devices that we use every day. In addition, with recent needs for lower power consumption and higher performance of equipment, there is a strong demand for higher performance such as lower power consumption, higher speed, and larger capacity in DRAMs.

One of the most effective means for realizing a high-performance DRAM is miniaturization of memory cells. By miniaturizing the memory cell, the length of the word line and the bit line connected to the memory cell is shortened. Therefore, the parasitic capacitance of the word line and the bit line is reduced and low voltage operation is possible, so that low power consumption can be realized. In addition, since the memory cell size is reduced, the capacity can be increased and the performance of the device can be improved. Thus, miniaturization of the memory cell greatly contributes to high performance of the DRAM.

In recent years, in semiconductor devices such as DRAMs, it has become difficult to form capacitors that require deep hole processing due to the progress of miniaturization of memory cells including cell transistors. Attempts have been made to reduce the parasitic capacitance of the bit line in order to ensure a sense margin in a situation where an increase in the capacitance of the capacitor cannot be expected.

For example, Japanese Patent Laying-Open No. 2012-099793 (Patent Document 1) discloses a semiconductor device having a configuration in which a bit line contact plug is formed of a silicon film and a bit line formed of a metal laminated film is disposed on the silicon film. Disclosure.

JP 2012-099793 (paragraphs [0029] to [0030], FIG. 4)

The bit line contact plug described in Patent Document 1 is provided by burying a contact hole formed in an interlayer insulating film with a silicon film. Therefore, the upper surface of the bit line contact plug is flush with the upper surface of the interlayer insulating film. That is, the contact area between the bit line and the bit line contact plug is defined by the diameter of the contact hole. In such a configuration, when the memory cell is further miniaturized, there is a problem that the contact area between the bit line and the bit line contact plug is reduced and the bit line contact resistance is increased. The increase in bit line contact resistance is a factor that hinders the high-speed operation of the DRAM.

A semiconductor device according to an aspect of the present invention includes a plurality of semiconductor devices that are surrounded by an element isolation region on a semiconductor substrate and are regularly aligned in a first direction and a second direction orthogonal to the first direction. An active region; a first word line and a second word line extending in a second direction across a plurality of active regions arranged in the second direction; a first word line and a first word line of the plurality of active regions; A plurality of bit line contact regions located between two word lines; a plurality of bit line contact plugs in contact with the top surfaces of the plurality of bit line contact regions; and top surfaces of the plurality of bit line contact plugs arranged in the first direction A bit line extending in the first direction; each of the plurality of bit line contact plugs includes a first plug contacting the upper surface of the bit line contact region; The first plug has a first side and a second side opposite to each other in the first direction; the second plug has a first end opposite to the first direction; and Having a second end; the spacing between the first end and the second end is configured to be longer than the spacing between the first side and the second side.

A semiconductor device according to another aspect of the present invention includes a plurality of semiconductor devices that are surrounded by an element isolation region on a semiconductor substrate and are regularly aligned in a first direction and a second direction orthogonal to the first direction. A first word line and a second word line extending in the second direction across a plurality of active regions arranged in the second direction; a first word line of the plurality of active regions; A plurality of bit line contact regions positioned between the second word lines; a plurality of bit line contact plugs respectively contacting the upper surfaces of the plurality of bit line contact regions; and a plurality of bit line contact plugs arranged in the first direction A bit line extending in the first direction and in contact with the upper surface; each of the plurality of bit line contact plugs includes a first plug contacting the upper surface of the bit line contact region; A first plug having a third side surface and a fourth side surface facing in the second direction; and a second plug having a fifth side surface and a second side facing in the second direction. The bit line has a seventh side surface and an eighth side surface facing in the second direction; the third side surface, the fifth side surface, and the seventh side surface are flush with each other; The sixth side surface and the eighth side surface are flush with each other.

A semiconductor device according to another aspect of the present invention is arranged on a semiconductor substrate so as to be surrounded by an element isolation region and regularly aligned in a first direction and a second direction orthogonal to the first direction. A plurality of active regions; a first word line and a second word line embedded in the active region across a plurality of active regions arranged in the second direction and extending in the second direction; A plurality of bit line contact regions located between the first word line and the second word line; an interlayer insulating film covering the top surfaces of the plurality of active regions; and a plurality of layers in contact with the top surfaces of the plurality of bit line contact regions, respectively. A bit line contact plug; and a bit line extending over the first direction in contact with the upper surfaces of the plurality of bit line contact plugs arranged in the first direction. Line contour Each of the top plugs is embedded in the interlayer insulating film and has a top surface flush with the top surface of the interlayer insulating film, and is connected to the top surface of the first plug and disposed above the top surface of the first plug. A second plug; the second plug has a projecting portion projecting in the first direction along the upper surface of the interlayer insulating film from the end in the first direction on the upper surface of the first plug. .

In the method of manufacturing a semiconductor device according to the present invention, the periphery is surrounded by an element isolation region on the semiconductor substrate, and is regularly arranged in the first direction and the second direction orthogonal to the first direction. Forming a plurality of active regions; forming a first word line and a second word line embedded in the active region across the plurality of active regions arranged in the second direction and extending in the second direction A step of forming an interlayer insulating film on the upper surface of the semiconductor substrate in which the first word line and the second word line are buried; in a plurality of active regions arranged in the second direction, Forming a plurality of bit line contact trenches in the interlayer insulating film that collectively open a plurality of bit line contact regions located between two word lines; and first forming the plurality of bit line contact trenches that are collectively opened. Embed with silicon film A step of selectively growing the second silicon film so as to protrude in the first direction from the upper surface of the first silicon film along the upper surface of the interlayer insulating film; and a metal film on the entire surface including the upper surface of the second silicon film. Forming a film; using a mask having a pattern intersecting with the plurality of bit line contact regions and extending in the first direction, the metal film, the second silicon film, and the first silicon film are collectively dry-etched, and the first Forming a bit line contact plug made of a silicon film and a second silicon film and a bit line made of a metal film at the same time.

According to the structure of the semiconductor device of the present invention, the second plug of the bit line contact plug expands in the direction in which the bit line extends on the upper surface of the insulating film, thereby increasing the area of the bit line contact, Contact resistance can be reduced.

Further, according to the method of manufacturing a semiconductor device according to the present invention, since good coverage is not required in the step of forming the bit line, an inexpensive PVD (Physical Vapor Deposition) device can be used, and the manufacturing cost can be reduced. Can be reduced.

FIG. 3 is a plan view showing an arrangement relationship among an active region, a word line, a bit line contact plug, and a bit line in the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a cross-sectional view of a line BB in FIG. 1 up to a second interlayer insulating film. FIG. 3 is a cross-sectional view of the line CC in FIG. 1 up to a second interlayer insulating film. It is an enlarged view of the A section enclosed with the rectangle in FIG. FIG. 2 is a plan view corresponding to FIG. 1 showing a first manufacturing step of the process for manufacturing the semiconductor device shown in FIG. 1. FIG. 7 is a cross-sectional view taken along line BB in FIG. 6 and corresponds to FIG. 3. FIG. 7 is a cross-sectional view taken along line CC in FIG. 6 and corresponds to FIG. 4. FIG. 5 is a cross-sectional view corresponding to FIG. 4 showing a second manufacturing step of the process for manufacturing the semiconductor device shown in FIG. 1. FIG. 7 is a plan view corresponding to FIG. 1 and showing a third manufacturing step in the process for manufacturing the semiconductor device shown in FIG. 1. FIG. 11 is a sectional view taken along line CC in FIG. 10 and corresponds to FIG. 4. FIG. 5 is a cross-sectional view corresponding to FIG. 4 showing a fourth manufacturing step in the process for manufacturing the semiconductor device shown in FIG. 1. FIG. 5 is a cross-sectional view corresponding to FIG. 4 showing a fifth manufacturing step of the process for manufacturing the semiconductor device shown in FIG. 1. FIG. 10 is a plan view corresponding to FIG. 1 and showing a fifth manufacturing step in the process for manufacturing the semiconductor device shown in FIG. 1. FIG. 15 is a cross-sectional view taken along line BB in FIG. 14 and corresponds to FIG. 3.

Hereinafter, a semiconductor device manufacturing method and a semiconductor device to which the present invention is applied will be described in detail with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .

Also, the XYZ coordinate system is set and the arrangement of each component will be described. In this coordinate system, the Z direction is a direction perpendicular to the surface of the semiconductor substrate, the X direction is a direction perpendicular to the Z direction in a plane parallel to the surface of the semiconductor substrate, and the Y direction is horizontal to the surface of the semiconductor substrate. This is a direction orthogonal to the X direction on a smooth surface. The W direction is a direction inclined obliquely with respect to the X direction. In this specification, the X direction is called a first direction, the Y direction is called a second direction, the W direction is called a third direction, and the Z direction is called a fourth direction.

[First Embodiment]
(Semiconductor device)
First, the structure of the semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a plan view showing an arrangement relationship of an active region, a word line, a bit line contact plug, and a bit line of the semiconductor device 100. FIG. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a cross-sectional view of the line BB in FIG. 1 up to the second interlayer insulating film. 4 is a cross-sectional view of the line CC in FIG. 1 up to the second interlayer insulating film. FIG. 5 is an enlarged view of a portion A surrounded by a rectangle in FIG.

The semiconductor device 100 finally functions as a DRAM, and includes a memory cell region and a peripheral circuit region (not shown) located around the memory cell region in the plane of the semiconductor substrate. Among these, the memory cell region is a region where a plurality of memory cells are arranged in a matrix.

First, referring to FIG. 1, the surface of a semiconductor substrate 101 (see FIG. 2) is partitioned by an element isolation region 102. A plurality of island-shaped active regions 103 having an inclination in the third direction W inclined with respect to the first direction X are provided in regular alignment in the first direction X and the second direction Y. A first word line 105a and a second word line 105b extending in the second direction Y intersecting with the plurality of active regions 103 and dividing each active region 103 into three are provided. The active region 103 sandwiched between the first word line 105a and the second word line 105b becomes the bit line contact region 103b. A bit line contact plug 205 (see FIG. 2) is provided at a position overlapping the bit line contact region 103b.

The bit line contact plug 205 includes a first plug 202 connected to the upper surface of the bit line contact region 103 b and a second plug 204 connected to the upper surface of the first plug 202. The first plug 202 has a first side surface 202b and a second side surface 202c that face in the first direction X, and a third side surface 202d and a fourth side surface 202e that face in the second direction Y. The second plug 204 has a first end portion 204b and a second end portion 204c that face the first direction X, and a fifth side surface 204d and a sixth side surface 204e that face the second direction Y.

The bit line 208 is in contact with the upper surface of the plurality of bit line contact plugs 205 (the upper surface of the second plug 204) arranged in the first direction X, and is arranged extending in the first direction X. The bit line 208 has a seventh side surface 208a and an eighth side surface 208b that face the second direction Y.

The semiconductor device 100 is configured such that the interval between the first end portion 204b and the second end portion 204c of the second plug 204 is longer than the interval between the first side surface 202b and the second side surface 202c of the first plug 202. have. In addition, the third side surface 202d, the fifth side surface 204d, and the seventh side surface 208a have the same configuration, and the fourth side surface 202e, the sixth side surface 204e, and the eighth side surface 208b have the same configuration.

Next, the structure of the semiconductor device 100 according to the first embodiment of the present invention will be described with reference to FIG.

The semiconductor device 100 according to the first embodiment of the present invention includes an element isolation region 102, an active region 103, a word trench 107, a gate insulating film 104, a gate electrode 105, and a first interlayer insulating film 106. The bit line contact trench 200, the bit line contact plug 205, the bit line contact 207, the bit line 208, the cover film 209, the second interlayer insulating film 300, the capacitive contact plug 301, and the capacitive element 302 are formed. Have.

The element isolation region 102 is disposed on the surface of the semiconductor substrate 101 as described above up to a depth of 200 nm. The active region 103 partitions the semiconductor substrate 101 with the element isolation region 102. The word trench 107 extends in a second direction Y (not shown) (see FIG. 1) so as to divide each of the plurality of active regions 103 into three, and is arranged up to a depth of 150 nm. The gate insulating film 104 is thin on the surface of the word trench 107, for example, with a thickness of 5 nm. The gate electrode 105 is disposed so as to bury a range of 80 nm from the bottom of the word trench 107 inside the gate insulating film 104.

The first interlayer insulating film 106 buryes the word trench 107 left on the gate electrode 105 and is disposed on the active region 103 and the element isolation region 102 with a thickness of 20 nm. The bit line contact trench 200 extends through the first interlayer insulating film 106 to the upper surface 103a of the active region 103 sandwiched between the word trenches 107, and extends in a second direction Y (not shown) to have a width D1 (see FIG. 5). Is arranged in.

The bit line contact plug 205 includes a first plug 202 and a second plug 204. The first plug 202 is embedded in the bit line contact trench 200 so as to be flush with the upper surface 106a of the first interlayer insulating film 106 so as to be connected to the upper surface 103a of the active region 103, and in a second direction Y (not shown). It has a width of D3 (see FIG. 3). The second plug 204 is connected to the upper surface 202 a of the first plug 202 and is disposed above the upper surface 202 a of the first plug 202, and the first interlayer insulating film 106 is formed from the end of the upper surface of the first plug 202. The upper surface 106a has an overhanging portion that extends to the width D2 (see FIG. 5) in the first direction X, and has a width of D3 (see FIG. 3) in the second direction Y (not shown).

The bit line contact 207 is a titanium silicide film (hereinafter referred to as a TiSi film) 16 that is in contact with the second plug 204 and disposed only on the second plug 204. The bit line 208 is in contact with the bit line contact 207 and is made of a metal composite film 206. The metal composite film 206 includes a titanium nitride film (hereinafter referred to as a TiN film) 14, a tungsten silicide film (hereinafter referred to as a WSi film) 15, and a tungsten nitride film disposed on the bit line contact 207 as described above. (Hereinafter referred to as WN film) 12, tungsten film (hereinafter referred to as W film) 11, and titanium film (hereinafter referred to as Ti film) described later.

The cover film 209 is disposed so as to cover the upper surface of the bit line 208. The second interlayer insulating film 300 covers a portion (not shown) of the bit line contact trench 200 other than the first plug 202 and the entire surface of the first interlayer insulating film 106 including the bit line 208 and the cover film 209. Are arranged as follows. The capacitor contact plug 301 is disposed so as to penetrate the second interlayer insulating film 300 and the first interlayer insulating film 106 and connect to the upper surface 103a of the active region 103 sandwiched between the word trench 107 and the element isolation region 102. Yes. The capacitive element 302 is connected to the upper surface of the capacitive contact plug 301 and is disposed on the capacitive contact plug 301 and the second interlayer insulating film 300.

Next, with reference to FIG. 3, a supplementary description will be given of the structure in the second direction Y of the semiconductor device 100 according to the first embodiment of the present invention.

The first plug 202 is in contact with the upper surface 103a of the active region 103, the upper surface 106a of the first interlayer insulating film 106 (not shown) and the upper surface 202a of the first plug 202 are flush, and the width in the second direction Y is D3. And it arrange | positions so that the width | variety of the 1st direction X which is not shown in figure may become D1 (refer FIG. 5). The second plug 204 is in contact with the upper surface 202a of the first plug 202, and is arranged such that the width in the second direction Y is D3, and the width in the first direction X (not shown) is D1 (see FIG. 5). The

The bit line contact plug 205 includes a first plug 202 and a second plug 204. That is, the bit line contact plug 205 is connected to the upper surface 103a of the active region 103, and the width in the first direction X is D1 and the width in the second direction Y at the height of the upper surface 106a of the first interlayer insulating film 106 (not shown). Is D3, and the width in the first direction X is D2 and the width in the second direction Y is enlarged only in D3 and the first direction X on the upper surface 106a of the first interlayer insulating film 106 (not shown).

The bit line contact 207 is arranged on the second plug 204 so that the width in the second direction Y is D3 and the width in the first direction X (not shown) is D2 (see FIG. 5). The bit line 208 and the cover film 209 are in contact with the bit line contact 207, arranged so that the width in the second direction Y is D3, and the width in the first direction X (not shown) is D1 (see FIG. 5). Is done. The second interlayer insulating film 300 is disposed so as to cover the entire surface of the semiconductor substrate 101 including the bit line 208 and the cover film 209.

Next, with reference to FIG. 4, the structure of the bit line of the semiconductor device 100 according to the first embodiment of the present invention will be supplementarily described.

The bit line 208 extends in the first direction X and is arranged so that the width in the second direction Y (not shown) is D1 (see FIG. 5). In the bit line 208, the Ti film 13, the TiN film 14, the WSi film 15, the WN film 12 and the W film 11 are stacked on the upper surface 106 a of the first interlayer insulating film 106, and the TiN film is formed on the bit line contact 207. 14, a WSi film 15, a WN film 12, and a W film 11 are composed of a metal composite film 206. The reason why the Ti film 13 disappears on the bit line contact 207 is that the Ti film 13, which is the lowest layer of the metal composite film 206, is replaced with the TiSi film 16, as described later in the method of manufacturing the semiconductor device 100 of the first embodiment. This is because it is consumed when forming.

Next, with reference to FIG. 5, details of the semiconductor device 100 according to the first embodiment of the present invention will be described.

The first plug 202 is embedded in the bit line contact groove 200 so as to be connected to the upper surface 103a of the active region 103 until the upper surface 202a of the first plug 202 and the upper surface 106a of the first interlayer insulating film 106 are flush with each other. The second direction Y (not shown) is arranged to have a width of D3 (see FIG. 3).

The second plug 204 is connected to the upper surface 202 a of the first plug 202 and is disposed above the upper surface 202 a of the first plug 202, and from the end of the upper surface 202 a of the first plug 202, the first interlayer insulating film 106. The upper surface 106a has projecting portions 204f and 204g that project to the width D2 in the first direction X, and is arranged so as to have a width of D3 (see FIG. 3) in the second direction Y (not shown).

The bit line contact plug 205 includes a first plug 202 and a second plug 204. That is, the bit line contact plug 205 is connected to the upper surface 103a of the active region 103, and the height in the first direction X is D1 and the width in the second direction Y is D3 at the height of the upper surface 106a of the first interlayer insulating film 106. (See FIG. 3), and the width in the first direction X is D2 and the width in the second direction Y is D3 (see FIG. 3) and the first direction X on the upper surface 106a of the first interlayer insulating film 106. Shape.

The bit line contact 207 which is the TiSi film 16 is in contact with the second plug 204 and is disposed only on the second plug 204. The bit line 208 extends in the first direction X, and is arranged so that the width in the second direction Y (not shown) is D3 (see FIG. 3). In the bit line 208, the Ti film 13, the TiN film 14, the WSi film 15, the WN film 12 and the W film 11 are stacked on the upper surface 106 a of the first interlayer insulating film 106, and the TiN film is formed on the bit line contact 207. 14, a WSi film 15, a WN film 12, and a W film 11 are composed of a metal composite film 206.

The cover film 209 is disposed so as to cover the upper surface of the bit line 208. Here, in the bit line contact 207, the width of the first plug in the first direction X is D1 in the prior art, whereas in the first embodiment of the present invention, the width of the second plug in the first direction X. By expanding to D2, the area of the bit line contact can be expanded and the bit line contact resistance can be reduced.

(Method for Manufacturing Semiconductor Device of First Embodiment)
A method for manufacturing the semiconductor device 100 according to the first embodiment of the present invention is now described with reference to FIGS.

First, the first manufacturing process of the process for manufacturing the semiconductor device 100 will be described with reference to FIGS. FIG. 6 is a plan view corresponding to FIG. 7 is a cross-sectional view taken along line BB in FIG. 6, and corresponds to FIG. FIG. 8 is a cross-sectional view taken along line CC in FIG. 6 and corresponds to FIG.

An element isolation region 102 is formed on the surface of the semiconductor substrate 101 by a known method, and the surface of the semiconductor substrate 101 is partitioned into a plurality of active regions 103. Then, the word trench 107, the gate insulating film 104, and the gate electrode 105 are formed by a known method. Thereafter, a first interlayer insulating film 106 is formed on the upper surface of the semiconductor substrate 101. Then, by lithography and dry etching, the active region is formed in a groove shape extending in the second direction Y (not shown) in a portion having a width D1 between the word trenches 107 applied to the same active region 103 of the first interlayer insulating film 106. Etching is performed until the upper surfaces of the element isolation region 102 and the element isolation region 102 appear, thereby forming a bit line contact trench 200.

Next, a second manufacturing process of the process for manufacturing the semiconductor device 100 will be described with reference to FIG. FIG. 9 is a cross-sectional view corresponding to FIG.

An amorphous silicon film (hereinafter referred to as an α-Si film) is formed on the entire surface of the semiconductor substrate 101 so as to fill the bit line contact trench 200 and cover the first interlayer insulating film 106. Then, polishing is performed by etch back or CMP (Chemical-Mechanical-Polishing) until the surface of the first interlayer insulating film 106 appears, leaving the α-Si film only inside the bit line contact trench 200, and the width is shown by D1. A first silicon film 201 extending in the second direction Y that is not formed is formed.

Next, the third manufacturing process of the process for manufacturing the semiconductor device 100 will be described with reference to FIGS. FIG. 10 is a plan view corresponding to FIG. FIG. 11 is a cross-sectional view corresponding to FIG.

An epitaxially grown silicon film (hereinafter referred to as an Epi-Si film) is grown only on the upper surface 201a of the first silicon film 201 using a selective epitaxial growth method. At this time, since the epitaxial growth grows not only in the Z direction but also in the horizontal direction, the Epi-Si film extends over the first interlayer insulating film 106 and extends in the second direction Y not shown by D2. A second silicon film 203 is formed.

Such selective epitaxial silicon growth is performed, for example, at a flow rate of 200 ml of SiH ₂ Cl ₂ , a flow rate of 80 to 120 ml of HCl, a temperature of 750 to 900 ° C. (eg, 800 ° C.), and 5 to 30 Torr (eg, 15 Torr). This can be realized under the condition of H ₂ at a pressure of.

Next, a fourth manufacturing process of the process for manufacturing the semiconductor device 100 will be described with reference to FIG. FIG. 12 is a cross-sectional view corresponding to FIG.

A Ti film 13 (for example, a film thickness of 2 nm) and a TiN film 14 (for example, a film thickness of 2 nm) are formed on the entire upper surface 106a of the first interlayer insulating film 106 including the second silicon film 203 by using a known PVD (Physical Vapor Deposition) method. For example, a metal composite comprising a 10 nm film thickness), a WSi film 15 (for example, 20 nm film thickness), a WN film 12 (for example, 2 nm film thickness), and a W film 11 (for example, 30 nm film thickness). A film 206 is formed. Then, a mask 40 made of a SiN film is formed on the metal composite film 206 by a known CVD (Chemical Vapor Deposition) method, and the surface is flattened by CMP (Chemical Mechanical Polishing).

Here, when the metal composite film 206 is formed, the bit line contact groove 200 of the first interlayer insulating film 106 is buried with the first silicon film 201 and the upper part is enlarged with the second silicon film 203. For this reason, it is possible to use a PVD method that does not require high coverage and that is inexpensive to manufacture.

Next, the fourth manufacturing process of the process for manufacturing the semiconductor device 100 will be described with reference to FIGS. 13 is a cross-sectional view taken along line CC of FIG. 1, and corresponds to FIG. FIG. 14 is a plan view corresponding to FIG. 15 is a cross-sectional view taken along line BB in FIG. 1 and corresponds to FIG.

The Ti film 13 in contact with the second silicon film 203 which is an Epi-Si film is silicided by heat treatment to form a TiSi film 16. At the same time, the first silicon film 201, which is an α-Si film, is polycrystallized and has good conductivity. Here, in this example, the first silicon film 201 is formed of an α-Si film, but boron doped amorphous silicon into which impurities (boron) are introduced (diborane (B ₂ H ₆ ) is added during film formation). A film or a hydrogenated amorphous silicon film may be used to provide good conductivity from the beginning.

Next, by lithography and dry etching, the pattern of the bit line 208 extending in the first direction X and repeating in the second direction Y is changed to the active surface of the upper surface of the first interlayer insulating film 106 and the bottom of the bit line contact trench 200. Etching is performed until the upper surfaces of the region 103 and the element isolation region 102 appear. As a result, the mask 40 composed of the first silicon film 201, the second silicon film 203, the TiSi film 16, the metal composite film 206, and the SiN film is divided into a width D3 in the second direction Y (not shown), and the first plugs are respectively formed. 202, the second plug 204, the bit line contact 207, the bit line 208, and the cover film 209, and the first plug 202 and the second plug 204 constitute the bit line contact plug 205.

Here, the bit line contact 207 is expanded in the first direction X by the second plug 204 to reduce the bit line contact resistance. In addition, since the width in the second direction Y is cut to D3 by etching, the possibility of a short circuit between adjacent bit line contacts 207 is small.

Next, a fifth manufacturing process of the process for manufacturing the semiconductor device 100 will be described with reference to FIGS.

The second interlayer insulating film 300, the capacitor contact 301, and the capacitor element 302 are formed by a known method, and the semiconductor device 100 of FIGS. 1 to 5 is completed.

The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

This application claims priority based on Japanese Patent Application No. 2013-082249 filed on Apr. 10, 2013, the entire disclosure of which is incorporated herein.

11 Tungsten film (W film)
12 Tungsten nitride film (WN film)
13 Titanium film (Ti film)
14 Titanium nitride film (TiN film)
15 Tungsten silicide film (WSi film)
16 Titanium silicide film (TiSi film)
40 mask 100 semiconductor device 101 semiconductor substrate 102 element isolation region 103 active region 103a upper surface 103b bit line contact region 104 gate insulating film 105 gate electrode 105a first word line 105b second word line 106 interlayer insulating film (first interlayer insulating film) )
106a upper surface 107 word trench 200 bit line contact groove 201 first silicon film 201a upper surface 202 first plug 202a upper surface 202b first side surface 202c second side surface 202d third side surface 202e fourth side surface 203 second silicon film 204 second plug 204b second 1st end portion 204c 2nd end portion 204d 5th side surface 204e 6th side surface 204f Overhang portion 204g Overhang portion 205 Bit line contact plug 206 Metal film (metal composite film)
207 Bit line contact 208 Bit line 208a Seventh side 208b Eight side 209 Cover film 300 Second interlayer insulating film 301 Capacitor contact plug 302 Capacitor element X direction (first direction)
Y Y direction (second direction)
W W direction (3rd direction)
Z Z direction (4th direction)

Claims (19)

On the semiconductor substrate, a plurality of active regions surrounded by an element isolation region and regularly arranged in a first direction and a second direction orthogonal to the first direction;
A first word line and a second word line extending in the second direction across the plurality of active regions arranged in the second direction;
A plurality of bit line contact regions located between the first word line and the second word line among the plurality of active regions;
A plurality of bit line contact plugs respectively in contact with the top surfaces of the plurality of bit line contact regions;
A bit line in contact with the top surface of the plurality of bit line contact plugs arranged in the first direction and extending in the first direction;
A semiconductor device comprising:
Each of the plurality of bit line contact plugs includes a first plug in contact with the upper surface of the bit line contact region and a second plug in contact with the upper surface of the first plug;
The first plug has a first side surface and a second side surface facing in the first direction,
The second plug has a first end and a second end facing in the first direction,
An interval between the first end and the second end is longer than an interval between the first side and the second side;
A semiconductor device. A bit line contact disposed in contact with the second plug and only on the second plug;
The bit line is in contact with the bit line contact;
The semiconductor device according to claim 1. The first plug comprises an amorphous silicon film, an amorphous silicon film doped with impurities, and a silicon film selected from the group consisting of a hydrogenated amorphous silicon film,
The second plug is made of an epitaxially grown silicon film,
The bit line contact is made of a titanium silicide film.
The semiconductor device according to claim 2. 4. The semiconductor device according to claim 2, wherein the bit line is made of a metal composite film. The metal composite film is
A titanium nitride film extending in a first direction in contact with the bit line contact;
A tungsten silicide film formed on the titanium nitride film;
A tungsten nitride film formed on the tungsten silicide film;
A tungsten film formed on the tungsten nitride film;
A titanium film provided in a lower layer of the titanium nitride film and extending in a first direction at a position excluding the bit line contact;
The semiconductor device according to claim 4, comprising: On the semiconductor substrate, a plurality of active regions surrounded by an element isolation region and regularly arranged in a first direction and a second direction orthogonal to the first direction;
A first word line and a second word line extending in the second direction across the plurality of active regions arranged in the second direction;
A plurality of bit line contact regions located between the first word line and the second word line among the plurality of active regions;
A plurality of bit line contact plugs respectively in contact with the top surfaces of the plurality of bit line contact regions;
A bit line in contact with the top surface of the plurality of bit line contact plugs arranged in the first direction and extending in the first direction;
A semiconductor device comprising:
Each of the plurality of bit line contact plugs includes a first plug in contact with the upper surface of the bit line contact region and a second plug in contact with the upper surface of the first plug;
The first plug has a third side surface and a fourth side surface facing in the second direction,
The second plug has a fifth side surface and a sixth side surface facing in the second direction,
The bit line has a seventh side surface and an eighth side surface facing in the second direction,
The third side surface, the fifth side surface, and the seventh side surface are flush with each other, and the fourth side surface, the sixth side surface, and the eighth side surface are flush with each other.
A semiconductor device. A bit line contact disposed in contact with the second plug and only on the second plug;
The bit line is in contact with the bit line contact;
The semiconductor device according to claim 6. The first plug comprises an amorphous silicon film, an amorphous silicon film doped with impurities, and a silicon film selected from the group consisting of a hydrogenated amorphous silicon film,
The second plug is made of an epitaxially grown silicon film,
The bit line contact is made of a titanium silicide film.
The semiconductor device according to claim 7. 9. The semiconductor device according to claim 7, wherein the bit line is made of a metal composite film. The metal composite film is
A titanium nitride film extending in a first direction in contact with the bit line contact;
A tungsten silicide film formed on the titanium nitride film;
A tungsten nitride film formed on the tungsten silicide film;
A tungsten film formed on the tungsten nitride film;
A titanium film provided in a lower layer of the titanium nitride film and extending in a first direction at a position excluding the bit line contact;
The semiconductor device according to claim 9, comprising: On the semiconductor substrate, a plurality of active regions surrounded by an element isolation region and regularly arranged in a first direction and a second direction orthogonal to the first direction;
A first word line and a second word line embedded in the active region across the plurality of active regions arranged in the second direction and extending in the second direction;
A plurality of bit line contact regions located between the first word line and the second word line among the plurality of active regions;
An interlayer insulating film covering upper surfaces of the plurality of active regions;
A plurality of bit line contact plugs respectively in contact with the top surfaces of the plurality of bit line contact regions;
A bit line extending across the first direction in contact with the upper surface of the plurality of bit line contact plugs arranged in the first direction;
A semiconductor device comprising:
Each of the plurality of bit line contact plugs is connected to the upper surface of the first plug, the first plug being embedded in the interlayer insulating film and having an upper surface flush with the upper surface of the interlayer insulating film. A second plug disposed above the upper surface of the one plug,
The second plug has an overhanging portion extending in the first direction along the upper surface of the interlayer insulating film from the end portion in the first direction of the upper surface of the first plug.
A semiconductor device. A bit line contact disposed in contact with the second plug and only on the second plug;
The bit line is in contact with the bit line contact;
The semiconductor device according to claim 11. The first plug comprises an amorphous silicon film, an amorphous silicon film doped with impurities, and a silicon film selected from the group consisting of a hydrogenated amorphous silicon film,
The second plug is made of an epitaxially grown silicon film,
The bit line contact is made of a titanium silicide film.
The semiconductor device according to claim 12. 14. The semiconductor device according to claim 12, wherein the bit line is made of a metal composite film. The metal composite film is
A titanium nitride film extending in a first direction in contact with the bit line contact;
A tungsten silicide film formed on the titanium nitride film;
A tungsten nitride film formed on the tungsten silicide film;
A tungsten film formed on the tungsten nitride film;
A titanium film provided on a lower layer of the titanium nitride film on the interlayer insulating film and extending in a first direction at a position excluding the bit line contact;
The semiconductor device according to claim 14, comprising: Forming, on a semiconductor substrate, a plurality of active regions that are surrounded by an element isolation region and are regularly aligned in a first direction and a second direction orthogonal to the first direction;
Forming a first word line and a second word line embedded in the plurality of active regions across the plurality of active regions arranged in the second direction and extending in the second direction;
Forming an interlayer insulating film on the upper surface of the semiconductor substrate in which the first word line and the second word line are embedded;
In the plurality of active regions arranged in the second direction, a plurality of bit line contact grooves that collectively open a plurality of bit line contact regions located between the first word line and the second word line are provided. Forming the interlayer insulating film;
Burying the plurality of bit line contact grooves that are collectively opened with a first silicon film;
Selectively growing a second silicon film so as to protrude from the upper surface of the first silicon film along the upper surface of the interlayer insulating film in the first direction;
Forming a metal film on the entire surface including the upper surface of the second silicon film;
The metal film, the second silicon film, and the first silicon film are collectively dry etched using a mask having a pattern that intersects the plurality of bit line contact regions and extends in a first direction, and the first silicon Forming a bit line contact plug comprising a film and the second silicon film and a bit line comprising the metal film simultaneously;
A method for manufacturing a semiconductor device, comprising: The first silicon film comprises a silicon film selected from the group consisting of an amorphous silicon film, an amorphous silicon film doped with impurities, and a hydrogenated amorphous silicon film,
The second silicon film is an epitaxially grown silicon film,
The method for manufacturing a semiconductor device according to claim 16. The step of forming the metal film comprises a step of forming a metal composite film comprising a titanium film, a titanium nitride film, a tungsten silicide film, a tungsten nitride film, and a tungsten film by using a PVD method. 18. A method for manufacturing a semiconductor device according to 17. The method for manufacturing a semiconductor device according to claim 16, further comprising a heat treatment step between the step of forming the metal film and the step of performing the batch dry etching.

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