JP2013008768A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To substantially reduce an occupied area of wiring.SOLUTION: A semiconductor device comprises: a plurality of first connection regions arranged on a semiconductor substrate in a first direction and a second direction crossing the first direction; and a plurality of wirings electrically connecting the plurality of first connection regions by row in the first direction. The plurality of wirings are arranged such that two neighboring wirings in the second direction are arranged in different wiring layers and curved so as to be seen as a honeycomb-shape where the two wirings partially overlap with each other, in plan view.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor memory device including a bit line and a manufacturing method thereof.

  In a DRAM (Dynamic Random Access Memory), which is one of semiconductor devices, a COB in which a cell capacitor is disposed above the bit line in order to avoid a decrease in the capacity of the cell capacitor due to high integration (element miniaturization). (Capacitor Over Bit Line) structure is mainstream.

  In the COB structure, after forming a bit line connected to one of the source / drain of a cell transistor, a capacitor contact plug for connecting a cell capacitor to the other of the source / drain must be formed. Therefore, it is necessary to lay out the bit line so that the bit line does not become an obstacle when forming the capacitor contact plug.

  In a related semiconductor device, bit lines connected to memory cells arranged along one direction are not laid out in a straight line, but are bent and meandered (in a snake pattern) (for example, a snake pattern). Patent Document 1).

JP 2007-287794 A

  As the integration of semiconductor devices increases, the elements contained therein, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), will also become smaller. In line with this, it is desirable to reduce the wiring and contact plugs, but the reduction of the wiring and the like is difficult because it leads to an increase in electrical resistance and, consequently, an increase in power consumption. Therefore, downsizing of wiring and the like is realized mainly by narrowing the wiring interval.

  However, in the above-described COB structure, a capacitor contact plug is formed between the bit lines. For this reason, if the interval between the bit lines is narrowed in order to meet the demand for further higher integration of the semiconductor device, it becomes difficult to form a capacitor contact plug. Therefore, in order to meet the demand for higher integration of the semiconductor device, it is necessary to relax the restrictions on the arrangement of contact plugs due to wiring.

  A semiconductor device according to an embodiment of the present invention includes a plurality of first connection regions arrayed on a semiconductor substrate along a first direction and a second direction intersecting the first direction, A plurality of wirings that electrically connect the plurality of first connection regions for each column along the first direction, and the plurality of wirings are two wirings adjacent to each other in the second direction. Are arranged in different wiring layers and bent so that they partially overlap each other in a plan view and look like a honeycomb.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate; and a first direction and a second direction intersecting the first direction. Among the plurality of first connection regions to be arranged on the semiconductor substrate along the first direction, the first belonging to a column along the first direction located odd or even in the two directions A contact opening is formed in the first insulating film at a position corresponding to each connection region, a first wiring connecting the contact opening for each column along the first direction is formed, and the first A second insulating film is formed on an upper layer side than the first wiring, and among the plurality of first connection regions, the column is arranged along the first direction, which is even-numbered or odd-numbered with respect to the two directions. At a position corresponding to each of the first connection areas belonging to Forming a first contact plug that penetrates the two insulating films, and forming a second wiring that connects the first contact plug for each column along the first direction, The first wiring and the second wiring are formed so as to be bent so that they partially overlap each other in a plan view and look like a honeycomb.

  According to the present invention, the bit line is divided into two layers and arranged so as to partially overlap when viewed in the layer direction, so that the area occupied by the bit line can be substantially reduced. The arrangement | positioning area | region can be expanded.

1 is a plan view showing a partial configuration of a semiconductor device (DRAM) according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1. FIG. 2 is a sectional view taken along line B-B ′ of FIG. 1. FIG. 2 is a cross-sectional view taken along line C-C ′ in FIG. 1. FIGS. 2A and 2B are diagrams for explaining a manufacturing process of the semiconductor device of FIG. 1, where FIG. 1A is a cross-sectional view at a position corresponding to a cross section along line AA ′ in FIG. 1, and FIG. It is sectional drawing of the position corresponding to a line cross section. FIG. 4 is a diagram for explaining a process following the process of FIG. 3, where (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. 5A and 5B are diagrams for explaining a process following the process of FIG. 4, in which FIG. 5A is a cross-sectional view at a position corresponding to a cross section along line AA ′ in FIG. 1, and FIG. It is sectional drawing of the position corresponding to a cross section. 6A and 6B are views for explaining a process following the process of FIG. 5, where FIG. 5A is a cross-sectional view at a position corresponding to the cross section along line AA ′ in FIG. 1, and FIG. It is sectional drawing of the position corresponding to a cross section. 7A and 7B are diagrams for explaining a process following the process of FIG. 6, where FIG. 7A is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and FIG. It is sectional drawing of the position corresponding to a cross section. 8A and 8B are diagrams for explaining a process following the process of FIG. 7, in which FIG. 7A is a cross-sectional view at a position corresponding to the cross section along line AA ′ in FIG. 1, and FIG. It is sectional drawing of the position corresponding to a cross section. FIGS. 9A and 9B are diagrams for explaining a process subsequent to the process of FIG. 8, where FIG. 9A is a cross-sectional view at a position corresponding to the cross section along line AA ′ in FIG. 1, and FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 10 is a diagram for explaining a process following the process of FIG. 9, in which (a) is a cross-sectional view at a position corresponding to the cross section along the line AA ′ in FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 11 is a diagram for explaining a process following the process of FIG. 10, in which (a) is a cross-sectional view at a position corresponding to a cross section along line AA ′ in FIG. 1, and (b) is a line along BB ′ in FIG. It is sectional drawing of the position corresponding to a cross section. 11A and 11B are diagrams for explaining a process following the process of FIG. 11, in which FIG. 11A is a cross-sectional view at a position corresponding to the cross section along line AA ′ in FIG. 1, and FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 13 is a diagram for explaining a process following the process of FIG. 12, where (a) is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 14 is a diagram for explaining a process following the process of FIG. 13, where (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 15 is a diagram for explaining a process following the process of FIG. 14, where (a) is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. 15A and 15B are diagrams for explaining a process following the process of FIG. 15, wherein FIG. 15A is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 17 is a diagram for explaining a process following the process of FIG. 16, in which (a) is a cross-sectional view at a position corresponding to the cross section along the line AA ′ in FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 18 is a diagram for explaining a process following the process of FIG. 17, wherein (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 19 is a diagram for explaining a process following the process of FIG. 18, where (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. Sectional drawing of the position corresponding to a cross section, (c) is sectional drawing of the position corresponding to the CC 'line | wire cross section of FIG. 19A and 19B are diagrams for explaining a process subsequent to the process of FIG. 19, in which FIG. 19A is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and FIG. Sectional drawing of the position corresponding to a cross section, (c) is sectional drawing of the position corresponding to the CC 'line | wire cross section of FIG. FIG. 21 is a diagram for explaining a process following the process of FIG. 20, where (a) is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. Sectional drawing of the position corresponding to a cross section, (c) is sectional drawing of the position corresponding to the CC 'line | wire cross section of FIG. FIG. 22 is a diagram for explaining a process following the process of FIG. 21, in which (a) is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. Sectional drawing of the position corresponding to a cross section, (c) is sectional drawing of the position corresponding to the CC 'line | wire cross section of FIG. FIG. 23 is a diagram for explaining a process following the process of FIG. 22, in which (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. Sectional drawing of the position corresponding to a cross section, (c) is sectional drawing of the position corresponding to the CC 'line | wire cross section of FIG. FIG. 24 is a diagram for explaining a process following the process of FIG. 23, wherein (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. Sectional drawing of the position corresponding to a cross section, (c) is sectional drawing of the position corresponding to the CC 'line | wire cross section of FIG. FIG. 25 is a diagram for explaining a process following the process of FIG. 24, in which (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 26 is a diagram for explaining a process following the process of FIG. 25, where (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 27 is a diagram for explaining a process following the process of FIG. 26, where (a) is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 28 is a diagram for explaining a process following the process of FIG. 27, in which (a) is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. FIG. 29 is a diagram for explaining a process following the process of FIG. 28, wherein (a) is a cross-sectional view at a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. 29 is a diagram for explaining a process following the process of FIG. 29, wherein (a) is a cross-sectional view of a position corresponding to the cross section along line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. 30 is a diagram for explaining a process following the process of FIG. 30, wherein (a) is a cross-sectional view of a position corresponding to the cross section along the line AA ′ of FIG. 1, and (b) is a line BB ′ of FIG. It is sectional drawing of the position corresponding to a cross section. It is a top view which shows the partial structure of the semiconductor device (DRAM) based on the 2nd Embodiment of this invention.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. Here, a DRAM will be described as an example of a semiconductor device, but the present invention can also be applied to other semiconductor devices having a configuration in which a contact plug or the like is disposed between wirings.

  First, the configuration of the DRAM 100 according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2A to 2C.

  FIG. 1 is a plan view showing a schematic configuration of a cell array portion (memory cell region) in the DRAM 100. 2A, 2B, and 2C are a cross-sectional view taken along line A-A ', a cross-sectional view taken along line B-B', and a cross-sectional view taken along line C-C 'in FIG. 1, respectively. However, in FIG. 1, the capacitor located on the capacitor contact pad and the upper metal wiring located on the capacitor are omitted in order to clarify the arrangement state of the components. 2B and 2C are cross-sectional views parallel to the X ′ direction having an inclination with respect to the X direction in FIG. 1, but are shown as cross-sectional views parallel to the X direction for convenience.

  The DRAM 100 is manufactured using a semiconductor substrate. Here, a single crystal silicon substrate (hereinafter, silicon substrate) 1 is used as the semiconductor substrate.

  DRAM 100 includes a number of planar MOS (Metal Oxide Semiconductor) transistors (hereinafter referred to as MOS transistors) formed on silicon substrate 1. The cell array region usually includes thousands to hundreds of thousands of MOS transistors. FIG. 1 shows a region where several tens of MOS transistors are arranged.

  The MOS transistor is formed in the active region 1A. The active region 1A is defined by an element isolation region provided on the surface of the silicon substrate 1, that is, an STI (Shallow Trench Isolation) region 9.

  In the STI region 9, a groove is formed on the surface of the silicon substrate 1, and insulating films 6 and 7 are stacked and buried. The STI regions 9 extend linearly along the X ′ direction (first direction), and a plurality of STI regions 9 are formed at predetermined intervals in the Y direction (second direction). A region sandwiched between two STI regions 9 adjacent in the Y direction is an active region 1A. The active region 1A also extends linearly along the X ′ direction.

  The active region 1A has a plurality of first active regions 1B so as to correspond to a plurality of first bit lines (first wirings) and a plurality of second bit lines (second wirings) which will be described later. And a plurality of second active regions 1C. The first active region 1B and the second active region 1C are alternately arranged in the Y direction. A plurality of MOS transistors are arranged in each of the first active region 1B and the second active region 1C.

  As shown in FIGS. 2B and 2C, each MOS transistor covers the gate insulating film 16 covering the inner wall of the groove provided in the active region 1A, and the upper surface portion and part of the side surface portion of the gate insulating film 16. The intervening layer 17, the conductive film 18 that becomes the buried word line 23 provided inside the intervening layer 17, and the impurity diffusion layer (first region) that becomes the source region and drain region provided in the low-concentration impurity diffusion layer 11. 1 connection region) 26 and an impurity diffusion layer 37.

  The low concentration impurity diffusion layer 11 is provided on the active region 1A excluding the region where the gate insulating film 16 is provided. The low-concentration impurity diffusion layer 11 is formed by diffusing impurities having a conductivity type opposite to the conductive impurities contained in the silicon substrate 1. The upper surface of the conductive film 18 is covered with a liner film 20 and a buried insulating film 21.

  The conductive film 18 </ b> A shown in FIG. 2A is formed as the same conductive film as the conductive film 18 that becomes the buried word line 23. However, the conductive film 18A is electrically separated from the buried word line 23 by subsequent patterning. The conductive film 18A functions as a buried wiring 22 that electrically isolates MOS transistors adjacent in the X ′ direction. That is, the DRAM 100 employs a field shield (FS) element isolation configuration. By maintaining the voltage of the buried wiring 22 at a predetermined value, the parasitic transistor is turned off, so that adjacent MOS transistors on the same active region 1A can be electrically isolated. Note that the method of isolating the active region 1A in the X direction is not limited to the FS method, and an STI region may be used in the same way as the device isolation method in the Y direction.

  Next, the configuration above (upper layer side) of the MOS transistor will be described.

  A capacitor 48 is formed above each of the MOS transistors described above. The MOS transistor is combined with the capacitor 48 to constitute a memory cell. The capacitor 48 is a cylinder type capacitor, and includes a lower electrode 45, a capacitive insulating film 46, and an upper electrode 47. The lower electrode 45 is cylindrical and has an inner wall and an outer wall, and the inner wall side is embedded with a capacitive insulating film 46 and an upper electrode 47.

  Next, the configuration between the MOS transistor and the capacitor 48 will be described.

  In FIG. 2B, the impurity diffusion layer 26 is connected to the first lower electrode film 27. The first lower electrode film 27 is provided on the first interlayer insulating film (first insulating film) 24, and is connected to the impurity diffusion layer 26 through an opening formed in the first interlayer insulating film 24. A first upper conductive film 28 is provided on the first lower conductive film 27. The first lower conductive film 27 and the first upper conductive film 28 constitute a first bit line 30. An upper surface of the first bit line 30 is covered with a first mask film 29, and an upper surface portion and a side surface portion thereof are covered with an insulating film 31.

  In FIG. 2C, the impurity diffusion layer 26 is connected to the second lower conductive film 27A via a bit contact plug (first contact plug) 54. The second lower conductive film 27 </ b> A is provided on the second interlayer insulating film (second insulating film) 34. A second upper conductive film 28A is provided on the second lower conductive film 27A. The second lower conductive film 27A and the second upper conductive film 28A constitute a second bit line 30A. The upper surface of the second bit line 30A is covered with a second mask film 29A, and its side surface is covered with an insulating film 31A.

  The first bit line 30 and the second bit line 30A are stacked above the STI region 9, as shown in FIG. 2A. The first bit line 30 and the second bit line 30A are electrically separated by the second interlayer insulating film 34. That is, the second interlayer insulating film 34 is formed so as to cover the first bit line 30, and the second bit line 30 A is formed on the second interlayer insulating film 34.

  As understood from FIG. 1, each of the first bit line 30 and the second bit line 30A is formed to meander in a snake pattern. Further, the first bit line 30 and the second bit line 30A are arranged so that they partially overlap each other and look almost like a honeycomb.

  More specifically, each of the first bit line 30 and the second bit line 30A includes first and second portions overlapping with two adjacent STI regions 9, and the first and second portions. And a third portion intersecting the active region 1A located between the two STI regions 9. Here, the first portion is a portion that overlaps with the STI region 9 located on one side in the Y direction (for example, the upper side in FIG. 1) of the two adjacent STI regions 9. Further, the second portion is a portion that overlaps with the STI region 9 located on the other side in the Y direction (for example, the lower side in FIG. 1) of the two adjacent STI regions 9. The first portion of the second bit line 30A is disposed so as to be stacked on the second portion of the first bit line 30 located on one side with respect to the Y direction. In addition, the second portion of the second bit line 30A is disposed so as to be stacked on the first portion of the first bit line 30 located on the other side in the Y direction.

  The third portions of the first bit line 30 and the second bit line 30A extend substantially along the Y direction. The third portion of the first bit line 30 intersects with the first active region 1B, and the third portion of the second bit line 30A intersects with the second active region 1C. The third portion of the first bit line 30 is connected to the impurity diffusion layer 26 of the MOS transistor provided in the first active region 1B. Each of the third portions of the second bit line 30A is connected to the impurity diffusion layer 26 of the MOS transistor provided in the second active region 1C.

  By arranging the first bit line 30 and the second bit line 30A as described above, the first part of the first bit line 30 and the second part of the second bit line, or the first part The second portion of the bit line 30 and the first portion of the second bit line are alternately present with respect to the STI region 9 in the Y direction. As a result, as shown by a broken line in FIG. 1, a region where no bit line is arranged, that is, an empty space 5 is formed. In FIG. 1, one empty space 5 is shown for the sake of space, but actual empty spaces 5 are provided at a plurality of locations in the cell array portion.

  Referring to FIGS. 2B and 2C again, a capacitor contact plug (second contact plug) 41 and a capacitor contact pad 42 are formed on the impurity diffusion layer 37 of the MOS transistor. The impurity diffusion layer 37 is connected to the lower electrode 45 through the capacitor contact plug 41 and the capacitor contact pad 42.

  The capacitor contact plug 41 has a laminated structure in which an intervening layer 39 is inserted between the conductive film 38 and the conductive film 40. A side surface portion of the capacitor contact plug 41 is covered with a sidewall insulating film 36.

  The capacitor contact pad 42 is provided to ensure an alignment margin between the capacitor 48 and the capacitor contact plug 41. Therefore, the capacitor contact pad 42 does not need to cover the upper surface of the capacitor contact plug 41. The capacitor contact pad 42 may be located on the capacitor contact plug 41 and connected to at least a part thereof.

  Referring to FIG. 2A, the first bit line 30 and the first mask film 29 are formed on the first interlayer insulating film 24 by the insulating film 31, the first liner film 32, and the first coating insulating film 33 (hereinafter referred to as the first insulating film 33). Is covered with a first SOD [Spin On Dielectrics] 33). Further, the second bit line 30A and the second mask film 29A are formed on the second interlayer insulating film 34 to be the insulating film 31A, the second liner film 32A, and the second coating insulating film 33A (hereinafter, Each side surface is covered with a second SOD 33A.

  As shown in FIGS. 2B and 2C, the sidewall insulating film 36 formed on the side surface of the capacitor contact plug 41 includes the first interlayer insulating film 24, the insulating film 31, the first liner film 32, the first SOD 33, the second The side surfaces are covered with the interlayer insulating film 34, the insulating film 31A, the second liner film 32A, and the second SOD 33A.

  The capacitor contact pad 42 is covered with a stopper film 43 for protecting the second SOD 33A. A third interlayer insulating film 44 is provided on the stopper film 43. Since the lower electrode 45 is formed in the cylinder hole 44A penetrating the third interlayer insulating film 44 and the stopper film 43, the lower electrode 45 is in contact with the third interlayer insulating film 44 and the stopper film 43.

  The upper surface of the third interlayer insulating film 44 is covered with a capacitive insulating film 46, and the exposed surface of the capacitive insulating film 46 is covered with an upper electrode 47. The upper electrode 47 is covered with a fourth interlayer insulating film 49. A contact plug 50 is provided in the fourth interlayer insulating film 49. An upper metal wiring 51 is provided on the fourth interlayer insulating film 49. The upper electrode 47 of the capacitor 48 is connected to the upper metal wiring 51 through the contact plug 50. The upper metal wiring 51 and the fourth interlayer insulating film 49 are covered with a protective film 52.

  As described above, according to DRAM 100 according to the present embodiment, the bit lines are divided and laminated into the first bit line arranged in the lower layer and the second bit line arranged in the upper layer. In such an arrangement, the arrangement density of the bit lines can be reduced as compared with the case where the bit lines are arranged in one layer. That is, an empty space where no bit line is arranged can be provided. As a result, the contact area between the capacitive contact portion on the surface of the semiconductor substrate and the capacitive contact plug can be expanded, and a DRAM having a capacitive contact with reduced contact resistance can be provided.

  Next, a method for manufacturing DRAM 100 according to the present embodiment will be described with reference to FIGS. In each figure, (a) is a diagram corresponding to the cross section along line AA ′ in FIG. 1, (b) is a diagram corresponding to the cross section along line BB ′ in FIG. 1, and (c) is C in FIG. The figure corresponding to the -C 'line cross section is shown. 2B and 2C, (b) and (c) display a cross section parallel to the X ′ direction as a cross section parallel to the X direction.

First, in order to obtain the state shown in FIGS. 3A and 3B, a sacrificial film 2 and a mask film 3 are sequentially deposited on a P-type silicon substrate 1. The sacrificial film 2 may be, for example, a silicon oxide film (SiO ₂ ) formed by a thermal oxidation method. The mask film 3 may be, for example, a silicon nitride film (Si ₃ N ₄ ) formed by a thermal CVD (Chemical Vapor Deposition) method.

  Next, the mask film 3, the sacrificial film 2 and the silicon substrate 1 are patterned using a photolithography technique and a dry etching technique. Thereby, an element isolation groove 4 (trench) for partitioning the active region 1A is formed in the silicon substrate 1. The element isolation groove 4 is formed as a line pattern extending in the X direction. The region that becomes the active region 1 </ b> A is covered with the beauty film 2 and the mask film 3.

  Next, an insulating film 6 is formed on the surface of the silicon substrate 1 and the mask film 3 in order to obtain the state shown in FIGS. The insulating film 6 may be a silicon oxide film formed by a thermal oxidation method, for example. Thereafter, an insulating film 7 is deposited so as to fill the inside of the element isolation trench 4. For example, the insulating film 7 may be a silicon nitride film formed by a thermal CVD method. Subsequently, the insulating film 7 is etched back to leave the insulating film 7 only in the element isolation trench 4.

  Next, in order to obtain the state shown in FIGS. 5A and 5B, the buried film 8 is deposited so as to fill the inside of the element isolation trench 4, and the surface is planarized to expose the mask film 3. . The buried film 8 may be a silicon oxide film formed by plasma CVD, for example. For the planarization, for example, a CMP (Chemical Mechanical Polishing) method can be used.

  Thereafter, the mask film 3 and the sacrificial film 2 are removed by wet etching, and a part of the insulating film 6 and the buried film 8 are removed, and the surface position of the buried film 8 is roughly set to the surface position of the silicon substrate 1. Match. Thereby, a line-shaped element isolation region using the STI 9 is formed.

  Next, as shown in FIGS. 6A and 6B, a sacrificial film 10 is formed on the surface of the silicon substrate 1. The sacrificial film 10 may later be a silicon oxide film formed by a thermal oxidation method. Thereafter, an N-type low-concentration impurity diffusion layer 11 is formed by injecting a low-concentration N-type impurity (such as phosphorus) into the silicon substrate 1 by an ion implantation method. The low concentration impurity diffusion layer 11 functions as (a part of) a source / drain (S / D) region of a transistor to be formed later.

  Next, in order to obtain the state shown in FIGS. 7A and 7B, a lower mask layer 12 and an upper mask layer 13 are sequentially deposited on the sacrificial film 10 so as to form a gate electrode trench (trench) pattern. The lower mask layer 12 and the upper mask layer 13 are patterned. Here, the lower mask film 12 may be, for example, a silicon nitride film formed by a CVD method. The upper mask film 13 may be a carbon film (amorphous carbon film) formed by plasma CVD.

  Next, as shown in FIGS. 8A and 8B, the silicon substrate 1 is etched by dry etching to form a gate electrode groove (trench) 15. The gate electrode trench 15 is formed as a line pattern extending in the Y direction intersecting with the active region 1A. On the side surface portion of the gate electrode trench 15 in contact with the STI 9, the thin film silicon substrate 1 remains in a sidewall shape and functions as a channel region 14 of the transistor. Further, at least a part of the lower layer mask film 12 remains on the silicon substrate 1 excluding the inside of the gate electrode trench 15.

  Next, as shown in FIGS. 9A and 9B, a gate insulating film 16 is formed, and an intervening layer 17 and a conductive layer 18 are sequentially deposited thereon. As the gate insulating film 16, a silicon oxide film formed by thermal oxidation can be used. The intervening layer 17 may be, for example, a titanium nitride (TiN) layer formed by a CVD method. The conductive layer 18 may be a tungsten (W) layer.

  Next, as shown in FIGS. 10A and 10B, the conductive layer 18 is etched back so that the conductive film 18 remains at the bottom of the gate electrode trench 15. Note that the height of the remaining conductive film 18 can be controlled by the etching back processing time.

  Subsequently, as shown in FIGS. 11A and 11B, an unnecessary intervening layer is formed by dry etching so that the intervening layer 17 remains at the same height as the surface of the conductive film 18 at the bottom of the gate electrode trench 15. 17 is removed. Note that the height of the remaining intervening layer 17 can be controlled by the dry etching processing time. By this dry etching, the buried word line 23 and the buried wiring 22 formed of the conductive film 18 having the same surface height as the intervening layer 17 can be formed at the bottom of the gate electrode trench 15.

Next, as shown in FIGS. 12A and 12B, a liner film 20 is formed so as to cover the remaining conductive film 18 and the inner wall of the gate electrode trench 15, and a buried insulating film 21 is formed thereon. To deposit. The liner film 20 may be a silicon nitride film formed by a thermal CVD method. As the buried insulating film 21, a silicon oxide film formed by a plasma CVD method, an SOD film as a coating film, or a laminated film thereof can be used. When the SOD film is used, annealing is performed in a high-temperature water vapor (H ₂ O) atmosphere to reform the solid silicon oxide film.

  Next, in order to obtain the state shown in FIGS. 13A and 13B, the surface of the buried insulating film 21 is polished by CMP until the liner film 20 is exposed. Subsequently, a part of the buried insulating film 21, a part of the liner film 20, a part of the gate insulating film 16, the lower mask film 12 and the sacrificial film 10 are removed by etching, and the remaining buried insulating film 21 is removed. The surface is made to be approximately the same height as the surface of the silicon substrate 1. As a result, the upper surfaces of the buried word line 23 and the buried wiring 22 for element isolation are insulated.

  Next, in order to obtain the state shown in FIGS. 14A and 14B, a first interlayer insulating film 24 is formed. The first interlayer insulating film 24 may be a silicon oxide film formed by plasma CVD. Then, by using a photolithography technique and a dry etching technique, a part of the first interlayer insulating film 24 is removed to form a plurality of bit contact openings 25. The plurality of bit contact openings 25 are arranged in the XY direction.

The plurality of bit contact openings 25 are formed on the first active region 1B and are not formed on the second active region 1C. The surface of the silicon substrate 1 is exposed at the bottom of each bit contact opening 25. After the bit contact opening 25 is formed, an N-type impurity (such as arsenic) is ion-implanted to form an N-type impurity diffusion layer 26 in the vicinity of the surface of the silicon substrate 1. The formed N-type impurity diffusion layer 26 functions as a source / drain region of the transistor.

  Next, as shown in FIGS. 15A and 15B, a first lower conductive film 27, a first upper conductive film 28, and a first mask film are sequentially deposited. The first lower electrode film 27 is formed so as to cover the impurity diffusion layer 26 and the first interlayer insulating film 24. The first lower electrode film 27 may be a polysilicon film containing an N-type impurity (such as phosphorus) by a thermal CVD method. The first upper conductive film 28 may be tungsten formed by sputtering. The first mask film 29 may be a silicon nitride film formed by plasma CVD. The first mask film 29 may be formed with a thickness of 200 nm, for example.

  Next, as shown in FIGS. 16A and 16B, the laminated film of the first lower conductive film 27, the first upper conductive film 28, and the first mask film 29 is patterned into a line shape, and the first A first bit line 30 composed of one lower conductive film 27 and a first upper conductive film 28 is formed. In the following description, the first bit line 30 including the first mask film 29 may be referred to.

  The first bit line 30 (first portion and second portion) is formed as a pattern extending in the X direction intersecting with the buried word line 23. In FIG. 1, the first portion, the second portion, and the third portion of the bit line 30 are drawn as straight lines, but at least a portion may be curved. In particular, the shape of the connecting portion between the first portion or the second portion and the third portion can be a curved shape.

  In the surface portion of the silicon substrate 1 exposed in the bit contact opening 25, the impurity diffusion layer 26 (one of the source / drain regions) and the first lower conductive film 27, which is the lower layer of the first bit line 30, Connect.

  Next, as shown in FIGS. 17A and 17B, an insulating film 31 and a first liner film 32 are sequentially formed. The insulating film 31 is formed so as to cover the side surface of the first bit line 30. For example, the insulating film 31 may be a silicon nitride film formed by a thermal CVD method. The film thickness of the insulating film 31 can be set to 30 nm, for example. The first liner film 32 is formed so as to cover the upper surface of the insulating film 31. The first liner film 32 may be a silicon nitride film formed by a thermal CVD method. The film thickness of the first liner film 32 can be 10 nm.

  Note that the first lower conductive film 27 and the first upper conductive film 28 constituting the first bit line 30 are used as gate electrodes of the planar type MOS transistor in the peripheral circuit portion. Further, the first insulating film 31 covering the side surface of the first bit line 30 is used as a part of the side wall of the gate electrode in the peripheral circuit portion.

Next, in order to obtain the states shown in FIGS. 18A and 18B, the first SOD film 33 is formed. The first SOD film 33 is applied to the coating insulating film so as to embed the first bit line 30, and then annealed in a high-temperature steam (H ₂ O) atmosphere to convert the coating insulating film into a solid silicon oxide film. It is formed by reforming.

  Subsequently, the first SOD is polished by CMP to expose the upper surface of the first liner film 32. Then, a second interlayer insulating film 34 is formed so as to cover the exposed upper surfaces of the first liner film 32 and the first SOD film 33. The second interlayer insulating film 34 may be a silicon oxide film formed by a plasma CVD method.

  Next, in order to obtain the states shown in FIGS. 19A, 19B, and 19C, the second interlayer insulating film 34, the first SOD 33, and the first liner film 32 are used by using a photolithography technique and a dry etching technique. The insulating film 31 and a part of the first interlayer insulating film 24 are removed to form a plurality of bit contact openings 25A.

  Etching conditions when the second interlayer insulating film 34, the first SOD 33, and the first interlayer insulating film 24 are silicon oxide films are, for example, as follows.

Hexafluoro-1.3-butadiene (C ₄ F ₆ ), trifluoromethane (CHF ₃ ) and oxygen (O ₂ ) are used as raw material gases, and the flow rate is 30 sccm [Standard Cubic Centimeter per Minute] (C ₄ F ₆ ) and 30 sccm (CHF). ₃ ) and 25 sccm (O ₂ ), the source power is 500 W, the bias power is 1000 W, the stage temperature is 20 ° C., and the pressure is 25 mTorr.

  The dry etching conditions when the first liner film 32 and the insulating film 31 are silicon nitride films are as follows.

Using trifluoromethane (CHF ₃ ) and oxygen (O ₂ ) as source gases, the flow rates are 80 sccm (CHF ₃ ) and 20 sccm (O ₂ ), the source power is 500 W, the bias power is 1000 W, the stage temperature is 20 ° C., and the pressure is 30 mTorr. And

  Under the above conditions, anisotropic etching in the normal direction of the silicon substrate 1 can be realized. Further, by changing the conditions for each film to be etched, the selectivity for each film can be made 5 or more. Therefore, when the second interlayer insulating film 34, the first SOD 33, and the first interlayer insulating film 24, which are silicon oxide films, are dry etched, the first mask film 29, which is a silicon nitride film, is not removed, and the bit contact opening is not removed. The first upper conductive film 28 is not exposed inside 25A.

  Even if the first mask film 29, which is a silicon nitride film, is exposed during the dry etching of the first liner film 32, which is a silicon nitride film, and the insulating film 31, the first mask film 29 is removed from the first mask film 29. By forming it sufficiently thicker than the liner film 32 and the insulating film 31, the first mask film 29 can be left. Therefore, even in such a case, the first upper conductive film 28 is not exposed inside the bit contact opening 25A.

  The plurality of bit contact openings 25A are arranged in the XY direction. The bit contact opening 25A is formed on the second active region 1C and is not formed on the first active region.

  The surface of the silicon substrate 1 is exposed at the bottom of the bit contact opening 25A. N-type impurities (such as arsenic) are ion-implanted into the exposed silicon substrate 1 to form an N-type impurity diffusion layer 26 </ b> A near the surface of the silicon substrate 1. The formed N-type impurity diffusion layer 26A functions as a source / drain region of the transistor.

Next, in order to obtain the states shown in FIGS. 20A, 20B, and 20C, a silicon nitride film is formed so as to cover the inner wall of the bit contact opening 25A. A thermal CVD method can be used to form the silicon nitride film. The film forming conditions in this case are, for example, that dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) are used as source gases, and the flow rates are 75 sccm (SiH ₂ Cl ₂ ) and 750 sccm (NH ₃ ), respectively. The temperature is 630 ° C. and the pressure is 300 Pa.

Next, the formed silicon nitride film is etched back to form a sidewall insulating film 53. The etch-back conditions are, for example, trifluoromethane (CHF ₃ ), oxygen (O ₂ ), and argon (Ar) as source gases, flow rates of 80 sccm (CHF ₃ ), 20 sccm (O ₂ ), 150 sccm (Ar), source The power is 1700 W, the bias power is 3000 W, the stage temperature is 30 ° C., and the pressure is 30 mTorr.

Next, a polysilicon film containing phosphorus is deposited inside the bit contact opening 25A in which the sidewall insulating film 53 is formed. A thermal CVD method can be used for depositing the polysilicon film. The film formation conditions are, for example, monosilane (SiH ₄ ) as a source gas, a flow rate of 1500 sccm, and a heating temperature of 550 ° C.

  Next, the surface of the polysilicon film is polished until the upper surface of the second interlayer insulating film 34 is exposed, a part of the polysilicon film is removed, and a bit contact plug 54 is formed. The impurity diffusion layer 26A (one of the source / drain regions) and the bit contact plug 54 are connected to the surface of the silicon substrate 1 exposed in the bit contact opening 25A.

  Next, as shown in FIGS. 21A, 21B, and 21C, a second lower conductive film 27A, a second upper conductive film 28A, and a second mask film 29A are sequentially deposited. The second lower conductive film 27A is formed so as to cover the second interlayer insulating film 34 and the bit contact plug 54. The second lower conductive film 27A may be a polysilicon film containing an N-type impurity (such as phosphorus). The second lower conductive film 27A can be formed by, for example, a thermal CVD method. The second upper conductive film 28A may be a tungsten film formed by sputtering, for example. The second mask film 29A may be, for example, a silicon nitride film formed by plasma CVD.

  Next, as shown in FIGS. 22A, 22B, and 22C, the laminated film of the second lower conductive film 27A, the second upper conductive film 28A, and the second mask film 29A is formed into a line shape. Patterning is performed to form a second bit line 30A composed of the second lower conductive film 27A and the second upper conductive film 28A. In the following description, the second bit line 30A including the second mask film 29A may be referred to.

  The second bit line 30 </ b> A (first portion and second portion) is formed as a pattern extending in the X direction intersecting the embedded word line 23. In FIG. 1, the first portion, the second portion, and the third portion of the bit line 30A are drawn as straight lines, but at least a portion may be curved. In particular, the shape of the connecting portion between the first portion or the second portion and the third portion can be a curved shape.

  The second lower conductive film 27A, which is the lower layer of the second bit line 30A, is connected to the bit contact plug 54. As a result, the second lower conductive film 27A and the impurity diffusion layer 26A (one of the source / drain regions) are connected via the bit contact plug 54.

  Next, as shown in FIGS. 23A, 23B, and 23C, an insulating film 31A and a second liner film 32A are formed. The insulating film 31A is formed so as to cover the side surface of the second bit line 30A. The insulating film 31A may be a silicon nitride film formed by a thermal CVD method. Further, the second liner film 32A is formed so as to cover the upper surface of the insulating film. The second liner film 32A may be a silicon nitride film formed by a thermal CVD method.

Next, in order to obtain the states shown in FIGS. 24A, 24B, and 24C, a second SOD film 33A, which is a coating insulating film, is deposited so as to embed the second bit line 30A. Subsequently, the deposited second SOD film 33A is annealed in a high-temperature steam (H ₂ O) atmosphere to be modified into a solid silicon oxide film. Further, the surface of the second SOD film 33A is polished by CMP to remove a part thereof, and the upper surface of the second liner film 32A is exposed. Then, an interlayer insulating film (third insulating film) 55 is formed so as to be exposed and cover the surfaces of the second liner film 32A and the second SOD film 33A. The interlayer insulating film 55 may be a silicon oxide film formed by a plasma CVD method, for example.

Next, in order to obtain the state shown in FIGS. 25A and 25B, the capacitor contact opening 35 is formed by using the photolithography technique and the dry etching technique. The dry etching conditions at this time include, for example, trifluoromethane (CHF ₃ ), tetrafluoromethane (CF ₄ ), and oxygen (O ₂ ) as source gases, and flow rates of 80 sccm (CHF ₃ ), 110 sccm (CF ₄ ), and 2 sccm. (O ₂ ), source power is 500 W, bias power is 1000 W, stage temperature is 20 ° C., and pressure is 5 mTorr. Here, the capacitor contact opening 35 is formed by the SAC (Self Alignment Contact) method using the insulating film 31 and the first liner film 32 formed on the side surface of the first bit line 30 as sidewalls. For this reason, the first bit line 30 is not exposed inside the capacitor contact opening 35. Further, the surface of the silicon substrate 1 is exposed at a portion where the capacitor contact opening 35 and the active region 1A overlap.

  Next, a silicon nitride film is formed so as to cover the inner wall of the capacitor contact opening 35, and the formed silicon nitride film is etched back to form a sidewall insulating film 36. The silicon nitride film can be formed by, for example, a thermal CVD method.

  Subsequently, an N-type impurity (phosphorus or the like) is ion-implanted into the silicon substrate 1 exposed in the capacitor contact opening 35 to form an N-type impurity diffusion layer 37 near the surface of the silicon substrate 1. The formed N-type impurity diffusion layer 37 functions as a source / drain region of the transistor.

  The capacitor contact opening 35 can also be formed by the SAC method using the insulating film 31A and the second liner film 32A formed on the side surface of the second bit line 30A described above as sidewalls. Also in this case, the second bit line 30 </ b> A is not exposed inside the capacitor contact opening 35.

  Next, in order to obtain the state shown in FIGS. 26A and 26B, a polysilicon film containing phosphorus is deposited so as to fill the contact opening 35. A thermal CVD method can be used for depositing the polysilicon film. Then, the formed polysilicon film is etched back to leave the polysilicon film at the bottom of the capacitor contact opening 35 to form a conductive film 38.

  Thereafter, an intervening layer 39 is formed on the surface of the conductive film 38 by sputtering, and a conductive film 40 is deposited so as to store the inside of the capacitor contact 35. The intervening layer 39 may be, for example, a cobalt silicide (CoSi) layer. The conductive film 40 may be a tungsten film formed by a CVD method.

  Next, the conductive film 40 is polished by CMP, for example, until the surface of the second SOD 33 </ b> A is exposed, and the conductive film 40 is left only in the capacitor contact opening 35. As a result, a capacitive contact plug 41 formed by laminating the conductive film 38, the intervening layer 39, and the conductive film 40 is formed.

  Next, as shown in FIGS. 27A and 27B, a capacitor contact pad 42 is formed. In order to form the capacitor contact pad 42, for example, a stacked film in which a tungsten nitride (WN) film and a tungsten (W) film are sequentially deposited is formed by sputtering. The stacked film is patterned by using a photolithography technique and a dry etching technique to form the capacitive contact pad 42. The capacitor contact pad 42 is formed so as to be connected to the capacitor contact plug 41.

  Next, as shown in FIGS. 28A and 28B, a stopper film 43 is formed so as to cover the capacitor contact pad 42, and a third interlayer insulating film 44 is formed thereon. The stopper film 43 may be, for example, a silicon nitride film formed by a thermal CVD method. The third interlayer insulating film 44 may be a silicon oxide film formed by plasma CVD.

  Next, in order to obtain the state shown in FIGS. 29A and 29B, the cylinder hole 44A is formed by using a photolithography technique and a dry etching technique. The cylinder hole 44A is formed through the third interlayer insulating film 44 and the stopper film 43 so that the upper surface of the capacitor contact pad 42 is exposed.

  Next, the lower electrode 45 is formed so as to cover the inner wall of the cylinder hole 44A. The lower electrode 45 may be titanium nitride formed by a CVD method. The bottom of the lower electrode 45 is connected to the capacitor contact pad 42.

Next, as shown in FIGS. 30A and 30B, a capacitive insulating film 46 covering the surface of the lower electrode 45 is formed, and an upper electrode 47 is further formed. As the capacitor insulating film 46, zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or a stacked film thereof can be used. The capacitor insulating film 46 can be formed by an ALD (Atomic Layer Deposition) method. The upper electrode 47 may be titanium nitride formed by a CVD method.

  Next, in order to obtain the state shown in FIGS. 31A and 31B, a fourth interlayer insulating film 49 covering the upper electrode 47 is formed. The fourth interlayer insulating film 49 may be a silicon oxide film formed by plasma CVD.

  Subsequently, a contact hole (not shown) is formed in the fourth interlayer insulating film 49 by using a photolithography technique and a dry etching technique. Next, a conductive film is formed so as to fill the contact hole formed in the fourth interlayer insulating film 49. As the conductive film, a tungsten film formed by a CVD method can be used. Next, an unnecessary conductive film on the fourth interlayer insulating film 49 is removed by a method such as CMP to form a contact plug 50 in the contact hole.

  Next, the upper metal wiring 51 is formed on the fourth interlayer insulating film. The upper metal wiring 51 is formed by forming a metal film such as aluminum (Al) or copper (Cu) on the fourth interlayer insulating film 49 and patterning the metal film. The upper metal wiring 51 is formed so as to be connected to the contact plug 50. Thus, the upper metal wiring 51 is connected to the upper electrode 47 through the contact plug 50.

  Thereafter, if the protective film 52 is formed on the surface, the memory cell of the DRAM 100 is completed.

  As described above, according to the method of manufacturing the DRAM 100 according to the present embodiment, the portion where the first bit line and the second bit line are stacked can be provided, and the area occupied by both bit lines. Can be reduced. Thereby, the area where the capacitor contact can be formed can be expanded, and the cross-sectional area of the capacitor contact can be increased accordingly. As a result, the contact between the capacitor contact and the capacitor contact plug can be ensured and the contact resistance can be reduced.

  Next, with reference to FIG. 32, a semiconductor device according to the second embodiment of the present invention will be described.

  FIG. 32 is a plan view showing a configuration of a DRAM 200 which is an example of a semiconductor device according to the second embodiment. However, also in FIG. 32, in the same manner as in FIG. 1, in order to clarify the arrangement state of the components, the capacitor located on the capacitor contact pad and the upper metal wiring located on the capacitor are omitted. Further, in some capacitive contact pads, the lower layer is shown through the capacitive contact pad in order to clarify the positional relationship with the lower layer.

  The DRAM 200 has a plurality of active regions 1A arranged along the X direction and the Y direction perpendicular to the X direction. Each active region 1A is partitioned by STI 9 (STI region 9) in the X direction and the Y direction. That is, the rectangular active region 1A is partitioned by the STI 9 formed in a lattice shape. The width of the STI 9 is set to a value F (F value) equal to the minimum processing dimension in both the X direction and the Y direction.

  The active region 1A is formed in a rectangular shape whose longitudinal direction extends in the X direction. The dimension of the active region 1A is 5F, in which the short side in the Y direction has an F value and the long side in the X direction has a size five times the F value. The plurality of active regions 1A are arranged with a pitch in the X direction of 6F and a pitch in the Y direction of 2F to constitute a memory cell region.

The unit cell in the memory cell region occupies an area of 6F ² obtained by multiplying 3F in the X direction and 2F in the Y direction. A bit contact opening 25 or 25A serving as a bit line contact (BC) is disposed in the center of one active region 1A. Capacitor contact plugs 41 (or 41A) serving as capacitor contacts (SC) are disposed at both ends of one active region 1A. The formation positions of the bit contact openings 25 and 25A are different from each other. That is, the bit contact opening 25 is provided in the first interlayer insulating film 24, whereas the bit contact opening 25 A is provided in the first interlayer insulating film 24 and the second interlayer insulating film 34.

  The buried word lines 23 and 23A extend in the Y direction so as to cross the plurality of active regions 1A. The width of the buried word lines 23 and 23A in the X direction is equal to the F value. The buried word lines 23 and 23A are arranged one by one in one active region 1A, and the interval between them is an F value.

  Similar to the first embodiment, the first bit line 30 and the second bit line 30A are formed in different layers so as to be a lower layer side bit line (BL) and an upper layer side BL, respectively. . These bit lines extend in the X direction as a whole.

  The memory cell region includes a bit line single layer region 56 and a bit line stacked region 57 that are continuously and repeatedly arranged in the X direction.

  In the bit line single layer region 56, each of the first bit line 30 and the second bit line 30A extends in an oblique direction having an inclination with respect to the X direction. In the bit line single layer region 56, the first bit line 30 crosses over the bit contact opening 25, and the second bit line 30A crosses over the bit contact opening 25A.

  In the bit line stacked region 57, the first bit line 30 and the second bit line 30A both extend in the X direction, and the first bit line 30 and the second bit line 30A are in the second interlayer insulation. They are stacked via the film 34. Specifically, in each bit line stacked region 57, the first bit line 30 is stacked with one of the second bit lines 30A located on both sides, and the second bit line 30A is located on both sides. One bit line 30 is stacked. In the bit line stacked region 57, the first bit line 30 and the second bit line 30A are arranged between columns of the active regions 1A adjacent in the Y direction.

  Focusing on one bit line 30 or 30A, the bit line crosses over the bit contact openings 25 or 25A of the plurality of active regions 1A arranged in the X direction, and is arranged so as to sew the columns of the active regions 1A. Has been.

  The two bit lines 30 and 30A adjacent to each other are arranged symmetrically with respect to a straight line 60 that connects the stacked portions in the X direction in plan view.

  Further, a contact pad is formed at one end of each of the first bit line 30 and the second bit line 30A. These contact pads are provided in a peripheral circuit region arranged outside the memory cell region. The contact pad of the first bit line 30 and the contact pad of the second bit line 30A are formed at opposite ends. In FIG. 32, the lower BL contact 58 serving as the contact pad for the first bit line 30 is disposed on the right side, and the upper BL contact 59 serving as the contact pad for the second bit line 30A is disposed on the left side.

  As described above, the active region of the DRAM 100 according to the first embodiment extends linearly in the oblique direction (X ′ direction) inclined with respect to the X direction. The active region of the DRAM 200 according to the layout has a layout extending in the X direction. Other configurations of the DRAM 200 are the same as those of the DRAM 100.

  Even in the DRAM 200 in which the active region extends in the X direction, an empty space for one bit line can be secured in the bit line stacked region 57 as in the DRAM 100 according to the first embodiment. Therefore, it is possible to enlarge the area where the capacitor contact can be formed, and to increase the cross-sectional area of the capacitor contact. As a result, the contact between the capacitor contact plug and the capacitor contact can be ensured and the contact resistance can be reduced.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, these are included in the scope of the invention.

DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 1A Active region 1B 1st active region 1C 2nd active region 2 Sacrificial film 3 Mask film 4 Element isolation groove 5 Empty space 6 Insulating film 7 Insulating film 8 Buried film 9 STI region 10 Sacrificial film 11 Low-concentration impurity diffusion layer 12 Lower mask layer 13 Upper mask layer 14 Channel region 15 Gate electrode groove 16 Gate insulating film 17 Intervening layer 18 Conductive film 18A Conductive film 20 Liner film 21 Embedded insulating film 22 Embedded wiring 23 Embedded word line 24 first interlayer insulating film 25 bit contact opening 25A bit contact opening 26 impurity diffusion layer 26A impurity diffusion layer 27 first lower electrode film 27A second lower conductive film 28 first upper conductive film 28A second upper conductive film 29 First mask film 29A Second mask film 30 First bit line 30A Second bit line 31 Edge film 31A Insulating film 32 First liner film 32A Second liner film 33 First coating insulating film 33A Second coating insulating film 34 Second interlayer insulating film 35 Capacitor contact opening 36 Side wall insulating film 37 Impurity diffusion layer 38 conductive film 39 intervening layer 40 conductive film 41 capacitive contact plug 42 capacitive contact pad 43 stopper film 44 third interlayer insulating film 44A cylinder hole 45 lower electrode 46 capacitive insulating film 47 upper electrode 48 capacitor 49 fourth interlayer insulating film 50 contact plug 51 Upper metal wiring 52 Protective film 53 Side wall insulating film 54 Bit contact plug 55 Interlayer insulating film 56 Bit line single layer region 57 Bit line laminated region 58 Lower layer BL contact 59 Upper layer BL contact 60 Straight line 100 DRAM
200 DRAM

Claims (11)

A plurality of first connection regions arranged on the semiconductor substrate along a first direction and a second direction intersecting the first direction;
A plurality of wirings that electrically connect the plurality of first connection regions for each column along the first direction;
The plurality of wirings are bent so that two wirings adjacent to each other in the second direction are arranged in different wiring layers and partially overlap each other in a plan view. Semiconductor device.   2. The plurality of wirings are arranged in a snake pattern so as to sew a row of the first connection regions formed along the first direction in a plan view. A semiconductor device according to 1. One of the two wirings adjacent to each other in the second direction is formed on the first insulating film formed on the semiconductor substrate, and the first connection is made through a contact opening formed in the first insulating film. Each connected to an area,
The other of the two wirings adjacent to each other in the second direction is formed on a second insulating film formed on an upper layer side than the other, and penetrates the second insulating film and the first insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the first connection region via a formed contact plug.   The plurality of first connection regions are formed in the center of the corresponding active region, respectively, second connection regions are formed on both sides of the active region, and a cylinder type is formed in the second connection region. The semiconductor device according to claim 1, wherein a capacitor is connected.   Each of the plurality of first connection regions is one of a source region and a drain region of a transistor formed on the semiconductor substrate, and the second connection region is the other of a source region and a drain region of the transistor. The semiconductor device according to claim 4.   The semiconductor device according to claim 1, wherein the first direction and the second direction form an angle different from 90 degrees.   6. The semiconductor device according to claim 1, wherein the first direction and the second direction are orthogonal to each other. Forming a first insulating film on the semiconductor substrate;
Of a plurality of first connection regions to be arranged on the semiconductor substrate along a first direction and a second direction intersecting the first direction, odd-numbered or even-numbered with respect to the two directions Forming a contact opening in the first insulating film at a position corresponding to each of the first connection regions belonging to the column along the first direction located at
Forming a first wiring connecting the contact openings for each column along the first direction;
Forming a second insulating film on an upper layer side than the first wiring;
Among the plurality of first connection regions, at positions corresponding to each of the first connection regions belonging to a row along the first direction that is even or odd numbered with respect to the two directions, Forming a first contact plug penetrating the second insulating film;
Forming a second wiring for connecting the first contact plug for each column along the first direction;
The method of manufacturing a semiconductor device, wherein the first wiring and the second wiring are formed so as to overlap each other in a plan view so that the first wiring and the second wiring look like a honeycomb.   Each of the first wiring and the second wiring is formed in a snake pattern so as to sew a row of the first connection regions formed along the first direction in plan view. A method for manufacturing a semiconductor device according to claim 8. After forming the contact opening, introducing impurities into the semiconductor substrate to form a part of the plurality of first connection regions,
Before forming the contact plug, impurities are introduced into the semiconductor substrate to form the remainder of the plurality of first connection regions;
10. A method for manufacturing a semiconductor device according to claim 8, wherein A third insulating film is formed above the second wiring, and a second contact plug penetrating the third insulating film, the second insulating film, and the first insulating film is formed. ,
Forming a cylinder-type capacitor connected to the second contact plug;
The method of manufacturing a semiconductor device according to claim 8, 9 or 10.

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