Classifications

• • H10P50/283—
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
  • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain

Definitions

• the present invention relates to a method of producing a semiconductor substrate product and an etching liquid.
• An insulated gate field effect transistor has been developed, with installing a high-dielectric constant (high-k) film for a gate insulator film and a metal for a gate electrode.
• This type of transistor can reduce its gate-leak current and to keep the power consumption at a low level.
• the insulated gate field effect transistor can be prepared according to the following method. That is, a dummy non-dielectric film is formed from a silicon oxide film on a silicon substrate and a dummy gate is formed thereon, and thereafter n-type impurities (or p-type impurities) are introduced into silicon substrates on both sides of the dummy gate to form a source/a drain.
• the phenomenon similarly arises that the gate end sides of the extension layers are etched. This is because although the impurity concentration of the extension layer is lower than that of the source or the drain, there is a difference in the impurity concentration between the extension layer and the channel-forming region, and the conductivity type of the impurity is opposite to one another.
• a gate insulator film to be formed at the end of the extension layer is formed in the void in the case of forming a transistor. As a result, electric field gets centered on the portion, which gets to insulation breakdown. Thus, sometimes the transistor does not run.
• Non-Patent Literature 1 ⁇ Antoine Pacco et al.,ECS Trans., Vol.4 l,Issue5,p.37-43
• the present invention addresses to the provision of a method of producing a semiconductor substrate product and an etching liquid, each of which enables selective etching of a silicon oxide layer by protecting a layer containing impurity, while keeping a sufficient etching rate. Further, the present invention addresses to the provision of a method of producing a semiconductor substrate product and an etching liquid, each of which enables, if needed, no variation in etching between substrates and exhibits good production suitability with suppression of foaming.
• a method of producing a semiconductor substrate product having the steps of: providing a semiconductor substrate having two or more impurity-containing silicon layers and a silicon oxide layer, each of the impurity-containing silicon layers containing a different impurity from one another;
• the etching liquid having water, a hydrofluoric acid compound, and an anionic compound
• R 1 to R 3 each independently represent an alkyl group or an alkenyl group;
• Ar represents an aromatic ring;
• Ac represents -SO3M or -COOM;
• M represents a hydrogen atom or a cation;
• n represents an integer of 1 to 3;
• m represents an integer of 0 to 3;
• h represents an integer of 1 to 3;
• j represents 0 or 1;
• k represents 0 or 1; and the total of j and k j+k) is 1 or 2.
• R , Ac, m, and n have the same meanings as those of formula (2), respectively.
• anionic compound is an alkylbenzene sulfonic acid
• the impurity-containing silicon layer constitutes a ground for the silicon oxide layer.
• the impurity-containing silicon layers are an n-type semiconductor layer and a p-type semiconductor layer.
• the impurity-containing silicon layer is disposed at the position such that the impurity-containing silicon layer comes into contact with the etching liquid at the time of etching processing.
• the impurity-containing silicon layer has at least boron as an impurity.
• the impurity-containing silicon layer has at least phosphorus or arsenic as an impurity.
• An etching liquid having:
• the etching liquid for being applied onto a substrate, the substrate having two or more impurity-containing silicon layers and a silicon oxide layer, each of the impurity-containing silicon layers containing a different impurity from one another, the etching liquid for selectively etching the silicon oxide layer.
• hydrofluoric acid compound has a concentration from 0.01 mass% to 10 mass%.
• anionic compound has a concentration from 0.00001 mass% to 85 mass%.
• R 1 to R 3 each independently represent an alkyl group or an alkenyl group;
• Ar represents an aromatic ring;
• Ac represents -S0 3 M or -COOM;
• M represents a hydrogen atom or a cation;
• n represents an integer of 1 to 3;
• m represents an integer of 0 to 3;
• h represents an integer of 1 to 3;
• j represents 0 or 1;
• k represents 0 or 1; and the total of j and k (j+k) is 1 or 2.
• R 2 , Ac, m and n have the same meanings as those in formula (2), respectively.
• a method of producing a semiconductor substrate product having the steps of: preparing a silicon substrate having a p-type impurity layer, an n-type impurity layer, and a silicon oxide layer in the state of the layers each capable of being exposed on the surface of the silicon substrate, each of the p-type impurity layer and n-type impurity layer being an impurity-doped layer of silicon;
• an etching liquid comprising water, a hydrofluoric acid compound, and an anionic compound
• a method of producing a semiconductor element having the steps of:
• the term “having” is to be construed in the open- ended meaning as well as the term “comprising” or “containing.” Further, the term “preparing” or “providing” is to be construed in the broadest manner as the meaning of making materials ready to be used, e.g., not only the meaning of producing or synthesizing the materials, but also purchasing them.
• anionic surfactant has a containment relationship with the anionic compound.
• anionic compounds having 3 or more carbon atoms act as the anionic surfactant.
• the silicon oxide layer can be subjected to selective etching with respect to the impurity-containing silicon layer with a sufficient etching rate.
• this method is able to produce a higher-quality semiconductor substrate product such as a High-K/Metal Gate transistor, of which miniaturization has been further advanced recently, and a higher-quality semiconductor device using the same.
• the production method of the present invention realizes, if needed, a good etching with suppression of variation in etching between substrates (substrate dependency) and good production suitability with suppression of foaming.
• the etching liquid of the present invention is useful for application to production of the semiconductor substrate product and the semiconductor device each of which achieves high quality as described above.
• Fig.l is a main part-enlarged sectional view schematically showing one of preferable embodiments of the production method according to the present invention. ⁇ Fig- 2 ⁇
• Fig.2 is a main part-enlarged sectional view schematically showing one of preferable embodiments (continued) of the production method according to the present invention (however, the enlarged portion inside of the circle shows the state of an example of the conventional art).
• a single crystal silicon substrate is used as substrate 1 1.
• well 12 is formed in the region where a transistor is formed, and further a channel dope layer 13 is formed.
• the well 12 is prepared so as to get a p-type well.
• boron (B + ) is used as an ion species, and an implant energy from lOOkeV to 2MeV and a dose amount of 1 ⁇ 10 1 1 atom/cm 2 to 1 ⁇ 10 12 atom/cm are employed.
• the well 12 is prepared so as to get an n-type well.
• the well 12 may not be produced depending on a conductivity type of the substrate 1 1.
• the channel dope layer 13 is prepared so as to get a p-type.
• boron (B + ) is used as an ion species, and an implant energy from lOkeV to 20KeV and a dose amount of 1 ⁇ 10 12 atom/cm 2 to 2 ⁇ 10 13 atom/cm 2 are employed.
• the channel dope layer 13 is prepared so as to 0 get an n-type.
• an element isolation (not shown in Fig. 1) that electrically sectionalizes a formation region of an element such as a transistor is usually formed by an insulating film element isolation (for example, STI; Shallow Trench Isolation), or a diffusion layer element isolation.
• substrate 11 besides the above-described single crystal silicon substrate, various kinds of substrates having silicon layer, such as SOI (Silicon On Insulator) substrate, SOS (Silicon On Sapphire) substrate, a compound
• semiconductor substrate having silicon layer may be used.
• a circuit, an element, and the like may be formed, in advance, on the substrate 1 1.
• a dummy film and a dummy gate film are formed on the substrate 1 1.
• a silicon oxide film is used as the dummy film 14.
• the silicon oxide film is formed, for example, in accordance with a CVD method, a thermal oxidation method, a rapid thermal oxidation method, a radical oxidation method, or the like, and impurities such as germanium, carbon, or the like may be incorporated in the film.
• the dummy gate film and the dummy film are processed using a lithographic technique to form a dummy gate (not shown in Fig. 1).
• the simultaneously processed dummy film 14 is left at the foot of the dummy gate.
• extension layers 15 and 16 are formed above the substrate 1 1 at each side of the dummy gate so that these layers are incorporated under the end of gate electrode, in order to improve pressure resistance by reducing a hot carrier.
• n-type impurities for example, arsenic (As + )
• implantation is performed under the conditions of implantation energy: from 0.1 KeV to 5KeV and dose amount from 5x l0 13 atom/cm 2 to 2x l0 16 atom/cm 2 .
• carbon may be doped at the formation region of the extension layers 15 and 16, in order to improve mobility of transistor. This is because tensile stress is generated by doping carbon into the extension layers 15 and 16, and the channel dope layer 13 receives the resultant tensile stress whereby mobility of an nMOS (nMIS) transistor is improved.
• nMIS nMOS
• germanium that generates compressive stress is doped into the extension layers 15 and 16, in order to improve mobility of transistor.
• halo layers 19 and 20 are formed at the positions that becomes respectively the end of source 17 and the end of drain 18 under the extension layers 15 and 16.
• the halo layers are formed by using BF 2 + as an ion species of a p-type impurity under the conditions of implantation energy: from lOKeV to 15KeV and dose amount from l x lO 12 atom/cm 2 to 1 > ⁇ 10 15 atom/cm 2 .
• the halo layers 19 and 20 are provided to reduce the impact of punch through generated in association with a short channel effect, and to adapt transistor characteristics to a desired value.
• these layers are formed by ion implantation of impurities each having a conductivity type opposite to that of the source 17 and the drain 18, and are usually formed so that impurity concentration of the halo layers is higher than that of the channel dope layer 13.
• Fig. 1 (a) shows the state immediately after formation of the halo layers 19 and 20. Formation of the halo layers 19 and 20 prior to removal of the dummy film 14 has the advantage that the dummy film 14 acts as a buffer film whereby damage to the channel dope layer 13 due to ion implantation is suppressed.
• the side wall-forming insulation film is etched using an etchback technique in a manner such that the side wall-forming insulation film is left at a sidewall of the dummy gate.
• sidewalls 21 are formed at the sidewalls of the dummy gate.
• the side wall-forming insulation film is formed of a silicon nitride film, favorably in accordance with a usual chemical vapor deposition.
• the source 17 and the drain 18 are formed on the substrate 1 1.
• the source 17 and the drain 18 are formed using, for example, an ion implantation technique in a manner such that n type impurities (for example, phosphorus (P + ) or arsenic (As + )) are doped up to the position deeper than the extension layers 15 and 16.
• n type impurities for example, phosphorus (P + ) or arsenic (As + )
• the source 17 and the drain 18 are formed using arsenic (As + ) as n-type impurities under the conditions of implantation energy: from lOKeV to 50KeV and dose amount from l x lO 12 atom/cm 2 to 5 l0 16 atom/cm 2 .
• an interlayer insulation layer 22 is formed on the entire surface of the substrate 11 of the side where a dummy gate has been formed. Further, the surface of the interlayer insulation layer 22 is subjected to a planarization step.
• the interlayer insulation layer 22 is formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.
• CMP Chemical Mechanical Polishing
• the dummy gate is selectively removed by etching using the interlayer insulation layer 22 as an etching mask.
• the etching of the dummy gate may be a wet etching or a dry etching.
• the above-described dummy film 14 is selectively removed in accordance with the wet etching.
• an etching liquid containing water, a hydrofluoric acid compound, and an anionic compound is used.
• the etching liquid is described below.
• the state immediately after removal of the dummy film 14 is shown in Fig. 2 (process (b)).
• the etching liquid only the dummy film 14 of silicon oxide is removed by etching without etching the extension layers 15 and 16 that are the underlying silicon layer. By this, generation of void is prevented in the extension layers 15 and 16 at the gate end.
• the tip of the extension layer 16 is shown by enlarging it in a circle.
• the state in which a void (depression) v generates there is illustrated.
• the void v can be favorably suppressed or prevented.
• a gate insulator film is formed on a surface of the exposed channel dope layer 13 and on sidewalls of the sidewalls 21, and the gate electrode film is formed so as to implant it between both sidewalls 21.
• redundant gate electrode film and gate insulator film on the interlayer insulation layer 22 are removed.
• a CMP technique is ordinarily used.
• a gate electrode that is composed of a gate electrode film is formed on the channel dope layer 13 between both side walls 21 through the gate insulator film.
• High-k film can be used.
• High-k film include hafnium oxide (Hf0 2 ), hafnium aluminum oxide (HfA10 2 ), hafnium silicate
• the gate insulator film may be a laminated film of a silicon oxide film and a silicon oxynitride film.
• Examples of the above gate electrode include titanium nitride (TiN), titanium (Ti), titanium silicon (TiSi), nickel (Ni), nickel silicide (NiSi), hafnium (Hf), hafnium silicide (HfSi), tungsten (W), tantalum (Ta), tantalum silicide (TaSi), tantalum nitride silicide (TaSiN), cobalt (Co), cobalt silicide (CoSi), ruthenium (Ru), and indium (Ir).
• the film is usually formed by ALD method or PVD: Physical Vapor Deposition) method.
• the dose amount and the implantation energy described in the above-described ion implantation steps are examples, and these amount and energy are appropriately determined according to the required characteristics of a transistor.
• the impurity-containing silicon layer at least two layers exist, and the impurities that has been introduced into the two layers are different from one another.
• the impurity-containing silicon layer is preferably disposed at the position such that the impurity-containing silicon layer comes into contact with the etching liquid at the time of etching processing. More specifically, an embodiment is exemplified in which the impurity-containing silicon layer constitutes a ground for the silicon oxide layer that is removed by etching.
• the impurity is explained by the above-described example, by virtue of the fact that the conductivity type impurity (for example, p-type) of a channel dope layer and the conductivity type impurity (for example, n-type) of an extension layer are different from one another, the effects of the present invention are more favorably exhibited.
• the above-described bimetallic corrosion becomes conspicuous.
• a damage of the layer, that becomes base in particular under the conditions that an unevenness of noble /base in potential appears on the exposed area can be suppressed or prevented.
• each layer may contain impurities or accessory components, insofar as a desired effect is exhibited.
• the silicon oxide layer may contain elements other than both silicon and oxygen (for example, carbon, nitrogen or the like).
• the etching liquid of the present invention can be quite efficiently used for the wet etching that has been explained in the step of removing the above-described dummy film 14.
• the etching liquid of the present embodiment contains water, a hydrofluoric acid compound, and an anionic compound. This enables the above- described removal of a silicon oxide layer without excessively etching the impurity- doped silicon layer that is disposed as a ground of the silicon oxide layer. The reason why such special effect is exhibited is not clear. However, an explanation including some presumption is as follows.
• Extension layers 15 and 16 are constituted of an impurity-containing silicon layer, and it is thought that a Si-H bond is exposed on the surface of this silicon layer. It is presumed that the anionic compound in the etching liquid adsorbs to the Si-H bond to form a protective layer, thereby inhibiting the silicon layer from being etched. On the other hand, it is thought that a hydrogen bond (Si-O-H) also exists on the surface of silicon oxide and the anionic compound adsorbs thereto. However, it is presumed that the anionic compound adsorbs selectively or predominantly to the Si-H, which results in achievement of a desirable selectivity while maintaining good etching rate.
• the etching liquid of the present invention contains an anionic compound.
• the anionic compound although it is not particularly limited, typically means a compound having a hydrophilic group and a lipophilic group in the molecule thereof, wherein a portion of the hydrophilic group dissociates in an aqueous solution to become an anion or to have an anionic property.
• the anionic compound may exist as an acid with a hydrogen atom, or may be an anion derived from dissociation of the acid, or may be a salt thereof.
• the anionic compound may be a non- dissociative compound, as long as it has an anionic property, and therefore an acid ester and the like are included therein.
• the anionic compound preferably has at least one carbon atom.
• the carbon number thereof is preferably at least 3, more preferably at least 5, and particularly preferably at least 10.
• the upper limit of the carbon number is not particularly limited. However, the carbon numbers of 40 or less are practical. By setting the carbon number to the lower limit or greater, effective etching selectivity is preferably achieved.
• anionic compound having from 1 to 40 carbon atom(s) examples include a carboxylic acid compound having from 1 to 40 carbon atom(s), a phosphoric acid compound having from 1 to 40 carbon atom(s), and a sulfonic acid compound having from 1 to 40 carbon atom(s).
• polyoxyethylene alkylether carboxylic acid a polyoxyethylene alkyl ether acetic acid, a polyoxyethylene alkylether propionic acid, an alkyl phosphoric acid, an aliphatic acid and salts of these acids are preferred.
• an alkylbenzene sulfonic acid, an alkylnaphthalene sulfonic acid, an alkyldiphenylether mono-sulfonic acid, an alkyldiphenylether disulfonic acid, or salts of these acids, or mixtures thereof are preferred.
• saltsalt include an ammonium salt, a sodium salt, a potassium salt, and a tetramethyl ammonium.
• the above-described anionic compound is preferably constituted of the compound represented by any one of formulae (1) to (3) described below.
• An alkylbenzene sulfonic acid, an alkylnaphthalene sulfonic acid, an alkyldiphenylether mono-sulfonic acid, an alkyldiphenylether disulfonic acid, or salts of these acids, or mixtures thereof are more preferred.
• An alkyldiphenylether mono-sulfonic acid, an alkyldiphenylether disulfonic acid, or salts of these acids, or mixtures thereof are particularly preferred.
• the compounds represented by the formulae (1) to (3) are typically known as a surfactant.
• R 1 to R 3 each independently represent an alkyl group or an alkenyl group.
• Ar represents an aromatic ring.
• Ac represents -S0 3 M or -COOM.
• M represents a hydrogen atom or a cation
• n represents an integer of 1 to 3.
• m represents an integer of 0 to 3.
• h represents an integer of 1 to 3.
• j represents 0 or 1;
• k represents 0 or 1.
• the total of j and k (j+k) is 1 or 2.
• the compound represented by formula (2) is preferably a compound
• R 2 , Ac, m and n have the same meanings as those in formula (2), respectively.
• R 1 to R 3 each independently represent an alkyl group or an alkenyl group.
• Each of R 1 and R 3 is preferably an alkyl group having from 1 to 20 carbon atom(s), or an alkenyl group having from 2 to 22 carbon atoms.
• the carbon number is more preferably from 1 to 10 and particularly preferably from 1 to 6.
• Each R 2 is preferably an alkyl group having from 0 to 20 carbon atom(s), or an alkenyl group having from 0 to 22 carbon atom(s).
• the carbon number is more preferably from 0 to 10 and particularly preferably from 0 to 6. Note that the carbon number "0" described herein means that number of substituent for R is 0.
• the carbon number for each of R 1 to R 3 is preferably from 5 to 20 and more preferably from 8 to 20. Note that in the case where the foaming is emphasized (a second embodiment), a preferable range of a compounding amount with respect to each of the structure and the carbon number is described below.
• Each of R to R may have a substituent and examples of the substituent include an alkyl group having from 1 to 3 carbon atom(s), a halogen atom (fluorine atom, chlorine atom and the like), a cyano group, an amino group, and a hydroxyl group.
• substituents include an alkyl group having from 1 to 3 carbon atom(s), a halogen atom (fluorine atom, chlorine atom and the like), a cyano group, an amino group, and a hydroxyl group.
• Ar represents an aromatic ring. Especially, an aromatic ring having from 6 to 24 carbon atoms is preferred, and an aromatic ring having from 6 to 14 carbon atoms is more preferred. Examples thereof include a benzene ring, a naphthalene ring, an anthracene ring, and a phenanthrene ring. A benzene ring or a naphthalene ring is more preferred.
• the aromatic ring Ar may have a substituent. The substituent has the same definition as the substituent which the each of R 1 to R 3 may have.
• M represents a hydrogen atom or a cation.
• M include an alkali metal, ammonium, tetramethyl ammonium, and triethanolamine.
• M is preferably a cation other than the alkali metal, and more preferably ammonium.
• a cation it means that M provides a salt with a counter anion (SO “ , COO " ).
• the salt may dissociate in water to become a pair of ions.
• the content of the anionic compound is preferably 85% by mass or less, more preferably 75% by mass or less, and particularly preferably 65% by mass or less, with respect to the total amount of the etching liquid according to the present embodiment.
• the content of 5% by mass or less is preferred, the content of 1% by mass or less is more preferred, and the content of 0.6% by mass or less is still more preferred.
• the lower limit thereof is preferably 0.00001% by mass or greater, more preferably 0.001% by mass or greater, still more preferably 0.01 ) by mass or greater, and still more preferably 0.1% by mass or greater.
• the content of 1 % by mass or greater is particularly preferred.
• the content is set according to the structure and the carbon number of the anionic compound as described below. Note that each ppm is based on mass standard. ⁇ 0036 ⁇
• R 1 has 1 to 2 carbon atom(s) in formula (1)
• R 1 has 3 to 5 carbon atoms in formula (1)
• R 1 has 6 or more carbon atoms in formula (1)
• R 2 has 0 to 2 carbon atom(s) in total in formula (2-1),
• R 2 has 0 to 2 carbon atom(s) in total in formula (2-2),
• the content of 5% by mass or less is preferable, the content of
• 1% by mass or less is more preferable, and the content of 0.6% by mass or less is still more preferable.
• the lower limit thereof is preferably 0.00001% by mass or greater, more preferably 0.001% by mass or greater, still more preferably 0.01% by mass or greater, and particularly preferably 0.1% by mass or greater.
• the content is preferably set as described above from the viewpoints of solubility or removability of silicon oxide in addition to the foaming.
• the total carbon number of R (the total carbon number of R 1 , R 2 and R 3 which are contained in the molecule thereof) is, in formula (1), preferably from 1 to 6, more preferably from 1 to 4, and particularly preferably 1 or 2, in terms of the carbon number for R 1 , from the viewpoint that the anionic compound can be more highly concentrated.
• the total carbon number of R 2 is preferably from 0 to 5, more preferably from 0 to 4, and particularly preferably from 0 to 2.
• the total carbon number of R is preferably from 1 to 30, more preferably from 1 to 20, and particularly preferably from 5 to 20. Due to highly-concentrated components of the chemical liquid, preferably its activity is hard to be reduced even when it is continuously used.
• anionic compounds may be used singly as one compound, or by mixing compounds of two or more kinds.
• the reason why the anionic compound exhibits such effects is not clear.
• the anionic compound favorably adsorbs to the surface of the impurity-containing silicon layer, which results in prevention from contact with hydrofluoric acid, thereby enabling corrosion inhibition of the above- described silicon layer.
• a possibility of forming a favorable adsorption state with a layer surface of more "basic" compound is suggested, and it is presumed that an excellent effect is exhibited by suppression and prevention of bimetallic corrosion.
• the etching liquid of the present invention is preferably an aqueous solution in which water is used as a medium and each of components contained therein is uniformly dissolved.
• the content of water (aqueous medium) is preferably from 10 to 99.5% by mass and more preferably from 15 to 99% by mass, with respect to the total mass of the etching liquid.
• a composition is composed primarily of water (50% by mass or more)
• the composition is preferable in terms of more inexpensive and more adaptable to the environment, compared to a composition with a high ratio of an organic solvent.
• the water may be an aqueous medium containing components dissolved therein in an amount by which the effects of the present invention are not deteriorated, or may contain inevitable microscopic amount of mixed components.
• distilled water or an exchanged water, or water which has been subjected to a purifying process, such as ultrapure water is preferable and the ultrapure water which is used for production of the semiconductor is particularly preferable.
• a hydrofluoric acid compound is defined as a compound which means a compound generating a fluorine ion (F-) in a system, examples of which include fluoric acid (hydrofluoric acid) and salts thereof.
• fluoric acid compound include fluoric acid, alkali metal fluoride (NaF, KF, and the like), amine hydrofluoride (monoethylamine hydrofluoride, triethylamine trihydrofluoride, and the like), pyridine hydrofluoride, ammonium fluoride, quaternary alkyl ammonium fluoride (tetramethyl ammonium fluoride, tetra n-butyl ammonium fluoride, and the like), H 2 SiF 6 , HBF 4 and HPF 6 .
• H 2 SiF 6 , HBF 4 and HPF 6 are preferably, fluoric acid, ammonium fluoride, quaternary alkyl ammonium fluoride (tetramethyl ammonium fluoride), H 2 SiF 6 , HBF 4 and HPF 6 are more preferably, fluoric acid is particularly preferred.
• the hydrofluoric acid compound is preferably incorporated within the amount of at least 0.01% by mass, more preferably incorporated in an amount of at least 0.05% by mass, and particularly preferably incorporated in an amount of at least 0.1% by mass, with respect to the total mass of the etching liquid according to the present embodiment.
• the upper limit thereof is preferably 20% by mass or less, more preferably 10% by mass or less, and particularly preferably 3% by mass or less.
• etching of the silicon layer can be preferably suppressed.
• a silicon oxide layer can be preferably etched at a velocity sufficient to do it.
• a showing of the compound is used to mean 3 not only the compound itself, but also a salt or ion thereof and the like. Further, the showing of the compound is also used to mean incorporation of derivatives modified by a predefined configuration to an extent necessary to obtain a desired effect. Further, in the present specification, a substituent (including a linking group) in which substitution or non-substitution is not explicitly stated means that the substituent may have any substituent.
• water-soluble organic solvent means an organic solvent that can be mixed with water in an arbitrary proportion. This is effective at capability of improving in-plane uniform etching property of the wafer.
• water-soluble organic solvent examples include: alcohol compound solvents, such as methyl alcohol, ethyl alcohol, 1 -propyl alcohol, 2-propyl alcohol, 2- butanol, ethylene glycol, propylene glycol, glycerol, 1,6-hexanediol, cyclohexanediol, sorbitol, xylitol, 2-methyl-2,4-pentanediol, 1 ,3-butanediol, and 1,4-butanediol; ether compound solvents, such as an alkylene glycol alkyl ether including ethylene glycol monomethyl ether, ethylene glycol monobuthyl ether, diethylene glycol, dipropylene glycol, propylene glycol monomethyl ether, diethylene glycol monomethyl ether, triethylene glycol, poly(ethylene glycol), dipropylene glycol monomethyl ether, tripropylene glycol monomethyl ether, and diethylene glycol monobutyl
• alcohol compound solvents having 2 to 15 carbon atoms and ether compound solvents having 2 to 15 carbon atoms preferably ether compound solvents containing a hydroxyl group. More preferred are alcohol compound solvents having 2 to 10 carbon atoms and at least 2 hydroxyl groups and ether compound solvents having 2 to 10 carbon atoms and at least 2 hydroxyl groups (preferably ether compound solvents containing a hydroxyl group).
• alcohol compound solvents having 2 to 10 carbon atoms and at least 2 hydroxyl groups and ether compound solvents having 2 to 10 carbon atoms and at least 2 hydroxyl groups preferably ether compound solvents containing a hydroxyl group.
• alkyleneglycol alkylethers having 3 to 8 carbon atoms may be used singly or appropriately in combination of two or more kinds.
• a compound having a hydroxyl group (-OH) and an ether group (-0-) in the molecule thereof shall be included in the category of the ether compound in principle (not called as the alcohol compound).
• the compound may be preferably called as "hydroxyl group-containing ether compound”.
• the water-soluble organic solvent can preferably be the compounds represented in following formula (O- 1 ).
• R and R" are, respectively and dependently, a hydrogen atom or an alkyl group having carbon number of 1 to 5.
• R is liner or branched alkyl ene group having
• n is integer of 1 to 6.
• propyleneglycol and dipropyleneglycol are preferable, more preferably dipropyleneglycol.
• the addition amount thereof is preferably from 0.1 to 70% by mass and more preferably from 10 to 50% by mass, with respect to the total mass of the etching liquid.
• the antifoamer (antifoaming agent) which is applicable to the etching liquid
• examples of the antifoamer which is applicable to the etching liquid include the above-described water-soluble organic solvent and a silicone compound.
• the content of the antifoamer when the antifoamer is a water-soluble organic solvent (for example, alkyleneglycol ether) or a silicone compound, it is preferably incorporated in a range of from 0.00001 to 3% by mass, more preferably from 0.0001 to 1% by mass, and still more preferably from 0.001 to 0.1% by mass, with respect to the total mass of the etching liquid of the present embodiment.
• the antifoamer is a water-soluble organic solvent
• the antifoamer is preferably incorporated in a range of from 10 to 90% by mass, more preferably from 20 to 85% by mass, and still more preferably from 30 to 80% by mass, with respect to the total mass of the etching liquid of the present embodiment.
• incorporation of the antifoamer in this amount inhibition of etching due to bubbles which generate at the time of etching is prevented and, as a result, etching resistance properties of the conductivity type impurity-containing silicon layer are preferably enhanced.
• the pH of the etching liquid according to the present invention is preferably 5 or less, more preferably 4.5 or less, and particularly preferably 4 or less.
• the lower limit thereof is not particularly limited, but the pH of 1 or greater is practical.
• the concentration of each component in the above-described etching liquid is suitable for use at the time of etching processing, but in preservation, distribution and the like, the etching liquid may be kept as a stock solution which is a concentrate of the etching liquid.
• the concentration rate although it may be determined as appropriate, is preferably from 2 to 20 times.
• a hydrofluoric acid compound is preferably from 0.1 to 50% by mass, and more preferably from 1 to 30% by mass.
• the anionic compound is preferably from 0.001 to 95% by mass, and more preferably of from 0.01 to 85% by mass.
• the etching liquid of the present invention may be constituted as a kit in which the raw materials thereof are divided into multiple parts.
• the kit include an embodiment in which, as a first liquid, a liquid composition in which the above- described anionic compound is contained in a water medium is prepared, and, as a second liquid, a liquid composition in which the above-described hydrofluoric acid compound is contained in a water medium is prepared.
• a first liquid a liquid composition in which the above- described anionic compound is contained in a water medium
• a second liquid a liquid composition in which the above-described hydrofluoric acid compound is contained in a water medium is prepared.
• both liquids are mixed to prepare an etching liquid, and after that, the etching liquid is applied to the above-described etching process on a timely basis. This avoids it from raising deterioration of the liquid properties due to decomposition of each components whereby a desired etching function can be effectively exhibited.
• the etching liquid of the present invention (whether it is a kit or not) can be stored, transported and used by filling it into an arbitrary container, as far as corrosion resistance properties and the like are not concerned. Further, it is preferred for semiconductor application that the container has high cleanness and less elution properties of impurities from the container.
• usable containers include "Clean Bottle” series, manufactured by AICELLO CHEMICAL CO., LTD., and "Pure Bottle", manufactured by KODAMA PLASTICS Co., Ltd. The present invention is not limited to these.
• any of a structure, a shape, a size and the like of a semiconductor substrate product to be processed is not particularly limited. However, in the production process of insulated gate field effect transistor which forms an extension layer and source/drain using a dummy gate, a dummy film and a sidewall, as described above, it is preferable to determine the structure, the shape, the size and the like so that high effect is obtained in etching of the dummy film after removal of the dummy gate in particular.
• the production method and the etching liquid of the present invention is not only applied to the above-described production process, but also can be used for various kinds of etching without any particular limitation.
• the etching equipment used in the present invention is not particularly limited, but single wafer type etching equipment or batch type etching equipment can be used.
• Single wafer type etching is a method of etching the wafers one by one.
• One embodiment of the single wafer etching is a method of causing the etching liquid spread to the whole surface of the wafer by a spin coater.
• Liquid temperature of the etching liquid, discharge rate of the etching liquid and rotation speed of the wafer of the spin coater are used to select the appropriate value by the choice of substrate to be etched.
• the etching condition is not particularly limited, the single wafer type etching is preferred.
• semiconductor substrates are transported or rotated in the predetermined direction, and an etching liquid is discharged (spray, falling, drop) in a space among them to put the etching liquid on the semiconductor substrate.
• etching liquid may be sprayed while rotating the semiconductor substrate using a spin coater.
• a semiconductor substrate is immersed in a liquid bath composed of an etching liquid, thereby bringing the semiconductor substrate into contact with the etching liquid in the liquid bath. It is preferred that these etching types be appropriately used depending on structures, materials and the like of the element.
• the temperature of the spraying interspace for etching is set to a range of preferably from 15 to 40°C, and more preferably from 20 to 30°C.
• the temperature of the etching liquid is preferably set from 15 to 40°C, and more preferably from 20 to 30°C. It is preferable to set the temperature to the above- described lower limit or more because an adequate etching rate with respect to a silicon oxide layer can be ensured by the temperature. It is preferable to set the temperature to the above-described upper limit or less because selectivity of etching can be ensured by the temperature.
• the supply rate of the etching liquid is not particularly limited, but is set to a range of preferably from 0.3 to 3 L/min, and more preferably from 0.5 to 2 L/min. It is preferable to set the supply rate to the above-described lower limit or more because uniformity of etching in a plane can be ensured by the supply rate. It is preferable to set the supply rate to the above-described upper limit or less because stable selectivity at the time of continuous processing can be ensured by the supply rate.
• temperature regulation refers to maintaining the chemical liquid at a predetermined temperature. Ordinarily, the chemical liquid is maintained by heating at a predetermined temperature.
• the chemical liquid already used in the method of the present invention can be re-used by circulation.
• Preferable method is not "free-flowing" (without re-use), but reuse by circulation. It is possible to continue circulation for 1 hour or longer after heating, which makes it possible to perform a repetitive etching.
• time limit of the circulating-reheating exchange within a week is preferable because etching rate deteriorates with age.
• the exchange within 3 days is more preferable.
• An exchange to a flesh liquid once a day is particularly preferable.
• the measurement position of the temperature-regulated temperature may be determined appropriately by the relation to a line configuration or a wafer. Typically, the measurement position is regulated by adjusting the tank temperature. In the case where relatively more strict conditions in terms of performance are required, wherever the measurement and the regulation are feasible, the temperature-regulated temperature may be defined by a wafer surface temperature. In this case, temperature measurement is conducted using a radiation thermometer.
• the underlayer in the preferable embodiment of the present invention is a silicon layer having a p-type impurity layer and an n-type impurity layer, or a silicon layer having a p-type impurity layer and an n-type impurity layer and further incorporating therein germanium or carbon.
• the silicon layer herein used typically refers to one single crystal grain of a single crystal silicon layer or a polycrystal silicon layer.
• the single crystal silicon layer refers to a silicon crystal in which orientation of the atomic arrangement is aligned throughout the crystal. In fact, however, when observed at the atomic level, the presence of various defects is found.
• the p- type impurity layer refers to a layer in which p-type impurities (for example, B + , BF 2+ and the like) are doped in the above-described silicon layer.
• the n- type impurity layer refers to a layer in which n-type impurities (for example, P + , As + , Sb + and the like) are doped in the above-described silicon layer.
• a layer to be etched in the present embodiment refers to a layer containing silicon and oxygen as constituent elements.
• the layer to be etched is composed of silicon dioxide (Si0 2 ), a silicon dioxide derivative of which Si has a dangling bond, a silicon dioxide derivative in which a dangling bond of Si combines with hydrogen, or the like.
• the other elements may be incorporated therein, for example, germanium or carbon may be incorporated therein.
• the etching liquid for silicon oxide makes it possible to remove a layer to be etched of a silicon oxide or a germanium or carbon-containing silicon oxide, by etching it without causing galvanic corrosion, even in the case where a silicon layer having different conductive type impurity layers is disposed as a ground.
• semiconductor substrate is not only used to mean a silicon substrate (wafer), but also used in a broader meaning that includes a whole substrate structure on which a circuit structure is provided.
• the semiconductor substrate member refers to a member that constitutes the above-defined semiconductor substrate, and may be composed of a single material or a plurality of materials.
• the processed semiconductor substrate may be called a semiconductor substrate product in order to distinguish it from a pre-processed semiconductor substrate.
• a chip picked up by singulation after a processing of the semiconductor substrate product, and a chip processed product are called a semiconductor element or semiconductor device. That is, in a broad sense, the semiconductor element (semiconductor device) belongs to the semiconductor substrate product.
• the direction of the semiconductor substrate is not particularly limited.
• First substrate Boron doping was conducted to a bare wafer composed of a single crystal ⁇ 100> silicon substrate by ion implantation under the conditions of the dose amount of 3> ⁇ 10 14 atom/cm 2 and the implantation energy of 210 keV. 1
• Second substrate Boron doping was conducted to a bare wafer composed of a single crystal ⁇ 100> silicon substrate by ion implantation under the conditions of the dose amount of 3 ⁇ 10 14 atom/cm 2 and the implantation energy of 210 keV. Then, arsenic doping was also conducted thereto by ion implantation under the conditions of the dose amount of 5 ⁇ 10 15 atom/cm 2 and the implantation energy of 210 keV.
• ion implantation of boron into the substrate under the conditions of dose amount of 3* 10 14 atom/cm 2 and implant energy of 210KeV was conducted to form a channel dope layer. Further, in order to form extension layers, ion implantation of arsenic was conducted under the conditions of dose amount of 1.0x 10 15 atom/cm 2 and implant energy of 3KeV.
• a silicon nitride film was used for a sidewall, and a Si0 2 film was used for a dummy film.
• the substrate having the above-described dummy film and sidewall formed thereon was etched under the following conditions using single wafer equipment (POLOS (trade name), manufactured by SPS-Europe B.V.).
• POLOS single wafer equipment
• the above-described chemical liquid temperature was measured as follows.
• a radiation thermometer IT-550F manufactured by HORIBA Ltd. was fixed at the height of 30cm from a wafer in the single wafer equipment. Temperature was measured while flowing the chemical liquid in a manner such that the thermometer was pointed to a wafer surface at the distance of 2cm outside from the center of the wafer. The temperature was output digitally from the radiation thermometer and recorded using a personal computer. With respect to the timing of measurement, because an initial temperature of the etching treatment is heading for an upturn, and thereafter the temperature becomes lower, an average value of the temperature for the last- 10 seconds of the treatment time as a sufficiently stable timing was defined as a temperature on the wafer.
• Evaluation was conducted in terms of removal property of a Si0 2 film on the channel dope layer and existence or non-existence of the void of the extension layer. In either evaluation, cross-section observation of the extension layer was visually performed using TEM. The removal rate was evaluated using a ratio of areas of the extension layer before and after the treatment.
• Removal rate was from 50% to less than 80%
• Evaluation of void was performed by determining if a void generated in the extension layer, and the case where the void generated was expressed by "existence", while the case where no void generated was expressed by "None-existence”. ⁇ 0062 ⁇
• the pH shown in the table is a value that was obtained by measuring the etching liquid at room temperature (25°C) using F-51 (trade name), manufactured by HORIBA, Ltd.
• the present invention enables efficient and generic process with a less dependency on substrates.
• Example 1 Evaluation of each item was conducted in the same manner as Example 1, except that a semiconductor substrate incorporating carbon or germanium in a silicon layer as an underlayer thereof was prepared. As a result, it was confirmed that the production method and the etching liquid each of which is the present invention exhibit equally excellent effects as Example 1.
• Antifoamers having components and compositions (mass%) described below were added to the above-described etching liquids containing water, the hydrofluoric acid compound and the anionic compound to prepare etching liquids (test liquids). As for the following addition amounts, concentrations of the components incorporated in final chemical liquids were indicated.
• the test of antifoaming property was conducted by placing 5 mL of a test liquid in a stoppered test tube having approximately 15 mm of inner diameter and approximately 200mm of length, and then mixing it by shaking vigorously for 3 minutes, and then an elapsed time until the generated bubbles almost had disappeared was measured. A stopwatch was used for time measurement.
• Example 4 To the present Example 4, the following test of antifoaming property was added. The other tests are the same as Example 1.
• the test of antifoaming property was conducted by placing 5 mL of a test liquid in a stoppered test tube having approximately 15 mm of inner diameter and approximately 200mm of length, and then mixing it by shaking vigorously for 3 minutes, and then an elapsed time until the generated bubbles almost had disappeared was measured. A stopwatch was used for time measurement.

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• Weting (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)
• Thin Film Transistor (AREA)

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• 2012
  • 2012-12-26 JP JP2012283429A patent/JP2014057039A/ja active Pending
• 2013
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