[go: up one dir, main page]

WO2014095353A1 - Procédé de fabrication d'une puce de semi-conducteur optoélectronique et puce de semi-conducteur optoélectronique - Google Patents

Procédé de fabrication d'une puce de semi-conducteur optoélectronique et puce de semi-conducteur optoélectronique Download PDF

Info

Publication number
WO2014095353A1
WO2014095353A1 PCT/EP2013/075399 EP2013075399W WO2014095353A1 WO 2014095353 A1 WO2014095353 A1 WO 2014095353A1 EP 2013075399 W EP2013075399 W EP 2013075399W WO 2014095353 A1 WO2014095353 A1 WO 2014095353A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor layer
current spreading
layer sequence
spreading layer
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2013/075399
Other languages
German (de)
English (en)
Inventor
Korbinian Perzlmaier
Sebastian Taeger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of WO2014095353A1 publication Critical patent/WO2014095353A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/832—Electrodes characterised by their material
    • H10H20/833—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/032—Manufacture or treatment of electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates

Definitions

  • Semiconductor chips can be produced.
  • the method comprises the step of epitaxially growing a
  • the semiconductor layer sequence is grown on a growth substrate.
  • Growth substrate is, for example, a
  • Semiconductor layer sequence one or more active zones for generating radiation.
  • the at least one active zone extends in a plane perpendicular to one
  • the semiconductor layer sequence is preferably based on a III-V compound semiconductor material.
  • the semiconductor material is, for example, a nitride compound semiconductor material such as Al n In] __ n _ m Ga m N or a phosphide compound semiconductor material such as Al n In] __ n _ m Ga m P or an arsenide compound semiconductor material such as Al n In ] __ n _ m Ga m As, where each 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and n + m -S 1.
  • the semiconductor layer sequence may have dopants and additional constituents.
  • an ultraviolet radiation, visible light and / or near-infrared radiation is emitted.
  • the active zone is designed to produce blue light, for example in the spectral range between 430 nm and 485 nm inclusive.
  • the method comprises the step of applying a current spreading layer to the semiconductor layer sequence.
  • the current spreading layer is preferably applied to a side of the semiconductor layer sequence facing away from the growth substrate. It comprises the current spreading layer of one or more transparent, conductive oxides or the current spreading layer consists of one or more such oxides. In this case, the current spreading layer may additionally have a doping.
  • Semiconductor layer sequence directly on the growth substrate applied.
  • the semiconductor layer sequence and the growth substrate then preferably touch over the whole area. It is possible that the growth substrate is attached to one of the
  • the growth substrate may be a so-called structured sapphire substrate, English patterned sapphire substrate or PSS for short.
  • Semiconductor layer sequence is one
  • the semiconductor layer sequence touches, seen in plan view, at least 70% or 80% or 90% of an area of the semiconductor layer sequence.
  • the method comprises the step of applying an etching mask to the
  • the etch mask is configured to provide the current spreading layer and the
  • the etching mask is formed by a photoresist.
  • the method comprises the step of structuring the current spreading layer.
  • the structuring is preferably carried out by etching, the structuring being predetermined by the etching mask.
  • the etching mask is preferably removed, in particular removed completely and without residue.
  • the current spreading layer and the semiconductor layer sequence are patterned using the same etching mask. By exactly one etching mask, the structure of the current spreading layer and the semiconductor layer sequence are predetermined.
  • a distance or a mean distance of an edge is
  • the distance or the mean distance is at most a twenty-fold, a tenfold, a fivefold or twice a mean layer thickness of
  • the edge of the current spreading layer is approximately
  • the method is for producing an optoelectronic semiconductor chip
  • the method comprises at least the following steps: A) Epitaxial growth of a semiconductor layer sequence on a growth substrate, wherein the semiconductor layer sequence has at least one active zone for generating radiation,
  • An etching mask wherein a distance or an average distance of an edge of the semiconductor layer sequence to an edge of
  • the structuring of the current spreading layer and the semiconductor layer sequence takes place with the same etching mask. It's about structuring the
  • a semiconductor layer sequence and the current spreading layer thus only a single photo level required. This is accompanied by a cost reduction and an increase in efficiency, by maximizing a radiation-active surface.
  • a semiconductor layer sequence is often in a first
  • Textured layer and a current spreading layer of a transparent conductive oxide, short TCO, is structured in a later photo level. Such a separation in photo planes is particularly necessary if the
  • a Sacrificial layer such as silicon dioxide
  • laser scribing is usually to be performed prior to applying the current spreading layer.
  • the step of structuring the current spreading layer comprises the sub-step of wet-chemical etching of the current spreading layer.
  • wet-chemical etching preferably no material of the semiconductor layer sequence is removed or it becomes the
  • the step of structuring comprises the substep of the dry chemical etching of the semiconductor layer sequence. This substep is performed after the current spreading layer for
  • Example wet-chemically removed in places preferably only one material of the semiconductor layer sequence is removed and not or not significantly a material of the
  • the active zone is at edges of the semiconductor layer sequence of a contamination with electrically conductive material from the
  • the current spreading layer tin and / or zinc.
  • the current spreading layer is a layer of indium tin oxide or zinc oxide. Also a
  • Multilayer structure of the current spreading layer of layers of different TCOs is possible. According to at least one embodiment, this remains.
  • the growth substrate is finished in the finished
  • Semiconductor layer sequence and the current spreading layer at least 100 nm or 200 nm or 300 nm or 500 nm
  • Layer thickness of the current spreading layer seen in plan view. By such a distance, the edges of the semiconductor layer sequence and the current spreading layer, for example by light microscopy or
  • Electron microscopy distinguishable from each other.
  • the step of wet-chemical etching of the current spreading layer the
  • Etched mask undercut This means that the etching mask projects beyond the current spreading layer.
  • the current spreading layer is then completely covered by the etching mask and the
  • Etch mask has a larger area than the
  • dry chemical etching can be Chemical Dry Etching, or CDE for short, or Reactive Ion Etching, or RIE for short. It can several dry etching steps are combined or only a single dry etching step can be used.
  • Current spreading layer and the semiconductor layer sequence preferably at most 200 nm or 100 nm or 50 nm. It can also overlap the edges congruent.
  • the method comprises a step E) which follows step D).
  • step E a distance of the edges of the current spreading layer and the semiconductor layer sequence from each other is changed. This alteration is preferably carried out by etching, in particular by wet-chemical etching, of the current spreading layer.
  • the method comprises a step F).
  • Step F) follows step D).
  • the growth substrate and the growth substrate are formed from the step F.
  • the separation is preferably done partially or completely by laser radiation.
  • the singulation can be a so-called stealth dicing. This is by
  • Growth substrate is transparent at moderate intensities, generated within the carrier composite a damaged area in the material.
  • the singulation takes place by means of laser radiation, the laser radiation being directed into the rear side facing away from the semiconductor layer sequence by a laser radiation Wax substrate is irradiated.
  • Semiconductor layer sequence can be generated. After generating the predetermined breaking points, for example, a break occurs to the individual semiconductor chips.
  • Semiconductor layer sequence has a thickness of at least 2.5 ⁇ or 3 ⁇ . Alternatively or additionally, the thickness of the semiconductor layer sequence is at most 15 ⁇ or 12 ⁇ or 9 ⁇ . According to at least one embodiment, a thickness of the growth substrate is at least 50 ⁇ or 75 ⁇ or 100 ⁇ . The thickness of the growth substrate may be alternatively or additionally at most 3 mm or 1.5 mm or 500 ⁇ or 400 ⁇ or 300 ⁇ . After a growth of
  • the growth substrate can be thinned.
  • the current spreading layer extends continuously across the current spreading layer
  • Constant thickness can be
  • Growth direction of the semiconductor layer sequence is, for example, at least 15 ° or 30 ° and / or at most 60 ° or 75 °.
  • a width of the flanks, in plan view is at most 1.0 ym or 0.5 ym. This is the case in particular when the current spreading layer is structured dry chemically.
  • the flanks seen in plan view of the Stromillerweitungs slaughter at least in places sawtooth or frayed limit the Stromaufweitungstik, so that an edge of the
  • the current spreading layer for example, at least 100 nm or 250 nm or the average thickness of the current spreading layer and / or at most 600 nm or 400 nm. The latter is especially the case when the current spreading layer is structured wet-chemically.
  • the metal contact is formed from one or more metals or metal alloys.
  • the metal contact is a bonding pad.
  • Current spreading layer can be continuous and
  • an electrically insulating insulating layer is located between the semiconductor layer sequence and the current spreading layer in a region covered by the metal contact.
  • Insulation layer may have the same basic shape and surface area as the metal contact, in particular with a
  • the insulating layer is larger than that
  • Insulation layer in particular no direct current path from the metal contact to the semiconductor layer sequence.
  • the metal contact in a region in which a bonding wire is applied to the metal contact, the metal contact
  • the semiconductor layer sequence can be electrically non-conductive.
  • the insulation layer can be transparent to radiation
  • Isolation layer structured and thus only locally
  • the invention is based on a
  • Applied passivation layer Preferably, the
  • Passivation layer a closed layer that the Semiconductor layer sequence continuously covered, wherein areas in which the at least one metal contact is applied, are preferably free of the passivation layer.
  • Metal contact partly between the passivation layer and the current spreading layer is covered to at most 10% or 20% of the passivation layer, seen in plan view.
  • Current spreading layer has a thickness of at least 30 nm or 50 nm or 70 nm or 100 nm. Alternatively or additionally, the current spreading layer has a thickness of at most 500 nm or 300 nm or 220 nm. According to at least one embodiment, the
  • the mean lateral dimension may be a mean edge length of the semiconductor chip and / or the
  • the average lateral dimension is at most 2 mm or 1, 5 mm or 1 mm. According to at least one embodiment, the distance
  • Consistent may mean that the respective local distance from an average distance of at most 50% or 30% or 15% or twice the mean thickness of
  • Current spreading layer has an average roughness of at most 10 nm or 5 nm.
  • a corresponding roughness may alternatively or additionally apply to a side of the semiconductor layer sequence facing away from the growth substrate and / or the passivation layer and / or the insulation layer.
  • An average particle size here is, for example, at least 10 nm or 30 nm or 50 nm and / or at most 300 nm or 200 nm or 150 nm.
  • a side facing away from the semiconductor layer sequence of the current spreading layer has an average roughness of at least 10 nm or 30 nm or 50 nm and / or of at most 200 nm or 100 nm or 50 nm.
  • a current widening is given exclusively by the current spreading layer.
  • a current spreading in the lateral direction, in the direction away from the metal contact, can thus take place exclusively through the current spreading layer. It is thus possible that none on a metal based, especially translucent and thin
  • Metal layer is used for current expansion. Specifically, then the semiconductor chip does not comprise a continuous or lattice-shaped metal electrode having a thickness of at most 15 nm or 20 nm, and the
  • Semiconductor layer sequence which are oriented transversely to a substrate top of the growth substrate. According to at least one embodiment, an angle of the flanks of the semiconductor layer sequence, relative to the
  • an optoelectronic semiconductor chip is specified.
  • the semiconductor chip is made as in
  • Semiconductor chip a growth substrate, on the directly one Semiconductor layer sequence is deposited epitaxially.
  • the semiconductor layer sequence comprises at least one active zone for generating a radiation.
  • At a side facing away from the growth substrate is at least in places on the
  • Current spreading layer is made of a transparent
  • a distance of an edge of the semiconductor layer sequence to an edge of the current spreading layer, in the direction perpendicular to a growth direction of the semiconductor layer sequence, is at most 1.0 ⁇ .
  • FIGS. 1 to 3 are schematic sectional views of FIG.
  • FIG. 1 schematically illustrates a production method for an optoelectronic semiconductor chip 1.
  • a semiconductor layer sequence 3 is formed on a growth substrate 2, preferably a sapphire substrate
  • the semiconductor layer sequence 3 is preferably based on InAlGaN.
  • the semiconductor layer sequence 3 is deposited directly on a substrate top side 20 of the growth substrate 2.
  • the substrate top 20 may
  • Substrate top 20 is an n-side 31 of
  • Semiconductor layer sequence 3 grown from an n-type material. Deviating from the illustration according to FIG. 1A, further layers of the semiconductor layer sequence 3 may be located between the substrate top side 20 and the n side 31, for example buffer layers, masking layers and / or growth layers. In the direction away from the growth substrate 2, the n-side follows at least one active zone 32.
  • the active zone 32 comprises at least one pn junction and / or at least one quantum well structure.
  • the active region 32 is formed from a p-side 33 of a p-type material, for example, GaN-doped GaN.
  • the p-side is closer to the growth substrate 2.
  • the growth substrate 2 is deposited on the growth substrate 2
  • the insulation layer 5 is for example off Made of silicon oxide, silicon nitride or a silicon oxynitride. A thickness of the insulating layer 5 is located
  • the insulating layer 5 preferably at most 20% or 10%.
  • a small step in the p-side at an edge of the insulating layer 5 is avoidable. Such a step may result from a subsequent etching of the insulating layer 5. As a result of such subsequent etching, a greater roughness can alternatively or additionally arise in regions of the p-side which are not covered by the insulation layer 5.
  • the entire surface of the semiconductor layer sequence 3 becomes a
  • Current spreading layer 4 is formed, for example, indium tin oxide, ITO short. It overmoulds and covers the
  • an etching mask 6 is applied to the current spreading layer 4.
  • the etching mask 6 is preferably formed from a photoresist and is patterned in particular by means of a photographic technique. In the etching mask 6 a plurality of recesses are formed, in which the
  • the current spreading layer 4 is removed wet-chemically in the recesses of the etching mask 6. Unlike shown, it is possible that the etching mask 6 is not undercut, but instead the current spreading layer 4 is flush with the etching mask 6, in a direction perpendicular to one
  • Growth direction G of the semiconductor layer sequence 3. is a supernatant of the etching mask 6 over the
  • Current spreading layer 4 at least 50 nm or 200 nm.
  • the current spreading layer 4 and the semiconductor layer sequence 3 are structured.
  • the structuring of the semiconductor layer sequence 3 is preferably carried out by dry chemical etching. After the dry-chemical etching of the semiconductor layer sequence 3, the etching mask 6 is removed.
  • Semiconductor layer sequence 3 are separated from one another by constrictions of the semiconductor layer sequence 3. It is possible that the subregions located next to the central subregion with the insulation layer 5 are each free of the insulation layer 5.
  • Subareas can also be omitted.
  • FIG. 1G an edge of the semiconductor layer sequence 3, which is formed by the etching, is shown in more detail.
  • the flank 35 has, for example, an angle to the growth direction G of about 45 °.
  • a distance D between an edge of the semiconductor layer sequence 3 and the current spreading layer 4 is about 1 ⁇ .
  • Such a small distance D can be realized by patterning the current spreading layer 4 and the semiconductor layer sequence 3 with the same etching mask 6.
  • metal contacts 7 are applied to the current spreading layer 4, in particular applied in a structured manner.
  • the insulating layer 5 is located between the metal contact 7 of the central portion and the semiconductor layer sequence 3. The insulating layer 5 is only partially covered by the central metal contact 7 and has a larger footprint than the metal contact 7. In the marginal
  • Metal contact 7 only the current spreading layer 4 is located. Unlike illustrated, the metal contacts 7 may comprise a plurality of different metal layers.
  • FIG. 2 shows that a passivation layer 8 is applied to the sides of the semiconductor layer sequence 3 and to the current spreading layer 4 which are opposite to the growth substrate 2.
  • the passivation layer 8 is formed of an electrically insulating oxide or nitride.
  • the passivation layer 8 the metal contacts 7 partially covered, seen in plan view.
  • the passivation layer 8 also in the direction transverse to the direction of growth G of the
  • FIG. 1J shows the step of uniting with the individual semiconductor chips 1.
  • the insulation layer, the passivation layer and the metal contacts are not drawn.
  • a side of the growth substrate 2 facing away from the semiconductor layer sequence 3 becomes one
  • predetermined breaking points 25 are created in the growth substrate. At these predetermined breaking points 25, a complete separation can then take place, for example, by breaking.
  • the laser radiation R is irradiated from the side on which the semiconductor layer sequence 2 is applied.
  • the semiconductor layer sequence 2 is preferably completely removed from the growth substrate 2 at those points at which the laser radiation R is irradiated. This allows a slag formation
  • FIGS. 2A and 2B correspond to FIGS. 1D to 1F.
  • the further method steps are not shown in FIG. 2 and can be carried out analogously to FIG.
  • the current spreading layer 4 and the semiconductor layer sequence 3 are etched dry chemically using the common etching mask 6 previously produced in FIG. 2A.
  • the semiconductor layer sequence 3 and the current spreading layer 4 can therefore be patterned in the same etching step. This makes it possible that a projection between the edges of the semiconductor layer sequence 3 and the Stromaufweitungs Mrs 4 disappears and is almost zero or zero.
  • Current spreading layer 4 can be flush. Another variant of the manufacturing process is shown in FIG. According to FIG. 3A, both the semiconductor layer sequence 3 and the current spreading layer 4 are etched through the recesses in the etching mask 6.
  • the etching is preferably dry chemical. In this case, it is possible for a projection of the current spreading layer 4 to result over the semiconductor layer sequence 3.
  • this projection of the current spreading layer 4 is removed via the semiconductor layer sequence 3, for example by means of a further wet chemical etching step.
  • This subsequent etching is preferably carried out as long as the etching mask 6 is not yet removed.
  • Insulation layer 5 applied to the semiconductor layer sequence 3 over the entire surface and subsequently structured to form a first etching mask 6a formed from S1O2. Subsequently, see FIG. 4B, the semiconductor layer sequence 3 is patterned on the basis of the first etching mask 6a.
  • the current spreading layer 4 is applied. Based on a formed from a photoresist second, not shown, the etching mask, the

Landscapes

  • Led Devices (AREA)

Abstract

Dans au moins un mode de réalisation, le procédé est adapté pour fabriquer une puce de semi-conducteur optoélectronique (1) et il comprend les étapes suivantes : A) croissance épitaxiale d'une succession de couches semi-conductrices (3) sur un substrat de croissance (2), B) dépôt d'une couche d'étalement du courant (4) en oxyde conducteur transparent sur la succession de couches semi-conductrices (3), C) dépôt d'un masque de gravure (6) sur la couche d'étalement du courant (4), D) structuration de la couche d'étalement du courant (4) ainsi que de la succession de couches semi-conductrices (3) par gravure au moyen du même masque de gravure (6), la distance entre un bord de la succession de couches semi-conductrices (3) et un bord de la couche d'étalement du courant (4) étant au maximum égale à 3 μm.
PCT/EP2013/075399 2012-12-20 2013-12-03 Procédé de fabrication d'une puce de semi-conducteur optoélectronique et puce de semi-conducteur optoélectronique Ceased WO2014095353A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102012112771.9A DE102012112771A1 (de) 2012-12-20 2012-12-20 Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
DE102012112771.9 2012-12-20

Publications (1)

Publication Number Publication Date
WO2014095353A1 true WO2014095353A1 (fr) 2014-06-26

Family

ID=49713080

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2013/075399 Ceased WO2014095353A1 (fr) 2012-12-20 2013-12-03 Procédé de fabrication d'une puce de semi-conducteur optoélectronique et puce de semi-conducteur optoélectronique

Country Status (3)

Country Link
DE (1) DE102012112771A1 (fr)
TW (1) TW201431118A (fr)
WO (1) WO2014095353A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111819702A (zh) * 2019-11-26 2020-10-23 天津三安光电有限公司 一种红外发光二极管

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014107306A1 (de) 2014-05-23 2015-11-26 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
DE102015111301B4 (de) 2015-07-13 2022-11-03 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronischer Halbleiterchip

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184456B1 (en) * 1996-12-06 2001-02-06 Canon Kabushiki Kaisha Photovoltaic device
US20040266044A1 (en) * 2003-06-24 2004-12-30 Park Young Ho Method for manufacturing gallium nitride-based semiconductor light emitting device
DE102004025610A1 (de) * 2004-04-30 2005-11-17 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement mit mehreren Stromaufweitungsschichten und Verfahren zu dessen Herstellung
US20110062479A1 (en) * 2008-05-14 2011-03-17 Showa Denko K.K. Method of manufacturing group-iii nitride semiconductor light-emitting device, and group-iii nitride semiconductor light-emitting device, and lamp
EP2325900A1 (fr) * 2008-08-29 2011-05-25 Nichia Corporation Élément semi-conducteur émetteur de lumière et dispositif semi-conducteur émetteur de lumière
JP2011211074A (ja) * 2010-03-30 2011-10-20 Toyoda Gosei Co Ltd 半導体発光素子
US20120241803A1 (en) * 2011-03-23 2012-09-27 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777257B2 (en) * 2002-05-17 2004-08-17 Shin-Etsu Handotai Co., Ltd. Method of fabricating a light emitting device and light emitting device
US7683380B2 (en) * 2007-06-25 2010-03-23 Dicon Fiberoptics, Inc. High light efficiency solid-state light emitting structure and methods to manufacturing the same
DE102008038852B4 (de) * 2008-06-03 2024-02-01 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines optoelektronischen Bauelementes und optoelektronisches Bauelement

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184456B1 (en) * 1996-12-06 2001-02-06 Canon Kabushiki Kaisha Photovoltaic device
US20040266044A1 (en) * 2003-06-24 2004-12-30 Park Young Ho Method for manufacturing gallium nitride-based semiconductor light emitting device
DE102004025610A1 (de) * 2004-04-30 2005-11-17 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement mit mehreren Stromaufweitungsschichten und Verfahren zu dessen Herstellung
US20110062479A1 (en) * 2008-05-14 2011-03-17 Showa Denko K.K. Method of manufacturing group-iii nitride semiconductor light-emitting device, and group-iii nitride semiconductor light-emitting device, and lamp
EP2325900A1 (fr) * 2008-08-29 2011-05-25 Nichia Corporation Élément semi-conducteur émetteur de lumière et dispositif semi-conducteur émetteur de lumière
JP2011211074A (ja) * 2010-03-30 2011-10-20 Toyoda Gosei Co Ltd 半導体発光素子
US20120241803A1 (en) * 2011-03-23 2012-09-27 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method for manufacturing same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
E.F. SCHUBERT: "Light-Emitting Diodes", 31 January 2007, CAMBRIDGE UNIVERSITY PRESS, Cambridge, UK, ISBN: 978-0-521-86538-8, XP002720310 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111819702A (zh) * 2019-11-26 2020-10-23 天津三安光电有限公司 一种红外发光二极管
US20210313486A1 (en) * 2019-11-26 2021-10-07 Tianjin Sanan Optoelectronics Co., Ltd. Infrared light-emitting diode
CN111819702B (zh) * 2019-11-26 2024-04-09 天津三安光电有限公司 一种红外发光二极管
US12009453B2 (en) * 2019-11-26 2024-06-11 Tianjin Sanan Optoelectronics Co., LTD Infrared light-emitting diode
US12336329B2 (en) 2019-11-26 2025-06-17 Tianjin Sanan Optoelectronics Co., Ltd. Infrared light-emitting diode

Also Published As

Publication number Publication date
TW201431118A (zh) 2014-08-01
DE102012112771A1 (de) 2014-06-26

Similar Documents

Publication Publication Date Title
DE102007019775B4 (de) Optoelektronisches Bauelement
DE102010024079B4 (de) Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip
DE112013004276B4 (de) Verfahren zur herstellung eines optoelektronischen halbleiterchips
DE102012106364B4 (de) Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
EP1920508B1 (fr) Procédé pour séparer latéralement une plaquette de semi-conducteurs empilés
WO2007124737A1 (fr) Corps semi-conducteur émetteur de rayonnement avec un substrat de support et son procédé de fabrication
DE102007004304A1 (de) Dünnfilm-Leuchtdioden-Chip und Verfahren zur Herstellung eines Dünnfilm-Leuchtdioden-Chips
WO2014053445A1 (fr) Procédé permettant de fabriquer un écran à diodes électroluminescentes, et écran à diodes électroluminescentes
DE102010034665A1 (de) Optoelektronischer Halbleiterchip und Verfahren zur Herstellung von optoelektronischen Halbleiterchips
DE112015000850B4 (de) Verfahren zur Herstellung einer Mehrzahl von Halbleiterbauelementen und Halbleiterbauelement
EP2340568A1 (fr) Corps semi-conducteur optoélectronique
DE102012109594A1 (de) Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils und optoelektronisches Halbleiterbauteil
DE102008062932A1 (de) Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
WO2011085895A1 (fr) Puce semi-conductrice optoélectronique
WO2014095353A1 (fr) Procédé de fabrication d'une puce de semi-conducteur optoélectronique et puce de semi-conducteur optoélectronique
WO2012107290A1 (fr) Puce semiconductrice optoélectronique à couche miroir encapsulée
WO2016023807A1 (fr) Puce en semiconducteur optoélectronique et son procédé de fabrication
EP2304816B1 (fr) Dispositif électroluminescent et procédé de production d'un dispositif électroluminescent
WO2018172205A1 (fr) Puce semi-conductrice optoélectronique et procédé de fabrication correspondant
EP2697835A1 (fr) Procédé pour la fabrication d'un corps semi-conducteur
WO2017158046A1 (fr) Puce semi-conductrice électroluminescente et procédé de fabrication d'une puce semi-conductrice électroluminescente
WO2015181005A1 (fr) Puce de semi-conducteur optoélectronique et procédé pour la fabriquer
WO2015176873A1 (fr) Procédé de fabrication d'une puce de semi-conducteur optoélectronique et puce de semi-conducteur optoélectronique
DE112015002477B4 (de) Elektrische Kontaktstruktur für ein Halbleiterbauelement und Halbleiterbauelement
WO2018162583A1 (fr) Composant semi-conducteur et procédé de production d'au moins un composant semi-conducteur

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13799536

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13799536

Country of ref document: EP

Kind code of ref document: A1