WO2014068774A1 - Information processing device, arithmetic processing device, and counter synchronization method - Google Patents

Abstract

A system in which the present invention has been applied has one or more arithmetic processing devices provided with counters for cyclically counting the total number of clocks supplied from outside after operation has started. The system is furthermore has: a stop control means for stopping all the counters provided to the first arithmetic processing device and to the respective arithmetic processing devices that are in operation from among the one or more arithmetic processing devices when a first arithmetic processing device, which is not included among the one or more arithmetic processing devices, has been added; a reading means for reading the value of a counter provided to one of the arithmetic processing units after the arithmetic processing unit has been stopped by the stop control means; a writing means for writing the value read by the reading means to the counter provided to the first arithmetic processing unit; and a resume control means for resuming operation of all the counters that were stopped by the stop control means, after the value has been written by the writing means.

Description

Information processing apparatus, arithmetic processing apparatus, and counter synchronization method

The present invention relates to an arithmetic processing apparatus equipped with a counter for counting a clock supplied from the outside as a timer.

In recent years, a partition function is installed in many computers (information processing devices) such as servers. The partition function is a function that divides resources of one information processing apparatus into processing units (groups) called a plurality of partitions and operates independently for each partition.

In each partition, an arbitrary OS (Operating System) or application program (hereinafter abbreviated as “application”) can be executed. Thereby, each partition can be operated as one independent information processing apparatus. Since one information processing apparatus can be used as a plurality of information processing apparatuses, the partition function is useful for suppressing the number of information processing apparatuses installed.

The resources allocated to each partition often include a plurality of arithmetic processing devices that execute programs. This is because each partition usually requires high processing power. The arithmetic processing device is, for example, a CPU (Central Processing Unit). Hereinafter, CPU is used as a general term for arithmetic processing devices.

In a partition to which a plurality of CPUs are assigned, each CPU is used for executing a program. In such a partition, one task may be executed in a distributed manner by a plurality of CPUs.

There are tasks that check the elapsed time such as the execution time or waiting time of tasks. A single CPU does not always execute such a task that requires confirmation of the elapsed time. For this reason, in each partition, each CPU checks the elapsed time as necessary. To confirm the elapsed time, TSC (Time Stamp Counter) is usually used.

This TSC is a free running counter installed in the CPU, and counts the total number of clocks supplied from the outside after starting the operation. The count is cyclically incremented (incremented) from an initial value of 0 to a maximum value corresponding to the number of bits (for example, 64 bits).

• 0 is set in TSC by resetting the installed CPU. The TSC of each CPU is usually supplied with the clock from the same clock source so that the count-up time interval does not differ for each TSC. For this reason, each CPU can appropriately check the elapsed time by resetting each CPU belonging to the same partition within an allowable range.

High-precision timers called HPET (High Performance Event Timer) are mounted on LSI (Large Scale Integration) chips for interconnection such as South Bridge and ICH (I / O Controller Hub). This HPET can be used for confirmation of the elapsed time by each CPU.

In recent years, multi-core CPUs are widely used as CPUs. Each core executes a thread which is the smallest execution unit of a program in parallel. Each core executing a thread may check the elapsed time. Therefore, in a partition having a multi-core CPU, many accesses to HPET are likely to be concentrated. Access concentration reduces processing performance. For this reason, at present, TSC is used rather than HPET for checking the elapsed time.

The partition function includes a dynamic partition (DP) function. This DP function refers to the dynamic addition (Hot-add) of hardware resources such as CPU and memory to the partition where the OS is running, or the dynamic replacement (Hot-replace) of existing hardware resources. It is a function that makes it possible. In an information processing apparatus equipped with a DP function, a hardware resource to be added or exchanged is usually modularized so that addition or exchange can be easily performed. Hereinafter, for convenience, modularized hardware resources are referred to as “processing modules”.

The CPU present in the processing module is reset when it is newly installed for addition or replacement. As a result, the TSC in the CPU existing in the newly installed processing module starts counting up from the initial value.

The processing module is installed without shutting down. Conventionally, a reset to a CPU existing in a newly installed processing module is automatically performed by recognition of the processing module. For this reason, the TSC value in the CPU existing in the newly installed processing module is usually greatly different from the TSC value in the CPU existing in another processing module belonging to the same partition.

As described above, in a partition, one CPU does not necessarily execute all tasks that require confirmation of elapsed time. For this reason, when the difference between the TSC value in the CPU existing in the newly installed processing module and the TSC value in the CPU existing in another processing module belonging to the same partition is not within the allowable range, It is very likely that a task that cannot be handled properly will occur. Therefore, the TSC value in the CPU existing in the newly installed processing module is synchronized with the TSC value in the CPU existing in another processing module belonging to the same partition within the allowable range. There is a need.

Conventionally, the TSC value can be rewritten not only for reading but for only the lower bits. However, even if an appropriate value is written only in the lower bits of the TSC in the CPU existing in the newly installed processing module, the overall value is not always appropriate. Even if all bit values are read from the TSC in the CPU existing in another processing module, and the read value is written to the TSC in the CPU existing in the newly installed processing module, the values of those TSC A relatively large difference may occur. This is because the TSC is a counter that counts up by input of a clock even when the installed processing unit is not operating. As a result, a difference more than the time required to write the value of one TSC to another TSC occurs. The time is the total time required for reading a value from a certain TSC, transferring the read value, writing the read value to another TSC, and the like.

* The above difference may be outside the allowable range depending on the task to be executed. The difference increases due to the presence of a heavily loaded CPU or the concentration of data transfer. Therefore, it seems important to synchronize the TSC value in the newly added CPU so as to be more accurate with the TSC value in the operating CPU.

Special table 2008-518367 gazette JP-A-6-332569 Japanese Patent Application Laid-Open No. 10-228397

In one aspect, an object of the present invention is to provide a technique for synchronizing a newly added TSC value in a CPU with a TSC value in an operating CPU.

One system to which the present invention is applied includes one or more arithmetic processing devices equipped with a counter that cyclically counts the total number of clocks supplied from the outside after the operation starts, and one or more arithmetic processing devices. When a first arithmetic processing device that is not included is newly added, each of the first arithmetic processing device and each of the arithmetic processing devices in operation among the one or more arithmetic processing devices Stop control means for stopping all mounted counters, reading means for reading the value of the counter mounted in one of the arithmetic processing units after stopping by the stop control means, and values read by the reading means Writing means to the counter mounted on the first arithmetic processing unit, and after the writing means writes the value, the operation of all the counters stopped by the stop control means is restarted. Having a control means.

In one system to which the present invention is applied, the value of a counter such as a TSC in a CPU that is newly added can be synchronized with the value of a counter such as a TSC in an operating CPU.

It is a figure explaining the structural example of the information processing apparatus by this embodiment. It is a figure explaining the schematic structural example of a system board, and CPU mounted in the system board. It is a figure explaining the structural example of a system board in detail. FIG. 10 is a sequence diagram showing an operation flow of an MMB, an existing system board, and a newly added system board when a new system board is added to a partition. It is a figure explaining the synchronization method of TSC by this embodiment. It is a flowchart showing the process which each CPU performs when a system board is added. It is a flowchart showing the process which each CPU performs when a system board is added (continuation).

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration example of the information processing apparatus according to the present embodiment. As shown in FIG. 1, the information processing apparatus according to the present embodiment includes a plurality of system boards (SB) 1 (1-1 to 1-4) and a plurality of IO (Input / Output) units 2 (2-1 to 2). -4), a crossbar switch 3, an MMB (ManageMent Board) 4, and a LAN 5.

The system board 1 is a processing module including one or more CPUs 11 and a memory 12. The IO unit 2 is a processing module that includes one or more IO devices 21. In the IO device 21, there is a storage storing an OS (Operating System) 21a. Hereinafter, only the storage 21 storing the OS 21a is assumed as the IO device 21 mounted in the IO unit 2.

The crossbar switch 3 is a relay device that connects the system boats 1, the IO units 2, and the system boards 1 and the IO units 2. The MMB 4 is a management dedicated unit that manages the entire information processing apparatus. The MMB 4 provides a user interface to the connected terminal device, and enables operation management such as hardware status monitoring, configuration information display, error information display, partition management, network management, and power supply control. The reason why the system boards 1 and the MMB 4 are connected by the LAN 5 is to perform a plurality of complicated operation management processes through one physical medium. FIG. 1 shows three partitions 6-1 to 6-3 as the partition 6 managed by the MMB 4. The partition 6-1 includes two system boards 1-1 and 1-2 and one IO unit 2-1. Similarly, the partition 6-2 includes one system board 1-2 and two IO units 2-2 and 2-3, and the partition 6-3 includes one system board 1-4 and IO unit, respectively. 2-4.

FIG. 2 is a diagram for explaining a schematic configuration example of a system board and a CPU mounted on the system board. A CPU 11 equipped with a TSC 110 is employed.

In each partition 6, one CPU 11 does not necessarily execute all tasks for which the elapsed time needs to be confirmed. Therefore, a common clock generator (“CLOCK Source” in FIG. 2) is used so that the difference in value between the TSCs 110 of the CPU 11 mounted on each system board 1 (1-1 to 1-n) does not change with time. The clock is supplied from 200 to the CPU 11 of each system board 1. The clock generator 200 is provided in the housing, but the arrangement location is not limited as long as it is in the housing. For example, the clock generator 200 may be mounted on any system board 1 or any IO unit 2.

Each system board 1 is equipped with a south bridge 13. An HPET 130 is mounted on the south bridge 13.

FIG. 3 is a diagram illustrating a configuration example of the system board in more detail.
As shown in FIG. 3, each system board 1 includes, in addition to the CPU 11, the memory 12, and the south bridge 13, a BMC (Baseboard Management Controller) 14, an FWH (Firm-Ware Hub) 15, an MC (Memory Controller) 16, And I2C (Inter-Integrated Circuit) GPIO (General Purpose Input / Output) 17. Although a plurality of CPUs 11 can be mounted on each system board 1, for convenience of explanation, it is assumed here that only one CPU 11 is mounted on each system board 1. The configuration of each system board 1 other than the number of CPUs 11 is not limited to that shown in FIG.

The BMC 14 is a processing device that performs various management processes including monitoring of the state of the own system board 1 and power on / off. The BMC 14 is connected to the MMB 4 via the LAN 5, and requests from the MMB 4 are processed by the BMC 14. The south bridge 13 is connected by an LPC (Low Pin Count) bus.

When the BMC 14 is connected to the LAN 5, the BMC 14 transmits the configuration information of the own system board 1 to the MMB 4. Thereby, the MMB 4 recognizes the configuration including the number of CPUs 11 of the newly added system board 1 and reflects it in the control.

The south bridge 13 is connected to the CPU 11 via a DMI (Desktop Management Interface) bus, for example, and performs interrupts such as SMI (System Management Interrupt) and SCI (System Control Interrupt) to the CPU 11 in accordance with instructions from the BMC 14. The FWH 15 connected to the south bridge 13 stores a BIOS (Basic Input / Output System) 15 a executed by each CPU 11. The SMI is processed by the BIOS 15a, and the SCI is processed by the OS 21a that is read from the IO device 21 and executed.

Only one South Bridge 13 is valid for each partition 6. In FIG. 3, only the south bridge 13 of the system board 1-1 is valid, and the south bridge 13 of the system board 1-2 is invalid.

MC 16 accesses memory 12 according to an instruction from CPU 11. Communication via the crossbar switch 3 is performed via the CPU 11.

The I2C GPIO 17 is connected to the MMB 4 via the I2C bus. The MMB 4 can reset the CPU 11 via the I2C GPIO 17.

The TSC 110 of the CPU 11 that has been reset starts counting up with 0 as an initial value. The reset by the MMB 4 is performed on the CPUs 11 on all the system boards 1 to be turned on for each partition 6. Thereby, the TSCs 110 of the CPUs 11 on all the system boards 1 that are simultaneously turned on are synchronized.

However, when a new system board 1 is added to the partition 6 by hot add or hot replacement, the reset is performed by recognizing the BMC 14 newly connected to the LAN 5, for example. For this reason, the value of the TSC 110 of the CPU 11 that is newly reset is usually significantly different from the value of the TSC 110 of the CPU 11 that has already been reset. From this, in this embodiment, the synchronization which makes the value of TSC110 of CPU11 newly reset correspond to the value of TSC110 of CPU11 already reset within an allowable range as follows is realized. Here, it is assumed that the system board 1-2 is newly added to the partition 6-1 and will be specifically described with reference to FIG.

FIG. 4 is a sequence diagram showing an operation flow of the MMB, the existing system board, and the newly added system board when a new system board is added to the partition. In FIG. 4, the system board 1-1 is indicated as “Initial SB”, and the system board 1-2 is indicated as “Hot-added SB”. The system board 1-1 represents the BMC 14, the south bridge 13, the I2C GPIO 17, and the CPU 11. The CPU 11 is divided into a TSC 110, a BIOS 15a, and an OS 21a. The system board 1-2 represents the BMC 14, the I2C GPIO 17, and the CPU 11.

In FIG. 4, the south bridge 13 is represented on the system board 1-1 and is not represented on the system board 1-2. This is because only one south bridge 13 is valid in each partition 6. Since the south bridge 13 of the system board 1-1 is enabled, the south bridge 13 of the system board 1-2 is disabled.

Unlike the CPU 11, the BMC 14 of each system board 1 is powered on when mounted on the information processing apparatus. From this, the BMC 14 of the system board 1-2 notifies the MMB 4 that the system board 1-2 on which the BMC 14 is mounted is newly added by connection with the LAN 5. Next, the MMB 4 is requested to start processing for adding the system board 1-2 mounted from the OS 21a to the partition 6-1 (system board HotAdd) (S1). This process can be instructed directly from the user interface on the MMB 4 as well as from the OS 21a. In response to the HotAdd start instruction of the system board, the MMB 4 instructs the BMC 14 to activate the CPU 11 of the system board 1-2 and reset the activated CPU 11 (S2, S3).

Next, the MMB 4 instructs the CPU 11 of the system board 1-1 to perform processing for incorporating the system board 1-2 into the partition 6-1 as hardware (S4 to S6). This instruction is given by the SMI via the BMC 14 and the south bridge 13. More specifically, for example, the BMC 14 asserts an SMI signal output from the mounted GPIO (not shown) to the south bridge 14 in response to an instruction from the MMB 4, and the south bridge 14 asserts the SMI by asserting the signal. I do.

The instruction by the SMI is processed by the BIOS 15a executed by the CPU 11, more specifically, by the SMI handler (Handler) which is a program incorporated in the BIOS 15a. The SMI handler here updates the setting related to the connection target of its own partition 6-1 and causes the CPU 11 of the system board 1-2 to perform the setting related to the connection target (S7). Thereafter, the SMI handler notifies the MMB 4 of the end of the instructed process (S8). This notification is not shown in detail in FIG. 4, but is performed via, for example, the south bridge 13 and the BMC 14.

The above S4 to S8 are performed to add the system board 1-2. Thereafter, processing for synchronizing the TSC 110 mounted on the CPU 11 of the system board 1-2 is performed.

The MMB 4 instructs the CPU 11 of the system board 1-1 to stop the operations of all the TSCs 110 existing in the partition 6-1 (S11 to S13). This instruction is performed by the SMI via the BMC 14 and the south bridge 13 as described above.

The instruction by the SMI is processed by the SMI handler of the BIOS 15a executed by the CPU 11. The SMI handler stops the TSC 110 of its own CPU 11, and instructs the CPU 11 on the system board 1-2 to stop the TSC 110 (S14). An instruction to the CPU 11 on the system board 1-2 is made through the crossbar switch 3.

Next, the SMI handler reads the value of the TSC 110 of its own CPU 11 (S15), and instructs the CPU 11 of the system board 1-2 to write the read value to the TSC 110 (S16). Thereafter, the SMI handler restarts the operation of the TSC 110 of its own CPU 11, and instructs the CPU 11 of the system board 1-2 to resume the operation of the TSC 110 (S17). In this manner, after all the operations of the TSC 110 existing in the partition 6-1 are resumed, the MMB 4 is notified that the synchronization of the TSC 110 is completed (S18). By this notification, the operation related to the synchronization of the TSC 110 is completed.

The MMB 4 notified that the synchronization of the TSC 110 is completed performs a process of activating the added system board 1-2 as a resource of the partition 6-1. Therefore, the MMB 4 causes the CPU 11 existing in the partition 6-1 to perform SCI for setting the configuration of the partition 6-1 from the MMB 4 (S21 to S23). This instruction is given by SCI via the BMC 14 and the south bridge 13. For example, the BMC 14 asserts an SCI signal output from the mounted GPIO to the south bridge 14 in response to an instruction from the MMB 4, and the south bridge 14 performs SCI by asserting the signal.

The SCI activates ACPI (Advanced Configuration and Power Interface) of OS 21a. The activated ACPI performs processing for logically incorporating resources (CPU and memory) on the system board 1-2 into the partition 6-1. Thereby, thereafter, in the partition 6-1, an application operation using both CPUs and memory resources of the two system boards 1-1 and 1-2 becomes possible.

FIG. 5 is a diagram for explaining a TSC synchronization method according to the present embodiment. Next, the synchronization method realized by the operation shown in FIG. 4 will be specifically described with reference to FIG.

5. “CPU From initial Power On” and “Hot-added CPU” shown in FIG. 5 represent the CPU 11 of the system board 1-1 and the CPU 11 of the system board 1-2, respectively. Below each notation, a change in the value of the TSC 110 mounted on the corresponding CPU 11 is represented by a broken line. A straight line extending under the notation “TSC” represents a time axis and a value of 0, and a broken line drawn on the right side of the straight line represents a change in the value of the corresponding TSC 110. For example, in the CPU 11 of the system board 1-1, a line extending diagonally to the right starting from the straight line is bent to the left beyond the time A. This indicates that the TSC 110 counts up using 0 as an initial value, and after the value reaches the maximum value, the value becomes 0 again.

5, S14 to S17 represented as symbols have the same meaning as the symbols illustrated in FIG. That is, the same reference numerals are used for the same operations as in FIG. The “BIOS SMI handler” is a program executed by the CPU 11 of the system board 1-1. “OS operation” represents a transition of a program executed by the CPU 11 of the system board 1-1.

In FIG. 5, the TSC 110 of the CPU 11 of the newly installed system board 1-2 starts counting up from time A. At the time A, the value held by the TSC 110 of the CPU 11 of the system board 1-1 is significantly different from zero. Since the values are usually so different, it is necessary to match the value of one of the TSCs 110 with the other. However, the value of the TSC 110 of the CPU 11 of the system board 1-1 that is already operating cannot be changed in view of the existence of the task being executed. Therefore, the value to be changed is the TSC 110 of the CPU 11 of the system board 1-2.

The MMB 4 recognizes the installation of the system board 1-2 through communication with the BMC 14 and performs SMI. Thereby, in the CPU 11 of the system board 1-1, the control is transferred from the OS 21a to the BIOS 15a at time B.

In the BIOS 15a to which the control has passed, the SMI handler is activated, and the activated SMI handler stops the TSC 110 of the CPU 11 and the TSC 110 of the CPU 11 of the system board 1-2 at time C (S14). Thereby, the value of TSC110 of each CPU11 after that is represented by a line parallel to the time axis.

After stopping the TSC 110 of each CPU 11, the SMI handler reads the value of the TSC 110 of its own CPU 11 (S15), and writes the read value to the TSC 110 of the CPU 11 of the system board 1-2 at time D (S16). As a result, the value of the TSC 110 of the CPU 11 of the system board 1-2 changes from the previous value to the value of the TSC 110 of the CPU 11 of the system board 1-1.

The SMI handler restarts the operation of the TSC 110 of each CPU 11 at time E after the writing is completed (S17). The TSC 110 of each CPU 11 at the time of resumption is the same value, and the difference in timing at which the TSC 110 of each CPU 11 resumes operation can be within an allowable range. For this reason, the TSC 110 mounted on each CPU 11 can be appropriately synchronized. After restarting, at time F, control passes from the BIOS 15a to the OS 21a.

6A and 6B are flowcharts showing processing executed by each CPU when a system board is added. The processing shown in FIGS. 6A and 6B is processing when the TSC 110 of each CPU 11 is synchronized, and is realized when each CPU 110 executes the BIOS 15a. In the processing shown in FIGS. 6A and 6B, the synchronization of the TSC 110 of each CPU 11 performed in S14 to S17 is realized by a method different from the method shown in FIG. Next, with reference to FIG. 6A and FIG. 6B, the process performed in order to synchronize the value of TSC110 of each CPU11 including CPU11 on the system board 1 added is demonstrated in detail.

“Master” shown in FIG. 6A is the CPU 11 that plays a role of leading the synchronization of the TSC 110, and “Slave” means all other CPUs 11 including the CPU 11 on the newly installed system board 1. . 6A and 6B, the CPU 11 on the newly installed system board 1 is handled in the same manner as the CPUs 11 other than the master.

In FIG. 6A, for the sake of convenience, only one process with the same content executed by the master and slave CPUs 11 is shown. A process that represents only one and a process that is basically the same will not be described separately for a master and a slave.

The MMB 4 that has recognized the newly installed system board 1 performs SMI. Thereby, all the CPUs 11 activate the SMI handler of the BIOS 15a (SM1, SS1). With the activation of the SMI handler, all the CPUs 11 transition to SMM (System Management Mode).

The activation of the SMI handler (BIOS 15 a) in each CPU 11 is performed by first activating the CPU 11 of the system board 1 in which the south bridge 13 is valid, and causing the CPU 11 to activate all other CPUs 11. Can be made. Alternatively, the south bridges 13 of all the system boards 1 may be validated, and the SMI handlers may be activated in all the CPUs 11 according to instructions from the MMB 4.

6A and 6B is realized by each CPU 11 executing the SMI handler of the BIOS 15a. The reason for causing each CPU 11 to execute the SMI handler is that the SMI handler can be basically activated in any situation. Depending on the status of each CPU 11, it is possible to prevent the timing at which each CPU 11 starts processing or the timing at which the processing ends from greatly shifting. This is an advantage in performing synchronization of the TSC 110 more appropriately.

Each CPU 11 that has activated the SMI handler waits for all other CPUs 11 to activate the SMI handler (SM2, SS2). Thereafter, each CPU 11 recognizes whether its own role is master or slave (SM3, SS3). As a result, the CPU 11 that has been recognized as a master subsequently performs processing as a master, and the CPU 11 that has been recognized as a slave thereafter performs processing as a slave. The recognition itself may be performed from the identification information assigned to the CPU 11, for example. More specifically, the CPU 11 having the smallest CPU number among the CPU numbers assigned as identification information may be set as the master.

The master CPU 11 checks whether all slaves have participated, for example, by waiting for the elapse of a predetermined time (SM4). Next, the master CPU 11 confirms the SMI factor (SM5), and determines whether the confirmed factor is for the synchronization request of the TSC 110 (SM6). When SMI is performed for the synchronization request, the determination of SM6 is YES and the process proceeds to SM7. When the SMI is performed for a purpose other than the synchronization request, the determination in SM6 is NO, and then the master CPU 11 executes processing for the confirmed request. Since the explanation of the processing is not particularly important, it is omitted here.

In SM7 to SM10, a TSC stop process for stopping the TSC 110 of all the CPUs 11 is performed.

In this embodiment, the master CPU 11 secures a work area in the memory 12, for example, and designates a process to be executed by each slave CPU 11, an instruction to start execution of the process, and the like through the work area. It has become. When the slave CPU 11 executes a designated process, the slave CPU 11 writes that fact in the work area.

In FIG. 6A and FIG. 6B, the work area is described as “Msg_box”. Hereinafter, the work area is referred to as a “message box”.

The “start flag” shown in FIGS. 6A and 6B is information for instructing the start of execution of the process, and “set start flag” means that the start of the execution of the process has been instructed. The “end flag” is information for notifying that the slave CPU 11 has executed the process, and “setting the end flag” means that the process has been executed. One start flag is sufficient, but an end flag is required for each slave CPU 11. When there is only one start flag, each slave CPU 11 may execute the process on condition that the start flag is set and the end flag corresponding to the CPU 11 is reset. Here, for convenience, it is assumed that there are as many start flags and end flags as there are slave CPUs 11.

The designation of the process to be executed represents, for example, storage of a command to be executed, storage of information used by the slave CPU 11 for processing, or address information indicating the storage location, or a command to be executed next in the SMI handler. This can be done by address information or the like. Other methods may be used.

When using the message box as described above, the CPU 11 of each slave recognizes and executes the process to be executed by polling to confirm the contents of the message box.

In SM7, the master CPU 11 stops the TSC 110 of its own CPU 11. Next, the master CPU 11 writes, for example, a command instructing to stop the TSC 110 in a message box (SM8), sets all start flags, and resets all end flags (SM9). After that, the master CPU 11 waits until it can be confirmed that the all end flag is set (SM10).

The slave CPU 11 after executing SS3 waits for the start flag corresponding to the CPU 11 in the message box to be set (SS4). When the set of the start flag is confirmed, the determination of SS4 is Yes and the process proceeds to SS5.

In SS5, the slave CPU 11 stops the TSC 110 of its own CPU 11 according to the command stored in the message box. Next, the slave CPU 11 sets an end flag corresponding to the CPU 11 in the message box (SS6). Thereafter, the slave CPU 11 proceeds to SS7 in order to wait until the next process is executed.

When the CPU 11 of all slaves sets the end flag, the determination of SM10 is YES and the process proceeds to SM11. In SM11 to SM14, a TSC write process is performed to write the value of the TSC 110 of the master CPU 11 to the TSC 110 of all the slave CPUs 11.

First, in SM11, the master CPU 11 reads the value of the TSC 110 of its own CPU 11. Next, the master CPU 11 writes, for example, a command for instructing writing of a value to the TSC 110 and the read value in the message box (SM12), sets all start flags, and resets all end flags (SM13). . Thereafter, the master CPU 11 waits until it can be confirmed that the all end flag has been set (SM14).

The CPU 11 of the slave that has shifted to SS7 shifts to SS8 by setting a start flag corresponding to its own CPU 11 in the message box. In SS8, the slave CPU 11 writes the value stored in the message box into the TSC 110 of the CPU 11 in accordance with the command in the message box (SS8). Next, the slave CPU 11 sets an end flag corresponding to the CPU 11 in the message box (SS9). Thereafter, the slave CPU 11 shifts to SS10 to wait until the next process is executed.

When the CPU 11 of all slaves sets the end flag, the determination of SM14 is YES and the process proceeds to SM15. In SM15 to SM18, TSC restart processing for restarting the operation of the TSC 110 of all the CPUs 11 is performed.

First, in SM15, the master CPU 11 writes, for example, a command instructing to resume the operation of the TSC 110 in a message box. Next, the master CPU 11 sets all start flags and resets all end flags (SM16). Further, the master CPU 11 resumes the operation of the TSC 110 of the own CPU 11 (SM17). Thereafter, the master CPU 11 waits until it can be confirmed that the all end flag is set (SM18).

The CPU 11 of the slave that has moved to SS10 moves to SS11 by setting a start flag corresponding to its own CPU 11 in the message box. In the SS 11, the slave CPU 11 resumes the operation of the TSC 110 of the own CPU 11 in accordance with the command in the message box. Next, the slave CPU 11 sets an end flag corresponding to its own CPU 11 in the message box (SS12). Thereafter, the slave CPU 11 proceeds to SS13 in order to wait until the next process is executed.

When the CPU 11 of all slaves sets the end flag, the determination of SM18 is YES and the process proceeds to SM19. In SM19 to SM22, SMI resume processing for returning all the CPUs 11 from the SMM to the state before the SMM transition is performed.

First, in SM 19, the master CPU 11 writes, for example, a command instructing the end of SMM in a message box. Next, the master CPU 11 sets all start flags in the message box and resets all end flags (SM20). Thereafter, the master CPU 11 waits until it can be confirmed that the all end flag has been set (SM21).

The CPU 11 of the slave that has shifted to SS13 shifts to SS14 according to the setting of the start flag in the message box. In the SS 14, the slave CPU 11 performs a process for returning to the state before the SMM transition according to the command in the message box. Next, the slave CPU 11 sets an end flag corresponding to its own CPU 11 in the message box (SS15). Thereafter, the slave CPU 11 ends the series of processing and returns to the state before the SMM transition.

When the CPU 11 of all slaves sets the end flag, the determination of SM21 is YES and the process proceeds to SM21. In SM 21, the master CPU 11 performs processing for returning to the state before the SMM transition and notifies the MMB 4 that the synchronization of the TSC 110 is completed. Thereafter, the master CPU 11 ends a series of processing and returns to the state before the SMM transition.

In this embodiment, the target of synchronization is TSC 110, but another counter may be used. Any information processing apparatus or a counter that exists in the partition 6 and is handled in the same manner as the TSC 110 can be set as a synchronization target.
In this embodiment, the CPU (system board) HotAdd is used as an example of synchronization. However, even when the partition is activated, the CPU 11 is reset to the CPU 11 due to a control delay between the MMB 4 and the GPIO 17 of each system board 1 shown in FIG. Assuming a case where the timing is greatly shifted and the synchronization is expected to be lost, TSC synchronization of all the CPUs 11 in the partition 6 can be guaranteed by performing TSC synchronization processing by SMI before starting the OS. Before starting the OS, the TSC is not used, so no problem occurs in the TSC synchronization processing.

The stop of the TSC 110 is performed by executing a command incorporated in the SMI handler, but if possible in hardware, it may be performed by cutting off the clock supply to the TSC 110. The mechanism for stopping may be determined according to the counter to be synchronized.

Claims (5)

One or more arithmetic processing units equipped with a counter that cyclically counts the total number of clocks supplied from the outside after starting operation;
When a first arithmetic processing device which is an arithmetic processing device not included in the one or more arithmetic processing devices is newly added, the first arithmetic processing device and the one or more arithmetic processing devices Stop control means for stopping all the counters mounted in each of the arithmetic processing devices in operation,
A reading means for reading a value of a counter mounted on one of the arithmetic processing units after being stopped by the stop control means;
Writing means for writing the value read by the reading means into a counter mounted in the first arithmetic processing unit;
After the writing means writes the value, restart control means for restarting the operation of all the counters stopped by the stop control means;
An information processing apparatus comprising: Recognizing means for recognizing the first arithmetic processing unit;
The stop control means stops all the counters when the recognition means recognizes the first arithmetic processing unit;
The information processing apparatus according to claim 1. When the one or more arithmetic processing devices are a plurality of arithmetic processing devices, and the plurality of arithmetic processing devices are divided into a plurality of groups, the recognition means performs the first arithmetic processing for each group. Recognize the device,
The information processing apparatus according to claim 2. A counter that cyclically counts the total number of externally supplied clocks after starting operation;
Stop means for stopping the counter;
Writing means for writing an externally designated value into the counter;
Restarting means for restarting the operation of the counter stopped by the stopping means;
An arithmetic processing apparatus comprising: When a first arithmetic processing device is newly added to an information processing device including one or more arithmetic processing devices equipped with a counter that cyclically counts the total number of clocks supplied from the outside after the operation is started ,
Stopping the counter mounted on each of the first arithmetic processing units and the one or more arithmetic processing units that are operating,
Read the value of the counter mounted on one of the arithmetic processing units,
The read value is written in a counter mounted on the first arithmetic processing unit,
Starting the operation of the first arithmetic processing unit and a counter mounted in each arithmetic processing unit,
And a counter synchronization method.

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