JP2011113163A - Inter-end point communication control device and method in io access communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication control device and method by which an IC access can be autonomously performed at an end point side to another end point. <P>SOLUTION: The inter-end point communication control device is configured to perform the communication control of an end point (EP) in a PCIe system, and provided with: a port (102) for communicating with a low order EP; a PCIe port (101) for communicating with high order communication equipment; a control part (105) for performing the synchronous processing of control information to associate EP as the object of IO access with each other between itself and a CPU; an RTI function part (103) for executing processing to transfer data received from the port (102) to a transfer EP by referring to the control information, and transmits the data through the PCIe port (101); and an RTO function part (104) for executing the data received from the PCIe port (101) to the transfer EP by referring to the control information, and transmitting the data through the port (102). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a communication system employing a high-speed serial interface called PCI Express, and more particularly to an apparatus and method for performing IO access communication control.

  In recent years, PCI Express (hereinafter referred to as “PCIe” as appropriate) has become widespread, and personal computers equipped with a PCIe slot are also commercially available. A general configuration of such a PCIe system is shown in FIG. 9 (see, for example, Patent Document 1). As is well known, the components of the PCIe system are a root complex, a PCIe switch, a PCIe bridge, an IO device end point (EP), and the like.

JP 2007-95025 A

  In the existing PCIe system described above, the IO access to each device (EP) requires the CPU to access the device driver of each EP. Since PCI Express only defines the rules for exchanging error information on the PCIe link, each device (EP) connected to the end of the PCIe switch or PCIe bridge is what kind of device on the PCIe link. (EP) can't know directly if connected. For this reason, in order for devices to exchange IO access, an OS (Operating System) on the CPU requires a process of teaching each device the destination of the communication destination.

  Thus, in the existing PCIe system, since there is no means by which each EP side can know the address information of the destination EP, it is impossible for the EP side to autonomously make IO access to other EPs. For this reason, CPU access is always involved in IO access communication between EPs, increasing the load on the CPU.

  Accordingly, an object of the present invention is to provide a communication system, an inter-endpoint communication control apparatus, and a method capable of performing IO access to other end points autonomously on the end point side.

  An inter-endpoint communication control apparatus according to the present invention is an apparatus for performing end point communication control in a communication system using a high-speed serial interface, and includes a first port for communicating with a lower end point, and an upper communication apparatus. Between the second port for communicating with the general-purpose control unit of the communication system, a control means for performing synchronization processing of control information for associating at least endpoints to be IO accessed, and the control information Referring to the control information, the first transfer means executes processing for transferring the data received from the first port to the transfer destination endpoint and sends it through the second port; , Executing processing for transferring data received from the second port to a transfer destination endpoint, the first port A second transfer means for sending through, and having a.

  In the communication system according to the present invention, a lower-order endpoint is connected to the first port of the inter-endpoint communication control apparatus described above, a switch of the communication system is connected to the second port, and a general-purpose control unit has a route complex connected to the switch. It is characterized by being connected via.

  An inter-endpoint communication control method according to the present invention is a communication control method between end points in a communication system using a high-speed serial interface in which a plurality of communication devices are hierarchically connected from a general-purpose control unit to a plurality of end points. When the control means executes a synchronization process of control information for associating at least an endpoint that is an IO access target with the general-purpose control unit, and receives a transfer start request from the general-purpose control unit as a transmission source, One transfer means executes processing for transferring data received from a lower-order endpoint with reference to the control information to a transfer-destination endpoint, and transmits the data to a higher-order communication device. When the transfer start request is received as the transfer destination, the second transfer means transfers the data received from the host communication device. Transmitting executes processing for transferring the endpoint to endpoint of the destination, and having a.

  A program according to the present invention causes a program control processor to function as a communication control apparatus between endpoints in a communication system using a high-speed serial interface in which a plurality of communication devices are hierarchically connected from a general-purpose control unit to a plurality of endpoints. And executing a synchronization process of control information for associating at least an endpoint that is an IO access target with the general-purpose control unit, and receiving a transfer start request from the general-purpose control unit as a transmission source. The first transfer means executes processing for transferring the data received from the lower-order endpoint with reference to the control information to the transfer-destination endpoint, and transmits the data to the higher-order communication device. When the transfer start request is received from the transfer unit as the transfer destination, the second transfer means sends the upper communication device Wherein the running process for transfer to the destination endpoint with respect et received data transmitted to the endpoint of the transfer destination, the functioning of the said program-controlled processor such.

  According to the present invention, IO access to other endpoints can be autonomously performed on the endpoint side.

It is a block diagram which shows the functional structure of the communication control apparatus between EP by 1st Embodiment of this invention. 1 is a system configuration diagram showing an example of a PCIe communication system employing an inter-EP communication control device according to a first embodiment of the present invention. FIG. 3 is a sequence diagram illustrating an example of configuration processing in the PCIe communication system illustrated in FIG. 2. FIG. 3 is a sequence diagram illustrating an example of processing for enabling a VF (Virtual Function) in the PCIe communication system illustrated in FIG. 2. It is a sequence diagram which shows an example of IO access communication between EP in the PCIe communication system shown in FIG. It is a schematic diagram which shows an example of the table content referred with the communication control apparatus between EP shown in FIG. It is a schematic diagram which shows matching of VF between EP in the PCIe communication system shown in FIG. It is a system block diagram which shows an example of the IO access communication system between EP by 2nd Embodiment of this invention. It is a system configuration diagram showing an example of a general PCIe system.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited by embodiment described below.

1. Inter-EP communication control apparatus The inter-EP communication control apparatus according to the first embodiment of the present invention is connected between a host device such as a PCIe switch and an end point EP, and is equipped with a device driver corresponding to each EP. And Further, it is assumed that the endpoint EP in this embodiment is provided with an SR-IOV (Single Root I / O Virtualization) function developed by PCI-SIG. As will be described later, the inter-EP communication control device performs data switching operation between the CPU and the EP or the EP-EP that controls the entire system. Therefore, in the drawing, e2eSW (end point to end point switch) Is displayed.

  In FIG. 1, an inter-EP communication control device (e2eSW) 100 has a PCIe port 101 for connecting to a host device on the CPU side and a port 102 for connecting to an endpoint EP, and further RTI (Routing to Inside). ) A functional unit 103, an RTO (Routing to Outside) functional unit 104, and a control unit 105 that controls the operation of the apparatus 100.

  The RTI function unit 103 is a data transfer function unit in the upstream direction from the port 102 to the PCIe port 101, and includes a reception unit 110, a memory 111, a transmission unit 112, and a table 113. The receiving unit 110 receives data from the EP through the port 102 and saves the received data in the memory 111 having a buffer function. The transmission unit 112 refers to the table 113, selects the device driver of the data destination EP stored in the memory 111, and performs data transfer to the destination EP. As will be described later, the table information of the table 113 is synchronized with the CPU.

  The RTO function unit 104 is a data transfer function unit in the downstream direction from the PCIe port 101 to the port 102, and includes a reception unit 120, a memory 121, a transmission unit 122, and a table 123. The receiving unit 120 receives data from the upper device through the PCIe port 101 and saves the received data in the memory 121 having a buffer function. The transmission unit 122 refers to the table 123 and transfers the data stored in the memory 121 to the EP connected to the port 102. As will be described later, the table information of the table 123 is common to the table 113 of the RTI function unit 103, and synchronization processing with the CPU is performed.

  The control unit 105 manages synchronization of control information with the CPU, and processes general-purpose requests by performing data transfer management of the RTI function unit 103 and the RTO function unit 104, as will be described later. The control unit 105 has a virtual configuration Type 1 register, which is set to Write by the CPU through the PCIe port # 1 in the configuration processing described later, and returns a response to it, so that the CPU recognizes it as an existing PCIe switch. The

  For example, a VF (Virtual Function) is generated based on configuration information (VF BAR, First VF Offset, VF Stride, etc.) set in each EP by a configuration cycle issued from the CPU when the power is turned on. Bus / Device / Function) number is set. When the CPU synchronizes the mapping table information with the control unit 105 of the apparatus 100, the inter-EP communication control apparatus 100 can know the address and BDF of the VF existing in each EP. As a result, the inter-EP communication control apparatus 100 according to the present embodiment can substitute an IO access command performed on the CPU side in a general PCIe system. That is, the inter-EP communication control apparatus 100 can assign the transfer destination based on the destination information of the data from the EP, and can directly communicate between the EPs even in the IO access.

  The control unit 105 can also realize the above-described equivalent function by executing a program stored in a storage device (not shown) on the program control processor.

2. IO access communication system
In the IO access communication system, the inter-EP communication control apparatus 100 shown in FIG. 1 is connected between each EP and its upper PCIe device. Here, it is assumed that the EP is an SR-IOV compatible EP having an SR-IOV function formulated by PCI-SIG.

  As shown in FIG. 2, the IO access communication system according to the present embodiment is similar to the existing IO access communication system in that the CPU 201, the root complex 202, the main memory 203, the PCIe switch 204, and the SR-IOV compatible EPs 206-1. 206-n, but n between the PCIe ports of the PCIe switch 204 and the SR-IOV compatible EPs 206-1 to 206-n (Device # 1 to Device # n) respectively corresponding to the n PCIe ports The inter-EP communication control devices 205-1 to 205-n (e2eSW # 1 to e2eSW # n) are respectively connected. That is, the CPU 201, the root complex 202, the main memory 203, the PCIe switch 204, and the like use general-purpose ones. However, by arranging the inter-EP communication control device e2eSW # i before the EP 206-i, direct IO between the EPs Access (IO access without CPU intervention) is possible (where i = 1, 2,... N).

  Specifically, the configuration access is performed by the CPU after the power is turned on, so that m virtual functions based on information set in the SR-IOV configuration space in each inter-EP communication control device e2eSW # i. VFi1 to VFim are generated, and the address mapping information of the EP considering the generated VF is synchronized with the corresponding inter-EP communication control device e2eSW # i, thereby enabling direct IO access between the EPs.

  In FIG. 2, as an example, the flow of data directly transferred between the virtual function VFp1 of EP206-p (Device # p) and the virtual function VFq1 of EP206-q (Device # q) is indicated by a dashed arrow. Data from the virtual function VFp1 of EP206-p (Device # p) to the virtual function VFq1 of EP206-q (Device # q) is the communication between the RTI function unit of the inter-EP communication control device e2eSW # p, the PCIe switch 204, and the inter-EP communication. The data is transferred to the inter-EP communication control device 205-q through the RTO function unit of the control device e2eSW # q. As described above, data transfer is executed between the EPs without intervention of the CPU except for the initial setting.

3. Inter-EP IO access communication In the present invention, it is assumed that the sequence from when the power is turned on to when the IO access communication system is constructed is the same as the existing one. When an IO access communication processing request between EPs occurs, a control information synchronization sequence is activated between the CPU and each EP, and this triggers IO access communication between the EPs. In the existing IO access communication system, the CPU must intervene to transfer one data, but the processing can be omitted.

3.1) Configuration Processing In FIG. 3, the CPU 201 generates a bus cycle for searching for an EP under the PCIe bus immediately after power-on (actually, the root complex (RC) 202 is generated). The inter-EP communication control device e2eSW # i that has received the bus cycle responds to it to complete the configuration access (step 301). Thus, the address and BDF number of the inter-EP communication control device e2eSW # i are determined.

  When configuration access is completed for all the inter-EP communication control devices e2eSW (here e2eSW # p and e2eSW # q), the CPU 201 generates a configuration bus cycle for the further device and receives the bus cycle. When the EP responds, the configuration access to the EP is completed (step 302). For this configuration access, the inter-EP communication control device e2eSW # i performs through transfer almost like the existing PCI bridge. This enables the CPU 201 to map the EP onto the memory space.

  Since a general-purpose PCIe switch can be considered to be logically composed of multiple PCI-PCI bridges, as a result of the configuration cycle by the CPU, the general-purpose PCIe switch has an EP under its own control. It is possible to determine which range the address is in. Therefore, similarly to the PCI bridge operation, the switch operation by confirming the destination address of the data entered from the outside is possible.

  Further, in this system, since it is assumed that the EP supports the SR-IOV function, the sequence shown in FIG. 4 is executed in order to enable the VF. However, since the inter-EP communication control device e2eSW # i does not affect the address mapping or the like resulting from the configuration access of the SR-IOV-compatible EP by the CPU 201, it will be briefly described.

  In FIG. 4, when the configuration type 0 register is read from the CPU 201 to each EP and SR-IOV Capability is found, the function is determined to be a physical function (PF: Physical function) (step 303). Subsequently, the number of valid VFs is retrieved from the SR-IOV Capability, and the VF is validated within the retrieved number of VFs (step 304). Then, RID (Requester ID) information such as VF Stride and First VF Offset is organized, and a memory map is organized using VF BAR, System Page Size, etc. (Step 305).

3.2) Table information As described above, control information such as address mapping information and BDF number generated by configuration access is synchronized with the general-purpose CPU 201 as table information of the inter-EP communication control device e2eSW # i. . Further, the inter-EP communication control device e2eSW # i installs a corresponding device driver and enables the transmission units 112 and 122 to perform the transmission operation.

  FIG. 5 shows an example of the table information of the tables 113 and 123 in FIG. In the table information, the source address indicating the source of IO access, the information of the source BDF and the source VF, the information of the transfer destination address indicating the transfer destination, the information of the transfer destination BDF and the transfer destination VF, and the device driver to be used The correspondence of is shown. The VF address, BDF, etc. in each EP are uniquely determined, and each VF is associated with the VFs of other EPs in a one-to-many manner. The inter-EP communication control device e2eSW # i realizes inter-EP IO access communication in the RTI function unit 103 and the RTO function unit 104 by using such table information. The table information is common to both the RTI function unit internal table 113 and the RTO function unit internal table 123, and transfer can be realized by distinguishing each reference destination.

3.3) Data Transfer Processing Next, IO access communication between EPs will be described with reference to FIGS. In this system, control information is synchronized as a trigger for data transfer between EPs.

  In FIG. 6, first, when an IO access communication request is generated between an EP (Device # p) and an EP (Device # q), the CPU 201 inter-EP communication control device corresponding to each of the transmission source and transfer destination EPs. A special message request is transmitted to e2eSW # p and the inter-EP communication control device e2eSW # q to make a transfer start request (step 401).

  When this transfer start request is received, the control unit 105 of each inter-EP communication control device e2eSW synchronizes table information with the CPU 201 (step 402). That is, when the control unit 105 receives control information from the CPU 201 and stores it in the table 113 of the RTI function unit 103 and the table 123 of the RTO function unit 104, the control unit 105 notifies the synchronization completion by returning the response. Since the current PCI-SIG standard does not stipulate what is directly commanded between EPs as a transaction, this system shall send a message request as a packet specific to this system.

  By performing table synchronization between the CPU and each e2eSW, a mesh structure associating VF in each EP as shown in FIG. 7 is constructed. That is, the correspondence relationship between the transmission source address and transmission source VF and the transfer destination address and transfer destination VF in FIG. 5 is established.

  When the table synchronization is completed in this way, the control unit 105 of the inter-EP communication control device e2eSW # p as the transmission source controls the transmission unit 122 to transmit a transfer request to the corresponding VF of EP (Device # p) (step 403). When the EP (Device # p) receives the transfer request for the target VF, the EP (Device # p) performs burst transfer of the data to the inter-EP communication control device e2eSW # p (step 404).

  When data is received from the EP (Device # p) through the port 102, the receiving unit 110 of the inter-EP communication control device e2eSW # p saves the received data in the memory 111. Subsequently, the transmission unit 112 refers to the table information of the table 113, operates the device driver used in the transfer destination EP (Device # q), and confirms the transfer destination address, the BDF of the transfer destination VF, and the like. The header portion of the data packet is rewritten to the transfer destination address of the inter-EP communication control device e2eSW # q, and is sent from the PCIe port 101 to the PCIe switch 204 (step 405).

  The receiving unit 120 of the inter-EP communication control device e2eSW # q that has received the packet from the PCIe switch 204 saves the received data in the memory 121. Subsequently, when the transmission unit 122 refers to the table 123 and confirms that the destination address of the reception data and the transfer destination address of the table 123 match the VF existing under its own, the transmission unit 122 stores the data in EP ( Step 406) of transferring to Device # q). When the Tendo is completed in this manner, the inter-EP communication control device e2eSW # p sends a transfer completion notification to the CPU 201 (step 407).

4). Effects As described above, according to the present embodiment, the CPU 201 sends an inter-EP transfer start request (message request) to the corresponding inter-EP communication control device, and thereby, between the CPU 201 and the inter-EP communication control device. Thus, if the table information is synchronized, direct IO access between the EPs becomes possible, and data transfer can be performed without intervention of the CPU. As a result, the load on the CPU can be reduced.

  Also, by using SR-IOV compatible EPs, multiple EPs can directly access one EP, and the processing speed of EPs can be expected to improve.

5. Other Embodiments As shown in FIG. 8, an IO access communication system according to another embodiment of the present invention has the same basic configuration as the embodiment shown in FIG. 2, but includes an inter-EP communication control device e2eSW. An EP (Device) can be designed as the PCIe board 501. In this case, it is possible to realize inter-IO communication by the number of expansion PCIe slots 502 installed in an existing server.

  In the embodiment shown in FIG. 6, the completion of the synchronization of the control information triggered by the message request from the CPU is a trigger that causes the IO access between the EPs, but after the synchronization of the CPU and the control table is performed. A message request from the CPU can also be used as a trigger for IO access between EPs.

  Further, as shown in FIG. 5, only the information that is the target of the IO access communication between the EPs is held as a table, but not only the target to perform the IO access but all the EPs existing in the IO access communication system It is also possible to synchronize all the information of the VFs and transfer data between the corresponding inter-EP communication control devices only when there is a data transfer command from the CPU as a trigger.

  The present invention is applicable to a communication system using PCI Express.

100 Inter-EP communication controller (e2eSW)
101 PCIe port 102 Port 103 connected to EP 103 RTI (Routing to Inside) function unit 104 RTO (Routing to Outside) function unit 105 Control unit 110 Reception unit 111 Memory 112 Transmission unit 113 Table 120 Reception unit 121 Memory 122 Transmission unit 123 Table 201 CPU
202 Route Complex (RC)
203 Memory 204 PCIe switch 205-p Communication control device between EPs (e2eSW # p)
205-q Inter-EP communication controller (e2eSW # q)
206-p EP (Device # p)
206-q EP (Device # q)

Claims (21)

An apparatus for performing endpoint communication control in a communication system using a high-speed serial interface,
A first port for communicating with lower endpoints;
A second port for communicating with a host communication device;
Control means for performing synchronization processing of control information that correlates at least endpoints that are targets of IO access with the general-purpose control unit of the communication system,
A first transfer means for referring to the control information, executing a process for transferring data received from the first port to a transfer destination endpoint, and sending the data through the second port;
A second transfer means for referring to the control information, executing a process for transferring the data received from the second port to a transfer destination endpoint, and sending the data through the first port;
An inter-endpoint communication control apparatus characterized by comprising: The first transfer means includes
A first table storing the control information including at least address mapping information of an endpoint subject to IO access and a BDF (Bus Device Function) number;
First receiving means for receiving data from the first port;
A first transmission means for referring to the first table and executing processing for transferring the received data to a destination endpoint and sending it through the second port;
The inter-endpoint communication control device according to claim 1, comprising:   The control information further includes device driver information used by an endpoint that is a target of IO access, and the first transmission unit performs data transfer processing by selecting a device driver corresponding to the transfer destination endpoint. The inter-endpoint communication control apparatus according to claim 2, wherein the inter-endpoint communication control apparatus is characterized. The second transfer means includes
A second table for storing the control information including at least address mapping information of an endpoint subject to IO access and a BDF (Bus Device Function) number;
Second receiving means for receiving data from the second port;
A second transmission means for referring to the second table and executing the process for transferring the received data to a destination endpoint and sending it through the first port;
The inter-endpoint communication control apparatus according to any one of claims 1 to 3, further comprising:   5. The inter-endpoint communication according to claim 1, wherein the control information further includes information related to a virtual function (VF) set in the end point targeted for the IO access. 6. Control device.   A lower-order endpoint is connected to the first port of the inter-endpoint communication control device according to any one of claims 1 to 5, a switch of the communication system is connected to the second port, and the switch A communication system, wherein the general-purpose control unit is connected via a root complex.   The inter-endpoint communication control apparatus according to any one of claims 1 to 5, and an IO device connected as a lower endpoint to the first port are integrally configured, and the second port is an expansion PCI Express A PCI Express board that can be connected to a slot. A communication control method between endpoints in a communication system using a high-speed serial interface in which a plurality of communication devices are hierarchically connected from a general-purpose control unit to a plurality of endpoints,
The control means executes a synchronization process of control information that correlates at least the endpoints that are the targets of IO access with the general-purpose control unit,
When a transfer start request is received from the general-purpose control unit as a transmission source, the first transfer unit refers to the control information and performs processing for transferring data received from a lower-order endpoint to a transfer destination endpoint. Execute and send to the higher-level communication device,
When a transfer start request is received as a transfer destination from the general-purpose control unit, the second transfer means executes processing for transferring the data received from the higher-level communication device to the transfer destination endpoint, and the transfer destination To the endpoint of
An inter-endpoint communication control method characterized by comprising: The first transfer means includes
The control information including at least the address mapping information of the endpoint subject to IO access and the BDF (Bus Device Function) number is stored in the first table,
Receive data from lower endpoints,
Referring to the first table, a process for transferring the received data to a transfer destination endpoint is executed and transmitted to a higher-level communication device.
The inter-endpoint communication control method according to claim 8.   The control information further includes device driver information used by an endpoint that is an IO access target, and the first transfer unit selects a device driver corresponding to the transfer destination endpoint and performs data transfer processing. The inter-endpoint communication control method according to claim 9, wherein: The second transfer means includes
Storing the control information including at least the address mapping information and BDF (Bus Device Function) number of the endpoint subject to IO access in the second table;
Receiving data from the higher-level communication device;
Referring to the second table, the process for transferring the received data to the transfer destination endpoint is executed and transmitted to the transfer destination endpoint.
The inter-endpoint communication control method according to any one of claims 8 to 10.   The inter-endpoint communication according to any one of claims 8 to 11, wherein the control information further includes information related to a virtual function (VF) set in an end point that is a target of the IO access. Control method.   When the control means receives the transfer start request, the control means executes a synchronization process of the control information, and the first transfer means or the second transfer means starts the transfer process triggered by the end of the synchronization process. The inter-endpoint communication control method according to any one of claims 8-12.   9. The first transfer unit or the second transfer unit starts transfer processing with a transfer start request from the general-purpose control unit as a trigger after the control information synchronization processing by the control unit ends. The inter-endpoint communication control method according to any one of -12. A program for causing a program control processor to function as a communication control device between endpoints in a communication system using a high-speed serial interface in which a plurality of communication devices are hierarchically connected from a general-purpose control unit to a plurality of endpoints,
Execute synchronization processing of control information that correlates at least the endpoints that are the targets of IO access with the general-purpose control unit,
When a transfer start request is received from the general-purpose control unit as a transmission source, the first transfer unit refers to the control information and performs processing for transferring data received from a lower-order endpoint to a transfer destination endpoint. Execute and send to the higher-level communication device,
When a transfer start request is received as a transfer destination from the general-purpose control unit, the second transfer means executes processing for transferring the data received from the higher-level communication device to the transfer destination endpoint, and the transfer destination To the endpoint of
A program for causing the program control processor to function as described above. The first transfer means is
The control information including at least the address mapping information of the endpoint subject to IO access and the BDF (Bus Device Function) number is stored in the first table,
Receive data from lower endpoints,
Referring to the first table, a process for transferring the received data to a transfer destination endpoint is executed and transmitted to a higher-level communication device.
The program according to claim 15, wherein the program control processor functions as described above.   The control information further includes device driver information used by an endpoint that is an IO access target, and the first transfer unit selects a device driver corresponding to the transfer destination endpoint and performs data transfer processing. The program according to claim 16, characterized in that: The second transfer means comprises:
Storing the control information including at least the address mapping information and BDF (Bus Device Function) number of the endpoint subject to IO access in the second table;
Receiving data from the higher-level communication device;
Referring to the second table, the process for transferring the received data to the transfer destination endpoint is executed and transmitted to the transfer destination endpoint.
The program according to any one of claims 15 to 17, wherein the program control processor is caused to function as described above.   The program according to any one of claims 15 to 18, wherein the control information further includes information on a virtual function (VF) set in an endpoint that is a target of the IO access.   When the transfer start request is received, the control information synchronization process is executed, and the program control processor functions so that the first transfer means or the second transfer means starts the transfer process triggered by the end of the synchronization process. The program according to any one of claims 15 to 19, characterized by that.   20. The transfer process according to claim 15, wherein the first transfer unit or the second transfer unit starts the transfer process by using a transfer start request from the general-purpose control unit as a trigger after the control information synchronization process ends. The program according to item 1.

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