WO2014054345A1 - Semiconductor device - Google Patents

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a reconfigurable semiconductor device and its error detection method.

FPGA (Field Programmable Gate)
PLD (Programmable Logic Device) whose circuit configuration can be reconfigured is widely used (for example, Patent Document 1 below). The applicant or inventor realizes a circuit configuration with a memory “MPLD (Memory
Research and development of “Basic Programmable Logic Devices” (registered trademark). MPLD is shown, for example, in Patent Document 2 below. MPLD is a memory function, LUT (Look)
It is composed of an MLUT (Multi Look Up Table) having all of the Up Table function and the switching function, and the MLUTs are arranged in an array and interconnected to realize a function substantially equivalent to the FPGA.

Also, the MPLD is a device in which the logic area and the wiring area are made flexible by using the MLUT as both a logic element and a wiring element, and is different from an FPGA having a switching circuit dedicated for connection between memories.

Responding to soft errors caused by cosmic rays and noise has become an important issue in FPGAs where semiconductor miniaturization is progressing. In contrast to hard errors where the memory cells do not function permanently, they are termed soft errors because incorrect information in the memory cells can be corrected by reprogramming. A soft error in the configuration information memory composed of the FPGA volatile memory may change the operation of the FPGA from the original operation and become a serious problem. Therefore, as a method for detecting a soft error, a programmable device including an ECC unit for detecting an error by storing bits for error checking in addition to configuration data in a memory cell and periodically reading out the data. Is disclosed (Patent Document 3 below).

US Pat. No. 5,815,726 JP 2009-194676 A JP 2007-293856 A

However, the proposed FPGA error detection unit is periodically checked for soft errors. Therefore, in the disclosed technique, an error is detected when a soft error check is periodically performed after an error occurs, so that the error cannot be detected simultaneously with the occurrence of the error. For this reason, the semiconductor device performs an operation process on the data in which an error has occurred, so that it is not robust.

A semiconductor device according to an embodiment of the present invention aims to improve the robustness of a semiconductor device by detecting a data error when outputting data.

The form to solve the above-mentioned problems is as described in the following items.

1. A reconfigurable semiconductor device comprising:
A truth table for outputting a logical operation of input values specified by a plurality of addresses to a data line, comprising a plurality of storage units constituting an array and connected to each other by address lines or data lines. Stores data, operates as a logic circuit, and / or stores truth table data for outputting an input value specified by a certain address to a data line connected to an address of another storage unit Configured to operate as a connection circuit,
The storage unit
A plurality of memory cells holding the truth table data and error check bits of the truth table data;
First data constituting a part of the truth table data, and an error detection unit that reads a first error check bit of the first data and determines whether or not an error has occurred in the first data. A reconfigurable semiconductor device characterized by comprising:
The semiconductor device improves the robustness of the semiconductor device by detecting a data error when outputting data.
2. The reconfigurable semiconductor device according to item 1, wherein the storage unit further includes an error correction unit that corrects and outputs an error bit detected by the error detection unit.
The semiconductor device continues normal operation of the semiconductor device by correcting and outputting the error bit.
3. The error check bit is a redundant bit,
The reconfigurable semiconductor device according to item 1 or 2, wherein the error detection unit decodes the first data and the first error check bit to determine whether an error has occurred in the first data.
4). The reconfigurable semiconductor device according to item 3, wherein the storage unit includes at least three or more data lines.
In the FPGA, the number of output bits is 1 or 2. For this reason, if an attempt is made to provide a redundant bit in the memory for error detection, the redundant bit is larger than the configuration data, and the memory capacity is doubled. On the other hand, the semiconductor device according to the present embodiment is greatly different from the FPGA in that it has multiple outputs including at least three data lines. Therefore, the relative increase in the memory area can be restricted, and the cost increase can be suppressed. As a result, error detection or correction in the storage unit becomes possible. 5. 5. The reconfigurable semiconductor device according to any one of items 1 to 4, wherein the storage unit includes a stage register that holds data output from the error detection unit and operates in synchronization with a clock.
Although the latency is increased by error detection or correction, the throughput can be increased by performing pipeline processing by synchronizing the reading.
6). The semiconductor device includes:
6. The reconfigurable semiconductor device according to any one of items 1 to 5, further comprising an error output unit that receives an error signal from each of the storage units and outputs an error as an error output signal.
By simply reporting the error to the outside rather than detecting or correcting the error, the semiconductor device can be maintained.
7). The semiconductor device includes:
6. The reconfigurable semiconductor device according to any one of items 1 to 5, further comprising an error output unit that receives an error signal from each storage unit and encodes the error signal to identify a storage unit in which an error has occurred. .
By specifying a storage unit in which an error has occurred, prohibiting the use of the storage unit can increase the robustness of the reconfigurable semiconductor device.
Item 8. 8. The reconfigurable semiconductor device according to any one of items 1 to 7, wherein the memory element of the memory cell is a phase change film.
The resistance value of the phase change film may vary for each memory cell. This is because even if the phase is changed from high resistance to low resistance, the high resistance remains, so that the error detection unit is suitable for a memory cell using a phase change film.
9. An error detection method in a reconfigurable semiconductor device, wherein the semiconductor device includes a plurality of storage units that form an array and are connected to each other by address lines or data lines, and the storage unit includes truth table data and A plurality of memory cells that hold error check bits of the truth table data, and the storage section outputs truth table data for outputting a logical operation of input values specified by a plurality of addresses to a data line. Storing truth table data for operating as a logic circuit and / or outputting an input value specified by a certain address to a data line connected to an address of another storage unit; Configured to operate as a connection circuit,
Read out the first truth table data of the truth table data and the first error check bit of the first truth table data;
An error detection method comprising: determining whether an error has occurred in the first truth table data.
10. 10. The error detection method according to item 9, further comprising correcting and outputting an error bit detected by the error detection unit.
11. The error check bit is a redundant bit,
Item 11. The error detection method according to Item 9 or 10, wherein the first truth table data and the first error check bit are decoded to determine whether an error has occurred in the first truth table data.
12 Item 12. The error detection method according to any one of Items 9 to 11, which holds data to be output and operates in synchronization with a clock.
13. Item 13. The error detection method according to any one of Items 9 to 12, wherein an error signal is received from each of the storage units and an error is output by outputting the error signal to the outside.
14 Item 13. The error detection method according to any one of Items 9 to 12, wherein an error signal is received from each storage unit, and the error signal is encoded to identify a storage unit in which an error has occurred.
15. 15. The error detection method according to any one of items 9 to 14, wherein the memory element of the memory cell is a phase change film.

In the semiconductor device according to the embodiment of the present invention, since each storage unit includes an error detection unit, error detection is performed when data is output from the storage unit, so that the robustness of the semiconductor device can be improved.

It is a figure which shows the 1st example of the whole structure of the semiconductor device which concerns on this embodiment. It is a figure which shows an example of an MLUT array. It is a figure which shows an example of MLUT concerning this embodiment. It is a figure which shows an example of a Hamming code. It is a figure which shows an example of a memory cell array. It is a figure which shows an example of MLUT with ATD. It is a figure which shows an example of the error detection flow of MLUT. 1 is a cross-sectional view of a memory cell according to one embodiment. It is a figure which shows an example of the variation in resistance value of a phase change film. It is a figure which shows an example of a memory cell circuit. It is a figure which shows an example of MLUT which operate | moves as a logical element. It is a figure which shows an example of MLUT which operate | moves as a logic circuit. It is a figure which shows the truth table of the logic circuit shown in FIG. It is a figure which shows an example of MLUT which operate | moves as a connection element. It is a figure which shows the truth table of the connection element shown in FIG. It is a figure which shows an example of the connection element implement | achieved by MLUT which has four AD pairs. It is a figure which shows an example in which one MLUT operates as a logic element and a connection element. FIG. 17 shows a truth table of logic elements and connection elements shown in FIG. 16. FIG. It is a figure which shows an example of the logic operation | movement implement | achieved by MLUT which has AD pair, and a connection element.

Hereinafter, with reference to the drawings, [1] MPLD, [2] MLUT, [3] MLUT error detection flow, [4] MLUT using PRAM, and [5] MLUT logical operation according to this embodiment These will be described in order.

[1] MPLD
FIG. 1 is a diagram illustrating an example of the overall configuration of the semiconductor device according to the present embodiment. An MPLD is a device having almost the same function as an FPGA, but its structure is different. The FPGA is configured by an LUT, a switch block, a connection block, and the like, and the ratio of logical resources and wiring resources is fixed. On the other hand, the MPLD has a configuration in which elements that can be used as both logic elements and wiring elements called MLUTs are arranged. With this configuration, it is possible to increase the ratio of the logic region in the entire area.

1 is an MPLD as a reconfigurable semiconductor device. The MPLD 20 includes an MLUT array 60 in which a plurality of MLUTs 30 as storage units are arranged in an array, a row decoder 12 that identifies a memory read operation and a write operation of the MLUT 30, a column decoder 14, and an error output unit 62.

MLUT 30 is composed of a memory. The MLUT 30 performs a logical operation that operates as a logical element, a connection element, or a logical element and a connection element by storing data regarded as a truth table in the storage element of the memory.

In the logic operation of the MPLD 20, a logic address LA indicated by a solid line and a signal of logic data LD are used. The logic address LA is used as an input signal for the logic circuit. The logic data LD is used as an output signal of the logic circuit. The logic address LA of the MLUT 30 is connected to the data line of the logic operation data LD of the adjacent MLUT.

The logic realized by the logic operation of the MPLD 20 is realized by truth table data stored in the MLUT 30. Some MLUTs 30 operate as logic elements as combinational circuits such as AND circuits and adders. The other MLUTs operate as connection elements that connect the MLUTs 30 that realize the combinational circuit. Rewriting of truth table data for the MLUT 20 to realize a logical element and a connection element is performed by a write operation to the memory.

The write operation of the MPLD 20 is performed by the write address AD and the write data WD, and the read operation is performed by the write address AD and the read data RD.

The write address AD is an address that identifies a memory cell in the MLUT 20. The write address AD is m signal lines and specifies 2 to the number M of memory cells. The MLUT decoder 12 receives the MLUT address via the m signal lines, decodes the MLUT address, and selects and specifies the MLUT 30 that is the target of the memory operation. The memory operation address is used in both the memory read operation and the write operation, and is decoded by the decoders 12 and 14 through m signal lines to select a target memory cell. In this embodiment, as will be described later, the logical operation address LA is decoded by a decoder in the MLUT.

The row decoder 12 decodes x bits of m bits of the write address AD in accordance with control signals such as a read enable signal RE and a write enable signal WE, and outputs a decoded address n to the MLUT 30. The decode address n is used as an address for specifying a memory cell in the MLUT 30.

The column decoder 14 decodes y bits of the m bits of the write address AD, has the same function as the row decoder 12, outputs the decode address n to the MLUT 30, and writes the write data WD. And the read data RD are input.

If the MLUT array has s rows and t columns, n × t-bit data is input from the MLUT array 60 to the decoder 14. Here, in order to select the MLUT for each row, the row decoder outputs re and we for o rows. That is, the o line corresponds to the s line of the MLUT. Here, a word line of a specific memory cell is selected by activating only one bit out of the o bits. Since t MLUTs output n-bit data, n × t-bit data is selected from the MLUT array 60, and the decoder 14 is used to select one column.

In this embodiment, n + α is used as write data. n is used as truth table data, and α is an error check bit used for error detection. The error check bit may be generated outside the MPLD 30.

The error output unit 62 receives the error flag EF output from the MLUT 30, and outputs an error signal ES that simply causes an error to the MPLD, or outputs an error signal EM that identifies the MLUT in which the error has occurred. When the error output unit 62 outputs the error signal ES without specifying the MLUT, the error output unit 62 is an OR circuit that performs a sum operation on the error flags from each MLUT. When the error output unit 62 outputs an error signal ES that identifies the MLUT in which an error has occurred, an encoder circuit is provided. When specifying a plurality of MLUTs having errors, the error output unit becomes a shift circuit, and shifts out a bitmap specifying the error MLUT from the signal ES.

FIG. 2 is a diagram illustrating an example of an MLUT array. The MLUT array 30 is configured by arranging the MLUTs 30 in an array as shown in the figure. The memory used as the MLUT 30 has the same address line width and data line width. As shown in the upper right of FIG. 2, a pseudo bidirectional line is defined by pairing each bit of the address line and the data line. This pseudo bidirectional line is called “AD pair” in MPLD. By using a memory whose address line width and data line width are N bits, an MLUT having N AD pairs is realized. The operation as the logic of the MPLD is realized by regarding the data written in the memory constituting the MLUT 30 as a truth table. Therefore, the MLUT may receive a soft error against cosmic rays and noise.

[2] MLUT
The MLUT according to the present embodiment will be described with reference to FIGS. FIG. 3 is a diagram illustrating an example of the MLUT according to the present embodiment. The MLUT 30 includes a memory cell array 110, an address decoder 120, an error detection unit 70, a multiplexer 72, an error correction unit 73, registers 71 and 74, and a demultiplexer 76. The multiplexer 72 selects a logic address input LA and a write address AD in accordance with a mode selection signal mode for selecting a logic operation and a write operation.

Note that the register 74 may be a stage register synchronized with an external clock. Thereby, pipeline processing can be performed. For example, the decoder, read / write, and ECC operations are asynchronous with the external clock, and only the register 74 is synchronized with the external clock to generate a pipeline, thereby improving the throughput.

The demultiplexer 76 outputs an input signal as either the logic operation data LD or the write address AD in accordance with the mode selection signal mode. The address decoder 120 decodes an address signal received from n address signal lines, and outputs a word line selection signal, which is a decode signal, to 2 n word lines.

The error detection unit 70 reads out data constituting the part of the truth table data and the error check bit from the memory cell array 110, and determines whether or not an error has occurred in the read data. After the determination, the error detection unit 70 outputs an error detection signal as an error flag EF and outputs data to the subsequent stage. The error detection unit 73 decodes the read data and one error check bit, and determines the occurrence of an error in the read data. In the present embodiment, the MLUT 30 may include only the error detection unit 70 or may include both the error detection unit 70 and the error correction unit 73.

Since MPLD is composed of logic cells composed of fine memory using N-bit address lines and N-bit data lines, it is possible to uniquely determine the logic output for the logic input. Therefore, error detection correction (ECC: Error Correction Codes) can be applied, and even if the configuration information in MPLD becomes unhealthy due to a hard error or a soft error, the logical output can be corrected by ECC.

Error detection and correction In this embodiment, a Hamming code is used as the ECC. The Hamming code is one of linear error correction codes that can detect and correct data errors. In general, a Hamming code is composed of the following equations 1 and 2 for a certain integer m.

Code length: n = 2 ^m −1 Equation 1
Number of information: k = n−m Equation 2

Here, the number of information is the number of bits of the original data, and the code length is the number of bits of the generated code. When m = 3, n = 7 and k = 4, and a Hamming code is formed by replacing a 4-bit bit string with a 7-bit code word. This case is referred to as a (7, 4) Hamming code. The Hamming code is processed using two matrices called a check matrix and a generator matrix. Note that all additions used in each matrix calculation are exclusive ORs. First, the check matrix will be described. This matrix is a matrix of m rows and n columns, and there is a condition that all column elements are not zero and are different. An example of the check matrix H of the (7, 4) Hamming code is shown below. An example of the check matrix H of the (7, 4) Hamming code is shown below.

Next, the generator matrix will be described. The generator matrix G is a non-zero matrix that satisfies the condition of Equation 3 below.
HG ^T = GH ^T = 0... Equation 3
Here, GT represents a transposed matrix of G. In the case of a systematic code, G is expressed by the following Equation 4.
G = [I _k A ^T ] Equation 4
G with respect to H shown in the above example is as follows.

In encoding encoding, a generator matrix G and data to be transmitted m1. . . Multiply with mk. Let us consider a case where bit sequence 1011 is encoded using G taken up in the previous example as a generator matrix. The code generated at this time is “1011100”.

In error correction, decoding error correction, and decoding, decoding is performed by obtaining the product of the check matrix H and the received data. Assume that received data Y is received. At this time, if there is no error in Y, it can be said that Y = xG. Here, x is a bit string before encoding. When the product of the transposed matrix of Y and H is obtained, Expression 5 is obtained from the relational expression of H and G.
Y · H ^T = x (G · H ^T ) = 0 0 Formula 5
That is, if the product of the received word and the check matrix is a zero vector, there is no error, and if it is non-zero, an error is included. Further, the error vector e _i is expressed by the following Equation 6.
Y · H ^T = e _i · H ^T Equation 6
Here, e _i, here i th bit and e _i is 1, the other bits are zero bits. Here, since ei is 1 only for the i-th bit, the i-th column of H is output. Therefore, the position of the error is detected by comparing with which column of the output this H matches, and the error can be corrected by inverting the bit of that portion.

As an example, it is assumed that the above code word is transmitted and 1111100 is received. This received data includes an error in 1111100, and this data is decoded. The product of the received data and the transposed matrix of H is as follows.

If there is no error, it becomes a zero vector, but an error has occurred, so it does not become a zero vector. If this output is transposed, it can be seen that it is the same value as the second column of H. Therefore, the error is in the second column, and when the bit in the second column is inverted, it becomes 1011100, which indicates that the original codeword has been corrected. In this way, errors can be corrected.

FIG. 4 is a diagram illustrating an example of a Hamming code. When m is an integer indicating a redundant bit (arbitrary), n is a code length, and k is the number of information (original data), the Hamming code has the relationship shown in the table shown in FIG. When k is 7 bits, encoding is performed with m = 4, 11−7 = 4 bits is assumed to be (1111) _2, and 11 bits of 7 + 4 (redundant bits) are held in the memory. An error can be detected by adding (1111) ₂ in the ECC circuit 70 and comparing with 15 bits.

By doing in this way, the error detection unit 70 can decode the code bit generated by adding the redundant bit, and if it is not a zero vector, can detect an error as an error vector. Furthermore, as described in Equation 6 above, the bit in which an error has occurred can be identified from the H shift matrix corresponding to the error vector. The error correction unit 73 can output data of a corrected bit string by inverting the error bit specified in this way and outputting it.

The input data to the memory cell unit is (n + α) bits. Of the input data, n bits are used as data (corresponding to k in FIG. 4), and α is an error check bit. For example, α is a redundant bit generated by Hamming coding or the like for n bits. The generation of redundant bits as described above is performed by processing outside the MPLD. For example, when 7 bits are output data, 4 bits are generated as redundant bits by Hamming encoding.

FIG. 5 is a diagram illustrating an example of a memory cell array. The memory cell array 110 includes a memory cell area that holds redundant bits and a memory cell area that holds data. Compared with the normal memory cell area shown in FIG. 5, the memory area is expanded by the redundant bits. However, as shown in FIG. 4, the number of redundant bits is small compared to the increase in the number of information, but it can be seen that the number of redundant bits is relatively large when the number of information is small. In other words, the expansion of the memory area by redundant bits is not suitable for small input and small output as the configuration information of the FPGA is used when realizing a logic circuit, and at least the data output bit as in MLUT. It can be seen that this is effective for a memory whose number exceeds 3 bits. In this way, since the MLUT has multiple inputs and multiple outputs, even if the ECC circuit 70 is provided in each MLUT, it is possible to suppress an increase in cost.

The error detection unit 70 detects an error by performing a decoding process as described in the example of FIG. If there is no match between the decoded data and the data read from the memory, an error detection signal is output as an error flag EF, and an error corrected signal is output as output data. In this way, the error detection unit 70 performs error check on the data output from the memory cell array by ECC, and the data output here becomes the data output of the MLUT. By adopting such a configuration, even when a soft error occurs in the memory cell array constituting the MLUT, the MLUT can perform a correct operation.

By performing error detection or correction in units of MLUTs, completeness can be improved in the same manner as an FPGA in which CRC (Cyclic Redundancy Check) or TMR (Triple Modulation Redundancy) is implemented. In TMR, the circuit scale increases three times, whereas MLUT can detect or correct errors in a small area. Further, the error receiving unit 62 shown in FIG. 1 receives the error flag EF output from each MLUT and externally outputs the error flag EF, so that it does not suddenly fail in the dependable system but fails and does not move. A system that warns that the time is near can be realized. Thus, when an error is detected, rewiring is performed avoiding the error MLUT, and a margin for replacing the chip is given to the user, so that a truly dependable MPLD system can be constructed.

FIG. 6 is a diagram showing an example of MLUT with ATD. The MLUT 30A with ATD shown in FIG. 6 includes an ATD circuit (Address Transition Detect) 121 as an address change detector in the address decoder 120. The ATD circuit is a circuit that is provided at an address input terminal, detects a change in an address input signal applied to the address input terminal, and outputs the changed address signal.

The ATD circuit outputs the changed address signal to the address decoder 120A only when the change of the address signal is detected. Therefore, the address decoder 120A outputs the word selection signal only when the address signal changes, and the address signal changes. If not, the word line selection signal is not output. In this way, when there is no address change, the word line selection signal is not output, so that a write malfunction due to disturbance noise can be prevented.

This can increase the robustness against soft errors. Although an example of the Hamming method has been described here as an error correction method, the present invention is not limited to this.

[3] MLUT Error Detection Flow Next, an example of an MLUT error detection flow will be described with reference to FIG. First, from the memory cell specified by the decoder 120, the error detection unit 70 reads data and error check bits constituting a part of the truth table data (S101). Next, the error detection unit 70 determines whether an error has occurred in the read data (S102). If no error is detected (NO in S102), the error detection unit 70 outputs the read data as it is to the subsequent circuit (S103). When an error is detected (YES in S102), the error detection unit outputs an error flag EF to the error output unit 62 (S104). The error output unit 62 receives the error flag EF output from the MLUT 30, and outputs an error signal ES that simply reports an error or an error signal EM that identifies an MLUT that has generated an error to the outside (S105). The error correction unit 73 corrects and outputs the error bit detected by the error detection unit 70 (S106).

[4] MLUT using PRAM
FIG. 8A is a cross-sectional view of a memory cell according to one embodiment. The memory element of the memory cell is composed of a phase change film layer 41. In the present embodiment, the phase change film layer 41 is made of germanium, antimony, and tellurium (hereinafter, “GST”), which are compound thin films. The phase change film 41 is hereinafter referred to as “GST”. An upper electrode 43 is provided on the upper surface of the phase change film layer 41, and a lower electrode 45 and an insulating layer 47 are provided on the lower surface. The upper electrode 43 is, for example, aluminum, the insulating layer 47 is, for example, silicon dioxide, and the lower electrode 45 is a through electrode made of, for example, TI / TINX / AL. A semiconductor circuit layer 50 is further provided below the lower electrode 45. When a current flows between the upper electrode 43 and the lower electrode 45, the phase change film layer 41 changes its phase to crystalline or amorphous, and the resistance value changes accordingly. When the phase change film layer 41 is heated above the melting temperature and rapidly cooled, an amorphous phase (high resistance) is obtained. When the phase change film layer 41 is heated above a certain temperature and gradually cooled, a crystalline phase (low resistance) is obtained. The phase change film layer 41 stores and holds as a storage element of the memory cell by making the state potential at the time of reading caused by the difference in resistance value correspond to 0/1 of the signal. In FIG. 8A, the upper electrode 43 and the phase change film 41 cover the entire surface of the chip except for the external electrode portion, and are not patterned.

The phase change region 48 is a region that changes from an amorphous phase to a crystalline phase. Since the phase change film layer 41 above the insulating layer 47 is initially in a high-resistance amorphous phase, the phase change regions 48 are prevented from being short-circuited. Phase change film layer 41 uses a part of the phase change film as a memory cell storage element. Conventionally, the PRAM has been realized with a configuration that insulates and protects the phase change material. However, since the phase change film layer 41 according to the present embodiment does not need to insulate and protect the phase change material, the manufacturing process can be simplified. I can plan.

FIG. 8B is a diagram illustrating an example of variation in the resistance value of the phase change film. In this configuration, since the phase change film layer 41 is not patterned, the sizes of the phase change regions 48A to 48C differ depending on the voltage applied to the upper electrode 43 and the lower electrode 45. As a result, the resistance value of the phase change film varies.

As shown in FIG. 8B, in the one-side film formation, the size of the phase change region 48 changes depending on the applied voltage, and the resistance value of the phase change varies, so that the circuit reads the data with a certain high resistance or low resistance. If it is designed, it may not work properly. In addition, because of the structure, in order to obtain heat necessary for the phase change, a certain write voltage (VDD_W) is required, and at the time of reading, the reading must be performed at a reading voltage (VDD_R) that does not cause the phase change. . In consideration of the above restrictions, the memory cells of the memory cell array 110 are configured.

FIG. 9 is a diagram illustrating an example of a memory cell circuit. The memory cell 40 shown in FIG. 9 includes five transistors and GST. Specifically, one PMOS (POSITIVE CHANNEL METAL OXIDE SEMICONDUCTOR) transistor 161 and four NMOS (NEGAIVE CHANNEL METAL OXIDE SEMICONDUCTOR). The transistors 162 to 165 and the GST 166 that is a resistor formed of a part of the phase change film layer 41 are included. When the GST 166 is an array, they can be connected to each other in common.

The GST 166 is constituted by a part of the phase change film layer 41, that is, the phase change film layer 41 on the upper part of the lower electrode 45 shown in FIG. The phase change film layer 41 changes to crystalline or amorphous, and the resistance value changes accordingly, so that the GST 166 functions as a memory element that maintains a state of “0” or “1”.

The source of the PMOS 161 is connected to VDD (power supply voltage terminal), and the source of the NMOS 162 is connected to VSS (ground voltage terminal). The PMOS 161 and the NMOS 162 operate as a CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR) inverter by connecting the respective drains. The CMOS inverter senses the signal level output according to the state held in GST 166 and outputs it to read data line RDATA via NMOS transistor 163.

The NMOS transistor 163 has a gate connected to the read word line R_ROW. When a signal from the read word line R_ROW is applied to the gate, the NMOS transistor 163 outputs a state signal of GST166 sensed by the CMOS inverter. As described above, the single-side film formation may cause variations in the initial resistance value in the manufacturing process. The NMOS transistor 165 has a gate connected to the GST 166 and a source connected to the low bias BIAS_L. By applying the voltage VDD_M of the medium bias BIAS_M to the gate, the conductance is adjusted, thereby the resistance of the GST 166 in the read operation. Reduce the variation of values. Then, the output of the state signal of GST166 is sensed by the CMOS inverter, and the voltage is amplified.

The low bias BIAS_L is a voltage for raising the division voltage when dividing the voltage of the NMOS transistor 165 of the GST 166 and bringing the central value of the voltage division to the threshold value of the CMOS inverter constituted by the PMOS 161 and the NMOS 162. .

The data line voltage control unit 142 which is a peripheral circuit is two inverters 181 and 182 for inverting input / output, and is provided on the write data line WDATA and the read data line RDATA. At the time of the writing process, the write data WDATA is converted to the inverted signal / WDATA by the inverter, so that the VSS is generated by the inverter when the write data WDATA is “1”, and writing to the GST 166 is performed. In this way, the voltage of the selected write data line WDATA is lowered to VSS during the write process.

The phase change film voltage control unit 150 is connected to all the GSTs 166 in the memory cell array. During the write process, the supply voltage (WR_VDD) to all the GSTs 166 in the memory cell array is changed to the write voltage (VDD_W), and during the read process, the supply voltage to the GST 166 is changed to the read voltage (VDD_R).

The voltage of the write data line WDATA is lowered by the data line voltage control unit 142 during the write operation. NMOS transistor 164 has a gate connected to write word line W_ROW, and when a signal from write word line W_ROW is applied to the gate, write data line WDATA and GST 166 are electrically connected. In the write operation, since the write voltage (VDD_W) higher than the read voltage (VDD_R) is applied to the GST 166 at the same time when the voltage of the write data line WDATA drops, a voltage that causes a phase change is applied to the GST 166. .

As described above, when a phase change memory is used for a memory cell, even in the same chip, the resistance value varies for each memory cell, so that stable writing cannot be performed. For example, even if the resistance is changed from high resistance to low resistance, if writing fails with high resistance, a problem such as inability to detect occurs. Even when such a hard error occurs, the MLUT according to the present embodiment can continue normal operation and identify the MLUT in which a failure has occurred by correcting the error.

[5] Logic operation of MLUT Logical Element FIG. 10 is a diagram illustrating an example of an MLUT that operates as a logical element. The MLUT shown in FIG. 10 is a circuit similar to the MLUT shown in FIG. 11 or the semiconductor memory device shown in FIG. In FIG. 10, the description of the address switching circuit 10A and the output data switching circuit 10B is omitted for the sake of simplicity. The MLUTs 30A and 30B shown in FIG. 10 include four logic address input LA lines A0 to A3, four logic operation data lines D0 to D3, 4 × 16 = 64 storage elements 40, and an address decoder 9. Respectively. The logic operation data lines D0 to D3 connect 24 memory elements 40 in series, respectively. The address decoder 9 is configured to select four storage elements connected to any of the 16 word lines based on signals input to the logic address input LA lines A0 to A3. These four storage elements are connected to logic operation data lines D0 to D3, respectively, and output data stored in the storage elements to logic operation data lines D0 to D3. For example, when an appropriate signal is input to the logical address input LA lines A0 to A3, the four storage elements 40A, 40B, 40C, and 40D can be selected. Here, the storage element 40A is connected to the logic operation data line D0, the storage element 40B is connected to the logic operation data line D1, and the storage element 40D is connected to the logic operation data line D2. 40D is connected to the logic operation data line D3. Then, signals stored in the storage elements 40A to 40D are output to the logic operation data lines D0 to D3. As described above, the MLUTs 30A and 30B receive the logical address input LA from the logical address input LA lines A0 to A3, and values stored in the four storage elements 40 selected by the address decoder 9 based on the logical address input LA. Are output as logic operation data to the logic operation data lines D0 to D3, respectively. The logical address input LA line A2 of the MLUT 30A is connected to the logical operation data line D0 of the adjacent MLUT 30B, and the MLUT 30A receives the logical operation data output from the MLUT 30B as the logical address input LA. . The logic operation data line D2 of the MLUT 30A is connected to the logic address input LA line A0 of the MLUT 30B, and the logic operation data output from the MLUT 30A is received by the MLUT 30B as the logic address input LA. For example, the logic operation data line D2 of the MLUT 30A is one of 16 storage elements connected to the logic operation data line D2 based on signals input to the logic address inputs LA lines A0 to A3 of the MLUT 30A. The signal stored in one is output to the logic address input LAA0 of the MLUT 30B. Similarly, the logic operation data line D0 of the MLUT 30B is one of 16 storage elements connected to the logic operation data line D0 based on signals input to the logic address input LA lines A0 to A3 of the MLUT 30B. The signal stored in one is output to the logic address input LAA2 of the MLUT 30A. As described above, the MPLDs are connected by using a pair of address lines and data lines. Hereinafter, a pair of address lines and data lines used for MLUT connection, such as the logic address input LA line A2 of the MLUT 30A and the logic operation data line D2, is referred to as an “AD pair”.

In FIG. 10, the MLUTs 30A and 30B have 4 AD pairs, but the number of AD pairs is not limited to 4 as will be described later.

FIG. 11 is a diagram illustrating an example of an MLUT that operates as a logic circuit. In this example, the logical address input LA lines A0 and A1 are input to the two-input NOR circuit 701, and the logical address input LA lines A2 and A3 are input to the two-input NAND circuit 702. Then, the output of the 2-input NOR circuit and the output of the 2-input NAND circuit 702 are input to the 2-input NAND circuit 703, and a logic circuit is configured to output the output of the 2-input NAND circuit 703 to the logic operation data line D0. .

FIG. 12 is a diagram showing a truth table of the logic circuit shown in FIG. Since the logic circuit of FIG. 11 has four inputs, all the inputs A0 to A3 are used as inputs. On the other hand, since there is only one output, only the output D0 is used as an output. “*” Is written in the columns of outputs D1 to D3 of the truth table. This indicates that any value of “0” or “1” may be used. However, when the truth table data is actually written into the MLUT for reconstruction, it is necessary to write either “0” or “1” in these fields.

B. Connection Element FIG. 13 is a diagram illustrating an example of an MLUT that operates as a connection element. In FIG. 13, the MLUT as a connection element outputs the signal of the logic address input LA line A0 to the logic operation data line D1, and outputs the signal of the logic address input LA line A1 to the logic operation data line D2. The logic address input LA line A2 operates to output the signal to the logic operation data line D3. The MLUT as the connection element further operates to output the signal of the logic address input LA line A3 to the logic operation data line D1.

FIG. 14 is a diagram showing a truth table of the connection elements shown in FIG. The connection element shown in FIG. 13 has 4 inputs and 4 outputs. Therefore, all inputs A0-A3 and all outputs D0-D3 are used. According to the truth table shown in FIG. 14, the MLUT outputs the signal of the input A0 to the output D1, outputs the signal of the input A1 to the output D2, outputs the signal of the input A2 to the output D3, and outputs the signal of the input A3. It operates as a connection element that outputs to the output D0.

FIG. 15 is a diagram illustrating an example of a connection element realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3. AD0 has a logic address input LA line A0 and a logic operation data line D0. AD1 has a logic address input LA line A1 and a logic operation data line D1. AD2 has a logic address input LA line A2 and a logic operation data line D2. AD3 has a logic address input LA line A3 and a logic operation data line D3. In FIG. 15, a one-dot chain line indicates a signal flow in which a signal input to the AD pair 0 logic address input LA line A0 is output to the AD pair 1 logic operation data line D1. A two-dot chain line indicates a signal flow in which a signal input to the logic address input LA line A1 of the second AD pair 1 is output to the logic operation data line D2 of the AD pair 2. A broken line indicates a signal flow in which a signal input to the logic address input LA line A2 of the AD pair 2 is output to the logic operation data line D3 of the AD pair 3. A solid line indicates a flow of a signal that is input to the logic address input LA line A3 of the AD pair 3 and is output to the logic operation data line D0 of the AD pair 0.

In FIG. 15, the MLUT 30 has 4 AD pairs, but the number of AD pairs is not particularly limited to 4.

C. Combination Function of Logic Element and Connection Element FIG. 16 is a diagram illustrating an example in which one MLUT operates as a logic element and a connection element. In the example shown in FIG. 16, the logical address input LA lines A 0 and A 1 are input to the 2-input NOR circuit 121, and the output of the 2-input NOR circuit 121 and the logical address input LA line A 2 are connected to the 2-input NAND circuit 122. A logic circuit is provided that inputs and outputs the output of the 2-input NAND circuit 122 to the logic operation data line D0. At the same time, a connection element for outputting the signal of the logic address input LA line A3 to the logic operation data line D2 is formed.

FIG. 17 shows a truth table of the logic elements and connection elements shown in FIG. The logic operation of FIG. 16 uses three inputs D0 to D3 and uses one output D0 as an output. On the other hand, the connection element in FIG. 17 is a connection element that outputs the signal of the input A3 to the output D2.

FIG. 18 is a diagram illustrating an example of logical operations and connection elements realized by an MLUT having four AD pairs of AD0, AD1, AD2, and AD3. Similarly to the MLUT shown in FIG. 15, AD0 has a logic address input LA line A0 and a logic operation data line D0. AD1 has a logic address input LA line A1 and a logic operation data line D1. AD2 has a logic address input LA line A2 and a logic operation data line D2. AD3 has a logic address input LA line A3 and a logic operation data line D3. As described above, the MLUT 30 realizes two operations, ie, a logic operation with three inputs and one output and a connection element with one input and one output, with one MLUT 30. More specifically, the logic operation is performed by using the logic address input LA line A0 of AD pair 0, the logic address input LA line A1 of AD pair 1 and the logic address input LA line A2 of AD pair 2 as inputs. use. Then, the address line of the logic operation data line D0 of AD pair 0 is used as an output. Further, the connection element outputs a signal input to the logic address input LA line A3 of the AD pair 3 to the logic operation data line D2 of the AD pair 2 as indicated by a broken line.

As described above, since the MLUTs in the MPLD are connected to each other via a plurality of address lines, an operation in which external noise is written to the memory cell via the word selection signal is likely to occur. Therefore, since there is an ATD circuit in the MLUT, writing to the memory cell is performed only when the address changes, so that it is possible to avoid an erroneous operation due to external noise.

The embodiments described above are merely given as typical examples, and combinations, modifications, and variations of the components of each embodiment will be apparent to those skilled in the art, and those skilled in the art will understand the principles and claims of the present invention. Obviously, various modifications may be made to the embodiments described above without departing from the scope of the described invention.

Claims (15)

A reconfigurable semiconductor device comprising:
A truth table for outputting a logical operation of input values specified by a plurality of addresses to a data line, comprising a plurality of storage units constituting an array and connected to each other by address lines or data lines. Truth table data configured to store data, operate as a logic circuit, and / or output an input value specified by an address to a data line connected to an address of another storage unit Configured to operate as a connection circuit,
The storage unit
A plurality of memory cells holding the truth table data and error check bits of the truth table data;
First data constituting a part of the truth table data, and an error detection unit that reads a first error check bit of the first data and determines whether or not an error has occurred in the first data. A reconfigurable semiconductor device characterized by comprising: The reconfigurable semiconductor device according to claim 1, wherein the storage unit further includes an error correction unit that corrects and outputs an error bit detected by the error detection unit. The error check bit is a redundant bit,
The reconfigurable semiconductor device according to claim 1, wherein the error detection unit decodes the first data and the first error check bit to determine whether an error has occurred in the first data. 4. The reconfigurable semiconductor device according to claim 3, wherein the storage unit includes at least three or more data lines. The reconfigurable semiconductor device according to any one of claims 1 to 4, wherein the storage unit includes a stage register that holds data output from the error detection unit and operates in synchronization with a clock. . The reconfigurable semiconductor device according to any one of claims 1 to 5, further comprising an error output unit that receives an error signal from each storage unit and outputs an error signal to the outside. 6. The reconfigurable semiconductor device according to claim 1, further comprising an error output unit that receives an error signal from each of the storage units and encodes the error signal to identify a storage unit in which an error has occurred. apparatus.
By specifying a storage unit in which an error has occurred, prohibiting the use of the storage unit can increase the robustness of the reconfigurable semiconductor device. The reconfigurable semiconductor device according to any one of claims 1 to 7, wherein the memory element of the memory cell is a phase change film. An error detection method in a reconfigurable semiconductor device, wherein the semiconductor device includes a plurality of storage units that form an array and are connected to each other by address lines or data lines, and the storage unit includes truth table data and A plurality of memory cells that hold error check bits of the truth table data, and the storage section outputs truth table data for outputting a logical operation of input values specified by a plurality of addresses to a data line. Storing truth table data for operating as a logic circuit and / or outputting an input value specified by a certain address to a data line connected to an address of another storage unit; Configured to operate as a connection circuit,
Read out the first truth table data of the truth table data and the first error check bit of the first truth table data;
An error detection method comprising: determining whether an error has occurred in the first truth table data. The error detection method according to claim 9, further comprising correcting and outputting an error bit detected by the error detection unit. The error check bit is a redundant bit,
The error detection method according to claim 9 or 10, wherein the first truth table data and the first error check bit are decoded to determine whether an error has occurred in the first truth table data. The error detection method according to any one of claims 9 to 11, wherein the output data is held and operated in synchronization with a clock. The error detection method according to any one of claims 9 to 12, wherein an error signal is received from each of the storage units, and an error is output by outputting the error signal to the outside. 13. The error detection method according to claim 9, wherein an error signal is received from each of the storage units, and the error signal is encoded to identify a storage unit in which an error has occurred. 15. The error detection method according to claim 9, wherein the memory element of the memory cell is a phase change film.

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