Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3674—Details of drivers for scan electrodes
  • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/04—Structural and physical details of display devices
  • G09G2300/0439—Pixel structures
  • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness

Definitions

• the present invention relates to the field of liquid crystal display, and more particularly to a gate driving circuit, a driving method, and a liquid crystal display system.
• the liquid crystal display system includes a scan line, a data line, and a thin film transistor, and the scan line is connected to the gate of the thin film transistor; the data line is connected to the source of the thin film transistor.
• the number of scanning lines and data lines of a liquid crystal display system constitutes the resolution of the liquid crystal display system. Taking a product with a resolution of MxN as an example, a single gate driving mode, an output line of a panel gate (panel) The number of gate fanouts and source fanouts are N and 3M, respectively.
• the product requires N/a gate control chip (gate IC) and 3M b Source control chip (source IC).
• the invention patent CN101707047A discloses a driving circuit for saving the number of gate chips on May 12, 2010.
• the invention provides a driving circuit for saving the number of gate chips, which is located in the gate chip and the scanning line in the liquid crystal panel.
• a set of driving circuits is added between the two, and the number of gate chips of the liquid crystal panel under the double gate structure is kept the same as that of the single gate structure.
• the driving circuit capable of saving the number of gate chips is more cost-effective than the prior art, and the driving circuit is used to make each scanning line
• the high-level signal is ended, a low-level signal is received to make the signal status of each scan line clearer.
• the interlocking design is required between the first and third control switches, which greatly limits the number of controllable scanning lines, so that one output line (fanout) can only correspond to two scanning lines, A low-cost way to flexibly configure the number of scan lines that can be controlled on one output line.
• the technical problem to be solved by the present invention is to provide a gate driving circuit, a driving method, and a liquid crystal display system which can further reduce the number of gate control chips and facilitate the design of a narrow bezel.
• a gate driving circuit includes a gate control chip and a scan line, and each output line of the gate control chip is connected with at least three controllable switches to control three or more scan lines, and each of the controllable switches The connection controls one scan line.
• the gate driving circuit further includes at least three control lines, and the controllable switches corresponding to the output lines of each of the gate control chips share the control lines, and the control ends of each of the controllable switches are respectively connected to one The control line. Therefore, assuming that each output line has N controllable switches, only N control lines need to be set. It is not necessary to separately design a drive for each controllable switch of each output line, and the control mode is greatly simplified.
• the other end of the scan line connected to the controllable switch is further connected with a controllable reset switch, the other end of the reset switch is connected to a low potential signal, and the controllable switch and the reset switch are independently controlled.
• the controllable switch connected to the same scan line is alternately turned on between the reset switch and the reset switch.
• the corresponding reset switch When the current scan line is driven, the corresponding reset switch remains in an off state, and the scan line is in a high state; at this time, other scan lines corresponding to the same output line need to be kept in a low state, and therefore, the scan lines correspond to
• the reset switch is in an on state, and a low level signal is introduced into the corresponding scan line, so that even if the controllable switch malfunctions, the corresponding scan line can be forced to remain at a low potential state, thereby improving the reliability of the drive system; Furthermore, by connecting the scan line to the low level signal through the reset switch, the scan line can be quickly switched from a high potential to a low potential, thereby improving the response speed of the drive.
• the gate driving circuit further includes at least three reset control lines and a common low potential line, and the control ends of each of the reset switches are respectively connected to one of the reset control lines, and each of the reset switches The other end is connected to a common low potential line, and the reset switch corresponding to the output line of each gate control chip shares the common low potential line.
• This is a specific implementation of a reset switch, the same vertical
• the reset switch corresponding to the controllable switch of the column can share a reset control line. Therefore, assuming that each output line has N reset switches, only N reset control lines need to be set, and there is no need for each of the output lines separately.
• the reset switch is designed separately and the control mode is greatly enlarged.
• each output line of the gate control chip is connected with a first controllable switch, a second controllable switch, and a third controllable switch;
• the gate drive circuit further includes a first control line, and a second a control line connected to the first control line, the control end of the second controllable switch is connected to the second control line, and the third controllable switch is connected to the second control line
• the control terminal is connected to the third control line.
• the other end of the scan line connected to the controllable switch is further connected with a controllable reset switch, and the other end of the reset switch is connected to a low potential signal.
• a controllable reset switch is added to improve driving reliability and response speed.
• the gate driving circuit further includes at least three reset control lines and a common low potential line, and the control ends of each of the reset switches are respectively connected to one of the reset control lines, and each of the reset switches The other end is connected to the common low potential line.
• This is a specific implementation of the reset switch.
• the reset switch corresponding to the controllable switch of the same column can share a reset control line. Therefore, it is assumed that each output line has N reset switches, and only N reset control lines need to be set. That is, there is no need to separately design a drive for each reset switch of each output line, and the control method is greatly simplified.
• controllable switch is a thin film transistor.
• the use of a thin film transistor as a controllable switch can be formed simultaneously in the fabrication of a thin film transistor of an array substrate without adding an additional process, which is advantageous in reducing the manufacturing cost.
• a driving method of the above gate driving circuit comprises the following steps:
• Each output line of the gate control chip sequentially outputs a high level, and at least three scanning intervals are continued.
• the other end of the scan line connected to the controllable switch is further connected with a controllable reset switch.
• the other end of the reset switch is connected to the low potential signal, and the step B further includes: when the current controllable switch is turned on, the reset switch of the same scan line is turned off; when the current controllable switch is turned off, controlling the reset of the same scan line The switch is turned on.
• the corresponding reset switch When the current scan line is driven, the corresponding reset switch remains in an off state, and the scan line is in a high state; at this time, other scan lines corresponding to the same output line need to be kept in a low state, and therefore, the scan lines correspond to
• the reset switch is in an on state, and a low level signal is introduced into the corresponding scan line, so that even if the controllable switch malfunctions, the corresponding scan line can be forced to remain at a low potential state, thereby improving the reliability of the drive system; Furthermore, by connecting the scan line to the low level signal through the reset switch, the scan line can be quickly switched from a high potential to a low potential, thereby improving the response speed of the drive.
• a liquid crystal display system comprising the above-described gate driving circuit.
• At least three controllable switches are connected to each output line of the gate control chip, and each controllable switch controls one scan line, so that one output line can correspond to more than three scan lines, so that the scan line is fixed.
• the number of output lines is further reduced, thereby reducing the number of gate drive ICs and reducing the cost; at the same time, the reduction of the output lines also reduces the space occupation, and the space of the circuit board area on the gate control side of the liquid crystal panel is saved for the narrow bezel design. It is beneficial to realize the narrow bezel design of the liquid crystal panel.
• the number of scan lines corresponding to one output line can be flexibly controlled, thus implementing a plurality of different configurations in a single implementation manner, thereby reducing development costs.
• 1 is a conventional scanning line and data line driving method
• Figure 2 is a schematic view of an embodiment of the present invention.
• 100 liquid crystal pixel
• 200 controllable switch
• 300 reset switch
• 400 scan line
• 500 data line
• 600 control line
• 700 reset control line
• a liquid crystal display system includes a liquid crystal panel and a backlight module at the bottom of the liquid crystal panel.
• the liquid crystal panel includes a plurality of liquid crystal pixels 100 and a vertical and horizontal interlaced scan line 400 and a data line 500.
• Each liquid crystal pixel 100 includes a pixel electrode and a thin film transistor connected to the pixel electrode, the gate of the thin film transistor being connected to the scan line 400; and the source thereof being connected to the data line 500.
• a gate driving circuit includes a gate control chip and a scan line 400. Each of the output lines of the gate control chip is connected with at least three controllable switches 200, and each of the controllable switches 200 is connected to one scan line. 400.
• the controllable switch 200 can be controlled by the control line 600, that is, the control end of each controllable switch 200 is respectively connected to one control line 600, and the controllable switch 200 corresponding to different output lines is located at the same column position,
• One control line 600 can be shared, such that one output line corresponds to N scanning lines 400, and only N control lines 600 are required.
• the other end of the scanning line 400 connected to the controllable switch 200 may be connected to a controllable reset switch 300, and the other end of the reset switch 300 is connected to a low potential signal.
• the corresponding reset switch 300 remains in an off state, and the scan line 400 is in a high state; at this time, the other scan lines 400 corresponding to the same output line need to be kept in a low state, therefore, these
• the reset switch 300 corresponding to the scan line 400 is in an on state, and a low level signal is introduced into the corresponding scan line 400, so that even if the controllable switch 200 malfunctions, the corresponding scan line 400 can be forced to remain at a low potential.
• the state improves the reliability of the driving system. Further, by connecting the scanning line 400 to the low level signal through the reset switch 300, the scanning line 400 can be quickly switched from a high potential to a low potential, thereby improving the response speed of the driving.
• the reset switch 300 can also adopt a control mode similar to the control switch, and set the same number of reset control lines 700 as the control line 600.
• the control terminals of each reset switch 300 are respectively connected to one of the reset control lines 700, and a common public can be set.
• the lower potential line, the other end of each reset switch 300 is connected to the common potential line.
• controllable switches 200 are connected to each output line of the gate control chip as an example to further explain the concept of the present invention.
• a set of controllable switches 200 are placed on the liquid crystal panel as a panel gate input, each The three controllable switches 200 within the group control the signal inputs of the three scan lines 400, respectively. And use the controllable switch 200 at the gate output end with a special signal input method to realize the scanning signal on and off line by line.
• GI_1, GI_2, and GI_3 are control lines 600, Gl_l, Gl_2, Gl_3, G2_l, G2_2, and G2_3 are scan lines 400; Dl, D2, Dn-1, and Dn are data lines 500; G03, G02 GO1 is the reset control line 700; Vgl is the common low potential line.
• GI_1, GI_2, and GI_3 respectively input high/low voltage and switch with time, that is, GI_1 inputs high level (H) at T1, GI_2 and GI_3 inputs low level (L), and T2 GI_1 and GI_3 input L, G, I_2 input H, T3, GI_1 and GI_2 input L, GI_3 input H.
• GI_1 inputs H GOl inputs L, G02 and G03 inputs H.
• G02 input GOl and G03 input H.
• G03 inputs GOl and G02 input H.
• Vgl keeps input L.
• Gl ⁇ Gn is the gate output line (Gate fanout)
• G03 input H Vgl maintains the L voltage.
• GI_1 Since GI_1 inputs H, the signal of G1 can be sent to Gl_l, and the TFT corresponding to Gl_l is turned on. At this time, G01 input is L, so the signal of Vgl will not be sent to Gl_l. At the same time, the input of GI_2 and GI_3 is L, so the H signal of G1 cannot be sent to Gl_2 and Gl_3, the input of G02 and G03 is H, and the L signal of Vgl is sent to Gl_2 and Gl_3.
• the G2 input is L. Since the GI_1 input is H, its L voltage can be fed into G2_l, and the G02 and G03 inputs are H. The Vgl L signal can be sent to G2_2 and G2_3.
• the scan line 400 corresponding to G3 ⁇ Gn is similar to the above.
• the signal of Gl can be sent to Gl_2, and the TFT corresponding to Gl_2 is turned on.
• the G02 input is L, so the signal of Vgl is not sent to Gl_2.
• the input of GI_1 and GI_3 is L, so the H signal of G1 cannot be sent to Gl_l and Gl_3, G01 and G03.
• the input is H, and the L signal of Vgl is sent to Gl_l and Gl_3.
• the G2 input is L. Since the GI_2 input is H, its L voltage can be fed into G2_2, and the G01 and G03 inputs are H. The Vgl L signal can be sent to G2_l and G2_3.
• the scan line 400 corresponding to G3 ⁇ Gn is similar to the above.
• GI_3 input H, GI_1 and GI_2 input L, Gl input H, G2 ⁇ Gate Gn input L, G03 input L, GOl and G02 input H, Vgl maintain L voltage.
• GI_3 Since GI_3 inputs H, the signal of Gl can be sent to Gl_3, and the TFT corresponding to Gl_3 is turned on. At this time, G03 input is L, so the signal of Vgl will not be sent to Gl_3. At the same time, the input of GI_1 and GI_2 is L, so the H signal of G1 cannot be sent to Gl_l and Gl_2, the input of G01 and G02 is H, and the L signal of Vgl is sent to Gl_l and Gl_2.
• the G2 input is L. Since the GI_3 input is H, its L voltage can be fed into G2_3, and the G01 and G02 inputs are H. The Vgl L signal can be sent to G2_l and G2_2.
• the scan line 400 corresponding to G3 ⁇ Gn is similar to the above.
• the panel with the new structure and the designed signal timing can realize the sequential opening and closing of the scanning line 400, and can only reduce the number of output lines of the original 1/3 of the gate to reduce the cost of the IC. effect. It is also possible to achieve such a driving effect by adding more controllable switches 200, for example, increasing the number of controllable switches 200 to four five or more, and only need to reduce the gate according to the above driving method. The purpose of the output line.

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• Crystallography & Structural Chemistry (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)

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• 2012
  • 2012-02-16 CN CN2012100341647A patent/CN102543028A/zh active Pending
  • 2012-04-05 WO PCT/CN2012/073515 patent/WO2013120310A1/fr not_active Ceased

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