Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
  • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/6733—Multi-gate TFTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
  • G02F1/1362—Active matrix addressed cells
  • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
  • G02F1/1362—Active matrix addressed cells
  • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
  • G02F1/13685—Top gates

Definitions

• Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
• a multi-gate structure or a doped structure can be used in order to reduce the off-state current Ioff. Since the multi-gate structure lowers the pixel aperture ratio, a thin film transistor of a doped structure is used.
• An embodiment of the present invention provides an array substrate, including: a substrate; a first active layer and a second active layer disposed on the substrate, one end of the first active layer and the second One end of the source layer is connected; a gate electrode and a gate line connected to the gate electrode are respectively disposed above the first active layer and above the second active layer, the first active layer a region not covered by the gate electrode and a region on the second active layer not covered by the gate line are formed as a doped region as an ohmic contact region; a drain connected to the ohmic contact region Provided above the first active layer; a data line and a source vertically crossing the gate line, disposed above the second active layer; and a pixel electrode connected to the drain And disposed on an area surrounded by the gate line and the data line.
• Another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.
• a further embodiment of the present invention provides a method of fabricating an array substrate, including: forming a first active layer and a second active layer on a substrate, one end of the first active layer and the second active Layered Connecting at one end; forming a gate electrode over the first active layer, forming a gate line connected to the gate electrode over the second active layer; not being on the first active layer a region covered by the gate electrode and a region on the second active layer not covered by the gate line form an ohmic contact region; forming a source and a drain connected to the ohmic contact region and the gate a data line connecting the polar line and connected to the source, the drain being above the first active layer, the source and the data line being above the second active layer; A pixel electrode connected to the drain is formed on a region where the gate line and the data line intersect.
• FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present invention.
• Figure 2 is a cross-sectional view taken along line A1-A2 of Figure 1. detailed description
• FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present invention
• FIG. 2 is a cross-sectional view taken along line A1-A2 of FIG.
• An array substrate and a method of fabricating the same according to an embodiment of the present invention will now be described with reference to FIGS. 1 and 2.
• the embodiment of the invention provides a method for fabricating an array substrate, which comprises the following steps Sl l-S15.
• a first polysilicon island 301 and a second polysilicon island 302 are formed on the substrate 20, and one end of the first polysilicon island 301 and the second polysilicon island 302 are formed. Connected at one end.
• the first polysilicon island 301 and the second polysilicon island 302 are both elongated, and the extending direction of the first polysilicon island 301 is different from the extending direction of the second polysilicon island 302.
• the extending directions of the first polysilicon island 301 and the second polysilicon island are perpendicular to each other, but the present invention The embodiment is not limited to this.
• step S11 may include, for example, the following steps A1-A3:
• a buffer layer 25 is formed on the substrate 20.
• the buffer layer 25 can be formed by deposition, coating, or the like.
• the substrate 20 may be a glass substrate or a quartz substrate; the material of the buffer layer 25 may be SiO 2 , SiN x or SiON x or the like.
• the buffer layer may have a thickness of from 100 nm to 300 nm.
• the buffer layer functions to prevent metal or other ions in the substrate from contaminating the amorphous silicon layer formed on the upper surface of the substrate, and also protect the substrate during the laser annealing process on the amorphous silicon layer to prevent temperature High damage to the substrate;
• a polysilicon layer is formed on the buffer layer 25.
• a polysilicon layer can be formed by deposition, coating, or the like.
• step A2 may include the following process:
• the amorphous silicon layer may have a thickness of 300 nm to 800 nm; converting the amorphous silicon layer into a polysilicon layer; for example, a laser annealing technique, an induced crystallization technique, or the like may be used.
• the crystalline silicon layer is converted into a polysilicon layer.
• the polysilicon layer is formed into a first polysilicon island 301 and a second polysilicon island 302 by a patterning process, and one end of the first polysilicon island 301 is connected to one end of the second polysilicon island 302 (refer to FIG. 1). And Figure 2);
• the patterning process may be an exposure etch process, or a patterning process such as printing or web printing may be used to directly form the final desired film pattern.
• a gate electrode 50 is formed over the first polysilicon island 301, and a gate line 55 connected to the gate electrode 50 is formed over the second polysilicon island 302.
• Step S12 may include, for example, the following steps B1-B3:
• the gate insulating layer 45 may be formed by deposition, coating, or the like;
• the thickness of the gate insulating layer 45 may be 100 nm to 200 nm; the material of the gate insulating layer 45 may be SiO 2 , SiN x or SiON x ;
• the gate metal layer may be formed by magnetron sputtering, deposition, or the like; the gate metal layer may have a thickness of 300 nm to 500 nm; B3, forming a gate electrode 50 and a gate line 55 connected to each other by using a gate metal layer (refer to FIG. 2, FIG. 3);
• the gate electrode 50 and the gate line 55 are formed by a patterning process; the gate electrode 50 and the gate line 55 are overlapped with the first polysilicon island 301 and the second polysilicon island 302, respectively, thereby forming a multi-gate structure. , the effect of reducing the off-state current Ioff of the switching element is achieved.
• step S13 may include the following process:
• the doped region That is, the ohmic contact region 30b; the undoped region under the gate metal layer is the channel 30a; the doping ions described in the ion doping process may be N+ ion doped or P+ ion doped.
• a drain 80a and a source 80b connected to the ohmic contact region 30b and a data line 60 crossing the gate line 55 and connected to the drain 80b are formed.
• the drain 80a is located above the first polysilicon island 301, and the source 80b and the data line 60 are located above the second polysilicon island 302.
• a drain 80a is formed over one end of the first polysilicon island 301, and a source 80b is formed at one end of the second polysilicon island 302.
• the gate electrode formed over the first polysilicon island 301 is located at one end of the first polysilicon island 301 forming the drain 80a and the connection end of the first polysilicon island 301 and the second polysilicon island 302
• the gate line formed over the second polysilicon island 302 is located at one end of the second polysilicon island 302 forming the source 80b and the first polysilicon island 301 is connected to the second polysilicon island 302. Between the ends.
• step S14 may include the following steps C1-C4:
• interlayer insulating layer 70 forming an interlayer insulating layer 70 over the gate electrode 50 and the gate line 55, the interlayer insulating layer covering the entire substrate; for example, the interlayer insulating layer 70 may be formed by deposition, coating, etc.; interlayer insulation The layer 70 may have a thickness of 100 nm to 300 nm;
• a first via hole 73a exposing the ohmic contact region 30b corresponding to the region of the drain electrode 80a and a second via hole 73b exposing the ohmic contact region 30b corresponding to the region of the source region 80b; for example, ⁇ Forming the above first via hole 73a and second via hole 73b by a patterning process;
• the forming method may be magnetron sputtering, deposition, etc.; for example, the data line metal layer may have a thickness of 300 nm to 500 nm;
• C4 a drain electrode 80a connected to the ohmic contact region 30b through the first via hole 73a is formed over the first polysilicon island 301 by a patterning process, and a second via hole is formed over the second polysilicon island 302.
• 73b is connected to the source 80b of the ohmic contact region 30b, and a data line 60 covering the second polysilicon island 302 and crossing the gate line 55 is formed over the second polysilicon island 302 (refer to FIG. 2, FIG. 3).
• the above data line 60, drain 80a and source 80b are formed by a patterning process.
• a pixel electrode 97 connected to the drain electrode 80a is formed, and the partial region is defined as a pixel region.
• the pixel electrode 97 partially overlaps the gate line 55, and the overlapping region forms a storage capacitor.
• step S15 may include the following steps D1-D4:
• a passivation layer 90 is formed over the drain electrode 80a and the source electrode 80b, and the passivation layer 90 covers the entire substrate.
• the formation method may be deposition, coating, etc.; for example, the passivation layer 90 may have a thickness of 3 ⁇ m;
• the material of the pixel electrode layer is, for example, indium tin oxide (ITO), indium oxide ( ⁇ ), etc. a material; for example, the pixel electrode layer may have a thickness of 5 nm to 150 nm;
• a pixel electrode 97 connected to the drain electrode 80a and connected to the gate line 55 through the third via 95 and the drain line 80a is formed on a region where the gate line 55 and the data line 60 are perpendicularly intersected by a patterning process (refer to FIG. 1 and Figure 2);
• the above-described pixel electrode 97 is formed by a patterning process.
• the array substrate display mode finally formed by the above-mentioned method for fabricating the array substrate is TN (Twisted Nematic) mode, and the present invention can also be used for preparing ADS (Advanced Super Dimension Switch).
• the array substrate of the display mode is prepared by forming a passivation layer over the pixel electrode 97 after forming the pixel electrode 97 by the above-described preparation method, and then forming a common electrode over the passivation layer, and finally An array substrate forming an ADS display mode.
• the gate and the gate line are designed over the two polysilicon islands, and the gate line is used as the second gate, so that the aperture ratio is not reduced.
• the multi-gate structure of the thin film transistor is formed to reduce the off-state current Ioff of the thin film transistor, and the use of the additional mask is removed while the Ioff is not increased and the aperture ratio is not lowered, thereby improving the extra in the prior art.
• the processing cost and processing time caused by the mask is wasted.
• the present invention also improves the disadvantages of prior art exposure alignment errors and doping structure shifts due to additional masks.
• the Ion reduction caused by the smaller W/L can be compensated by the high mobility of the LTPS because the refresh rate of the pixel voltage is much lower than the operating frequency of the peripheral circuit.
• W/L is the width to length ratio of the thin film transistor channel
• W is the channel width
• L is the channel length
• Ids ⁇ eff((8 ms 8 0 /t ms )(W/L)(Vgs-Vth)Vds,
• Ids (1/2) ⁇ eff ⁇ (8 ms 8o/t ms )(W/L)(Vgs-Vth) 2 ,
• ⁇ is the vacuum dielectric constant
• t ms is the thickness of the gate insulating layer
• ns is the relative dielectric constant of the gate insulating layer
• /t ms is the capacitance value of the gate insulating layer per unit area
• Vgs is the gate-source voltage
• Vds is the drain-source voltage
• Vth is the cutoff voltage
• ⁇ ⁇ is the equivalent carrier mobility.
• an embodiment of the present invention provides an array substrate, including:
• the upper surface of the substrate 20 (ie, the light-emitting surface of the substrate) has a buffer layer 25;
• the buffer layer 25 is provided with a first polysilicon island 301 and a second polysilicon island 302, and one end of the first polysilicon island 301 is connected to one end of the second polycrystalline silicon island 302;
• a gate electrode 50 is disposed above the first polysilicon island 301, and a gate line 55 connected to the gate electrode 50 is disposed above the second polysilicon island 302;
• a region of the first polysilicon island 301 not covered by the gate electrode 50 and a region of the second polysilicon island 302 not covered by the gate line 55 are doped regions as the ohmic contact region 30b;
• a drain 80a connected to the ohmic contact region 30b is disposed above the first polysilicon island 301, and a data line 60 and a source 80b perpendicularly intersecting the gate line 55 are disposed above the second polysilicon island 302; The region where the polar line 55 and the data line 60 are perpendicularly intersected is provided with the drain 80a and the gate The pixel electrode 97 connected to the pole line 55.
• a drain 80a is formed over one end of the first polysilicon island 301, and a source 80b is formed at one end of the second polysilicon island 302.
• the gate electrode formed over the first polysilicon island 301 is located at one end of the first polysilicon island 301 forming the drain 80a and the connection end of the first polysilicon island 301 and the second polysilicon island 302
• the gate line formed over the second polysilicon island 302 is located at one end of the second polysilicon island 302 forming the source 80b and the first polysilicon island 301 is connected to the second polysilicon island 302. Between the ends.
• the display mode of the array substrate is a TN mode.
• the embodiment of the present invention further provides an array substrate of an ADS display mode, which is configured to provide a passivation layer on the upper surface of the pixel electrode 97 of the array substrate of the TN mode.
• a common electrode is disposed on the upper surface of the passivation layer to finally form an array substrate structure of the ADS mode.
• a gate electrode and a gate line are designed over two polysilicon islands, and the gate line is skillfully used as a second gate electrode, thereby forming a thin film without reducing the aperture ratio.
• the multi-gate structure of the transistor achieves the effect of reducing the off-state current loff of the thin film transistor.
• the use of an additional mask is removed while the loff is not increased and the aperture ratio is not lowered, which improves the processing cost and processing time waste of the additional mask in the prior art.
• the present invention also improves the disadvantages of prior art exposure alignment errors and doping structure shifts due to additional masks.
• the polysilicon island is taken as an active layer as an example.
• the embodiment according to the present invention is not limited thereto.
• the material of the active layer in which the array substrate according to the embodiment of the present invention is fabricated may be amorphous silicon, an oxide semiconductor or any other suitable semiconductor material.
• first polysilicon island and the second polysilicon island extend perpendicular to each other as an example. However, they can also intersect at other angles. For example, the first polysilicon island is parallel to the gate line and the second polysilicon island is parallel to the data line.
• the embodiment of the present invention further provides a display device including the array substrate.
• the display device may be: a liquid crystal panel, a liquid crystal display, a liquid crystal television, an OLED display panel, an OLED display, an electronic paper, or the like.
• An array substrate comprising:
• Substrate a first active layer and a second active layer disposed on the substrate, one end of the first active layer being connected to one end of the second active layer;
• a drain connected to the ohmic contact region, disposed above the first active layer; a data line and a source vertically crossing the gate line, disposed above the second active layer; as well as
• a pixel electrode connected to the drain is provided on a region where the gate line and the data line intersect.
• a display device comprising the array substrate according to any one of (1) to (6).
• a method for fabricating an array substrate comprising:
• a pixel electrode connected to the drain is formed on a region where the gate line and the data line intersect.
• the active layer material is formed into the interconnected first active layer and second active layer by a patterning process.
• the gate metal layer is formed into interconnected gate electrodes and gate lines by a patterning process.
• the manufacturing method according to any one of (8), wherein the region on the first active layer not covered by the gate electrode and the second active layer are Forming an ohmic contact region on the layer that is not covered by the gate line includes:
• the manufacturing method includes: forming an interlayer insulating layer over the gate electrode and the gate line, the interlayer insulating layer covering the entire substrate;
• the pixel electrode connected to the gate line includes:
• a pixel electrode connected to the drain through the third via hole is formed on a region where the gate line and the data line are intersected by a patterning process.

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• 2012
  • 2012-05-04 CN CN201210138055.XA patent/CN102709240B/zh active Active
  • 2012-12-11 WO PCT/CN2012/086318 patent/WO2013163880A1/fr not_active Ceased

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