WO2013163880A1 - Array substrate, manufacturing method therefor and display device - Google Patents

Description

 Array substrate, manufacturing method thereof and display device

 Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique

 In the prior art, in the case of a thin film transistor device in a pixel region of a thin film transistor (TFT-LCD), in order to reduce the off-state current Ioff, a multi-gate structure or a doped structure can be used. Since the multi-gate structure lowers the pixel aperture ratio, a thin film transistor of a doped structure is used.

 In the prior art, when a pixel portion thin film transistor device is fabricated, a photoresist pattern layer needs to be formed through an additional mask. In the photolithography process, the doping structure is easily displaced due to alignment errors during exposure. Moreover, since an additional mask is required, the prior art is limited by the processing cost and processing time increase brought by one more photolithography process, and the problem of misalignment of the doping structure is easily generated. Summary of the invention

 An embodiment of the present invention provides an array substrate, including: a substrate; a first active layer and a second active layer disposed on the substrate, one end of the first active layer and the second One end of the source layer is connected; a gate electrode and a gate line connected to the gate electrode are respectively disposed above the first active layer and above the second active layer, the first active layer a region not covered by the gate electrode and a region on the second active layer not covered by the gate line are formed as a doped region as an ohmic contact region; a drain connected to the ohmic contact region Provided above the first active layer; a data line and a source vertically crossing the gate line, disposed above the second active layer; and a pixel electrode connected to the drain And disposed on an area surrounded by the gate line and the data line.

 Another embodiment of the present invention provides a display device comprising an array substrate according to any of the embodiments of the present invention.

A further embodiment of the present invention provides a method of fabricating an array substrate, including: forming a first active layer and a second active layer on a substrate, one end of the first active layer and the second active Layered Connecting at one end; forming a gate electrode over the first active layer, forming a gate line connected to the gate electrode over the second active layer; not being on the first active layer a region covered by the gate electrode and a region on the second active layer not covered by the gate line form an ohmic contact region; forming a source and a drain connected to the ohmic contact region and the gate a data line connecting the polar line and connected to the source, the drain being above the first active layer, the source and the data line being above the second active layer; A pixel electrode connected to the drain is formed on a region where the gate line and the data line intersect. DRAWINGS

 In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

 1 is a schematic plan view of an array substrate according to an embodiment of the present invention;

 Figure 2 is a cross-sectional view taken along line A1-A2 of Figure 1. detailed description

 The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

 1 is a schematic plan view of an array substrate according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A1-A2 of FIG. An array substrate and a method of fabricating the same according to an embodiment of the present invention will now be described with reference to FIGS. 1 and 2.

 The embodiment of the invention provides a method for fabricating an array substrate, which comprises the following steps Sl l-S15.

As shown in FIG. 1 and FIG. 2, a first polysilicon island 301 and a second polysilicon island 302 are formed on the substrate 20, and one end of the first polysilicon island 301 and the second polysilicon island 302 are formed. Connected at one end. For example, the first polysilicon island 301 and the second polysilicon island 302 are both elongated, and the extending direction of the first polysilicon island 301 is different from the extending direction of the second polysilicon island 302. In this embodiment, as shown in FIG. 1, the extending directions of the first polysilicon island 301 and the second polysilicon island are perpendicular to each other, but the present invention The embodiment is not limited to this.

 Specifically, step S11 may include, for example, the following steps A1-A3:

 Al, as shown in Fig. 2, a buffer layer 25 is formed on the substrate 20. For example, the buffer layer 25 can be formed by deposition, coating, or the like.

The substrate 20 may be a glass substrate or a quartz substrate; the material of the buffer layer 25 may be SiO ₂ , SiN _x or SiON _x or the like. The buffer layer may have a thickness of from 100 nm to 300 nm. The buffer layer functions to prevent metal or other ions in the substrate from contaminating the amorphous silicon layer formed on the upper surface of the substrate, and also protect the substrate during the laser annealing process on the amorphous silicon layer to prevent temperature High damage to the substrate;

 A2, a polysilicon layer is formed on the buffer layer 25. For example, a polysilicon layer can be formed by deposition, coating, or the like.

 For example, step A2 may include the following process:

 Forming an amorphous silicon layer on the buffer layer 25, the amorphous silicon layer may have a thickness of 300 nm to 800 nm; converting the amorphous silicon layer into a polysilicon layer; for example, a laser annealing technique, an induced crystallization technique, or the like may be used. The crystalline silicon layer is converted into a polysilicon layer.

 A3. The polysilicon layer is formed into a first polysilicon island 301 and a second polysilicon island 302 by a patterning process, and one end of the first polysilicon island 301 is connected to one end of the second polysilicon island 302 (refer to FIG. 1). And Figure 2);

 The patterning process may be an exposure etch process, or a patterning process such as printing or web printing may be used to directly form the final desired film pattern.

 S12, as shown in FIG. 3, a gate electrode 50 is formed over the first polysilicon island 301, and a gate line 55 connected to the gate electrode 50 is formed over the second polysilicon island 302.

 Step S12 may include, for example, the following steps B1-B3:

 Bl, forming a gate insulating layer 45 over the first polysilicon island 301 and the second polysilicon island 302, for example, the gate insulating layer 45 may be formed by deposition, coating, or the like;

The thickness of the gate insulating layer 45 may be 100 nm to 200 nm; the material of the gate insulating layer 45 may be SiO ₂ , SiN _x or SiON _x ;

 B2, forming a gate metal layer over the gate insulating layer 45;

For example, the gate metal layer may be formed by magnetron sputtering, deposition, or the like; the gate metal layer may have a thickness of 300 nm to 500 nm; B3, forming a gate electrode 50 and a gate line 55 connected to each other by using a gate metal layer (refer to FIG. 2, FIG. 3);

 The gate electrode 50 and the gate line 55 are formed by a patterning process; the gate electrode 50 and the gate line 55 are overlapped with the first polysilicon island 301 and the second polysilicon island 302, respectively, thereby forming a multi-gate structure. , the effect of reducing the off-state current Ioff of the switching element is achieved.

 513. Form an ohmic contact region 30b on a region of the first polysilicon island 301 that is not covered by the gate electrode 50 and a region of the second polysilicon island 302 that is not covered by the gate line 55.

 For example, step S13 may include the following process:

 Performing an ion doping process using the gate metal layer as a photomask to form a doped region on a region of the first polysilicon island 301 and the second polysilicon island 302 that is not covered by the gate metal layer, the doped region That is, the ohmic contact region 30b; the undoped region under the gate metal layer is the channel 30a; the doping ions described in the ion doping process may be N+ ion doped or P+ ion doped.

 514. As shown in FIGS. 1 and 2, a drain 80a and a source 80b connected to the ohmic contact region 30b and a data line 60 crossing the gate line 55 and connected to the drain 80b are formed. The drain 80a is located above the first polysilicon island 301, and the source 80b and the data line 60 are located above the second polysilicon island 302.

 In one embodiment, for example, as shown in FIGS. 1 and 2, a drain 80a is formed over one end of the first polysilicon island 301, and a source 80b is formed at one end of the second polysilicon island 302. Above, and the gate electrode formed over the first polysilicon island 301 is located at one end of the first polysilicon island 301 forming the drain 80a and the connection end of the first polysilicon island 301 and the second polysilicon island 302 The gate line formed over the second polysilicon island 302 is located at one end of the second polysilicon island 302 forming the source 80b and the first polysilicon island 301 is connected to the second polysilicon island 302. Between the ends.

 For example, step S14 may include the following steps C1-C4:

 Cl, forming an interlayer insulating layer 70 over the gate electrode 50 and the gate line 55, the interlayer insulating layer covering the entire substrate; for example, the interlayer insulating layer 70 may be formed by deposition, coating, etc.; interlayer insulation The layer 70 may have a thickness of 100 nm to 300 nm;

 C2, on the interlayer insulating layer 70, a first via hole 73a exposing the ohmic contact region 30b corresponding to the region of the drain electrode 80a and a second via hole 73b exposing the ohmic contact region 30b corresponding to the region of the source region 80b; for example, 釆Forming the above first via hole 73a and second via hole 73b by a patterning process;

C3, forming a data line metal layer on the interlayer insulating layer 70, the forming method may be magnetron sputtering, deposition, etc.; for example, the data line metal layer may have a thickness of 300 nm to 500 nm; C4, a drain electrode 80a connected to the ohmic contact region 30b through the first via hole 73a is formed over the first polysilicon island 301 by a patterning process, and a second via hole is formed over the second polysilicon island 302. 73b is connected to the source 80b of the ohmic contact region 30b, and a data line 60 covering the second polysilicon island 302 and crossing the gate line 55 is formed over the second polysilicon island 302 (refer to FIG. 2, FIG. 3).

 The above data line 60, drain 80a and source 80b are formed by a patterning process.

 S15, in a region surrounded by the intersection of the gate line 55 and the data line 60, a pixel electrode 97 connected to the drain electrode 80a is formed, and the partial region is defined as a pixel region.

 The pixel electrode 97 partially overlaps the gate line 55, and the overlapping region forms a storage capacitor.

 For example, step S15 may include the following steps D1-D4:

 D1, a passivation layer 90 is formed over the drain electrode 80a and the source electrode 80b, and the passivation layer 90 covers the entire substrate. The formation method may be deposition, coating, etc.; for example, the passivation layer 90 may have a thickness of 3 μm;

 D2, forming a third via 95 exposing the drain 80a on the passivation layer 90;

 Forming the above third via 95 by a patterning process;

 D3, forming a pixel electrode layer, for example, forming a pixel electrode layer by deposition or the like; the material of the pixel electrode layer is, for example, indium tin oxide (ITO), indium oxide (ΙΖΟ), etc. a material; for example, the pixel electrode layer may have a thickness of 5 nm to 150 nm;

 D4. A pixel electrode 97 connected to the drain electrode 80a and connected to the gate line 55 through the third via 95 and the drain line 80a is formed on a region where the gate line 55 and the data line 60 are perpendicularly intersected by a patterning process (refer to FIG. 1 and Figure 2);

 The above-described pixel electrode 97 is formed by a patterning process.

 The array substrate display mode finally formed by the above-mentioned method for fabricating the array substrate is TN (Twisted Nematic) mode, and the present invention can also be used for preparing ADS (Advanced Super Dimension Switch). The array substrate of the display mode is prepared by forming a passivation layer over the pixel electrode 97 after forming the pixel electrode 97 by the above-described preparation method, and then forming a common electrode over the passivation layer, and finally An array substrate forming an ADS display mode.

In the method for fabricating the array substrate provided by the embodiment of the present invention, the gate and the gate line are designed over the two polysilicon islands, and the gate line is used as the second gate, so that the aperture ratio is not reduced. The multi-gate structure of the thin film transistor is formed to reduce the off-state current Ioff of the thin film transistor, and the use of the additional mask is removed while the Ioff is not increased and the aperture ratio is not lowered, thereby improving the extra in the prior art. The processing cost and processing time caused by the mask is wasted. At the same time, the present invention also improves the disadvantages of prior art exposure alignment errors and doping structure shifts due to additional masks.

 And because the size of W/L is reduced, Ioff is further reduced. The Ion reduction caused by the smaller W/L can be compensated by the high mobility of the LTPS because the refresh rate of the pixel voltage is much lower than the operating frequency of the peripheral circuit.

 Where W/L is the width to length ratio of the thin film transistor channel, W is the channel width, and L is the channel length. When Vgs-Vth ≥ Vds, there are:

Ids= μ eff((8 _ms 8 ₀ /t _ms )(W/L)(Vgs-Vth)Vds,

 When Vgs-Vth < Vds, there are:

Ids = (1/2) μ eff {(8 _ms 8o/t _ms )(W/L)(Vgs-Vth) ² ,

Where εο is the vacuum dielectric constant, t _ms is the thickness of the gate insulating layer, _ns is the relative dielectric constant of the gate insulating layer, and thus _ns s. /t _ms is the capacitance value of the gate insulating layer per unit area, Vgs is the gate-source voltage, Vds is the drain-source voltage, Vth is the cutoff voltage, and μ _είΓ is the equivalent carrier mobility. As can be seen from the above formula, Ids is always proportional to W/L, so W/L is reduced, which reduces the TFT turn-on current Ion and also reduces the turn-off current Ioff.

 Referring to FIG. 1 and FIG. 2, an embodiment of the present invention provides an array substrate, including:

 Substrate 20;

 The upper surface of the substrate 20 (ie, the light-emitting surface of the substrate) has a buffer layer 25;

 The buffer layer 25 is provided with a first polysilicon island 301 and a second polysilicon island 302, and one end of the first polysilicon island 301 is connected to one end of the second polycrystalline silicon island 302;

 a gate electrode 50 is disposed above the first polysilicon island 301, and a gate line 55 connected to the gate electrode 50 is disposed above the second polysilicon island 302;

 A region of the first polysilicon island 301 not covered by the gate electrode 50 and a region of the second polysilicon island 302 not covered by the gate line 55 are doped regions as the ohmic contact region 30b;

A drain 80a connected to the ohmic contact region 30b is disposed above the first polysilicon island 301, and a data line 60 and a source 80b perpendicularly intersecting the gate line 55 are disposed above the second polysilicon island 302; The region where the polar line 55 and the data line 60 are perpendicularly intersected is provided with the drain 80a and the gate The pixel electrode 97 connected to the pole line 55.

 In one embodiment, for example, as shown in FIGS. 1 and 2, a drain 80a is formed over one end of the first polysilicon island 301, and a source 80b is formed at one end of the second polysilicon island 302. Above, and the gate electrode formed over the first polysilicon island 301 is located at one end of the first polysilicon island 301 forming the drain 80a and the connection end of the first polysilicon island 301 and the second polysilicon island 302 The gate line formed over the second polysilicon island 302 is located at one end of the second polysilicon island 302 forming the source 80b and the first polysilicon island 301 is connected to the second polysilicon island 302. Between the ends.

 The display mode of the array substrate is a TN mode. The embodiment of the present invention further provides an array substrate of an ADS display mode, which is configured to provide a passivation layer on the upper surface of the pixel electrode 97 of the array substrate of the TN mode. A common electrode is disposed on the upper surface of the passivation layer to finally form an array substrate structure of the ADS mode.

 In the array substrate provided by the embodiment of the present invention, a gate electrode and a gate line are designed over two polysilicon islands, and the gate line is skillfully used as a second gate electrode, thereby forming a thin film without reducing the aperture ratio. The multi-gate structure of the transistor achieves the effect of reducing the off-state current loff of the thin film transistor. The use of an additional mask is removed while the loff is not increased and the aperture ratio is not lowered, which improves the processing cost and processing time waste of the additional mask in the prior art. At the same time, the present invention also improves the disadvantages of prior art exposure alignment errors and doping structure shifts due to additional masks.

 In the above description of the array substrate and the method of fabricating the same according to the embodiment of the present invention, the polysilicon island is taken as an active layer as an example. However, the embodiment according to the present invention is not limited thereto. For example, the material of the active layer in which the array substrate according to the embodiment of the present invention is fabricated may be amorphous silicon, an oxide semiconductor or any other suitable semiconductor material.

 Further, although the above embodiment has been described by taking the direction in which the first polysilicon island and the second polysilicon island extend perpendicular to each other as an example. However, they can also intersect at other angles. For example, the first polysilicon island is parallel to the gate line and the second polysilicon island is parallel to the data line.

 The embodiment of the present invention further provides a display device including the array substrate. The display device may be: a liquid crystal panel, a liquid crystal display, a liquid crystal television, an OLED display panel, an OLED display, an electronic paper, or the like.

(1) An array substrate comprising:

Substrate a first active layer and a second active layer disposed on the substrate, one end of the first active layer being connected to one end of the second active layer;

 a gate electrode and a gate line connected to the gate electrode, respectively disposed above the first active layer and above the second active layer, the first active layer not being on the gate a region covered by the electrode and a region on the second active layer not covered by the gate line are formed as doped regions as ohmic contact regions;

 a drain connected to the ohmic contact region, disposed above the first active layer; a data line and a source vertically crossing the gate line, disposed above the second active layer; as well as

 A pixel electrode connected to the drain is provided on a region where the gate line and the data line intersect.

 (2) The array substrate according to (1), wherein the drain is formed above one end of the first active layer, and the source is formed above one end of the second active layer And a gate electrode formed over the first active layer is located at an end of the first active layer forming the drain and a connection end of the first active layer and the second active layer a gate line formed over the second active layer between an end of the second active layer forming the source and the first active layer and the second active layer Between the connections.

 (3) The array substrate according to (1) or (2), wherein the first active layer and the second active layer are formed in an elongated shape, and an extending direction of the first active layer Parallel to the gate line, the extending direction of the second active layer is different from the extending direction of the first active layer.

 The array substrate according to any one of (1), wherein the extending direction of the first active layer is perpendicular to an extending direction of the second active layer.

 The array substrate according to any one of (1), wherein the second active layer extends in a direction parallel to the data line.

 The array substrate according to any one of (1), wherein the material of the first active layer and the second active layer comprises polysilicon.

 (7) A display device comprising the array substrate according to any one of (1) to (6).

(8) A method for fabricating an array substrate, comprising:

Forming a first active layer and a second active layer on the substrate, one end of the first active layer being connected to one end of the second active layer; Forming a gate electrode over the first active layer, and forming a gate line connected to the gate electrode over the second active layer;

 Forming an ohmic contact region on a region of the first active layer not covered by the gate electrode and a region on the second active layer not covered by the gate line;

 Forming a source and a drain connected to the ohmic contact region, and a data line crossing the gate line and connected to the source, the drain being located above the first active layer, a source and the data line are located above the second active layer;

 A pixel electrode connected to the drain is formed on a region where the gate line and the data line intersect.

 (9) The manufacturing method according to (8), wherein the drain is formed over one end of the first active layer, and the source is formed above one end of the second active layer And a gate electrode formed over the first active layer is located at an end of the first active layer forming the drain and a connection end of the first active layer and the second active layer a gate line formed over the second active layer between an end of the second active layer forming the source and the first active layer and the second active layer Between the connections.

 (10) The manufacturing method of (8) or (9), wherein the forming the first active layer and the second active layer on the substrate comprises:

 Forming a buffer layer on the substrate;

 Forming an active layer material on the buffer layer;

 The active layer material is formed into the interconnected first active layer and second active layer by a patterning process.

 The manufacturing method according to any one of (8), wherein the first active layer and the second active layer are formed in an elongated shape, the first active The extending direction of the layer is parallel to the gate line, and the extending direction of the second active layer is different from the extending direction of the first active layer.

 (12) The manufacturing method according to (11), wherein the extending direction of the first active layer is perpendicular to the extending direction of the second active layer.

 (13) The manufacturing method according to (11) or (12), wherein the extending direction of the second active layer is parallel to the data line.

The manufacturing method according to any one of (8), wherein the gate electrode is formed over the first active layer, and is formed over the second active layer. Connected to the gate electrode The connected gate lines include:

 Forming a gate insulating layer over the first active layer and the second active layer, the gate insulating layer covering the entire substrate;

 Forming a gate metal layer over the gate insulating layer;

 The gate metal layer is formed into interconnected gate electrodes and gate lines by a patterning process.

The manufacturing method according to any one of (8), wherein the region on the first active layer not covered by the gate electrode and the second active layer are Forming an ohmic contact region on the layer that is not covered by the gate line includes:

 Performing an ion doping process using the gate electrode and the gate line as a mask to form regions on the first active layer and the second active layer that are not covered by the gate electrode and the gate line a doped region of the ohmic contact region.

 The manufacturing method according to any one of (8), wherein the source and the drain connected to the ohmic contact region and the data perpendicular to the gate line are formed. The wire includes: forming an interlayer insulating layer over the gate electrode and the gate line, the interlayer insulating layer covering the entire substrate;

 Forming, on the interlayer insulating layer, a first via hole exposing an ohmic contact region corresponding to the drain region and a second via hole exposing an ohmic contact region corresponding to the source region;

 Forming a data line metal layer on the interlayer insulating layer;

 Forming a drain connected to the ohmic contact region through the first via hole over the first active layer by a patterning process, forming a second pass over the second active layer a source connected to the ohmic contact region, and a data line covering the second active layer and crossing the gate line is formed over the second active layer.

 The manufacturing method according to any one of (8) to (16), wherein the source and the source are formed on a region where the gate line and the data line intersect The pixel electrode connected to the gate line includes:

 Forming a passivation layer over the source and the drain, the passivation layer covering the entire substrate; forming a third via hole exposing a corresponding drain on the passivation layer;

 Forming a pixel electrode layer;

A pixel electrode connected to the drain through the third via hole is formed on a region where the gate line and the data line are intersected by a patterning process. (18) The manufacturing method according to (17), wherein the pixel electrode is partially overlapped with the gate line.

 (19) The manufacturing method according to (8), wherein the material of the first active layer and the second active layer comprises polysilicon.

 The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim 1. An array substrate comprising:  Substrate  a first active layer and a second active layer disposed on the substrate, one end of the first active layer being connected to one end of the second active layer;  a gate electrode and a gate line connected to the gate electrode, respectively disposed above the first active layer and above the second active layer, the first active layer not being on the gate a region covered by the electrode and a region on the second active layer not covered by the gate line are formed as doped regions as ohmic contact regions;  a drain connected to the ohmic contact region, disposed above the first active layer; a data line and a source vertically crossing the gate line, disposed above the second active layer; as well as  A pixel electrode connected to the drain is provided on a region where the gate line and the data line intersect.  The array substrate according to claim 1, wherein the drain is formed above one end of the first active layer, and the source is formed above one end of the second active layer. And a gate electrode formed over the first active layer is located at an end of the first active layer forming the drain and a connection end of the first active layer and the second active layer a gate line formed over the second active layer is located at an end of the second active layer forming the source and a connection between the first active layer and the second active layer Between the ends.  The array substrate according to claim 1 or 2, wherein the first active layer and the second active layer are formed in an elongated shape, and an extending direction of the first active layer is The gate lines are parallel, and the extending direction of the second active layer is different from the extending direction of the first active layer.  The array substrate according to any one of claims 1 to 3, wherein an extending direction of the first active layer is perpendicular to an extending direction of the second active layer.  The array substrate according to any one of claims 1 to 4, wherein a direction in which the second active layer extends is parallel to the data line. The array substrate according to any one of claims 1 to 5, wherein materials of the first active layer and the second active layer comprise polysilicon. A display device comprising the array substrate according to any one of claims 1-6. 8. A method of fabricating an array substrate, comprising:  Forming a first active layer and a second active layer on the substrate, one end of the first active layer being connected to one end of the second active layer;  Forming a gate electrode over the first active layer, and forming a gate line connected to the gate electrode over the second active layer;  Forming an ohmic contact region on a region of the first active layer not covered by the gate electrode and a region on the second active layer not covered by the gate line;  Forming a source and a drain connected to the ohmic contact region, and a data line crossing the gate line and connected to the source, the drain being located above the first active layer, a source and the data line are located above the second active layer;  A pixel electrode connected to the drain is formed on a region where the gate line and the data line intersect.  The method according to claim 8, wherein the drain is formed above one end of the first active layer, and the source is formed above one end of the second active layer. And a gate electrode formed over the first active layer is located at an end of the first active layer forming the drain and a connection end of the first active layer and the second active layer a gate line formed over the second active layer is located at an end of the second active layer forming the source and a connection between the first active layer and the second active layer Between the ends.  The method according to claim 8 or 9, wherein the forming the first active layer and the second active layer on the substrate comprises:  Forming a buffer layer on the substrate;  Forming an active layer material on the buffer layer;  The active layer material is formed into the interconnected first active layer and second active layer by a patterning process.  The manufacturing method according to any one of claims 8 to 10, wherein the first active layer and the second active layer are formed in an elongated shape, and the extension of the first active layer The direction is parallel to the gate line, and the extending direction of the second active layer is different from the extending direction of the first active layer. The method according to claim 11, wherein the extending direction of the first active layer is perpendicular to the extending direction of the second active layer. The manufacturing method according to claim 11 or 12, wherein the extending direction of the second active layer is parallel to the data line.  The fabrication method according to any one of claims 8 to 13, wherein the gate electrode is formed over the first active layer, and the photocatalyst is formed over the second active layer The gate lines connected to the gate electrodes include:  Forming a gate insulating layer over the first active layer and the second active layer, the gate insulating layer covering the entire substrate;  Forming a gate metal layer over the gate insulating layer;  The gate metal layer is formed into interconnected gate electrodes and gate lines by a patterning process. The manufacturing method according to any one of claims 8 to 14, wherein the region on the first active layer not covered by the gate electrode and the second active layer are not Forming an ohmic contact region by the region covered by the gate line includes:  Performing an ion doping process using the gate electrode and the gate line as a mask to form regions on the first active layer and the second active layer that are not covered by the gate electrode and the gate line a doped region of the ohmic contact region.  The manufacturing method according to any one of claims 8 to 15, wherein the forming a source and a drain connected to the ohmic contact region and a data line vertically crossing the gate line comprises: Forming an interlayer insulating layer over the gate electrode and the gate line, the interlayer insulating layer covering the entire substrate;  Forming, on the interlayer insulating layer, a first via hole exposing an ohmic contact region corresponding to the drain region and a second via hole exposing an ohmic contact region corresponding to the source region;  Forming a data line metal layer on the interlayer insulating layer;  Forming a drain connected to the ohmic contact region through the first via hole over the first active layer by a patterning process, forming a second pass over the second active layer a source connected to the ohmic contact region, and a data line covering the second active layer and crossing the gate line is formed over the second active layer.  The manufacturing method according to any one of claims 8 to 16, wherein the source and the gate are formed on a region where the gate line and the data line intersect The pixel electrodes connected to the pole line include: Forming a passivation layer over the source and the drain, the passivation layer covering the entire substrate; Forming a third via hole exposing a corresponding drain on the passivation layer;  Forming a pixel electrode layer;  A pixel electrode connected to the drain through the third via hole is formed in a region where the gate line and the data line are intersected by a patterning process.  The method according to claim 17, wherein the pixel electrode is partially overlapped with the gate line.  The fabrication method according to any one of claims 8 to 18, wherein the materials of the first active layer and the second active layer comprise polysilicon.