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WO2013037186A1 - Islandless pre-encapsulated plating-then-etching lead frame structures and manufacturing method - Google Patents

Islandless pre-encapsulated plating-then-etching lead frame structures and manufacturing method Download PDF

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Publication number
WO2013037186A1
WO2013037186A1 PCT/CN2012/001160 CN2012001160W WO2013037186A1 WO 2013037186 A1 WO2013037186 A1 WO 2013037186A1 CN 2012001160 W CN2012001160 W CN 2012001160W WO 2013037186 A1 WO2013037186 A1 WO 2013037186A1
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WO
WIPO (PCT)
Prior art keywords
metal substrate
photoresist film
metal layer
back surface
top surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/001160
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French (fr)
Inventor
Xinchao Wang
Zhizhong Liang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
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Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Publication of WO2013037186A1 publication Critical patent/WO2013037186A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10W70/042
    • H10W70/479
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H10W70/457
    • H10W90/736

Definitions

  • the present invention generally relates to the field of semiconductor assembly or packaging and, more particularly, to lead frame structures and related manufacturing processes.
  • Quad Flat No-Lead (QFN) metal lead frame As shown in Figure 14, to prevent molding compound overflow from the back surface of the lead frame during an encapsulation process on the top surface of the lead frame, a layer of expensive high-temperature resistant film 23 is affixed on the back surface of the lead frame.
  • QFN Quad Flat No-Lead
  • Such lead frame may have certain disadvantages:
  • the cost of lead frame is substantially increased (e.g., at least 50%); 2)
  • the adhesive film affixed on the back surface of the metal lead frame often is a soft organic material.
  • high-temperature baking may cause organic volatile contamination, which may have direct impact on the bonding characteristics between the wires and the top surface of the chip and between the wires and the top surface of the lead frame. It may even cause bonding failure (so-called delamination) between the molding compound and the top surfaces of the chip and lead frames in later packaging processes;
  • the metal wire material used in the wire bonding process may be limited to relatively softer and more expensive gold wires. Other relatively harder but less expensive materials, such as copper, aluminum, or other metal wires or strips, may be undesirable;
  • the molding pressure during the molding process may cause certain mold bleeding between the lead frame and the adhesive film, which may put bleeding material between the lead pad 22 or die pad 21 and the organic adhesive film, as shown in Figs. 15 and 16 (molding compound under certain metal leads and die pad on the left side of the drawing); and 6)
  • a metal island or die pad is needed for chip mounting in a QFN product, which causes some difficulties in circuit board design due to the extra efforts to prevent any short circuit between the circuitries and the metal island.
  • the other type is a two-side etching and pre-encapsulated lead frame, as shown in Fig. 17.
  • etching process is first performed on the back surface of the metal substrate, and the etched areas on the back surface are sealed with encapsulation material. Further, etching and plating processes for inner leads are performed on the top surface of the metal substrate.
  • lead frame structure may have following disadvantages:
  • the lead frame needs to be etched from the top surface and the back surface separately, it may likely cause dislocation due to re-positioning errors when setting the top surface and back surface etching positions.
  • One aspect of the present disclosure includes a method for manufacturing an islandless lead frame structure for semiconductor packaging.
  • the method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, and forming a top surface plating pattern in the first photoresist film using photolithography.
  • the method also includes forming a second photoresist film on the back surface of the metal substrate, forming a back surface plating pattern in the second photoresist film using photolithography, and performing a plating process on the top surface and the back surface of the metal substrate to form a first metal layer on the top surface and a second metal layer on the back surface.
  • the method includes removing the first photoresist film and the second photoresist film, forming a third photoresist film on the top of the metal substrate covering the first metal layer, and forming a top surface etching pattern in the first photoresist film using photolithography.
  • the method also includes forming a fourth photoresist film on the back surface of the metal substrate covering the second metal layer, forming a back surface etching pattern in the fourth photoresist film using photolithography, and performing an etching process on the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks to form etched regions in the metal substrate and a plurality of leads, without forming any island.
  • the method includes removing the third photoresist film and the fourth photoresist film, and pre-encapsulating the etched metal substrate using a molding compound to form the pre-encapsulated lead frame structure.
  • the islandless lead frame structure includes a plurality of leads formed based on a metal substrate, a first metal layer formed on top surfaces of the plurality of leads and a second metal surface on back surfaces of the plurality of leads by a plating process, and a molding compound used to encapsulate the plurality of leads by a pre- encapsulation process.
  • the plating process is performed by forming a first photoresist film on a top surface of the metal substrate, forming a top surface plating pattern in the first photoresist film using photolithography, forming a second photoresist film on a back surface of the metal substrate, forming a back surface plating pattern in the second photoresist film using
  • the plurality of leads are formed by an etching process.
  • the etching process includes forming a third photoresist film on top of the metal substrate covering the first metal layer, forming a top surface etching pattern in the first photoresist film using photolithography, and forming a fourth photoresist film on back of the metal substrate covering the second metal layer.
  • the etching process also includes forming a back surface etching pattern in the fourth photoresist film using photolithography, etching the top surface and the back surface of the metal substrate
  • Figures 1-12 illustrate an exemplary process for manufacturing an islandless lead frame structure consistent with the disclosed embodiments
  • Figure 13 illustrates an exemplary islandless lead frame structure consistent with the disclosed embodiments
  • Figure 14 shows a high-temperature resistant film affixed on a lead frame
  • Figures 15-16 shows molding material infiltrated the high-temperature resistant film affixed on the lead frame
  • Figure 17 shows a two-side etched lead frame; and [0014] Figure 18 shows an exemplary islandless lead frame structure manufacturing process consistent with the disclosed embodiments.
  • Fig. 13 illustrates an exemplary islandless lead frame structure 100 consistent with the disclosed embodiments.
  • lead frame 100 includes a plurality of leads 2, a first metal layer 5 on the top surfaces of the plurality of leads 2, a second metal layer 6 on the back surfaces of the plurality of leads 2, and molding compound 4 filled in etched areas and areas between the leads of the plurality of leads 2.
  • Lead frame structure 100 does not include a die pad or island. Other components may also be included and certain components may be omitted.
  • the plurality of leads 2 may be made from a metal substrate.
  • the molding compound 4 is filled up to the first metal layer and the second metal layer on the metal substrate (e.g., plurality of leads 2) such that both the top side and the back side of the metal substrate are flat surfaces.
  • Islandless lead frame structure 100 may be formed by a plating-etching- encapsulation manufacturing process.
  • Fig. 18 illustrates an exemplary plating-etching- encapsulation process 200 consistent with the disclosed embodiments.
  • Figs. 1-12 illustrate corresponding structures during the plating-etching-encapsulation process 200.
  • a metal substrate is provided (202).
  • Fig. 1 shows a corresponding structure.
  • a metal substrate 9 is provided.
  • the metal substrate 9 may have a top surface and a back surface, and may also have a desired thickness.
  • the metal substrate 9 may be made of any appropriate metal materials, such as copper, aluminum, iron, copper alloy, stainless steel, or nickel-iron alloy. The particular metal used for metal substrate 9 may be determined based on the functionalities and characteristics of the chips to be packaged.
  • adhesive films may be attached to the top surface and the back surface of the metal substrate 9 (204). More particularly, as shown in Fig. 2, a photoresist film 10 is attached to the top surface of the metal surface 9, and a photoresist film 11 is attached to the back surface of the metal surface 9.
  • the photoresist film 10 and photoresist film 11 may be attached using certain film equipment to protect the substrate from a later plating process. Further, the photoresist film 10 and photoresist film 1 1 can be used in a photolithographic process, and any of the photoresist film 10 and photoresist film 11 may be a dry photoresist film or a wet photoresist film.
  • plating patterns may be formed based on the photoresist film 10 and photoresist film 11 (206). Specifically, as shown in Fig. 3, a top surface plating pattern is formed using the photoresist film 10 and a back surface plating pattern is formed using the photoresist film 11 via photolithography. That is, the plating patterns may be formed using a photolithographic process.
  • a top surface plating mask is used to expose the photoresist film 10, which is followed by development, and certain parts of the photoresist film 10 are removed to form the top surface plating pattern to uncover the areas on the metal substrate 9 that need to be plated.
  • a back surface plating mask is used to expose the photoresist film 11, which is followed by development, and certain parts of the photoresist film 11 are removed to form the back surface plating pattern to uncover the areas on the metal substrate 9 that need to be plated.
  • a plating process is performed on the top surface and back surface of the metal substrate 9 (208).
  • the corresponding structure is illustrated in Fig. 4.
  • the plating process is performed on the top surface of the lead frame and the back surface of the lead frame to form a first metal layer 5 on the top surface and a second metal layer 6 on the back surface. That is, the top surface of metal substrate 9 is plated using the top surface plating pattern as a mask, and the back surface of metal substrate 9 is plated using the back surface plating pattern as a mask. The portions of the top surface of the metal substrate 9 covered by the top surface plating pattern and the portions of back surface of the metal substrate 9 covered by the back surface plating pattern are not plated.
  • the plating process may include any appropriate type of electrical or chemical plating process, such as a multi-layer electrical plating process.
  • the top surface plating pattern and the back surface plating pattern are designed based on the plurality of lead 2 to be formed in a later process. That is, the first metal layer 5 is formed on areas of the top surface of the metal substrate 9 corresponding to the later formed plurality of leads 2 to provide inner leads for the plurality of leads 2. Similarly, the second metal layer 6 is formed on areas of the back surface of the metal substrate 9 corresponding to the later plurality of leads 2 to provide outer leads for the plurality of leads 2. [0024] The first metal layer 5 and the second metal layer 6 may be plated during a single plating process and at the same time.
  • the plating of the first metal layer 5 and the second metal layer 6 may be done in sequence: the first metal layer 5 is plated first or the second metal layer 6 may be plated first.
  • the plating material may include gold, nickel-gold, nickel- palladium-gold, or silver. Other materials may also be used.
  • the remaining adhesive films on the surfaces of metal substrate 9 are removed (210). As shown in Fig. 5, both remaining photoresist film 10 on the top surface of the metal substrate 9 and remaining photoresist film 11 on the back surface of the metal substrate 9 are removed, and the first metal layer 5 and second metal layer 6 remain on the top surface and back surface of the metal substrate 9.
  • the films may be removed by mechanical means or chemical means.
  • photoresist film 10 is attached to the top surface of the metal substrate 9, and photoresist film 11 is attached to the back surface of the metal substrate 9.
  • the photoresist film 10 and photoresist film 11 may be attached using the film equipment to protect the substrate from a later etching process.
  • etching patterns may be formed based on the photoresist film 10 and photoresist film 11 (214). Specifically, as shown in Fig. 7, a top surface etching pattern is formed using the photoresist film 10 and a back surface etching pattern is formed using the photoresist film 11 via photolithography. That is, the etching patterns may be formed using a photolithographic process.
  • a top surface etching mask is used to expose the photoresist film 10, which is followed by development, and certain parts of the photoresist film 10 are removed to form the top surface etching pattern to uncover the areas on the metal substrate 9 need to be etched.
  • a back surface etching mask is used to expose the photoresist film 11, which is followed by development, and certain parts of the photoresist film 11 are removed to form the back surface etching pattern to uncover the areas on the metal substrate 9 need to be etched.
  • the top surface etching pattern and the back surface etching pattern are designed corresponding to the top surface plating pattern and the back surface plating pattern such that the etching patterns cover the first and second metal layers in a subsequent etching process, while exposing the areas to be etched.
  • an etching process is performed on the top surface and back surface of the metal substrate 9 (216).
  • the corresponding structure is illustrated in Fig. 8.
  • an etching process is performed on the exposed areas on the top surface and back surface of the metal substrate 9 by the etching patterns. That is, the top surface of metal substrate 9 is etched using the top surface etching pattern as a mask, and the back surface of metal substrate 9 is etched using the back surface etching pattern as a mask.
  • the etching process may use a half etching or a full etching, and may be performed on both the top surface and the back surface simultaneously.
  • etched areas or regions 12 are formed on the top surface and the back surface of the metal substrate 9.
  • the plurality of leads 2 are also formed during the etching process, without forming any island or die pad.
  • the metal substrate 9 including the leads 2 and etched regions 12 is encapsulated in a molding process or a pre- encapsulating process (220). That is, a molding compound 4 is filled into the etched metal substrate 9 using a mold.
  • pre-encapsulation refers to the encapsulation or molding process that is performed during the lead frame manufacturing to encapsulate the lead frame before other subsequent packaging processes, such as chip mounting.
  • Figs. 10-12 illustrate corresponding structures formed during the molding process.
  • the etched metal substrate 9, after removing the films on the top and back surfaces, is placed in the mold.
  • the mold may include any appropriate type of mold for IC packaging, such as an injection mold. Further, the mold may include an upper mold 7 and a lower mold 8. Both the upper mold 7 and the lower mold 8 have a flat contact surface, and the metal substrate 9 may be placed between the flat surfaces of the upper mold 7 and the lower mold 8.
  • the surface of the upper mold 7 may include downward injection holes and/or the surface of the lower mold 8 may include upward injection holes.
  • the upper mold 7 and the lower mold 8 are clamped to two sides of the metal substrate 9. That is, the injection mold clamps the upper mold 7 and the lower mold 8 such that the first metal layer 5 and the second metal layer 6 on the metal substrate 9 are in direct contact with the flat surfaces of the upper mold and the lower mold, respectively, such that the first metal layer 5 and second metal layer 6 are covered by the mold surfaces.
  • molding compound 4 is injected in the etched regions 12 and areas between leads of the plurality of leads 2, as shown in Fig. 1 1.
  • the injected molding compound 4 and the first metal layer 5 together form a flat top surface of the encapsulated metal substrate 9, and the injected molding compound 4 and the second metal layer 6 together form a flat back surface on the encapsulated metal substrate 9.
  • the molding compound 4 is injected in the metal substrate 9, i.e., the lead frame is pre-encapsulated, the encapsulated metal substrate 9 is removed from the mold, as shown in Fig. 12.
  • the pre-encapsulated lead frame 100 has a flat top surface comprising the exposed first metal layer 5 and the molding compound 4, and a flat back surface comprising the exposed second metal layer 6 and the molding compound 4. [0036] After the encapsulation process, as shown in Fig. 13, the islandless lead frame 100 is completed. Other subsequent packaging processes may be performed on the islandless lead frame 100 to form various packaging structures, such as single chip or multi-chip structures.
  • the disclosed islandless lead frame structures and manufacturing methods may be applied in a variety of semiconductor packaging applications for different carriers with different substrates and filling materials.
  • the disclosed structures and methods may be used to package plastic leaded chip carrier (PLCC), plastic quad flat pack (PQFP), ball grid array (BGA), system in package (SiP) or 3D ICs, and multi-chip module, etc.
  • PLCC plastic leaded chip carrier
  • PQFP plastic quad flat pack
  • BGA ball grid array
  • SiP system in package
  • 3D ICs 3D ICs
  • multi-chip module etc.
  • the etching process on both top surface and back surface of the islandless lead frame can be performed simultaneously.

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  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A method for manufacturing an islandless lead frame structure (100) for semiconductor packaging includes providing a metal substrate, forming a first photoresist film on the top surface of the metal substrate, and forming a top surface plating pattern in the first photoresist film using photolithography. The metal also includes performing a plating process on the top surface and the back surface of the metal substrate to form a first metal layer (5) on the top surface and a second metal layer (6) on the back surface. Further, the method includes performing an etching process on the top surface and the back surface of the metal substrate simultaneously using a top surface etching pattern and a back surface etching pattern as the respective masks to form etched regions in the metal substrate and a plurality of leads (2), without forming any island. Further, the method includes removing the third photoresist film and the fourth photoresist film, and pre-encapsulating the etched metal substrate using a molding compound (4) to form the pre-encapsulated lead frame structure.

Description

ISLANDLESS PRE-ENCAPSULATED PLATING-THEN-ETCHING LEAD FRAME STRUCTURES AND MANUFACTURING METHOD
CROSS-REFERENCES TO RELATED APPLICATIONS [0001 ] This application claims the priority of Chinese patent application
no.201110268357.4. filed on 13/09/2011. the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention generally relates to the field of semiconductor assembly or packaging and, more particularly, to lead frame structures and related manufacturing processes.
BACKGROUND
[0003] There are mainly two types of conventional lead frame structures used in semiconductor packaging processes. One type is a Quad Flat No-Lead (QFN) metal lead frame. For this type, as shown in Figure 14, to prevent molding compound overflow from the back surface of the lead frame during an encapsulation process on the top surface of the lead frame, a layer of expensive high-temperature resistant film 23 is affixed on the back surface of the lead frame. Such lead frame may have certain disadvantages:
1) Because an high-temperature film is affixed on the back surface of the metal lead frame, the cost of lead frame is substantially increased (e.g., at least 50%); 2) The adhesive film affixed on the back surface of the metal lead frame often is a soft organic material. During subsequent assembly and wire bonding processes, high-temperature baking may cause organic volatile contamination, which may have direct impact on the bonding characteristics between the wires and the top surface of the chip and between the wires and the top surface of the lead frame. It may even cause bonding failure (so-called delamination) between the molding compound and the top surfaces of the chip and lead frames in later packaging processes;
3) In the subsequent wire bonding process, because the back surface of the lead frame is affixed with the soft organic adhesive film, part of the bonding strength may be absorbed by the soft organic adhesive film. This may increase the difficulty for wire bonding, cause unstable wire bonding yield, and may cause reliability issues; 4) Because the back surface of the lead frame is affixed with the soft organic adhesive film, the metal wire material used in the wire bonding process may be limited to relatively softer and more expensive gold wires. Other relatively harder but less expensive materials, such as copper, aluminum, or other metal wires or strips, may be undesirable;
5) In the subsequent molding process, because the back surface of the lead frame is affixed with the soft organic adhesive film, the molding pressure during the molding process may cause certain mold bleeding between the lead frame and the adhesive film, which may put bleeding material between the lead pad 22 or die pad 21 and the organic adhesive film, as shown in Figs. 15 and 16 (molding compound under certain metal leads and die pad on the left side of the drawing); and 6) In general, a metal island or die pad is needed for chip mounting in a QFN product, which causes some difficulties in circuit board design due to the extra efforts to prevent any short circuit between the circuitries and the metal island. [0004] The other type is a two-side etching and pre-encapsulated lead frame, as shown in Fig. 17. To form this type of lead frame, an etching process is first performed on the back surface of the metal substrate, and the etched areas on the back surface are sealed with encapsulation material. Further, etching and plating processes for inner leads are performed on the top surface of the metal substrate. However, such lead frame structure may have following disadvantages:
1) Because the manufacturing process of the lead frame is complicated, manufacturing cost may be increased;
2) Because the lead frame needs to be etched from the top surface and the back surface separately, it may likely cause dislocation due to re-positioning errors when setting the top surface and back surface etching positions.
[0005] The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
BRIEF SUMMARY OF THE DISCLOSURE [0006] One aspect of the present disclosure includes a method for manufacturing an islandless lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, and forming a top surface plating pattern in the first photoresist film using photolithography. The method also includes forming a second photoresist film on the back surface of the metal substrate, forming a back surface plating pattern in the second photoresist film using photolithography, and performing a plating process on the top surface and the back surface of the metal substrate to form a first metal layer on the top surface and a second metal layer on the back surface. Further, the method includes removing the first photoresist film and the second photoresist film, forming a third photoresist film on the top of the metal substrate covering the first metal layer, and forming a top surface etching pattern in the first photoresist film using photolithography. The method also includes forming a fourth photoresist film on the back surface of the metal substrate covering the second metal layer, forming a back surface etching pattern in the fourth photoresist film using photolithography, and performing an etching process on the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks to form etched regions in the metal substrate and a plurality of leads, without forming any island. Further, the method includes removing the third photoresist film and the fourth photoresist film, and pre-encapsulating the etched metal substrate using a molding compound to form the pre-encapsulated lead frame structure.
[0007] Another aspect of the present disclosure includes an islandless lead frame structure for semiconductor packaging. The islandless lead frame structure includes a plurality of leads formed based on a metal substrate, a first metal layer formed on top surfaces of the plurality of leads and a second metal surface on back surfaces of the plurality of leads by a plating process, and a molding compound used to encapsulate the plurality of leads by a pre- encapsulation process. The plating process is performed by forming a first photoresist film on a top surface of the metal substrate, forming a top surface plating pattern in the first photoresist film using photolithography, forming a second photoresist film on a back surface of the metal substrate, forming a back surface plating pattern in the second photoresist film using
photolithography, performing the plating process on the top surface and the back surface of the metal substrate to form the first metal layer on the top surface and the second metal layer on the back surface, and removing the first photoresist film and the second photoresist film. Further, the plurality of leads are formed by an etching process. The etching process includes forming a third photoresist film on top of the metal substrate covering the first metal layer, forming a top surface etching pattern in the first photoresist film using photolithography, and forming a fourth photoresist film on back of the metal substrate covering the second metal layer. The etching process also includes forming a back surface etching pattern in the fourth photoresist film using photolithography, etching the top surface and the back surface of the metal substrate
simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks to form the plurality of leads and etched regions in the metal substrate, without forming any island, and removing the third photoresist film and the second photoresist film.
[0008] Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
FJRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figures 1-12 illustrate an exemplary process for manufacturing an islandless lead frame structure consistent with the disclosed embodiments;
[0010] Figure 13 illustrates an exemplary islandless lead frame structure consistent with the disclosed embodiments;
[0011] Figure 14 shows a high-temperature resistant film affixed on a lead frame;
[0012] Figures 15-16 shows molding material infiltrated the high-temperature resistant film affixed on the lead frame;
[0013] Figure 17 shows a two-side etched lead frame; and [0014] Figure 18 shows an exemplary islandless lead frame structure manufacturing process consistent with the disclosed embodiments.
DETAILED DESCRIPTION
[0015] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
[0016] Fig. 13 illustrates an exemplary islandless lead frame structure 100 consistent with the disclosed embodiments. As shown in Fig. 13, lead frame 100 includes a plurality of leads 2, a first metal layer 5 on the top surfaces of the plurality of leads 2, a second metal layer 6 on the back surfaces of the plurality of leads 2, and molding compound 4 filled in etched areas and areas between the leads of the plurality of leads 2. Lead frame structure 100 does not include a die pad or island. Other components may also be included and certain components may be omitted. The plurality of leads 2 may be made from a metal substrate. The molding compound 4 is filled up to the first metal layer and the second metal layer on the metal substrate (e.g., plurality of leads 2) such that both the top side and the back side of the metal substrate are flat surfaces.
[0017] Islandless lead frame structure 100 may be formed by a plating-etching- encapsulation manufacturing process. Fig. 18 illustrates an exemplary plating-etching- encapsulation process 200 consistent with the disclosed embodiments. Figs. 1-12 illustrate corresponding structures during the plating-etching-encapsulation process 200.
[0018] As shown in Fig. 18, at the beginning of process 200, a metal substrate is provided (202). Fig. 1 shows a corresponding structure. As shown in Fig. 1, a metal substrate 9 is provided. The metal substrate 9 may have a top surface and a back surface, and may also have a desired thickness. The metal substrate 9 may be made of any appropriate metal materials, such as copper, aluminum, iron, copper alloy, stainless steel, or nickel-iron alloy. The particular metal used for metal substrate 9 may be determined based on the functionalities and characteristics of the chips to be packaged.
[0019] Returning to Fig. 18, after the metal substrate 9 is provided (202), adhesive films may be attached to the top surface and the back surface of the metal substrate 9 (204). More particularly, as shown in Fig. 2, a photoresist film 10 is attached to the top surface of the metal surface 9, and a photoresist film 11 is attached to the back surface of the metal surface 9. The photoresist film 10 and photoresist film 11 may be attached using certain film equipment to protect the substrate from a later plating process. Further, the photoresist film 10 and photoresist film 1 1 can be used in a photolithographic process, and any of the photoresist film 10 and photoresist film 11 may be a dry photoresist film or a wet photoresist film. Other types of film may also be used. [0020] Returning to Fig. 18, after the photoresist film 10 and photoresist film 1 1 are attached to the metal substrate 9 (204), plating patterns may be formed based on the photoresist film 10 and photoresist film 11 (206). Specifically, as shown in Fig. 3, a top surface plating pattern is formed using the photoresist film 10 and a back surface plating pattern is formed using the photoresist film 11 via photolithography. That is, the plating patterns may be formed using a photolithographic process. A top surface plating mask is used to expose the photoresist film 10, which is followed by development, and certain parts of the photoresist film 10 are removed to form the top surface plating pattern to uncover the areas on the metal substrate 9 that need to be plated. Similarly, a back surface plating mask is used to expose the photoresist film 11, which is followed by development, and certain parts of the photoresist film 11 are removed to form the back surface plating pattern to uncover the areas on the metal substrate 9 that need to be plated.
[0021] Further, as shown in Fig. 18, a plating process is performed on the top surface and back surface of the metal substrate 9 (208). The corresponding structure is illustrated in Fig. 4. [0022] As shown in Fig. 4, the plating process is performed on the top surface of the lead frame and the back surface of the lead frame to form a first metal layer 5 on the top surface and a second metal layer 6 on the back surface. That is, the top surface of metal substrate 9 is plated using the top surface plating pattern as a mask, and the back surface of metal substrate 9 is plated using the back surface plating pattern as a mask. The portions of the top surface of the metal substrate 9 covered by the top surface plating pattern and the portions of back surface of the metal substrate 9 covered by the back surface plating pattern are not plated.
[0023] The plating process may include any appropriate type of electrical or chemical plating process, such as a multi-layer electrical plating process. The top surface plating pattern and the back surface plating pattern are designed based on the plurality of lead 2 to be formed in a later process. That is, the first metal layer 5 is formed on areas of the top surface of the metal substrate 9 corresponding to the later formed plurality of leads 2 to provide inner leads for the plurality of leads 2. Similarly, the second metal layer 6 is formed on areas of the back surface of the metal substrate 9 corresponding to the later plurality of leads 2 to provide outer leads for the plurality of leads 2. [0024] The first metal layer 5 and the second metal layer 6 may be plated during a single plating process and at the same time. Alternatively, the plating of the first metal layer 5 and the second metal layer 6 may be done in sequence: the first metal layer 5 is plated first or the second metal layer 6 may be plated first. The plating material may include gold, nickel-gold, nickel- palladium-gold, or silver. Other materials may also be used.
[0025] After the plating process, as shown in Fig. 18, the remaining adhesive films on the surfaces of metal substrate 9 are removed (210). As shown in Fig. 5, both remaining photoresist film 10 on the top surface of the metal substrate 9 and remaining photoresist film 11 on the back surface of the metal substrate 9 are removed, and the first metal layer 5 and second metal layer 6 remain on the top surface and back surface of the metal substrate 9. The films may be removed by mechanical means or chemical means.
[0026] Further, as shown in Fig. 18, after remaining adhesive films from the plating process are removed (210), new adhesive films may be again attached to the top surface and the back surface of the metal substrate 9 covering the first and second metal layers 5 and 6 (212).
More particularly, as shown in Fig. 6, photoresist film 10 is attached to the top surface of the metal substrate 9, and photoresist film 11 is attached to the back surface of the metal substrate 9.
The photoresist film 10 and photoresist film 11 may be attached using the film equipment to protect the substrate from a later etching process.
[0027] As shown in Fig. 18, after the photoresist film 10 and photoresist film 1 1 are attached to the metal substrate 9 (212), etching patterns may be formed based on the photoresist film 10 and photoresist film 11 (214). Specifically, as shown in Fig. 7, a top surface etching pattern is formed using the photoresist film 10 and a back surface etching pattern is formed using the photoresist film 11 via photolithography. That is, the etching patterns may be formed using a photolithographic process. A top surface etching mask is used to expose the photoresist film 10, which is followed by development, and certain parts of the photoresist film 10 are removed to form the top surface etching pattern to uncover the areas on the metal substrate 9 need to be etched. Similarly, a back surface etching mask is used to expose the photoresist film 11, which is followed by development, and certain parts of the photoresist film 11 are removed to form the back surface etching pattern to uncover the areas on the metal substrate 9 need to be etched.
[0028] The top surface etching pattern and the back surface etching pattern are designed corresponding to the top surface plating pattern and the back surface plating pattern such that the etching patterns cover the first and second metal layers in a subsequent etching process, while exposing the areas to be etched.
[0029] Further, as shown in Fig. 18, an etching process is performed on the top surface and back surface of the metal substrate 9 (216). The corresponding structure is illustrated in Fig. 8. As shown in Fig. 8, an etching process is performed on the exposed areas on the top surface and back surface of the metal substrate 9 by the etching patterns. That is, the top surface of metal substrate 9 is etched using the top surface etching pattern as a mask, and the back surface of metal substrate 9 is etched using the back surface etching pattern as a mask. The etching process may use a half etching or a full etching, and may be performed on both the top surface and the back surface simultaneously. After the etching process, etched areas or regions 12 are formed on the top surface and the back surface of the metal substrate 9. At the same time, the plurality of leads 2 are also formed during the etching process, without forming any island or die pad.
[0030] After the etching process, as shown in Fig. 18, the remaining adhesive films on the surfaces of metal substrate 9 are removed (218). As shown in Fig. 9, both remaining photoresist film 10 on the top surface of the metal substrate 9 and remaining photoresist film 11 on the back surface of the metal substrate 9 are removed. [0031] Further, as shown in Fig. 18, the metal substrate 9 including the leads 2 and etched regions 12 (i.e., the lead frame) is encapsulated in a molding process or a pre- encapsulating process (220). That is, a molding compound 4 is filled into the etched metal substrate 9 using a mold. The term "pre-encapsulation" refers to the encapsulation or molding process that is performed during the lead frame manufacturing to encapsulate the lead frame before other subsequent packaging processes, such as chip mounting. Figs. 10-12 illustrate corresponding structures formed during the molding process.
[0032] As shown in Fig. 10, the etched metal substrate 9, after removing the films on the top and back surfaces, is placed in the mold. The mold (unnumbered) may include any appropriate type of mold for IC packaging, such as an injection mold. Further, the mold may include an upper mold 7 and a lower mold 8. Both the upper mold 7 and the lower mold 8 have a flat contact surface, and the metal substrate 9 may be placed between the flat surfaces of the upper mold 7 and the lower mold 8.
[0033] The surface of the upper mold 7 may include downward injection holes and/or the surface of the lower mold 8 may include upward injection holes. After the metal substrate 9 is placed between the upper mold 7 and the lower mold 8, the upper mold 7 and the lower mold 8 are clamped to two sides of the metal substrate 9. That is, the injection mold clamps the upper mold 7 and the lower mold 8 such that the first metal layer 5 and the second metal layer 6 on the metal substrate 9 are in direct contact with the flat surfaces of the upper mold and the lower mold, respectively, such that the first metal layer 5 and second metal layer 6 are covered by the mold surfaces.
[0034] Further, using the downward injection holes on the upper mold 7 and/or the upward injection holes on the lower mold 8, molding compound 4 is injected in the etched regions 12 and areas between leads of the plurality of leads 2, as shown in Fig. 1 1. The injected molding compound 4 and the first metal layer 5 together form a flat top surface of the encapsulated metal substrate 9, and the injected molding compound 4 and the second metal layer 6 together form a flat back surface on the encapsulated metal substrate 9. [0035] After the molding compound 4 is injected in the metal substrate 9, i.e., the lead frame is pre-encapsulated, the encapsulated metal substrate 9 is removed from the mold, as shown in Fig. 12. The pre-encapsulated lead frame 100 has a flat top surface comprising the exposed first metal layer 5 and the molding compound 4, and a flat back surface comprising the exposed second metal layer 6 and the molding compound 4. [0036] After the encapsulation process, as shown in Fig. 13, the islandless lead frame 100 is completed. Other subsequent packaging processes may be performed on the islandless lead frame 100 to form various packaging structures, such as single chip or multi-chip structures.
INDUSTRIAL APPLICABILITY AND ADVANTAGEOUS EFFECTS
[0037] Without limiting the scope of any claim and/or the specification, examples of industrial applicability and certain advantageous effects of the disclosed embodiments are listed for illustrative purposes. Various alternations, modifications, or equivalents to the technical solutions of the disclosed embodiments can be obvious to those skilled in the art.
[0038] The disclosed islandless lead frame structures and manufacturing methods may be applied in a variety of semiconductor packaging applications for different carriers with different substrates and filling materials. For example, the disclosed structures and methods may be used to package plastic leaded chip carrier (PLCC), plastic quad flat pack (PQFP), ball grid array (BGA), system in package (SiP) or 3D ICs, and multi-chip module, etc. [0039] By using the disclosed methods and structures, an islandless lead frame structure can be created using a plating-etching-encapsulation process, which eliminates the need for a high-temperature resistant adhesive film on the back surface of the lead frame and all
disadvantages associated with the soft adhesive film. By simplifying fabrication processes, such islandless lead frame structures and methods can reduce the cost of packaging materials, production processes, and productivity while increasing the reliability of the packaging processes. Further, because no metal island needs to be considered for chip mounting, the circuit design may have fewer difficulties.
[0040] By using the disclosed methods and structures, the etching process on both top surface and back surface of the islandless lead frame can be performed simultaneously.
Comparing to the two-side etching and pre-encapsulated lead frame, such process can reduce the process complexity by at least 50% and also reduce costs. Further, the re-positioning errors can also be reduced or avoided.
Reference Signs List
Islandless lead frame structure 100
Leads 2
Molding compound 4
First metal layer 5
Second metal layer 6
Upper mold 7
Lower mold 8
Photoresist film 10
Photoresist film 11
Etched areas 12
Lead frame manufacturing process 200
Providing a metal substrate 202
Attaching adhesive films 204
Forming plating patterns 206
Performing a plating process 208
Removing adhesive films 210
Attaching adhesive films 212
Forming etching patterns 214
Performing an etching process 216
Removing adhesive films 218
Pre-encapsulating the lead frame 220
Island 21
Leads 22
High-temperature resistant film 23
Molding compound 24

Claims

What is claimed is:
1. A method for manufacturing an islandless lead frame structure for semiconductor
packaging, comprising: providing a metal substrate having a top surface and a back surface; forming a first photoresist film on the top surface of the metal substrate;
forming a top surface plating pattern in the first photoresist film using photolithography; forming a second photoresist film on the back surface of the metal substrate; forming a back surface plating pattern in the second photoresist film using
photolithography;
performing a plating process on the top surface and the back surface of the metal substrate to form a first metal layer on the top surface and a second metal layer on the back surface; removing the first photoresist film and the second photoresist film;
forming a third photoresist film on the top of the metal substrate covering the first metal layer; forming a top surface etching pattern in the first photoresist film using photolithography; forming a fourth photoresist film on the back surface of the metal substrate covering the second metal layer; forming a back surface etching pattern in the fourth photoresist film using
photolithography; performing an etching process on the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks to form etched regions in the metal substrate and a plurality of leads, without any island; removing the third photoresist film and the fourth photoresist film; and pre-encapsulating the etched metal substrate using a molding compound to form the pre- encapsulated lead frame structure.
2. The method according to claim 1 , wherein: the etching process is a full etching process.
3. The method according to claim 1 ,wherein the pre-encapsulating the etched metal
substrate further includes: placing the etched metal substrate in a mold; and encapsulating the etched metal substrate using the mold such that the molding compound is filled in the etched regions and areas between the plurality of leads, while exposing the first metal layer and the second metal layer.
4. The method according to claim 3, wherein: the mold is an injection mold including an upper mold and a lower mold; the etched metal substrate is placed between a flat surface of the upper mold and a flat surface of the lower mold; and a plurality of injection holes configured on at least one of the flat surfaces of the upper mold and the lower mold;
5. The method according to claim 4, wherein encapsulating the etched metal substrate further includes: clamping the upper mold and the lower mold such that the first metal layer and the second metal layer of the metal substrate are in contact with the flat surfaces of the upper mold and the lower mold, respectively, such that the first metal layer and the second metal layer are covered; and injecting the molding compound into the etched regions and the areas between the plurality of leads to same levels of the first metal layer and the second metal layer to form a flat top surface and a flat back surface on the etched metal substrate.
6. The method according to claim 1, wherein: the first metal layer contains a plurality of inner leads on the plurality of leads; and the second metal layer contains a plurality of outer leads on the plurality of leads.
7. The method according to claim 1, wherein: the plating process uses a plating material from one of gold, nickel-gold, nickel- palladium-gold, and silver.
8. An islandless lead frame structure for semiconductor packaging, comprising: a plurality of leads formed based on a metal substrate; a first metal layer formed on top surfaces of the plurality of leads and a second metal surface on back surfaces of the plurality of leads by a plating process; and a molding compound used to encapsulate the plurality of leads by a pre-encapsulation process, wherein the plating process is performed by: forming a first photoresist film on a top surface of the metal substrate; forming a top surface plating pattern in the first photoresist film using photolithography; forming a second photoresist film on a back surface of the metal substrate; forming a back surface plating pattern in the second photoresist film using photolithography; performing the plating process on the top surface and the back surface of the metal substrate to form the first metal layer on the top surface and the second metal layer on the back surface; and removing the first photoresist film and the second photoresist film;
wherein the plurality of leads are formed by an etching process, including: forming a third photoresist film on top of the metal substrate covering the first metal layer; forming a top surface etching pattern in the first photoresist film using photolithography; forming a fourth photoresist film on back of the metal substrate covering the second metal layer; forming a back surface etching pattern in the fourth photoresist film using photolithography; etching the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks to form the plurality of leads and etched regions in the metal substrate, without forming any island; and removing the third photoresist film and the second photoresist film.
9. The islandless lead frame structure according to claim 8, wherein the pre-encapsulation process is performed by: placing the etched metal substrate in a mold; and encapsulating the etched metal substrate using the mold such that the molding compound is filled in the etched regions and areas between the plurality of leads, while exposing the first metal layer and the second metal layer.
10. The islandless lead frame structure according to claim 9, wherein: the mold is an injection mold including an upper mold and a lower mold; the etched metal substrate is placed between a flat surface of the upper mold and a flat surface of the lower mold; and
a plurality of injection holes configured on at least one of the flat surfaces of the upper mold and the lower mold;
11. The islandless lead frame structure according to claim 10, wherein the pre-encapsulation process further includes: clamping the upper mold and the lower mold such that the top surface and the back surface of the metal substrate are in contact with the flat surfaces of the upper mold and the lower mold, respectively, such that the surfaces of the plurality leads are covered; and injecting the molding compound into the etched regions and the areas between the plurality of leads to form a flat top surface and a flat back surface on the etched metal substrate.
12. The islandless lead frame structure according to claim 9, wherein: the first metal layer contains a plurality of inner leads on the plurality of leads; and the second metal layer contains a plurality of outer leads on the plurality of leads.
13. The islandless lead frame structure according to claim 9, wherein: the first metal layer and the second metal layer are formed by the plating process using a plating material from one of gold, nickel-gold, nickel-palladium-gold, and silver.
PCT/CN2012/001160 2011-09-13 2012-08-28 Islandless pre-encapsulated plating-then-etching lead frame structures and manufacturing method Ceased WO2013037186A1 (en)

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