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WO2013037187A1 - A pre-encapsulated lead frame structure with island and manufacturing method - Google Patents

A pre-encapsulated lead frame structure with island and manufacturing method Download PDF

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Publication number
WO2013037187A1
WO2013037187A1 PCT/CN2012/001161 CN2012001161W WO2013037187A1 WO 2013037187 A1 WO2013037187 A1 WO 2013037187A1 CN 2012001161 W CN2012001161 W CN 2012001161W WO 2013037187 A1 WO2013037187 A1 WO 2013037187A1
Authority
WO
WIPO (PCT)
Prior art keywords
leads
island
metal substrate
top surface
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/001161
Other languages
French (fr)
Inventor
Xinchao Wang
Zhizhong Liang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Publication of WO2013037187A1 publication Critical patent/WO2013037187A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10W70/042
    • H10W70/479
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H10W70/457
    • H10W72/075
    • H10W72/952
    • H10W90/736

Definitions

  • the present invention generally relates to the field of semiconductor assembly or packaging and, more particularly, to lead frame structures and related manufacturing processes.
  • Fig. 1 shows a conventional QFN lead frame having an island 21 and leads 22.
  • Fig. 2 shows a chip 23 is mounted on island 21 using mounting glue 24 and sealed by molding compound 25.
  • the chip 23 because the size of the chip 23 is larger than the size of the island 21, the chip 23 also touches the inner leads of the leads 22 and mounting glue 24 also touches or contaminates the inner leads of the leads 22. Therefore, to avoid such contamination, the size of the chip 23 to be mounted on the lead frame is limited, and the chip scale may be low.
  • the disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
  • One aspect of the present disclosure includes a method for manufacturing a lead frame structure in a semiconductor packaging process.
  • the method includes providing a metal substrate having a top surface and a back surface, .forming a first photoresist film on the top surface of the metal substrate, and forming a top surface etching pattern in the first photoresist film using photolithography.
  • the method also includes forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, and performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form an island and a plurality of leads.
  • Outer leads of the plurality of leads on the back surface extend to the proximity of the island such that a length of the outer leads is greater than a length of inner leads of the plurality of leads on the top surface by a predetermined amount. Further, the method includes removing the first photoresist film and the second photoresist film, and encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the island and the plurality leads.
  • the lead frame includes an island and a plurality of leads formed based on a metal substrate by an etching process, and a molding compound used to encapsulate the etched metal substrate with the island and plurality of leads.
  • the etching process is performed by: providing the metal substrate; forming a first photoresist film on a top surface of the metal substrate; forming a top surface etching pattern in the first photoresist film using photolithography; forming a second photoresist film on a back surface of the metal substrate; forming a back surface etching pattern in the second photoresist film using photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form an island and a plurality of leads, where outer leads of the plurality of leads on the back surface extend to the proximity of the island such that a length of the outer leads is greater than a length of inner leads of the plurality of leads on the top surface by a predetermined amount; and removing the first photoresist film and the second photoresist film.
  • Figure 1 shows a conventional QFN lead frame
  • Figure 2 shows a large-size chip mounted on the conventional QFN lead frame with mounting glue contamination
  • Figure 3 illustrates an exemplary pre-encapsulated lead frame structure consistent with the disclosed embodiments
  • Figure 4 illustrates a large-size chip mounted on the pre-encapsulated lead frame structure
  • Figure 5 shows an exemplary packaging process based on the pre-encapsulated lead frame structure consistent with the disclosed embodiments.
  • Fig. 3 illustrates an exemplary pre-encapsulated lead frame structure 100 consistent with the disclosed embodiments.
  • lead frame 100 includes a die pad or island 1, a plurality of leads 2, and molding compound filled in the areas between the island 1 and the leads and the areas between the leads of the plurality of leads 2.
  • Other components may also be included and certain components may be omitted.
  • lead frame 100 may also include a first metal layer (not shown) on the top surfaces of the island 1 and leads 2 and a second metal layer (not shown) on the back surfaces of the island 1 and leads 2.
  • the island 1 and leads 2 may be made from a metal substrate (unnumbered).
  • the molding compound may be filled up to the top surface and the back surface of the metal substrate (e.g., island 1 and leads 2) such that both the top surface and the back surface of the metal substrate are flat.
  • Lead frame structure 100 may be formed as a part of a packaging process or as an independent lead frame manufacturing process.
  • Fig. 5 illustrates an exemplary packaging process or lead frame manufacturing process 200 consistent with the disclosed embodiments. As shown in Fig. 5, at the beginning of the packaging process 200, a metal substrate is provided (202).
  • the metal substrate may have a top surface and a back surface, and may also have a desired thickness.
  • the metal substrate may be made of any appropriate metal materials, such as copper, aluminum, iron, copper alloy, stainless steel, or nickel-iron alloy. The particular metal used for metal substrate may be determined based on the functionalities and characteristics of the chips to be packaged.
  • adhesive films may be attached to the top surface and the back surface of the metal substrate (204). More particularly, a first photoresist film may be attached to the top surface of the metal substrate, and a second photoresist film may be attached to the back surface of the metal substrate.
  • the first photoresist film and the second photoresist film may be attached using certain film equipment to protect the substrate from a later etching process. Further, the first photoresist film and second photoresist film can be used in a photolithographic process, and any of the first photoresist film and second photoresist film may be a dry photoresist film or a wet photoresist film. Other types of film may also be used.
  • etching patterns may be formed based on the first photoresist film and second photoresist film (206). More specifically, a top surface etching pattern may be formed using the first photoresist film and a back surface etching pattern may be formed using the second photoresist film via photolithography. That is, the etching patterns may be formed using a photolithographic process. A top surface etching mask is used to expose the first photoresist film, which is followed by development, and certain parts of the first photoresist film are removed to form the top surface etching pattern to uncover the areas on the metal substrate that need to be etched.
  • the top surface etching pattern corresponds to inner contact surface of the island 1 and inner leads of the plurality of leads 2
  • the back surface etching pattern corresponds to outer contact surface of the island 1 and outer leads of the plurality of leads 2.
  • the top surface etching pattern is designed in a way that the distance between the inner contact surface of the island 1 and inner leads of the plurality of leads 2 is substantially extended to fit a large chip.
  • the distance between the island 1 and inner leads of the plurality of leads 2 is within a predetermined range such that a large chip can be mounted on the island 1 without touching the plurality of leads 2.
  • a large chip may refer to a chip having a surface area larger than the surface area of a corresponding island.
  • the back surface etching pattern is designed in a way that the outer leads of the plurality of leads 2 extends to the proximity of the island 1 such that the length of the outer leads is larger than the length of the inner leads.
  • an etching process may be performed on the top surface and back surface of the metal substrate (208). That is, the etching process is performed on the exposed areas on the top surface and back surface of the metal substrate, which are exposed by removing parts of the first and second photoresist films.
  • the top surface of metal substrate is etched using the top surface etching pattern as a mask, and the back surface of metal substrate is etched using the back surface etching pattern as a mask.
  • the etching process may be a half etching and may be performed on both the top surface and the back surface simultaneously.
  • the island 1, the plurality of leads 2, and certain etched areas are formed on the metal substrate.
  • the plurality of leads 2 have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate. That is, the length of the inner leads is less than the length of the outer leads by a predetermined amount.
  • the amount may be determined based on a particular application of the lead frame 100.
  • the lead frame 100 may have a maximum chip size that can be fitted into the lead frame 100 or onto the island 1, and the amount may be determined based on the maximum chip size.
  • the inner leads may retreat from the island 1 by a first value, and the outer leads may extend towards the island 1 by a second value such that the length of the outer leads is greater than the length of the inner leads based on the first value and the second value.
  • etching such as a full etching, may also be used.
  • the remaining adhesive films on the surfaces of metal substrate are removed (210).
  • the films may be removed by mechanical means or chemical means.
  • the etched metal substrate is encapsulated in a molding process or a pre- encapsulating process (212). That is, molding compound 5 is filled into the etched metal substrate using a mold.
  • pre-encapsulation refers to the encapsulation or molding process that is performed during the lead frame manufacturing to encapsulate the lead frame before other subsequent packaging processes, such as chip mounting.
  • the pre-encapsulated lead frame After the molding compound is injected in the metal substrate, i.e., the lead frame is pre-encapsulated, the pre-encapsulated lead frame has a flat top surface comprising the exposed top surfaces of the island 1 and leads 2 and the molding compound, and a flat back surface comprising the exposed back surfaces of the island 1 and leads 2 and the molding compound.
  • a plating process may be performed on the pre-encapsulated lead frame to form the first metal layer and the second metal layer.
  • the plating process may include any appropriate type of electrical or chemical plating process, such as a multi-layer electrical plating process.
  • the plating material may include gold, nickel-gold, nickel-palladium-gold, or silver. Other materials may also be used.
  • the first metal layer may be formed on the top surfaces of the island 1 and leads 2 to provide the inner contact surface for the island 1 and inner leads for leads 2.
  • the second metal layer may be formed on back surfaces of the island 1 and leads 2 to provide the outer contact surface for the island and outer leads for leads 2.
  • the first metal layer and the second metal layer may be formed on the top surface and the back surface of the metal substrate, respectively, before the etching process.
  • the pre-encapsulated lead frame 100 may then be used in other subsequent processes in the packaging process 200 (214).
  • a die 3 may be attached on the island 1 using conductive or non-conductive adhesive material 4 in a die attaching process.
  • the size of die 3 may be larger than the size of the island 1, the adhesive material 4 does not contaminate the inner leads of the plurality of leads 2. That is, even when the area of the die 3 is outside the island, the die 3 does not touch or is above any of the plurality of leads 2.
  • the top surface of die 3 and the top surface of the inner leads of the plurality of leads 2 are connected with metal wires in a wire bonding process.
  • the inner leads, the die 3, and the metal wires are then encapsulated using encapsulation material 5.
  • encapsulation material 5 For example, molding equipment may be used to seal or encapsulate the packaging structure by the molding compound 5. Post-molding curing may also be performed such that the molding compound 5 or other plastic encapsulation materials may also be cured.
  • the disclosed lead frame structures and manufacturing methods may be applied in a variety of semiconductor packaging applications for different carriers with different substrates and filling materials.
  • the disclosed structures and methods may be used to package plastic leaded chip carrier (PLCC), plastic quad flat pack (PQFP), ball grid array (BGA), system in package (SiP) or 3D ICs, and multi-chip module, etc.
  • PLCC plastic leaded chip carrier
  • PQFP plastic quad flat pack
  • BGA ball grid array
  • SiP system in package
  • 3D ICs 3D ICs
  • multi-chip module etc.
  • a lead frame with island structure can be created using etching and pre-encapsulation.
  • Such lead frame structures and methods can be suitable for mounting large-size chips.
  • the outer leads extends to the proximity of the island such that the length of the outer leads is bigger than the length of the inner leads. That is, the plurality of leads have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate.
  • Such small-top-size and large-bottom-size lead structure can fit larger chip without causing mounting glue contamination and the chip scale can also be increased.

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A method is provided for manufacturing a lead frame structure (100) in a semiconductor packaging process. The method includes providing a metal substrate having a top surface and a back surface, forming a top surface etching pattern and a back surface etching pattern. The method also includes performing an etching process to form an island (1) and a plurality of leads (2). Outer leads of the plurality of leads (2) on the back surface extend to the proximity of the island (1) such that a length of the outer leads is greater than a length of inner leads of the plurality of leads (2) on the top surface by a predetermined amount. Further, the method includes encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the island (1) and the plurality of leads (2).

Description

A PRE-ENCAPSULATED LEAD FRAME STRUCTURE WITH ISLAND AND
MANUFACTURING METHOD
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001 ] This application claims the priority of Chinese patent application
no.201110268347.0, filed on 13/09/2011 , the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The present invention generally relates to the field of semiconductor assembly or packaging and, more particularly, to lead frame structures and related manufacturing processes.
BACKGROUND
[0003] In a conventional Quad Flat No-Lead (QFN) lead frame, it is generally required that the size of the chip to be mounted is less than the size of the island or die pad to avoid mounting glue (electrically conductive or non-conductive) contaminating the leads of the lead frame. For example, Fig. 1 shows a conventional QFN lead frame having an island 21 and leads 22. Fig. 2 shows a chip 23 is mounted on island 21 using mounting glue 24 and sealed by molding compound 25. As shown in Fig. 2, because the size of the chip 23 is larger than the size of the island 21, the chip 23 also touches the inner leads of the leads 22 and mounting glue 24 also touches or contaminates the inner leads of the leads 22. Therefore, to avoid such contamination, the size of the chip 23 to be mounted on the lead frame is limited, and the chip scale may be low. [0004] The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
BRIEF SUMMARY OF THE DISCLOSURE
[0005] One aspect of the present disclosure includes a method for manufacturing a lead frame structure in a semiconductor packaging process. The method includes providing a metal substrate having a top surface and a back surface, .forming a first photoresist film on the top surface of the metal substrate, and forming a top surface etching pattern in the first photoresist film using photolithography. The method also includes forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, and performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form an island and a plurality of leads. Outer leads of the plurality of leads on the back surface extend to the proximity of the island such that a length of the outer leads is greater than a length of inner leads of the plurality of leads on the top surface by a predetermined amount. Further, the method includes removing the first photoresist film and the second photoresist film, and encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the island and the plurality leads.
[0006] Another aspect of the present disclosure includes a lead frame structure for semiconductor packaging. The lead frame includes an island and a plurality of leads formed based on a metal substrate by an etching process, and a molding compound used to encapsulate the etched metal substrate with the island and plurality of leads. The etching process is performed by: providing the metal substrate; forming a first photoresist film on a top surface of the metal substrate; forming a top surface etching pattern in the first photoresist film using photolithography; forming a second photoresist film on a back surface of the metal substrate; forming a back surface etching pattern in the second photoresist film using photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form an island and a plurality of leads, where outer leads of the plurality of leads on the back surface extend to the proximity of the island such that a length of the outer leads is greater than a length of inner leads of the plurality of leads on the top surface by a predetermined amount; and removing the first photoresist film and the second photoresist film.
[0007] Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
BRIEF DESCRIPTION OF THE DRA WINGS [0008] Figure 1 shows a conventional QFN lead frame;
[0009] Figure 2 shows a large-size chip mounted on the conventional QFN lead frame with mounting glue contamination;
[0010] Figure 3 illustrates an exemplary pre-encapsulated lead frame structure consistent with the disclosed embodiments;
[0011] Figure 4 illustrates a large-size chip mounted on the pre-encapsulated lead frame structure; and
[0012] Figure 5 shows an exemplary packaging process based on the pre-encapsulated lead frame structure consistent with the disclosed embodiments. DETAILED DESCRIPTION
[0013] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. [0014] Fig. 3 illustrates an exemplary pre-encapsulated lead frame structure 100 consistent with the disclosed embodiments. As shown in Fig. 3, lead frame 100 includes a die pad or island 1, a plurality of leads 2, and molding compound filled in the areas between the island 1 and the leads and the areas between the leads of the plurality of leads 2. Other components may also be included and certain components may be omitted. For example, lead frame 100 may also include a first metal layer (not shown) on the top surfaces of the island 1 and leads 2 and a second metal layer (not shown) on the back surfaces of the island 1 and leads 2.
[0015] The island 1 and leads 2 may be made from a metal substrate (unnumbered). The molding compound may be filled up to the top surface and the back surface of the metal substrate (e.g., island 1 and leads 2) such that both the top surface and the back surface of the metal substrate are flat.
[0016] Lead frame structure 100 may be formed as a part of a packaging process or as an independent lead frame manufacturing process. Fig. 5 illustrates an exemplary packaging process or lead frame manufacturing process 200 consistent with the disclosed embodiments. As shown in Fig. 5, at the beginning of the packaging process 200, a metal substrate is provided (202).
[0017] The metal substrate may have a top surface and a back surface, and may also have a desired thickness. The metal substrate may be made of any appropriate metal materials, such as copper, aluminum, iron, copper alloy, stainless steel, or nickel-iron alloy. The particular metal used for metal substrate may be determined based on the functionalities and characteristics of the chips to be packaged.
[0018] After the metal substrate is provided (202), adhesive films may be attached to the top surface and the back surface of the metal substrate (204). More particularly, a first photoresist film may be attached to the top surface of the metal substrate, and a second photoresist film may be attached to the back surface of the metal substrate. The first photoresist film and the second photoresist film may be attached using certain film equipment to protect the substrate from a later etching process. Further, the first photoresist film and second photoresist film can be used in a photolithographic process, and any of the first photoresist film and second photoresist film may be a dry photoresist film or a wet photoresist film. Other types of film may also be used.
[0019] Further, etching patterns may be formed based on the first photoresist film and second photoresist film (206). More specifically, a top surface etching pattern may be formed using the first photoresist film and a back surface etching pattern may be formed using the second photoresist film via photolithography. That is, the etching patterns may be formed using a photolithographic process. A top surface etching mask is used to expose the first photoresist film, which is followed by development, and certain parts of the first photoresist film are removed to form the top surface etching pattern to uncover the areas on the metal substrate that need to be etched. Similarly, a back surface etching mask is used to expose the second photoresist film, which is followed by development, and certain parts of the second photoresist film are removed to form the back surface etching pattern to uncover the areas on the metal substrate that need to be etched. [0020] The top surface etching pattern corresponds to inner contact surface of the island 1 and inner leads of the plurality of leads 2, and the back surface etching pattern corresponds to outer contact surface of the island 1 and outer leads of the plurality of leads 2. The top surface etching pattern is designed in a way that the distance between the inner contact surface of the island 1 and inner leads of the plurality of leads 2 is substantially extended to fit a large chip. That is, the distance between the island 1 and inner leads of the plurality of leads 2 is within a predetermined range such that a large chip can be mounted on the island 1 without touching the plurality of leads 2. A large chip may refer to a chip having a surface area larger than the surface area of a corresponding island. [0021 ] On the other hand, the back surface etching pattern is designed in a way that the outer leads of the plurality of leads 2 extends to the proximity of the island 1 such that the length of the outer leads is larger than the length of the inner leads.
[0022] Further, an etching process may be performed on the top surface and back surface of the metal substrate (208). That is, the etching process is performed on the exposed areas on the top surface and back surface of the metal substrate, which are exposed by removing parts of the first and second photoresist films. The top surface of metal substrate is etched using the top surface etching pattern as a mask, and the back surface of metal substrate is etched using the back surface etching pattern as a mask.
[0023] The etching process may be a half etching and may be performed on both the top surface and the back surface simultaneously. After the etching process, the island 1, the plurality of leads 2, and certain etched areas are formed on the metal substrate. The plurality of leads 2 have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate. That is, the length of the inner leads is less than the length of the outer leads by a predetermined amount. The amount may be determined based on a particular application of the lead frame 100. For example, the lead frame 100 may have a maximum chip size that can be fitted into the lead frame 100 or onto the island 1, and the amount may be determined based on the maximum chip size. [0024] More specifically, the inner leads may retreat from the island 1 by a first value, and the outer leads may extend towards the island 1 by a second value such that the length of the outer leads is greater than the length of the inner leads based on the first value and the second value. Thus, with same size as conventional lead frames, such small-top-size and large-bottom- size lead structure can fit larger chip without causing any extra problems, such as mounting glue contamination, i.e., support a larger maximum chip size. Other types of etching, such as a full etching, may also be used.
[0025] After the etching process, the remaining adhesive films on the surfaces of metal substrate are removed (210). The films may be removed by mechanical means or chemical means. Further, the etched metal substrate is encapsulated in a molding process or a pre- encapsulating process (212). That is, molding compound 5 is filled into the etched metal substrate using a mold. The term "pre-encapsulation" refers to the encapsulation or molding process that is performed during the lead frame manufacturing to encapsulate the lead frame before other subsequent packaging processes, such as chip mounting.
[0026] After the molding compound is injected in the metal substrate, i.e., the lead frame is pre-encapsulated, the pre-encapsulated lead frame has a flat top surface comprising the exposed top surfaces of the island 1 and leads 2 and the molding compound, and a flat back surface comprising the exposed back surfaces of the island 1 and leads 2 and the molding compound. [0027] Optionally, if the lead frame 100 includes the first metal layer on the top surface of the metal substrate and the second metal layer on the back surface of the metal substrate, a plating process may be performed on the pre-encapsulated lead frame to form the first metal layer and the second metal layer. The plating process may include any appropriate type of electrical or chemical plating process, such as a multi-layer electrical plating process. The plating material may include gold, nickel-gold, nickel-palladium-gold, or silver. Other materials may also be used.
[0028] The first metal layer may be formed on the top surfaces of the island 1 and leads 2 to provide the inner contact surface for the island 1 and inner leads for leads 2. The second metal layer may be formed on back surfaces of the island 1 and leads 2 to provide the outer contact surface for the island and outer leads for leads 2. Alternatively, the first metal layer and the second metal layer may be formed on the top surface and the back surface of the metal substrate, respectively, before the etching process.
[0029] The pre-encapsulated lead frame 100 may then be used in other subsequent processes in the packaging process 200 (214). For example, as shown in Fig. 4, a die 3 may be attached on the island 1 using conductive or non-conductive adhesive material 4 in a die attaching process. Although the size of die 3 may be larger than the size of the island 1, the adhesive material 4 does not contaminate the inner leads of the plurality of leads 2. That is, even when the area of the die 3 is outside the island, the die 3 does not touch or is above any of the plurality of leads 2.
[0030] Further, the top surface of die 3 and the top surface of the inner leads of the plurality of leads 2 are connected with metal wires in a wire bonding process. The inner leads, the die 3, and the metal wires are then encapsulated using encapsulation material 5. For example, molding equipment may be used to seal or encapsulate the packaging structure by the molding compound 5. Post-molding curing may also be performed such that the molding compound 5 or other plastic encapsulation materials may also be cured.
INDUSTRIAL APPLICABILITY AND ADVANTAGEOUS EFFECTS
[0031 ] Without limiting the scope of any claim and/or the specification, examples of industrial applicability and certain advantageous effects of the disclosed embodiments are listed for illustrative purposes. Various alternations, modifications, or equivalents to the technical solutions of the disclosed embodiments can be obvious to those skilled in the art.
[0032] The disclosed lead frame structures and manufacturing methods may be applied in a variety of semiconductor packaging applications for different carriers with different substrates and filling materials. For example, the disclosed structures and methods may be used to package plastic leaded chip carrier (PLCC), plastic quad flat pack (PQFP), ball grid array (BGA), system in package (SiP) or 3D ICs, and multi-chip module, etc.
[0033] By using the disclosed methods and structures, a lead frame with island structure can be created using etching and pre-encapsulation. Such lead frame structures and methods can be suitable for mounting large-size chips. The outer leads extends to the proximity of the island such that the length of the outer leads is bigger than the length of the inner leads. That is, the plurality of leads have smaller length on top surface of the metal substrate and larger length on back surface of the metal substrate. Such small-top-size and large-bottom-size lead structure can fit larger chip without causing mounting glue contamination and the chip scale can also be increased. Reference Signs List
Island 21
Leads 22
Die 23
Adhesive material 24
Molding compound 25
Lead frame structure 100
Island 1
Leads 2
Die 3
Adhesive material 4
Molding compound 5
Packaging process 200
Providing a metal substrate 202
Attaching adhesive films 204
Forming etching patterns 206
Performing an etching process 208
Removing adhesive films 210
Pre-encapsulating the lead frame 212
Performing other packaging processes 214

Claims

What is claimed is:
1. A method for manufacturing a lead frame structure in a semiconductor packaging
process, comprising: providing a metal substrate having a top surface and a back surface; forming a first photoresist film on the top surface of the metal substrate; forming a top surface etching pattern in the first photoresist film using photolithography; forming a second photoresist film on the back surface of the metal substrate; forming a back surface etching pattern in the second photoresist film using
photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form an island and a plurality of leads, wherein outer leads of the plurality of leads on the back surface extend to the proximity of the island such that a length of the outer leads is greater than a length of inner leads of the plurality of leads on the top surface by a predetermined amount; removing the first photoresist film and the second photoresist film; and
encapsulating the etched metal substrate using a molding compound exposing top surfaces and back surfaces of the island and the plurality leads.
2. The method according to claim 1, wherein: the etching process is a half etching process.
3. The method according to claim 2, wherein: the etching process is performed on the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks.
4. The method according to claim 1, further including: performing a plating process on the metal substrate to form a first metal layer on the top surface of the metal substrate and a second metal layer on the back surface of the metal substrate, wherein the first metal layer contains an inner surface of the island and the inner leads of the plurality of leads, and the second metal layer contains an outer surface of the island and the outer leads of the plurality of leads.
5. The method according to claim 1, further including: attaching a die on the island using an adhesive material in a die attaching process, wherein a substantial area of the die is outside the island without touching the plurality of leads; connecting a top surface of the die and top surfaces of the inner leads of the plurality of leads with metal wires in a wire bonding process; and encapsulating the inner leads, the die, and the metal wires using a molding compound.
6. A lead frame structure for semiconductor packaging, comprising: an island and a plurality of leads formed based on a metal substrate by an etching process; and
a molding compound used to encapsulate the etched metal substrate with the island and plurality of leads, wherein the etching process is performed by: providing the metal substrate;
forming a first photoresist film on a top surface of the metal substrate; forming a top surface etching pattern in the first photoresist film using
photolithography; forming a second photoresist film on a back surface of the metal substrate; forming a back surface etching pattern in the second photoresist film using photolithography; performing an etching process on the top surface and the back surface of the metal substrate using the top surface etching pattern and the back surface etching pattern as the respective masks to form an island and a plurality of leads, outer leads of the plurality of leads on the back surface extending to the proximity of the island such that a length of the outer leads is greater than a length of inner leads of the plurality of leads on the top surface by a predetermined amount; and removing the first photoresist film and the second photoresist film.
7. The lead frame structure according to claim 6, wherein: the etching process is a half etching process.
8. The lead frame structure according to claim 7, wherein: the etching process is performed on the top surface and the back surface of the metal substrate simultaneously using the top surface etching pattern and the back surface etching pattern as the respective masks.
9. The lead frame structure according to claim 6, further including: a first metal layer formed on the top surface of the metal substrate and a second metal layer formed on the back surface of the metal substrate by a plating process performed on the metal substrate, wherein the first metal layer contains an inner surface of the island and the inner leads of the plurality of leads, and the second metal layer contains an outer surface of the island and the outer leads of the plurality of leads.
10. The lead frame structure according to claim 6, further including: a die attached on the island using an adhesive material by a die attaching process, wherein a substantial area of the die is outside the island without touching the plurality of leads; metal wires connecting a top surface of the die and top surfaces of the inner leads of the plurality of leads by a wire bonding process; and a molding compound encapsulating the inner leads, the die, and the metal wires.
PCT/CN2012/001161 2011-09-13 2012-08-28 A pre-encapsulated lead frame structure with island and manufacturing method Ceased WO2013037187A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111653542A (en) * 2020-06-17 2020-09-11 佛山市蓝箭电子股份有限公司 A semiconductor package lead frame

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102315191A (en) * 2011-09-13 2012-01-11 江苏长电科技股份有限公司 Novel base-island prepacked plastic packaging material lead frame structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823067A (en) * 1994-07-05 1996-01-23 Toppan Printing Co Ltd Lead frame
CN101211886A (en) * 2006-12-28 2008-07-02 日月光半导体制造股份有限公司 Packaging structure of lead frame without external pin
CN101814446A (en) * 2010-04-28 2010-08-25 江苏长电科技股份有限公司 Island expose and multi-salient-point island expose lead frame structure and carving and plating method thereof
CN102315191A (en) * 2011-09-13 2012-01-11 江苏长电科技股份有限公司 Novel base-island prepacked plastic packaging material lead frame structure
CN102324413A (en) * 2011-09-13 2012-01-18 江苏长电科技股份有限公司 Sequentially etched and plated lead frame structure with island prepacked plastic sealed material and producing method thereof
CN202259266U (en) * 2011-09-13 2012-05-30 江苏长电科技股份有限公司 Novel lead frame structure with base island and prefilled plastic sealing material

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100337317C (en) * 2005-07-18 2007-09-12 江苏长电科技股份有限公司 Novel integrated circuit or discrete component flat bump package technics and its package structure
CN101241893A (en) * 2007-02-08 2008-08-13 台湾应解股份有限公司 Chip packaging substrate and packaging structure thereof
CN201149867Y (en) * 2007-11-01 2008-11-12 矽格股份有限公司 Leadless Semiconductor Package Structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0823067A (en) * 1994-07-05 1996-01-23 Toppan Printing Co Ltd Lead frame
CN101211886A (en) * 2006-12-28 2008-07-02 日月光半导体制造股份有限公司 Packaging structure of lead frame without external pin
CN101814446A (en) * 2010-04-28 2010-08-25 江苏长电科技股份有限公司 Island expose and multi-salient-point island expose lead frame structure and carving and plating method thereof
CN102315191A (en) * 2011-09-13 2012-01-11 江苏长电科技股份有限公司 Novel base-island prepacked plastic packaging material lead frame structure
CN102324413A (en) * 2011-09-13 2012-01-18 江苏长电科技股份有限公司 Sequentially etched and plated lead frame structure with island prepacked plastic sealed material and producing method thereof
CN202259266U (en) * 2011-09-13 2012-05-30 江苏长电科技股份有限公司 Novel lead frame structure with base island and prefilled plastic sealing material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111653542A (en) * 2020-06-17 2020-09-11 佛山市蓝箭电子股份有限公司 A semiconductor package lead frame

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