[go: up one dir, main page]

WO2013035189A1 - Dispositif de prise de vue à semi-conducteur - Google Patents

Dispositif de prise de vue à semi-conducteur Download PDF

Info

Publication number
WO2013035189A1
WO2013035189A1 PCT/JP2011/070534 JP2011070534W WO2013035189A1 WO 2013035189 A1 WO2013035189 A1 WO 2013035189A1 JP 2011070534 W JP2011070534 W JP 2011070534W WO 2013035189 A1 WO2013035189 A1 WO 2013035189A1
Authority
WO
WIPO (PCT)
Prior art keywords
island
conductor layer
region
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2011/070534
Other languages
English (en)
Japanese (ja)
Inventor
舛岡　富士雄
原田　望
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisantis Electronics Singapore Pte Ltd
Original Assignee
Unisantis Electronics Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisantis Electronics Singapore Pte Ltd filed Critical Unisantis Electronics Singapore Pte Ltd
Priority to CN2011800431859A priority Critical patent/CN103119719A/zh
Priority to JP2013511423A priority patent/JP5281215B1/ja
Priority to KR1020137005981A priority patent/KR20130061723A/ko
Priority to PCT/JP2011/070534 priority patent/WO2013035189A1/fr
Priority to TW101131985A priority patent/TW201312736A/zh
Priority to US13/606,823 priority patent/US8564034B2/en
Publication of WO2013035189A1 publication Critical patent/WO2013035189A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H10F39/80373—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor characterised by the gate of the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors

Definitions

  • the present invention relates to a solid-state imaging device including an SGT (Surround Gate Transistor) in which a channel region is formed in a semiconductor having an island-shaped semiconductor structure, and to a solid-state imaging device having a pixel and a drive output circuit.
  • SGT Square Gate Transistor
  • CMOS solid-state imaging devices are widely used for video cameras, still cameras, and the like. These solid-state imaging devices are composed of a pixel and a drive output circuit connected to the pixel. Further, there is a constant demand for performance improvements such as higher pixel density, higher resolution, lower color mixing in color imaging, and higher sensitivity in solid-state imaging devices. On the other hand, technological innovations such as higher pixel density have been performed in order to achieve higher resolution of solid-state imaging devices.
  • FIG. 8A to 8D show a conventional solid-state imaging device.
  • FIG. 8A shows a cross-sectional structure diagram of a solid-state imaging device in which one pixel is configured in one island-like semiconductor 100 according to the conventional example (see, for example, Patent Document 1).
  • N + region a signal line N + region 102
  • N + region is a semiconductor region containing a lot of donor impurities on a substrate 101. .
  • a P region 103 (hereinafter, a semiconductor region containing an acceptor impurity is referred to as a “P region”) is formed on the signal line N + region 102, and an insulating layer 104 is formed on the outer periphery of the P region 103.
  • a gate conductor layer 105 is formed with the insulating layer 104 interposed therebetween.
  • An N region (hereinafter, a semiconductor region containing donor impurities is referred to as an “N region”) 106 is formed on the outer peripheral portion of the P region 103 in the upper portion of the gate conductor layer 105.
  • a P + region (hereinafter, a semiconductor region containing a lot of acceptor impurities is referred to as a “P + region”) 107 is formed on the island-shaped semiconductor 100.
  • the P + region 107 is connected to the pixel selection line conductor layer 108.
  • the insulating layers 104 described above are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100.
  • the gate conductor layers 105 are connected to each other so as to surround the outer periphery of the island-shaped semiconductor 100.
  • incident light is irradiated from the P + region 107 side on the upper surface of the island-shaped semiconductor 100.
  • a photodiode region including a P region 103 and an N region 106 is formed in the island-like semiconductor 100.
  • signal charges here, free electrons
  • This signal charge is accumulated in the N region 106 of the photodiode region.
  • a junction transistor is configured with the N region 106 as a gate, the P + region 107 as a source, and the P region 103 near the signal line N + region 102 as a drain.
  • the drain-source current (output signal) of the junction transistor changes corresponding to the amount of signal charge accumulated in the N region 106, and is extracted from the signal line N + region 102 and read out.
  • the N region 106 of the photodiode region is the source
  • the gate conductor layer 105 is the reset gate
  • the signal line N + region 102 is the drain
  • the P between the N region 106 and the signal line N + region 102 is the P between the N region 106 and the signal line N + region 102.
  • a reset MOS transistor using the region 103 as a channel is formed (hereinafter, this gate conductor layer is referred to as “reset gate conductor layer”).
  • the signal charge accumulated in the N region 106 is removed to the signal line N + region 102 by applying a plus-on voltage to the reset gate conductor layer 105 of the reset MOS transistor.
  • the imaging operation of this solid-state imaging device includes the following operations. That is, in a state where the ground voltage (0 V) is applied to the signal line N + region 102, the reset gate conductor layer 105, and the P + region 107, the photoelectric conversion region (photographing region) is irradiated by irradiation of light incident from the upper surface of the island-shaped semiconductor 100.
  • FIG. 8B is a schematic diagram of a solid-state imaging device having a drive output circuit around a pixel region in which island-shaped semiconductors P11 to P33 (corresponding to the island-shaped semiconductor 100 of FIG. 8A) constituting pixels are arranged two-dimensionally. A plan view is shown (see, for example, Patent Document 2). As shown in FIG. 8B, island-like semiconductors P11 to P33 constituting pixels are formed on the signal line N + regions 102a, 102b, and 102c (corresponding to 102 in FIG. 8A). Pixel selection line conductor layers 108a, 108b, and 108c (corresponding to 108 in FIG.
  • the reset gate conductor layers 105a, 105b, and 105c are connected to each horizontal column of the island-shaped semiconductors P11 to P33 constituting the pixel, and the pixel region It is connected to a reset line vertical scanning circuit 112 provided in the periphery.
  • This reset line vertical scanning circuit 112 includes CMOS inverter circuits 113a, 113b, 113c made of SGT connected to the respective reset gate conductor layers 105a, 105b, 105c, and a shift register 114 connected to the CMOS inverter circuits 113a, 113b, 113c.
  • the CMOS inverter circuits 113a, 113b, and 113c are configured using, for example, two P-channel SGTs and one N-channel SGT.
  • CMOS inverter circuit 113a, 113b the low-level voltage to the input terminal of the shift register 114 of 113c is applied, the reset-on voltage V RH from the output terminal is reset gate conductor layer 105a, 105b, while being applied to 105c , when the high level voltage is applied, the reset-off voltage V RL is reset gate conductor layer 105a, 105b, is applied to 105c from the output terminal.
  • the lower part of each signal line N + region 102a, 102b, 102c is connected to the switches SGT 115a, 115b, 115c, and the gate of each switch SGT 115a, 115b, 115c is connected to the signal line horizontal scanning circuit 116.
  • SGT Short Gate Transistor
  • SGT refers to a transistor having a structure in which a gate conductor layer is formed on the outer periphery of a silicon pillar via a gate insulating layer.
  • the signal line N + regions 102a, 102b, and 102c are applied with an off voltage from the signal line horizontal scanning circuit 116 to the gates of the switches SGTs 115a, 115b, and 115c, and the switch circuits 118a, 118b, and 118c by becoming the ground voltage side, condition that the ground voltage, the reset gate conductor layer 105a, 105b, a state in which the reset-off voltage V RL is applied to 105c, the pixel selection line conductor layers 108a, 108b, a ground voltage to 108c In a state where is applied.
  • a reset / off voltage VRL is applied to the reset gate conductor layers 105a, 105b, and 105c, a high-level voltage is applied to the pixel selection line conductor layers 108a, 108b, and 108c of the pixel to be read, and reading is performed.
  • An ON voltage is applied to the gates of the switches SGT 115a, 115b, and 115c connected to the pixel signal line N + regions 102a, 102b, and 102c, the output terminals of the switch circuits 118a, 118b, and 118c are floating, and the input terminal of the output circuit 117 is low.
  • the output circuit 117 takes in the source / drain current of the junction transistor of the pixel to be read out.
  • the signal charge removal operation the pixel-like semiconductors P11 to P11 for removing the accumulated signal charge are removed in a state where all the pixel selection line conductor layers 108a, 108b, and 108c are at the ground voltage and all the switches SGT115a, 115b, and 115c are off.
  • reset gate conductor layer 105a connected to the P33, 105b, reset-on voltage is applied to 105c, the switch circuits 118a, 118b, an output terminal of 118c is performed by going reset voltage V RD.
  • FIG. 8C shows a schematic plan view of a region A surrounded by a two-dot chain line in FIG. 8B.
  • the island-shaped semiconductor P11 constituting the pixel is formed on the signal line N + region 102a
  • the island-shaped semiconductor 119a constituting the N-channel SGT of the CMOS inverter circuit 113a is formed on the first semiconductor layer 120a
  • the P-channel SGT Are formed on the second semiconductor layer 120b.
  • a P well region 121a is formed above the first semiconductor layer 120a so as to be connected to a lower portion of the island-shaped semiconductor 119a constituting the N channel SGT (overlapping in the drawing).
  • An N well region 121b is formed above the second semiconductor layer 120b so as to be connected to the lower portion of the island-shaped semiconductors 119b and 119c constituting the P channel SGT (overlapping in the drawing).
  • a lower portion of the island-shaped semiconductor 119a constituting the N channel SGT and an N + region 122a connected to the lower portion are formed.
  • the N well region 121b lower portions of the island-shaped semiconductors 119b and 119c constituting the P channel SGT and a P + region 122b connected thereto are formed.
  • Drain N + region 123a of the N-channel SGT is formed on top of the island-like semiconductor 119a for N-channel, the drain N + region 123a via a contact hole 124a, the reset-off voltage V RL is applied It is connected to the first metal wiring layer 125a (shown with a one-dot chain line).
  • the drain P + regions 123b and 123c of the P channel SGT are formed on the island-shaped semiconductors 119b and 119c for the P channel, and the drain P + regions 123b and 123c are reset via the contact holes 124b and 124c. It is connected to the first-layer metal wiring layer 125b (denoted by a one-dot chain line) to which the on-voltage VRH is applied.
  • N-channel SGT and P-channel SGT gate conductor layer 126 are formed so as to be connected, and first-layer metal wiring layer 125c (denoted by an alternate long and short dash line) in which this gate conductor layer 126 is connected to shift register circuit 114 through contact hole 127a It is connected to the.
  • the reset gate conductor layer 105a of the island-shaped semiconductor P11 and the drain P + region 122b of the P-channel SGT constituting the pixel are first-layer metal wiring layers 125e (shown by alternate long and short dash lines) through contact holes 127e and 127f. It is connected.
  • the source P + region 122b of the P channel SGT and the drain N + region 122a of the N channel SGT are connected to each other by a first layer metal wiring layer 125b (shown by a one-dot chain line) via contact holes 127b and 127d. ing.
  • the P well region 121a is connected to a second metal wiring layer 128a (shown by a dotted line) located above the first metal wiring layers 125a, 125b, 125c, 125d, and 125e through a contact hole 127c. Yes.
  • the N well region 121b is connected to a second metal wiring layer 128b (shown by a dotted line) located above the first metal wiring layers 125a, 125b, 125c, 125d, and 125e through a contact hole 127e.
  • a second metal wiring layer 128a shown by a dotted line
  • FIG. 8D shows a cross-sectional structure diagram taken along the line BB ′ of FIG. 8C.
  • the cross-sectional structure of the island-shaped semiconductor P11 constituting the pixel is the same as that shown in FIG. 8A.
  • a pixel signal line N + region 102a, a first semiconductor layer 120a, and a second semiconductor layer 120b are formed on a substrate 100 (for example, a SiO 2 layer).
  • the island-shaped semiconductor P11 that forms the pixel is formed on the signal line N + region 102a, and the island-shaped semiconductor 119a that forms the N-channel SGT is formed on the first semiconductor layer 120a, and the island-shaped semiconductor that forms the P-channel SGT Semiconductors 119b and 119c are formed on the second semiconductor layer 120b.
  • a P well region 121a is formed above the first semiconductor layer 120a, and an N well region 121b is formed above the second semiconductor layer 120b.
  • a source N + region 122a is formed above the P-well region 121a and below the island-shaped semiconductor 119a constituting the N-channel SGT.
  • a source P + region 122b is formed above the N well region 121b and below the island-shaped semiconductors 119b and 119c constituting the P channel SGT.
  • a drain N + region 123a is formed on the island-shaped semiconductor 119a constituting the N channel SGT. Then, drain P + regions 123b and 123c are formed above the island-shaped semiconductors 119b and 119c constituting the P channel SGT.
  • the channel of the N-channel SGT is the P region 131a, and the source / drain of the island-shaped semiconductor constituting the P-channel SGT Between the P + regions 122b and 123b, 123c, the channels of the P channel SGT are the N regions 131b, 131c.
  • An N-channel SGT gate insulating layer 129a is formed on the outer periphery of the island-shaped semiconductor 119a constituting the N-channel SGT, and an insulating layer 132a is formed on the outer periphery of the first semiconductor layer 120a so as to be connected to the N-channel SGT gate insulating layer 129a. Is formed.
  • P-channel SGT gate insulating layers 129b and 129c are formed on the outer peripheral portions of the island-shaped semiconductors 119a and 119c constituting the P-channel SGT, and the second connected to the gate insulating layers 129b and 129c constituting the P-channel SGT.
  • An insulating layer 132b is formed on the outer periphery of the semiconductor layer 120b.
  • the reset gate conductor layer 105a of the reset MOS transistor connected to the outer periphery of the island-shaped semiconductor P11 constituting the pixel is connected to the first-layer metal wiring layer 125e through the contact hole 127f, and this first-layer metal wiring layer 125e is connected to the source P + region 122b connected to the lower part of the island-shaped semiconductors 119b and 119c constituting the P-channel SGT through the contact hole 127b.
  • the N-channel SGT and the P-channel SGT gate conductor layer 126 are formed between the island-shaped semiconductor 119a constituting the N-channel SGT and the island-shaped semiconductors 119b and 119c constituting the P-channel SGT, and between the gate insulating layers 129b and 129c.
  • the first metal wiring layer 125c is connected to the outer periphery and connected to the shift register circuit through the contact hole 127a.
  • the drain N + region 123a is connected to the first metal wiring layer 125a to which the reset / off voltage VRL is applied via the contact hole 124a.
  • the drain P + regions 123b and 123c of the P channel SGT are connected to the first metal wiring layer 125b to which the reset-on voltage VRH is applied via the contact holes 124b and 124c.
  • the first interlayer insulating layer 130a, the second interlayer insulating layer 130b, the third interlayer insulating layer 130c, the fourth interlayer insulating layer 130d, and the fifth interlayer insulating layer 130e are formed between the semiconductor P11 and on the substrate 100. Is formed.
  • the pixel reset gate conductor layer 105a is wired on the first interlayer insulating layer 130a, the P-channel / N-channel SGT gate conductor layer 126 is wired on the second interlayer insulating layer 130b, and the third interlayer insulating layer 130d.
  • the pixel selection line conductor layer 108a is wired thereon, the first metal wiring layers 125a, 125b, 125c, 125e are formed on the fourth interlayer insulating layer 130d, and the P-well is formed on the fifth interlayer insulating layer 130e.
  • a second metal wiring layer 128a connected to region 121a and a second metal wiring layer 128b connected to N well region 121b are formed.
  • the reset gate conductor layer 105a of the reset MOS transistor in the island-shaped semiconductor P11 constituting the pixel is at the bottom of the island-shaped semiconductor P11 constituting the pixel, whereas the CMOS inverter
  • the SGT gate conductor layer 126 of the circuit 113a is at the bottom of the island-shaped semiconductors 119a, 119b, and 119c constituting the SGT on the first and second semiconductor layers 120a and 120b.
  • the photodiode region of the island-shaped semiconductor P11 constituting the pixel has a height of 2.5 to 3 ⁇ m in order to efficiently absorb light incident from the upper surface of the island-shaped semiconductor P11 constituting the pixel. Necessary (see Non-Patent Document 1).
  • the height of the reset gate conductor layer 105a and the SGT gate conductor layer 126 may be about 0.1 ⁇ m or less.
  • semiconductor layers 120a and 120b having the same thickness as the sum of the signal line N + region 102a and the island-shaped semiconductor P11 constituting the pixel are formed in the drive output circuit region including the CMOS inverter circuit 113a. Thereafter, island-shaped semiconductors P11 and 119b that form SGT and island-shaped semiconductors P11 that form pixels are formed.
  • the height difference between the reset gate conductor layer 105a of the island-shaped semiconductor P11 constituting the pixel and the height direction of the SGT gate conductor layer 126 inevitably differs in the height of the island-shaped semiconductor P11 constituting the pixel. Occurs. Since the reset gate conductor layer 105a is formed on the first interlayer insulating layer 130a and the SGT gate conductor layer 126 is formed on the second interlayer insulating layer 130b, the reset gate conductor layer 105a and the SGT gate are formed. The conductor layer 126 must be formed separately. Similarly, the signal line N + region 102a and the source N + region 122a of the N channel SGT must be formed separately.
  • this solid-state imaging device requires a step of forming an SGT that constitutes the drive output circuit in addition to the step of forming the structure of the island-shaped semiconductor P11 that constitutes the pixel. This leads to a decrease in yield and an increase in cost of the solid-state imaging device.
  • a P well region 121a and an N well region 121b are formed above the first and second semiconductor layers 120a and 120b. Due to the presence of the P well region 121a and the N well region 121b, for example, current generated by leakage light incident on the first and second semiconductor layers 120a and 120b causes the source N + region 122a of the N channel SGT and the source of the P channel SGT. This prevents the CMOS inverter circuit 113a from malfunctioning by preventing it from flowing into the P + region 122b.
  • the CMOS inverter circuit 113a can be made more stable. It can be operated.
  • the N channel / P channel SGT is a drive output circuit other than the CMOS inverter circuit 113a, which is a shift register 114 of the reset line vertical scanning circuit 112, a pixel selection scanning circuit 110, a horizontal scanning circuit 116, an output circuit 117, a switch SGT 115a, 115b and 115c and switch circuits 118a, 118b, and 118c are also formed, resulting in a problem that leads to a decrease in yield and an increase in cost of the solid-state imaging device described above.
  • the reset gate conductor layer 105a of the reset MOS transistor in the island-shaped semiconductor P11 constituting the pixel is at the bottom of the island-shaped semiconductor P11 constituting the pixel, whereas in the drive output circuit
  • the SGT gate conductor layer 126 is located on the island-shaped semiconductors 119a and 119b constituting the SGT on the first and second semiconductor layers 120a and 120b, which are substantially at the same height as the upper surface of the island-shaped semiconductor P11 constituting the pixel.
  • the difference in height between the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit is as large as 2.5 to 3 ⁇ m necessary for the photodiode region of the island-shaped semiconductor P11 constituting the pixel.
  • the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit are formed on different interlayer insulating layers 130a and 130b. Therefore, inevitably, the reset gate conductor layer 105a of the reset MOS transistor and the SGT gate conductor layer 126 in the drive output circuit must be formed separately. Similarly, the signal line N + region 102a and the source N + region 122a of the N channel SGT must be formed separately.
  • the step of forming the SGT in the drive output circuit is required.
  • a solid-state imaging device in which the island-shaped semiconductor P11 that constitutes the pixel and the SGT that constitutes the drive output circuit are formed on the same substrate 100, a solid-state imaging device that can suppress a decrease in yield and an increase in cost is desired. It is done.
  • the present invention has been made in view of the above circumstances, and an object thereof is to realize a solid-state imaging device capable of suppressing a decrease in yield and an increase in cost.
  • the solid-state imaging device of the present invention includes: In a solid-state imaging device having two-dimensionally arranged pixels, and a drive output circuit that drives the pixels and reads signals from the pixels,
  • the pixel has a first island-shaped semiconductor formed on a substrate,
  • the drive output circuit has at least one second island-shaped semiconductor formed on the substrate to have the same height as the first island-shaped semiconductor,
  • the first island-shaped semiconductor is A first semiconductor region formed at the bottom of the first island-shaped semiconductor;
  • a second semiconductor region formed on the first semiconductor region and made of a semiconductor having a conductivity type opposite to that of the first semiconductor region or an intrinsic type;
  • a first gate insulating layer formed at a lower portion and an outer periphery of the second semiconductor region;
  • a first gate conductor layer formed so as to surround the first gate insulating layer;
  • a third semiconductor region formed on the outer periphery of the second semiconductor region adjacent to the first gate conductor layer and made of a semiconductor having the same conductivity type as the first semiconductor region;
  • the height of the first gate conductor layer and the second gate conductor layer may be the same.
  • a third gate conductor layer formed so as to surround a part of the second island-shaped semiconductors among the plurality of second island-shaped semiconductors; Among the two island-shaped semiconductors, the third gate conductor layer is formed so as to surround the second island-shaped semiconductor different from the second island-shaped semiconductor surrounded by the third gate conductor layer, And a fourth gate conductor layer made of a different material.
  • the heights of the third gate conductor layer and the fourth gate conductor layer may be different from each other.
  • the height of the third gate conductor layer and the fourth gate conductor layer may be the same.
  • the seventh semiconductor region is formed on the sixth semiconductor region, and a conductor layer made of a silicide layer or a metal layer is formed on the seventh semiconductor region. It can be said.
  • a metal layer may be provided so as to surround the sixth semiconductor region.
  • a conductor layer formed inside the third island-shaped semiconductor is connected to at least one of the first semiconductor region and the fifth semiconductor region at a lower portion of the third island-shaped semiconductor. It can be said that.
  • FIG. 3 is a cross-sectional structure diagram for explaining a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment.
  • FIG. 5 is a cross-sectional structure diagram for explaining a method of manufacturing a pixel and a CMOS inverter circuit of the solid-state imaging device according to the first embodiment. It is a cross-section figure for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 2nd Embodiment of this invention.
  • FIG. 1 It is a cross-sectional structure figure of the pixel and CMOS inverter circuit of the solid-state imaging device concerning a 2nd embodiment. It is a cross-section figure for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 3rd Embodiment of this invention. It is sectional structure drawing for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on 3rd Embodiment. It is sectional structure drawing for demonstrating the manufacturing method of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on 3rd Embodiment. FIG.
  • FIG. 6 is a cross-sectional structure diagram of a pixel and a CMOS inverter circuit of a solid-state imaging device according to a third embodiment. It is a cross-section figure of a pixel and CMOS inverter circuit of a solid imaging device concerning a 4th embodiment of the present invention. It is a cross-sectional structure figure of the pixel and CMOS inverter circuit of the solid-state imaging device which concern on the 5th Embodiment of this invention. It is a cross-section figure for demonstrating the manufacturing method of the pixel of the solid-state imaging device which concerns on the 6th Embodiment of this invention, and a CMOS inverter circuit.
  • FIG. 1A shows a schematic circuit diagram of a region A surrounded by a two-dot chain line in the schematic plan view of the solid-state imaging device shown in FIG. 8B.
  • the reset gate conductor layer 105 a is connected to a CMOS inverter circuit 113 a composed of two P-channel SGTs 4 aa and 4 bb and one N-channel SGT 4 cc.
  • the CMOS inverter circuit 113 a is connected to the shift register 114.
  • the reset-on voltage V RH is applied to the reset gate conductor layer 105a from the output terminal, the input terminal of the CMOS inverter circuit 113a
  • the reset-off voltage VRL is applied from the output terminal to the reset gate conductor layer 105a.
  • FIG. 1B shows a schematic plan view of FIG. 1A.
  • the signal line N + region 102a in the pixel region, the source plate N + region 3a of the N channel SGT4cc in the CMOS inverter circuit 113a region, and the source plate of the P channels SGT4aa and 4bb A shaped P + region 3b is formed.
  • an island-shaped semiconductor P11 that constitutes a pixel is formed on the signal line N + region 102a, and an island-like semiconductor 4a that constitutes an N-channel SGT4cc is formed on the source plate-like N + region 3a, and the P-channel SGT4aa, Island-like semiconductors 4b and 4c constituting P-channel SGTs 4aa and 4bb are formed on the 4bb source plate-like P + region 3b.
  • a continuous gate conductor layer 7a is formed so as to surround the island-shaped semiconductor constituting the N-channel SGT4cc and the island-shaped semiconductor constituting the P-channel SGT4aa, 4bb, and surrounds the island-shaped semiconductor P11 constituting the pixel in the horizontal direction.
  • a connected reset gate conductor layer 105a is formed.
  • a contact hole 9a is formed on the gate conductor layer 7a, and the gate conductor layer 7a is connected to the first metal wiring layer 12a (one-dot chain line) connected to the shift register 114 via the contact hole 9a.
  • a contact hole 9b is formed on the reset gate conductor layer 105a, and the reset gate conductor layer 105a is connected to the first metal wiring layer 12e (one-dot chain line) through the contact hole 9b.
  • a contact hole 9c is formed on the boundary between the source plate N + region 3a of the N channel SGT4cc and the source plate P + region 3b of the P channels SGT4aa and 4bb, and the N channel SGT4cc of the N channel SGT4cc is formed via the contact hole 9c.
  • the source plate N + region 3a and the source plate P + regions 3b of the P channels SGT4aa and 4bb are connected to the first metal wiring layer 12e (one-dot chain line).
  • Drain N + region 8b of the drain N + region on 8a at the top of the island-like semiconductor 4a constituting the N-channel SGT4cc to form a contact hole 11a, the top of the island-like semiconductor 4b constituting P-channel SGT4aa, the 4bb, Contact holes 11b and 11c are formed on 8c.
  • the drain N + region 8a is connected to the first metal wiring layer 12b (one-dot chain line) to which the reset low level voltage VRL is applied via the contact hole 11a, and the drain P + regions 8b and 8c are in contact with each other.
  • the holes are connected to the first metal wiring layers 12c and 12d (one-dot chain lines) to which the reset high level voltage VRH is applied through the holes 11b and 11c.
  • the first metal wiring layers 12c and 12d are connected to the second metal wiring layer 14 (dotted line) to which the reset on voltage VRH is applied.
  • FIG. 1C shows a cross-sectional structure diagram along line AA ′ of FIG. 1B.
  • the cross-sectional structure of the island-shaped semiconductor P11 constituting the pixel is the same as that shown in FIG. 8D.
  • a signal line N + region 102a of a pixel, a source N + region 3a of an N channel SGT 4cc, and a source P + region 3b of P channels SGT 4aa and 4bb are formed on the substrate 1 (for example, SiO 2 layer).
  • the island-shaped semiconductor P11 constituting the pixel is formed on the signal line N + region 102a, and the island-shaped semiconductor 4a constituting the N-channel SGT4cc is formed on the source semiconductor layer N + region 3a to constitute the P-channel SGT4aa and 4bb. Insulating semiconductors 4a and 4b are formed on the source P + region 3b.
  • the source N + region 3a is connected to the lower portion of the island-shaped semiconductor 4a constituting the N-channel SGT4cc
  • the source P + region 3b is connected to the lower portion of the island-shaped semiconductors 4b and 4c constituting the P-channel SGT4aa and 4bb. .
  • the channel P region 5a of the N channel SGT4cc is connected to the source N + region 3a, the channel N regions 5b and 5c of the P channels SGT4aa and 4bb are connected to the source P + region 3b, and the signal line N + region 2 of the pixel is connected. It is connected to the channel of the reset MOS transistor and the P region which becomes the drain of the junction transistor (the channel semiconductor regions 5a, 5b and 5c, and the P region 5d region of the island-shaped semiconductor P11 constituting the pixel may be an intrinsic type. ).
  • a gate insulating layer 6a of the N-channel SGT4cc is formed on the outer periphery of the island-shaped semiconductor 4a constituting the N-channel SGT4cc connected to the source N + region 3a, and P-channel SGT4aa and 4bb connected to the source P + region 3b are formed.
  • Gate insulating layers 6b and 6c of P-channel SGTs 4aa and 4bb are formed on the outer periphery of the island-shaped semiconductors 4b and 4c.
  • a reset MOS gate insulating film 6d is formed on the outer periphery of the island-shaped semiconductor P11 constituting the pixel connected to the signal line N + region 102a of the pixel.
  • the outer periphery of the gate insulating layer 6a of the N-channel SGT4cc and the gate insulating layers 6b and 6c of the P-channel SGT4aa and 4bb is connected to the first interlayer insulating layer 14a formed on the substrate 1 and connected to the N-channel P Gate conductor layers 7a of channels SGT4aa, 4bb, 4cc are formed.
  • the reset gate conductor layer 105a of the pixel includes the outer periphery of the gate insulating film 6d of the reset MOS, and is connected to the first interlayer insulating layer 14a.
  • a drain N + region 8a is formed in the island-like semiconductor 4a constituting the N-channel SGT4cc adjacent to the upper portion of the N-channel SGT4cc gate conductor layer 7a.
  • Drain P + regions 8b and 8c are formed in the island-like semiconductors 4b and 4c constituting the channels SGT4aa and 4bb.
  • a photodiode region composed of a P region 5d and an N region 8d formed so as to surround the P region 5d is formed in the island-shaped semiconductor P11 constituting the pixel adjacent to the upper portion of the reset gate conductor layer 105a of the pixel.
  • the drain N + region 8a of the N channel SGT4cc and the drain P + regions 8b, 8c of the P channels SGT4aa, 4bb are formed so as to be connected to the top surfaces of the island-like semiconductors 4a, 4b, 4c constituting the SGT.
  • the pixel selection P + region 10 is formed on the upper surface of the island-shaped semiconductor P11 constituting the pixel.
  • the pixel selection P + region 10 is connected to a pixel selection line conductor layer 108a formed on the third interlayer insulating layer 14c on the second interlayer insulating layer 14b.
  • N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a is formed on fourth interlayer insulating layer 14d through contact hole 9a, and is connected to first-layer metal interconnection layer 12a connected to the shift register. ing.
  • the drain N + region 8a above the island-shaped semiconductor 4a constituting the N channel SGT4cc is connected to the first metal wiring layer 12b to which the reset off voltage VRL is applied via the contact hole 11a.
  • the drain P + regions 8b and 8c above the island-shaped semiconductors 4b and 4c constituting the P-channel SGT are applied to the first layer metal to which the reset-on voltage VRH is applied via the contact holes 11b and 11c.
  • the wiring layers 12c and 12d are connected.
  • the reset gate conductor layer 105a of the pixel is electrically connected to the source N + region 3a of the N channel SGT4cc and the source P + region 3b of the P channels SGT4aa and 4bb on the fourth interlayer insulating layer 14d through the contact hole 9b. Is connected to the first-layer metal wiring layer 12e.
  • the first-layer metal wiring layers 12c and 12d are formed on the fifth interlayer insulating layer 14e through the contact holes 15a and 15b, and the second-layer metal wiring to which the reset-on voltage VRH is applied. Connected to layer 16.
  • the solid-state imaging device of this embodiment has the following structural features.
  • the first feature is that a semiconductor containing donor or acceptor impurities of the source N + region 3a, the P + region 3b, and the signal line N + region 102a of the N channel / P channel SGT4aa, 4bb, 4cc directly on the substrate 1. Regions are formed and they are formed in the same layer.
  • the second feature is that an N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a and a pixel reset gate conductor layer 105a are formed on the same first interlayer insulating layer 14a, and each island-shaped It is formed on the outer periphery of the gate insulating films 6a, 6b, 6c, 6d connected to the bottoms of the semiconductors 4a, 4b, 4c, P11, and is formed in the same layer.
  • the third feature is that the SGT channel P region 5a or N regions 5b and 5c and the pixel reset MOS channel P region 5d are formed in the same layer.
  • the fourth feature is that the drain N + region 8a of the N-channel SGT4cc and the drain P + regions 8b, 8c of the P-channel SGT4aa, 4bb are arranged on the island-shaped semiconductors 4a, 4b, 4c constituting the SGT.
  • the N region 8d and the selective P + region 10 constituting the photodiode are formed in the same layer.
  • the present embodiment has the following advantages.
  • the first advantage is that in the solid-state imaging device of the conventional example (FIG. 8D), the island-shaped semiconductors 119a, 119b, and 119c constituting the SGT and the island-shaped semiconductor P11 constituting the pixel are individually formed.
  • the island-shaped semiconductors 4a, 4b, and 4c constituting the SGT and the island-shaped semiconductor P11 constituting the pixel can be formed in the same process.
  • the second advantage is that the N + region 3a of the N channel SGT4cc and the source P + region 3b of the P channels SGT4aa and 4bb are formed directly on the substrate 1, so that the conventional solid state imaging device (FIG. 8D) is used.
  • a third advantage is that the N + region 3a of the N-channel SGT4cc formed individually in the conventional solid-state imaging device (see FIG. 8D) can be formed in the same process as the pixel signal line N + region 102a. It is.
  • the fourth advantage is that in the conventional solid-state imaging device (see FIG. 8D), the N-channel / P-channel SGT4aa, 4bb, 4cc gate conductor layer 7a and the pixel reset gate conductor layer 105a are formed in the same process. This is a possible point.
  • a fifth advantage is that contact holes 9a and 9b formed on the gate conductor layers 7a and 105a, which are individually formed in the solid-state imaging device of the conventional example (see FIG. 8D), can be formed in the same process.
  • the solid-state imaging device of the present invention can be manufactured with a smaller number of processes than the conventional solid-state imaging device. Thereby, cost reduction of a solid-state imaging device is implement
  • a manufacturing method for forming the solid-state imaging device according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2Q, and AA ′ in the plan view of the pixel portion and CMOS inverter circuit portion in FIG. 1B.
  • the manufacturing method which forms the cross-sectional structure along a line is shown.
  • a single crystal semiconductor silicon layer (hereinafter simply referred to as “Si layer”) 22 is formed on a SiO 2 substrate 21.
  • the SiO 2 layer 23 formed by oxidizing the Si layer 22 surface, and the silicon nitride layer on the SiO 2 layer 23 (which is hereafter written as SiN layer) 24, CVD (Chemical Vapor Deposition ) method using SiO 2 layer 25 Form.
  • the SiO 2 layer 25 by the CVD method serves as an etching mask in etching the Si layer 22 by the RIE (Reactive Ion Etching) method.
  • the SiN layer 24 serves as a stopper layer in planarizing a CMP (Chemical Mechanical Polishing) SiO 2 film in a later process.
  • the SiO 2 layer 23 on the Si layer 22 serves as a buffer layer for stress relaxation between the Si layer 22 and the SiN layer 24.
  • the silicon layer constituting the N channel SGT is etched by etching the Si layer 22 of the N channel SGT part, the P channel SGT part, and the pixel part using the SiO 2 layer 25 as an etching mask.
  • Si pillar will be referred to as “Si pillar”.
  • 26a, Si pillars 26b and 26c constituting the P channel SGT, and Si pillar 26d constituting the pixel are formed, and a plate-like Si is formed at the bottom of the Si layer 22.
  • the layers 22a and 22b are left.
  • etching plate Si layer 22a, the Si layer 22 of 22b region to SiO 2 substrate 21 surface, then Si pillars 26a, 26b, 26c, by forming 26d form the structure of FIG. 2B.
  • SiO 2 layers 27a, 27b, 27c, and 27d are formed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d and the plate-like Si layers 225a and 22b.
  • polycrystalline Si layers 28a, 28b, 28c, and 28d are formed surrounding the SiO 2 layers 27a, 27b, 27c, and 27d of the Si pillars 26a, 26b, 26c, and 26d, and a photoresist layer is formed except for the P-channel SGT portion.
  • the polycrystalline Si layers 28a, 28b, 28c, 28d are stopper layers for preventing boron ions from being implanted into the Si pillars 26a, 26b, 26c, 26d when boron ions are implanted.
  • the photoresist layer 29 is removed, and the plate-like Si layer 22a and the pixel-like plate-like Si layer 22b in the N-channel SGT portion are formed by the same photolithography technique and donor impurity phosphorus (P) or arsenic (As) ion implantation. N + regions are formed.
  • the polycrystalline Si layers 28a, 28b, 28c, 28d are removed and heat treatment is performed, so that the Si pillars 26a, 26b, 26c, N + regions 31a, 31c, and P + regions 31b connected to the lower portion of 26d are formed.
  • a photoresist layer 32 is formed by photolithography so as to cover the Si pillars 26b and 26c constituting the P channel SGT, and ion implantation of acceptor impurities such as boron (B) is further performed. Then, P regions 33a and 33d are formed in the Si pillar 26a constituting the N channel SGT and the Si pillar 26d constituting the pixel. Thereafter, the photo resist layer 32 is removed.
  • a photoresist layer is formed by photolithography so as to cover the Si pillar 26a constituting the N channel SGT and the Si pillar 26d constituting the pixel, and arsenic (As), phosphorus (P).
  • As arsenic
  • P phosphorus
  • N regions 33b and 33c are formed in the Si pillars 26b and 26c constituting the P channel SGT by performing ion implantation of donor impurities such as the above and further removing the photo resist layer and performing heat treatment.
  • the first interlayer insulating layer 34a is formed, and the SiO 2 layers 27a, 27b, 27c, 27d are removed (at the same time, the SiO 2 layers 25a, 25b, 25c, 25d are removed).
  • the gate insulating layers 35a, 35b, 35c, and 35d made of a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 ) are formed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d.
  • polycrystalline Si, tungsten (W), cobalt (Co), platinum (Pt), silicide material by CVD (Chemical Vapor Deposition) method so as to surround the Si pillars 26a, 26b, 26c, and 26d on the interlayer insulating layer 34a Is formed on the gate region of the N channel / P channel SGT, and the photo resist layer 37a is formed on the pixel reset gate region.
  • CVD Chemical Vapor Deposition
  • the first interlayer insulating layer 34a is formed by depositing a SiO 2 film to a position higher than the Si pillars 26a, 26b, 26c, and 26d by the CVD method, and forming the Si pillars 26a, 26b, 26c, and 26d by the CMP (Chemical Mechanical Polishing) method. It is formed by polishing and flattening to a height and then performing etching by RIE (hereinafter referred to as etch back).
  • etch back etch back
  • the SiN so as to surround the plate-like N + regions 31a and 31c, the plate-like P + region 31b, and the Si pillars 26a, 26b, 26c, and 26d on the SiO 2 substrate 1.
  • a film may be deposited and the SiN film surrounding the Si pillars 26a, 26b, 26c, and 26d may be removed after the SiO 2 film is etched back.
  • the SiN film serves as a protective film for preventing the Si pillars 26a, 26b, 26c, and 26d from being etched during the etch back.
  • the conductor layer 36 is etched using the photoresist layers 37a and 37b as a mask. Thereafter, the photoresist layers 37a and 37b are removed. Subsequently, as shown in FIG. 2H, a second interlayer insulating layer 34b is formed. Similarly to the first interlayer insulating film 34a, the second interlayer insulating layer 34b is also formed by SiO 2 film deposition by the CVD method, SiO 2 film polishing by the CMP method, and etch back by the RIE method.
  • the gate conductor layers 36aa and 36bb exposed so as to surround the Si pillars 26a, 26b, 26c and 26d without being covered with the second interlayer insulating layer 34b are etched.
  • an N-channel / P-channel SGT gate conductor layer 36a and a pixel reset gate conductor layer 36b are formed.
  • the N-channel / P-channel SGT gate conductor layer 36a is formed so as to surround the outer periphery of the lower portion of the Si pillars 26a, 26b, and 26c constituting the SGT and to be connected to the first interlayer insulating layer 34a.
  • an SiN layer 38 is formed on the second interlayer insulating layer 34b, and an SiO 2 layer 39 formed by CVD is formed so as to cover the second interlayer insulating layer 34b and the Si pillar.
  • a SiN layer 40 is formed on the formed and planarized SiO 2 layer 39, and a photoresist layer 41 in which holes are formed in the Si pillars 26b and 26c constituting the P channel SGT is formed using a photolithography technique.
  • SiN layer 38 plays a role of etch quenching stopper layer of the SiO 2 layer 39
  • SiN layer 40 on the SiO 2 layer 39 serves as an etching mask layer of SiO 2 layer 39.
  • the SiN layer 40 on the Si pillars 26b and 26c constituting the P-channel SGT is etched using the photoresist layer 41 as a mask, and after removing the photoresist layer 41, an SiO 2 layer is formed using the SiN layer 40 as an etching mask. 39 is etched to the surface of the SiN layer 38 by RIE. Thereafter, the gate insulating layers 35b and 35c on the outer periphery of the Si pillars 26b and 26c are removed.
  • a SiO 2 layer 42b containing an acceptor impurity such as boron (B) is formed by a CVD method.
  • the SiO 2 layer 42b containing the acceptor impurity is first deposited up to the SiN layer 40, and then polished to the SiN layer 40 by CMP to form a flat surface.
  • the SiN layer 40 is removed, a new SiN layer 43 is deposited, and a hole is formed on the Si pillar 26a constituting the N channel SGT of the SiN layer 43 by forming a resist layer by photolithography and SiN etching. To do.
  • the SiN layer 43 as an etching mask, the SiO 2 layer 39 is etched to the surface of the SiN layer 36.
  • a SiO2 layer 42a containing donor impurities such as phosphorus (P) and arsenic (As) is formed.
  • donor impurities and acceptor impurities are diffused from the SiO 2 layers 42a and 42b formed by the CVD method in the Si pillars 26a, 26b, and 26c, and N + in the Si pillars 26a, 26b, and 26c.
  • Region 37a and P + regions 37b and 37c are formed.
  • the SiON containing donor impurities is formed on the SiN layer 38 in the Si pillar 26d region constituting the pixel.
  • a two- layer 42c is formed, and an N region 43 is formed on the outer periphery of the Si pillar 26d by heat treatment.
  • the amount of donor impurities contained in the SiO 2 layer 42c is less than that of the SiO 2 layer 42a for forming the N + region 37a.
  • the SiO 2 layers 39, 42a, 42b, and 42c are removed.
  • the surfaces of the Si pillars 26a, 26b, 26c, and 26d where the Si surface is exposed are oxidized to form SiO 2 layers 45a, 45b, 45c, and 45d.
  • the SiN layers 24a, 24b, 24c, 24d, and 38 are removed to form a third interlayer insulating layer 34c. Boron (B) using the photolithography technique and the photoresist layer formed thereby as a mask.
  • the P + region 47 is formed on the Si pillar 26d constituting the pixel by ion implantation of acceptor impurities such as.
  • Si pillars 26a, 26b, 26c, the SiO 2 layer 23a on the 26 d, 2b, 23c, and 23d, the SiO 2 layer at the top than the third interlayer insulating layer 34c is removed.
  • a pixel selection line conductor layer 48 such as aluminum (Al), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN) is formed, and a fourth interlayer insulating layer 34d is formed thereon, and a gate A contact hole 50a is formed on the conductor layer 36a, contact holes 50b, 50c and 50d are formed on the Si pillars 26a, 26b and 26c constituting the SGT, and a contact hole 50e is formed on the pixel reset gate conductor layer 36b.
  • the SGT gate conductor layer 36a and the first metal wiring layer 51a Si pillar 26a constituting the SGT, 26b, 26c of N + regions 37a, P + regions 37b, 37c and the first layer metal interconnection layers 51b, 51c, 51d and the reset gate conductor layer 36b and the first layer metal Connection to the wiring layer 51e is performed.
  • a fifth interlayer insulating layer 34e is formed, contact holes 51a and 51b are formed, and the first metal wiring layers 51c and 51d are formed through the contact holes 51a and 51b. Are connected to the second metal wiring layer 52.
  • FIG. 3E shows a cross-sectional structure of the solid-state imaging device according to the present embodiment
  • FIGS. 3A to 3D show a manufacturing method leading to this
  • 3A to 3E show a cross-sectional structure along the line AA ′ in the plan view of the pixel portion and CMOS inverter circuit portion in FIG. 1B, as in FIGS. 2A to 2Q.
  • the N-channel / P-channel SGT gate conductor layer 7a is formed by being connected with the same material, whereas in the solid-state imaging device of the present embodiment, a plurality of gates formed with different materials. It is characterized by being composed of a conductor layer.
  • the technical idea of the present invention is applied to a solid-state imaging device in which an N-channel SGT and a pixel gate conductor layer are formed of the same material and a P-channel SGT gate conductor layer is formed of different materials.
  • the gate insulating layers 35a, 35b, and 35c made of a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 ) are disposed on the outer periphery of the Si pillars 26a, 26b, 26c, and 26d. , 35d and surrounding the Si pillars 26a, 26b, 26c, 26d on the first interlayer insulating layer 34a, for example, polycrystalline Si, tungsten (W), cobalt (Co) by CVD (Chemical Vapor Deposition) method Then, a conductor layer 36 of platinum (Pt) and a silicide material is formed.
  • a high dielectric constant insulating material such as SiO 2 and hafnium oxide (HfO 2 )
  • a SiN layer 55 is deposited on the entire surface.
  • the photoresist layers 56a.. are covered by photolithography so as to cover the N channel SGT portion and the pixel portion. 56b is formed.
  • the SiN layer 55 and the conductor layer 36 are etched using the photoresist layers 56a and 56b as a mask.
  • the SiN layers 55a and 55b are formed by etching so as to be side-etched inside the regions covered with the photoresist layers 56a and 56b.
  • the photoresist layers 56a and 56b are removed.
  • an N channel SGT part conductor layer 57a covering the N channel SGT part and a pixel part conductor layer 57b covering the pixel part are formed.
  • a second conductor layer 58 is formed so as to cover the entire structure.
  • a photoresist layer 59 is formed by using a photolithography technique so as to cover the P channel SGT portion.
  • the second conductor layer 58 is etched to form a P-channel SGT portion conductor layer 58a.
  • the photoresist layer 59 is removed.
  • the SiN layers 55a and 55b here serve as etching protective films for the N-channel SGT portion conductor layer 57a and the pixel portion conductor layer 57b in the etching of the conductor layer 58.
  • the SiN layers 55a and 55b are removed.
  • N channel SGT part conductor layer 57a, P channel SGT part conductor layer 58a, and pixel part conductor layer 57b are etched using first interlayer insulating layer 34a as a mask to form N channel SGT part gate conductor layer 57aa and P channel SGT.
  • the part gate conductor layer 58bb and the pixel part reset gate conductor layer 57bb are formed.
  • the N channel SGT gate conductor layer 57aa, the P channel SGT gate conductor layer 58bb, and the pixel portion reset gate conductor layer 57bb are connected to the gate insulating layer 35a on the outer periphery of the Si pillar 26a constituting the N channel SGT and the P channel SGT.
  • 3F is the same as FIG. 2Q except that the P-channel SGT part gate conductor layer 58bb is different from the N-channel SGT part gate conductor layer 57aa and the pixel part gate conductor layer 57bb.
  • the second embodiment of the present invention has the same features as the first embodiment.
  • the P region 33aa of the Si pillar 26a constituting the N channel SGT, the Si pillar 26bb constituting the P channel SGT, the N regions 33b and 33c of 26cc, and the P region 33d of the Si pillar constituting the pixel are intrinsic types. Also good.
  • the threshold voltages of the N channel / P channel SGT and the pixel reset transistor are set according to the work functions of the gate conductor layers 57aa, 58bb, and 57bb.
  • the photolithography process for forming the P regions 33a and 33d and the N regions 33b and 33c described with reference to FIGS. 2E and 2F in the first embodiment, and the ion implantation process of acceptor impurities and donor impurities are performed. It becomes unnecessary.
  • FIG. 4D shows a cross-sectional structure of the solid-state imaging device according to the present embodiment
  • FIGS. 4A to 4C show a manufacturing method leading to FIG. 4D
  • 4A to 4D show the pixel portion of FIG. 1B and the cross-sectional structure along the line AA ′ in the plan view of the CMOS inverter circuit portion, as in FIGS. 2A to 2Q.
  • FIG. 4D shows a cross-sectional structure of the solid-state imaging device according to the present embodiment
  • FIGS. 4A to 4C show a manufacturing method leading to FIG. 4D
  • 4A to 4D show the pixel portion of FIG. 1B and the cross-sectional structure along the line AA ′ in the plan view of the CMOS inverter circuit portion, as in FIGS. 2A to 2Q.
  • the N + region 8a which is the drain of the N channel SGT and the P + region 8b which is the drain of the P channel SGT above the Si pillars 4a, 4b and 4c constituting the SGT.
  • 8c are connected to the first metal wiring layers 12b, 12c, 12d through the contact holes 11a, 11b, 11c from the upper surfaces of the Si pillars 4a, 4b, 4c.
  • the drain resistance of the N channel / P channel SGT is determined by the resistance values of the N + region 8a and the P + regions 8b and 8c. The smaller the resistance value, the better.
  • the present embodiment is characterized in that the electrical resistance value is reduced by forming the upper portion of the N + region 8a and the P + regions 8b and 8c as a silicide layer.
  • FIG. 4A the process before the SiN layer 38 in FIG. 2M is formed on the first interlayer insulating layer 34a is formed in the same process as in FIGS. 2A to 2L, and a new SiN layer 38a is formed in the first interlayer insulating layer 34a.
  • the N + region 37a and the Si pillars 26b and 26c constituting the P channel SGT are formed on the insulating layer 34a and formed on the Si pillar 26a constituting the N channel SGT through the same process as shown in FIGS. 2M and 2N.
  • P + regions 26b and 26c are formed on the upper portion, an N region 43 is formed on the outer periphery of the upper portion of the Si pillar 26d constituting the pixel, and a P + region 47 is formed on the upper surface of the Si pillar 26d constituting the pixel.
  • 26c, and 26d the cross-sectional structure in the case where the insulating layers 45a, 45b, 35c, and 45d are formed on the outer peripheral portion is shown.
  • the insulating layers 45a, 45b, 45c on the outer periphery of the Si pillars 26a, 26b, 26c constituting the N-channel / P-channel SGT are removed.
  • the entire structure is covered with, for example, tungsten (W), platinum (Pt), nickel (Ni), cobalt (Co), or a metal layer 54 containing these, and heat treatment is performed.
  • the silicide layers 55a, 55b, and 55c are formed on the Si pillars 26a, 26b, and 26c constituting the N channel / P channel SGT.
  • N + regions 56a and P + regions 56b and 56c are formed below the silicide layers 55a, 55b and 55c. It is formed. Thereafter, the metal layer 54 is removed.
  • the N + region 56a and the P + regions 56b and 56c become the drains of the N channel / P channel SGT, and the N + region 56a, the P + regions 56b and 56c, and the first metal wiring layers 51b, 51c and 51d. Is performed through silicide layers 55a, 55b, and 55c having lower electrical resistance values.
  • tungsten (W), platinum (Pt), nickel (Ni), and cobalt (N) are enclosed so as to surround the N + region 55 a, the P + region 55 b, and the P + region 55 c.
  • Co or metal layers 56a, 56b and 56c containing them.
  • the SiO 2 layer 45d formed on the outer periphery of the Si pillar 26d constituting the pixel is connected to the P + region on the upper surface of the Si pillar 26d constituting the pixel at the same time.
  • the pixel selection line metal layer 56d surrounding the pixel selection line, it is not necessary to separately form the pixel selection line conductor layer 108a in FIG. 1C.
  • the pixel selection line conductor layer 108a is formed so as to surround the N region 43 of the photodiode portion which is a photoelectric conversion region, so that light incident on the Si pillar 26d constituting the pixel from an oblique direction can be obtained.
  • the pixel selection line conductor layer 108a is formed so as to surround the N region 43 of the photodiode portion which is a photoelectric conversion region, so that light incident on the Si pillar 26d constituting the pixel from an oblique direction can be obtained.
  • silicide layers 55a, 55b, and 55c are provided on the drain N + region 56a in the N channel SGT and the drain P + regions 56b and 56c in the P channel SGT.
  • the electrical resistance values between the drain N + region 56a and P + regions 56b and 56c and the first metal wiring layers 51b, 51c and 51d are lowered.
  • the present embodiment is characterized in that copper (Cu) metal layers 58a, 58b, and 58c are formed in place of the silicide layers 55a, 55b, and 55c, as shown in FIG.
  • the electrical resistance value between the drain N + region 56a and P + regions 56b and 56c and the first metal wiring layers 51b, 51c and 51d can be further reduced.
  • the Cu metal layers 58a, 58b, and 58c are formed by the damascene technique, the N + regions 56a and P + are interposed between the Cu metal layers 58a, 58b, and 58c and the insulating layers 57a, 57b, and 57c.
  • a material layer such as TiN, TaN, or Cu for preventing reaction / diffusion with the Cu metal layers 58a, 58b, 58c and maintaining adhesion of the Cu metal layers 58a, 58b, 58c on the upper surfaces of the regions 56b, 56c.
  • barrier seed layers 59a, 59b and 59c are formed.
  • FIG. 7C shows a cross-sectional structure diagram of the solid-state imaging device of the present embodiment
  • FIGS. 7A and 7B show a manufacturing method leading to that.
  • the N-channel / P-channel SGT gate conductor layer 7a and the reset gate conductor layer 105a of the pixel are connected to the first metal wiring layer 12a, deep contact holes 9a, 9b. 12e.
  • These contact holes 9a and 9e are formed by etching the N-channel / P-channel SGT gate conductor layer 7a and the first, second and third interlayer insulating layers 14a, 14b and 14c on the reset gate conductor layer 105a of the pixel. To do. In this case, it is necessary to stop the etching of the deep contact holes 9a and 9b on the N-channel / P-channel SGT gate conductor layer 7a and the pixel reset gate conductor layer 105a with good control. Further, the N channel / P channel SGT gate conductor layer 7a and the pixel reset gate conductor layer 105a and the pixel reset gate conductor layer 7b are not removed by the overetching at this time. It is necessary to increase the thickness. This embodiment can further improve such manufacturing difficulties.
  • insulating layers 35e and 35f are formed on the outer peripheral portions of the Si pillars 26e and 26f constituting the gate conductor layer contact.
  • the first interlayer insulating layer 34a is formed, and the SGT gate conductor layer 36aa is formed so as to surround the Si pillars 26a, 26b, 26c constituting the SGT and the Si pillar 26e constituting the gate conductor layer contact.
  • the pixel reset gate conductor layer 36bb is formed so as to surround the Si pillar 26d constituting the pixel and the Si pillar 26f constituting the gate conductor layer contact.
  • the gate conductor layer 36aa and the reset gate conductor layer 36bb are wired on the first interlayer insulating layer 34a, and the second interlayer insulating layer 34b so as to surround the Si pillars 26a, 26b, 26c, 26d, 26e, and 26f. Formed at the same height.
  • the previous steps are basically the same as those shown in FIGS. 2A to 2I.
  • the silicide layers 55a, 55b, and 55c and the drain N + regions 56a and P + regions 56b and 56c in the SGT are formed on the Si pillars 26a, 26b, and 26c constituting the SGT. Then, the silicide layers 55a, 55b, and 55c are removed. Thereby, as shown in FIG. 7B, holes 60a, 60b, and 60c are formed on the drain N + region 56a and the P + regions 56b and 56c of the Si pillars 26a, 26b, and 26c constituting the SGT.
  • the Si layers 33e and 33f of the Si pillars 26e and 26f constituting the gate conductor layer contact are etched to a position lower than the upper end positions of the gate conductor layer 36aa and the pixel reset gate conductor layer 36bb.
  • the SiO 2 layers 35e and 35f exposed by this etching are removed to form holes 60d and 60e.
  • a conductive material layer such as TiN, TaN, or Cu for preventing the reaction / diffusion with Cu and maintaining the adhesion of the Cu metal layer 62, which is necessary for the formation of the Cu layer 62 by the damascene technology.
  • the barrier seed layer 61 is formed on the inner surfaces of the holes 60a, 60b, 60c, 60d, 60e and the fourth interlayer insulating layer 34d. Then, a Cu layer 62 is formed in the holes 60a, 60b, 60c, 60d, and 60e and on the fourth interlayer insulating layer 34d by plating. As a result, the SGT gate conductor layer 33aa and the pixel reset gate conductor layer 36bb are electrically connected to the Cu layer 62 via the barrier / seed layer 61 which is a conductor material layer.
  • the Cu layer 62 and the barrier / seed layer 61 are etched to form first metal wiring layers 62a, 62b, 62c, 62d, and 62e.
  • the entire structure is covered with the fifth interlayer insulating layer 34e, contact holes 63a and 63b are formed on the P-channel SGT first-layer metal wiring layers 62c and 62d, and the P-channel SGT first-layer is formed.
  • the metal wiring layers 62c and 62d are connected to the second metal wiring layer 64 formed on the fifth interlayer insulating layer 34e through contact holes 63a and 63b.
  • the etching of the Si layers 33e and 33f of the Si pillars 26e and 26f constituting the gate conductor layer contact is performed to a position lower than the upper end positions of the gate conductor layer 36aa and the pixel reset gate conductor layer 36bb. may be etched, it may be etched until the SiO 2 substrate 21 upper surface. For this reason, this etching process becomes easy. Further, in this etching, since the SGT gate conductor layer 36aa and the reset gate conductor layer 36bb are protected by the SiO 2 layers 35e and 35f, as shown in FIG. 1C, the gate conductor layer 36aa, the pixel reset gate It is not necessary to increase the thickness of the conductor layer 36bb.
  • the SGT gate conductor layer 36aa and the pixel reset gate conductor layer 36bb surround the Si pillars 26e and 26f constituting the gate conductor layer contact, the Si pillar 26d constituting the pixel, and the Si pillars 26a, 26b and 26c constituting the SGT. , Simultaneously and at the same height. This facilitates the manufacturing process as described above.
  • the silicide layers 55a, 55b, and 55c are all removed. However, some silicide on the drain N + region 56a and the P + regions 56b and 56c may remain. . Further, the silicide layers 55a, 55b, and 55c may be replaced with N + regions 8a and P + regions 8b and 8c as shown in FIG. 1C. Further, the metal material formed inside the holes 60a, 60b, 60c, 60d, and 60e may be a conductive material layer containing W, Co, Ni, Ti, or these substances instead of Cu.
  • the island-shaped semiconductors P11 to P33 constituting the pixel are present in the pixel region, and the SGT is present in the drive output circuit.
  • the SGT is present in the pixel region. Needless to say, the technical idea of the present invention can be applied even when the SGTs are formed adjacent to each other.
  • the N regions 8d and 43 constituting the photodiode are formed on the outer surface of the Si pillar P11 constituting the island-like semiconductor constituting the pixel.
  • the charge on the surface of the Si pillar P11 that forms the pixel on the outer periphery of the N regions 8d and 43 is opposite to the signal charge (free electrons). It is also possible to form a P + region that accumulates (holes).
  • the pixel reset gate conductor layers 7b, 36b, and 36bb formed at the same height as the SGT gate conductor layers 7a, 36a, and 36aa are connected to the signal line N + regions 2 and 31c of the signal charges accumulated in the photodiode. It may be provided as a light shielding layer instead of removing the light.
  • the SGT gate conductor layer 36aa and the pixel reset gate conductor layer 36bb are connected to the first layer via the Cu layer 62 formed on the Si pillars 26e and 26f constituting the gate conductor layer contact.
  • the case where the metal wiring layers 62a and 62e are connected has been described.
  • the pixel reset gate conductor layer 7b (gate conductor layer 36bb in FIG. 7C) and the SGT source N + region 3a (in FIG. 7C).
  • N + region 31a) and P + region 3b (P + region 31bb in FIG. 7C) are connected to each other via contact hole 9 and first metal wiring layer 12e. Can be applied.
  • a Si pillar constituting a contact is formed on the contact hole 9 and the pixel reset gate conductor layer 7b (the gate conductor layer 36bb in FIG. 7C) and the SGT source are formed in the same manner as in FIGS. 7A to 7C. Connection to the N + region 3a (N + region 31a in FIG. 7C) and the P + region 3b (P + region 31bb in FIG. 7C) can be made.
  • the present invention can be widely applied to semiconductor devices in which circuit elements are formed in columnar semiconductors such as solid-state imaging devices and SGTs.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

L'invention porte sur un dispositif de prise de vue à semi-conducteur dans lequel un pixel comprend une première section de semi-conducteur en forme d'îlot (P11) formée sur un substrat (1), et un circuit de sortie d'attaque comprend des secondes sections de semi-conducteur en forme d'îlot (4a-4c), qui sont formées sur le substrat avec une hauteur égale à celle de la première section de semi-conducteur en forme d'îlot (P11). La première section de semi-conducteur en forme d'îlot (P11) comprend une première couche d'isolation de grille (6b) formée sur la circonférence extérieure de la première section de semi-conducteur en forme d'îlot, et une première couche de conducteur de grille (105a) qui entoure la première couche d'isolation de grille (6b). Les secondes sections de semi-conducteur en forme d'îlot (4a-4c) comprennent une seconde couche d'isolation de grille (6a) formée sur la circonférence extérieure des secondes sections de semi-conducteur en forme d'îlot, et une seconde couche de conducteur de grille (7a) qui entoure la seconde couche d'isolation de grille (6a). La première couche de conducteur de grille (105a) et la seconde couche de conducteur de grille (7a) ont des parties inférieures respectives positionnées sur un même plan.
PCT/JP2011/070534 2011-09-08 2011-09-08 Dispositif de prise de vue à semi-conducteur Ceased WO2013035189A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN2011800431859A CN103119719A (zh) 2011-09-08 2011-09-08 固体摄像器件
JP2013511423A JP5281215B1 (ja) 2011-09-08 2011-09-08 固体撮像装置
KR1020137005981A KR20130061723A (ko) 2011-09-08 2011-09-08 고체 촬상 장치
PCT/JP2011/070534 WO2013035189A1 (fr) 2011-09-08 2011-09-08 Dispositif de prise de vue à semi-conducteur
TW101131985A TW201312736A (zh) 2011-09-08 2012-09-03 固體攝像裝置
US13/606,823 US8564034B2 (en) 2011-09-08 2012-09-07 Solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/070534 WO2013035189A1 (fr) 2011-09-08 2011-09-08 Dispositif de prise de vue à semi-conducteur

Publications (1)

Publication Number Publication Date
WO2013035189A1 true WO2013035189A1 (fr) 2013-03-14

Family

ID=47831674

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/070534 Ceased WO2013035189A1 (fr) 2011-09-08 2011-09-08 Dispositif de prise de vue à semi-conducteur

Country Status (5)

Country Link
JP (1) JP5281215B1 (fr)
KR (1) KR20130061723A (fr)
CN (1) CN103119719A (fr)
TW (1) TW201312736A (fr)
WO (1) WO2013035189A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017212644A1 (fr) * 2016-06-10 2017-12-14 株式会社ソシオネクスト Dispositif à semi-conducteurs

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7056994B2 (ja) * 2018-05-08 2022-04-19 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 柱状半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024799A (ja) * 2004-07-08 2006-01-26 Sharp Corp 固体撮像装置およびその製造方法
WO2009034731A1 (fr) * 2007-09-12 2009-03-19 Unisantis Electronics (Japan) Ltd. Élément d'imagerie à semi-conducteur
WO2011111662A1 (fr) * 2010-03-08 2011-09-15 日本ユニサンティスエレクトロニクス株式会社 Dispositif de capture de semi-conducteurs

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024799A (ja) * 2004-07-08 2006-01-26 Sharp Corp 固体撮像装置およびその製造方法
WO2009034731A1 (fr) * 2007-09-12 2009-03-19 Unisantis Electronics (Japan) Ltd. Élément d'imagerie à semi-conducteur
WO2009034623A1 (fr) * 2007-09-12 2009-03-19 Unisantis Electronics (Japan) Ltd. Capteur d'image à semi-conducteur
WO2011111662A1 (fr) * 2010-03-08 2011-09-15 日本ユニサンティスエレクトロニクス株式会社 Dispositif de capture de semi-conducteurs

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017212644A1 (fr) * 2016-06-10 2017-12-14 株式会社ソシオネクスト Dispositif à semi-conducteurs
JPWO2017212644A1 (ja) * 2016-06-10 2019-04-11 株式会社ソシオネクスト 半導体装置

Also Published As

Publication number Publication date
JP5281215B1 (ja) 2013-09-04
CN103119719A (zh) 2013-05-22
TW201312736A (zh) 2013-03-16
KR20130061723A (ko) 2013-06-11
JPWO2013035189A1 (ja) 2015-03-23

Similar Documents

Publication Publication Date Title
US8564034B2 (en) Solid-state imaging device
CN110034139B (zh) 图像传感器
JP5938946B2 (ja) 固体撮像装置、固体撮像装置の製造方法及び電子機器
US8987852B2 (en) Solid-state image pickup apparatus, image pickup system including solid-state image pickup apparatus, and method for manufacturing solid-state image pickup apparatus
EP3706172A1 (fr) Dispositif de capture d'images à semiconducteurs
JP6193695B2 (ja) 半導体装置およびその製造方法
KR20060000061A (ko) 이미지 센서
CN100382327C (zh) 固态图像拾取装置及其制造方法
JP2012064822A (ja) 固体撮像装置及びその製造方法
JP6325904B2 (ja) 固体撮像装置の製造方法、固体撮像装置、および、カメラ
JP2012060076A (ja) 固体撮像装置およびその製造方法
JP2017045838A (ja) 撮像装置およびその製造方法
JP2011211000A (ja) 固体撮像装置、固体撮像装置の製造方法、電子機器
JP5281215B1 (ja) 固体撮像装置
JP2025541515A (ja) 垂直電荷転送型光電センサ、その製造方法、及びその動作方法
JP4972924B2 (ja) 固体撮像装置およびその製造方法、並びにカメラ
JP2012009652A (ja) 固体撮像装置およびその製造方法
CN223310206U (zh) 影像传感器
CN112310128B (zh) 图像传感器、用于图像传感器的半导体结构及其制造方法
KR20100025880A (ko) 불순물 거름막을 갖는 시모스 이미지 센서 및 그 제조 방법
KR100688589B1 (ko) 필 팩터가 증대된 이미지 센서 및 그의 제조방법
JP2008193050A (ja) 固体撮像装置および撮像装置
CN220963352U (zh) 集成芯片以及半导体结构
JP4867226B2 (ja) 固体撮像装置およびその製造方法、並びにカメラ
TWI836771B (zh) 影像感測器及用於形成其的方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201180043185.9

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2013511423

Country of ref document: JP

Kind code of ref document: A

Ref document number: 20137005981

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11872112

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11872112

Country of ref document: EP

Kind code of ref document: A1