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WO2013018589A1 - Dispositif de circuit intégré à semi-conducteur - Google Patents

Dispositif de circuit intégré à semi-conducteur Download PDF

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Publication number
WO2013018589A1
WO2013018589A1 PCT/JP2012/068737 JP2012068737W WO2013018589A1 WO 2013018589 A1 WO2013018589 A1 WO 2013018589A1 JP 2012068737 W JP2012068737 W JP 2012068737W WO 2013018589 A1 WO2013018589 A1 WO 2013018589A1
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Prior art keywords
conductivity type
power supply
type well
conductivity
wiring
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PCT/JP2012/068737
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English (en)
Japanese (ja)
Inventor
石橋　孝一郎
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University of Electro Communications NUC
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University of Electro Communications NUC
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10W20/40—

Definitions

  • the present invention relates to a semiconductor integrated circuit device having a CMOS structure.
  • CMOS Complementary Metal Oxide Semiconductor, hereinafter the same
  • LSI Large Scale Integration
  • Non-Patent Document 1 describes a microprocessor manufactured in a 0.2 ⁇ m CMOS technology for a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, etc.) when the microprocessor is on standby. It is described that the leakage current during standby can be reduced by about three orders of magnitude by applying a substrate bias.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a standard cell composed of MOSFETs for applying a substrate bias a layout of a switch cell for controlling the application of the substrate bias (see FIG. 5), and a power source by arranging a collection of cells.
  • a layout showing the wiring of the substrate bias is described.
  • Non-Patent Document 1 since a metal wiring layer for applying a substrate bias is arranged in each standard cell, it is possible to reduce the impedance of the substrate bias and to apply a stable substrate bias. .
  • Patent Document 1 discloses that a well contact for applying a substrate bias is arranged in a place other than a standard cell, and metal wiring for applying the substrate bias to the standard cell is provided. Techniques that do not insert are described.
  • Non-Patent Document 1 has a problem that the occupied area becomes large when standard cells are arranged due to the following two factors.
  • the first factor is that since the power supply wiring and the substrate bias wiring in the standard cell are constituted by the first metal wiring layer (M1), each wiring requires a predetermined area.
  • the second factor is that the standard cells must be arranged between the switch cells arranged at intervals of 200 ⁇ m. Therefore, the standard cells having various widths cannot be arranged at the maximum between the switch cells. An area where the standard cell is not arranged is generated between the switch cells arranged in (1).
  • the present invention has been made in view of the above points, and an object thereof is to provide a semiconductor integrated circuit device capable of stably applying a substrate bias in a small area.
  • the semiconductor integrated circuit device is a semiconductor integrated circuit device having a CMOS structure including a first conductivity type MOSFET and a second conductivity type MOSFET, wherein a second conductivity type well and a drain and a source are formed in the second conductivity type well.
  • the first conductivity type MOSFET, the second conductivity type diffusion layer formed in the second conductivity type well, and the second conductivity type diffusion layer are provided on the first conductivity type MOSFET.
  • the second conductivity type The diffusion layer is a power supply layer for applying a substrate bias to the first conductivity type well and the second conductivity type well, respectively, and the first conductivity type diffusion layer and the second power supply line are interlayer insulating layers.
  • the second conductive type diffusion layer and the first power supply line are arranged in parallel with each other through an interlayer insulating layer. In addition, it is a requirement that at least a portion overlaps in plan view.
  • a semiconductor integrated circuit device capable of stably applying a substrate bias in a small area can be provided.
  • FIG. 1 is a circuit diagram illustrating a semiconductor integrated circuit device according to a first embodiment
  • 1 is a plan view illustrating a semiconductor integrated circuit device according to a first embodiment
  • It is sectional drawing which follows the AA line of FIG. 1B.
  • It is sectional drawing which follows the BB line of FIG. 1B.
  • FIG. 1C of 1st Embodiment in 2nd Embodiment.
  • FIG. 1D of 1st Embodiment in 2nd Embodiment.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 1 of the second embodiment.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 2 of the second embodiment.
  • FIG. 6 is a plan view illustrating a semiconductor integrated circuit device according to a third embodiment; FIG. It is sectional drawing which follows the CC line of FIG. 5A. It is sectional drawing which follows the DD line
  • inverter circuit logic inversion circuit
  • the present invention is not limited to this, and the present invention is applied to a semiconductor integrated circuit device having a CMOS structure other than the inverter circuit. Is also widely applicable.
  • FIG. 1A is a circuit diagram illustrating the semiconductor integrated circuit device according to the first embodiment.
  • a semiconductor integrated circuit device 1 is a semiconductor integrated circuit device having a CMOS structure including an N-type MOSFET 10 and a P-type MOSFET 20, and has a function as an inverter circuit.
  • the first conductivity type is N-type or P-type
  • the second conductivity type is P-type or N-type opposite to the first conductivity type.
  • the ground wiring 16 (Vss) is connected to the source S 1 of the N-type MOSFET 10 .
  • the substrate wiring 12 (Vbn) is a wiring for applying a substrate bias to the N-type MOSFET 10 and is connected to the back gate B 1 of the N-type MOSFET 10 .
  • the power supply wiring 26 (Vdd) is connected to the source S 2 of the P-type MOSFET 20 .
  • the substrate wiring 22 (Vbp) is a wiring for applying a substrate bias to the P-type MOSFET 20, and is connected to the back gate B 2 of the P-type MOSFET 20 .
  • the input terminal 31 is an input terminal of the inverter circuit, and is connected to the gate G 1 of the N-type MOSFET 10 and the gate G 2 of the P-type MOSFET 20 .
  • the output terminal 32 is an output terminal of the inverter circuit, and is connected to the drain D 1 of the N-type MOSFET 10 and the drain D 2 of the P-type MOSFET 20 .
  • the voltages applied to the ground wiring 16, the power supply wiring 26, the substrate wiring 12, and the substrate wiring 22 can be determined as appropriate. For example, 0 v, 0.5 to 1.0 v, +0.5 to ⁇ 3.3 v, and It can also be changed to be 0 to 3.8v.
  • FIG. 1B is a plan view illustrating the semiconductor integrated circuit device according to the first embodiment.
  • 1C is a cross-sectional view taken along the line AA in FIG. 1B.
  • 1D is a cross-sectional view taken along line BB in FIG. 1B.
  • the ground wiring 16, the power supply wiring 26, the input terminal 31, and the output terminal 32 are drawn transparently, and the lower layer is seen through.
  • the substrate wirings 12 and 22 are shown in a satin pattern.
  • the N-type MOSFET 10 and the P-type MOSFET 20 are arranged so as to be adjacent to each other in the YY direction in plan view (viewed from the ZZ direction in FIG. 1C or FIG. 1D). ing.
  • a source electrode 13 and a drain electrode 14 are arranged at predetermined intervals in the XX direction near the upper surface (surface on the gate electrode 15 side) of the P-type well 11 containing a low-concentration P-type impurity. It is installed.
  • An isolation layer 33 is formed on one side of each of the source electrode 13 and the drain electrode 14.
  • a gate electrode 15 is provided at a position overlapping a channel region sandwiched between the source electrode 13 and the drain electrode 14 via a gate insulating film (not shown).
  • the P-type well 11, the source electrode 13, the drain electrode 14, and the gate electrode 15 correspond to the back gate B 1 , the source electrode S 1 , the drain electrode D 1 , and the gate electrode G 1 shown in FIG. 1A, respectively.
  • substrate wiring 12 is provided in the XX direction on the side near the top surface of the P-type well 11 and not adjacent to the N-type well 21.
  • the substrate wiring 12 is formed of a P-type diffusion layer containing a P-type impurity having a concentration higher than that of the P-type well 11 in order to fix the potential of the P-type well 11. Further, a low resistance material such as metal silicide may be formed on the surface of the diffusion layer. That is, the substrate wiring 12 is a power feeding layer for applying a substrate bias to the P-type well 11.
  • a ground wiring 16 is provided in the XX direction via an interlayer insulating layer (not shown).
  • the ground wiring 16 extends to the source electrode 13 side (in the YY direction) and is connected to the source electrode 13 through a through wiring 16x that penetrates an interlayer insulating layer (not shown).
  • the ground wiring 16 and the through wiring 16x can be formed of a metal such as copper (Cu) or tungsten (W), for example.
  • the ground wiring 16 is an upper layer of the substrate wiring 12, and the substrate wiring 12 and the ground wiring 16 are arranged in parallel to each other through an interlayer insulating layer (not shown). In order to reduce the area of the semiconductor integrated circuit device 1, it is preferable that at least a part of the substrate wiring 12 and the ground wiring 16 overlap in plan view. More preferably, the substrate wiring 12 and the ground wiring 16 all overlap in plan view.
  • the substrate wiring 12 and the ground wiring 16 are each formed in a substantially linear shape in the XX direction, but either one or both may include a portion that is not linear. Further, the substrate wiring 12 and the ground wiring 16 may have the same width (YY direction) or different widths. For example, in order to stabilize the power supply, the width of the ground wiring 16 can be made larger than the width of the substrate wiring 12, and the substrate wiring 12 can be arranged at a position overlapping the ground wiring 16 in plan view.
  • parallel means approximately parallel and does not mean strictly parallel. Therefore, the semiconductor integrated circuit device according to the first embodiment may be deviated from parallelism within a range that does not substantially impair the predetermined effect.
  • a source electrode 23 and a drain electrode 24 are arranged in parallel at a predetermined interval in the XX direction near the upper surface (surface on the gate electrode 25 side) of the N-type well 21 containing a low-concentration N-type impurity. It is installed.
  • An isolation layer 33 is formed on one side of each of the source electrode 23 and the drain electrode 24.
  • a gate electrode 25 is provided at a position overlapping the channel region sandwiched between the source electrode 23 and the drain electrode 24 via a gate insulating film (not shown).
  • the N-type well 21, the source electrode 23, the drain electrode 24, and the gate electrode 25 correspond to the back gate B 2 , the source electrode S 2 , the drain electrode D 2 , and the gate electrode G 2 shown in FIG. 1A, respectively.
  • substrate wiring 22 is provided in the XX direction near the upper surface of the N-type well 21 and on the side not adjacent to the P-type well 11.
  • the substrate wiring 22 is formed of an N-type diffusion layer containing an N-type impurity at a concentration higher than that of the N-type well 21 in order to fix the potential of the N-type well 21. That is, the substrate wiring 22 is a power feeding layer for applying a substrate bias to the N-type well 21.
  • a power supply wiring 26 is provided in the XX direction via an interlayer insulating layer (not shown).
  • the power supply wiring 26 extends to the source electrode 23 side (in the YY direction) and is connected to the source electrode 23 through a through wiring 26x that penetrates an interlayer insulating layer (not shown).
  • the power supply wiring 26 and the through wiring 26x can be formed of a metal such as copper (Cu) or tungsten (W), for example.
  • the power supply wiring 26 is an upper layer of the substrate wiring 22, and the substrate wiring 22 and the power supply wiring 26 are arranged in parallel to each other through an interlayer insulating layer (not shown). In order to reduce the area of the semiconductor integrated circuit device 1, it is preferable that at least a part of the substrate wiring 22 and the power supply wiring 26 overlap in plan view. It is more preferable that the substrate wiring 22 and the power supply wiring 26 are all overlapped in plan view.
  • the substrate wiring 22 and the power supply wiring 26 are each formed in a substantially linear shape in the XX direction, but either one or both may include a portion that is not linear. Further, the substrate wiring 22 and the power supply wiring 26 may have the same width (YY direction) or different widths. For example, in order to stabilize power supply, the width of the power supply wiring 26 can be made larger than the width of the substrate wiring 22, and the substrate wiring 22 can be arranged at a position overlapping the power supply wiring 26 in plan view.
  • An input terminal 31 and an output terminal 32 are provided on the upper surfaces of the P-type well 11 and the N-type well 21 via an interlayer insulating layer (not shown).
  • the input terminal 31 is connected to the gate electrodes 15 and 25 through a through wiring 31x that passes through an interlayer insulating layer (not shown).
  • the output terminal 32 is connected to the drain electrodes 14 and 24 through a through wiring 32x that passes through an interlayer insulating layer (not shown).
  • the ground wiring 16 is a typical example of the first power supply line according to the present invention.
  • the substrate wiring 12 is a typical example of the second conductivity type diffusion layer according to the present invention.
  • the power supply wiring 26 is a typical example of the second power supply line according to the present invention.
  • the substrate wiring 22 is a typical example of the first conductivity type diffusion layer according to the present invention.
  • the substrate wiring 12 is formed by the P-type diffusion layer containing P-type impurities at a higher concentration than the P-type well 11 in the vicinity of the upper surface of the P-type well 11.
  • the ground wiring 16 is arranged in parallel to the substrate wiring 12 via an interlayer insulating layer (not shown).
  • a substrate wiring 22 is formed by an N-type diffusion layer containing an N-type impurity at a concentration higher than that of the N-type well 21 in the vicinity of the upper surface of the N-type well 21 and an interlayer insulating layer (not shown) is formed as the power supply wiring 26.
  • the substrate wiring 12 and the ground wiring 16 are at least partially overlapped in plan view, and the substrate wiring 22 and the power supply wiring 26 are at least partially overlapped in plan view.
  • the distance between the portion of the P-type well 11 below the gate electrode 15 and the substrate wiring 12 can be shortened. Further, in the P-type MOSFET 20, the distance between the portion of the N-type well 21 below the gate electrode 25 and the substrate wiring 22 can be shortened.
  • the respective impedances of the substrate wirings 12 and 22 can be reduced, and the N-type MOSFET 10 (the portion under the gate electrode 15 of the P-type well 11) and the P-type MOSFET 20 (the gate electrode 25 of the N-type well 21).
  • a substrate bias can be stably applied to each of the lower portions. Further, an extra wiring area for applying the substrate bias is not necessary, and the substrate bias can be applied in a small area. That is, a semiconductor integrated circuit device capable of stably applying a substrate bias in a small area can be provided.
  • FIG. 2A is a diagram corresponding to FIG. 1C of the first embodiment in the second embodiment.
  • FIG. 2B is a diagram corresponding to FIG. 1D of the first embodiment in the second embodiment. Since the circuit diagram and the plan view are the same as those in the first embodiment, the illustration is omitted.
  • the semiconductor integrated circuit according to the first embodiment is that the N-type MOSFET 10A and the P-type MOSFET 20A are formed on a thin film oxide film of SOI. This is different from the apparatus 1 (see FIGS. 1B to 1D).
  • the oxide film 17 is a thin insulating film constituting the SOI.
  • the oxide film 17 is provided at least between the P-type well 11 and the source and drain electrodes 13 and 14.
  • the oxide film 17 is not provided between the P-type well 11 and the substrate wiring 12.
  • the oxide film 27 is a thin insulating film constituting the SOI.
  • the oxide film 27 is provided at least between the N-type well 21 and the source electrode 23 and the drain electrode 24.
  • the oxide film 27 is not provided between the N-type well 21 and the substrate wiring 22.
  • the oxide films 17 and 27 can be made of SiO 2 , for example.
  • the thicknesses of the oxide films 17 and 27 are determined from the substrate wirings 12 and 22, respectively, by the N-type MOSFET 10A (the portion under the gate electrode 15 of the P-type well 11) and the P-type MOSFET 20A (the gate electrode 25 of the N-type well 21). Can be determined as appropriate within a range in which the substrate bias can be applied to the lower portion), but can be about 10 nm, for example.
  • the oxide film 17 is a typical example of the first insulating film according to the present invention.
  • the oxide film 27 is a typical example of the second insulating film according to the present invention.
  • the N-type MOSFET 10A and the P-type MOSFET 20A are formed on the SOI thin film substrate. Even in such a structure, the oxide films 17 and 27 of the P-type well 11 and the N-type well 21 are respectively reduced by sufficiently reducing the thicknesses of the oxide films 17 and 27 (for example, about 10 nm). By applying a substrate bias to the upper region via the substrate wirings 12 and 22, the characteristics of the N-type MOSFET 10A and the P-type MOSFET 20A can be controlled.
  • the threshold values of the MOSFET 10A and the P-type MOSFET 20A can be varied.
  • the oxide films 17 and 27 are each an insulating film, a leak current due to application of a substrate bias does not occur. Therefore, the power consumption of the semiconductor integrated circuit device 1A can be reduced.
  • the substrate wiring 12 made of the P-type diffusion layer and the substrate wiring 22 made of the N-type diffusion layer in the region where the oxide films 17 and 27 of the P-type well 11 and the N-type well 21 are not formed are provided.
  • Modification 1 of the second embodiment shows another example using an SOI substrate.
  • the description of the same components as those of the already described embodiment is omitted.
  • FIG. 3 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 1 of the second embodiment.
  • an N-type MOSFET 10A is formed on a P-type substrate 11A
  • an N-type well 21 is formed on a P-type substrate 11A.
  • the point that the P-type MOSFET 20A is formed in the N-type well 21 is different from the semiconductor integrated circuit device 1A (see FIGS. 2A and 2B).
  • the N-type MOSFET 10A is directly formed on the semiconductor substrate (P-type substrate 11A), and the same semiconductor substrate (P-type substrate 11A) is formed.
  • the P-type MOSFET 20A is formed via the N-type well 21, the same effects as those of the second embodiment can be obtained even in such a structure.
  • the second modification of the second embodiment shows an example in which a plurality of N-type MOSFETs and P-type MOSFETs are formed on an SOI substrate, and a substrate bias is individually applied to the MOSFETs.
  • the description of the same components as those of the already described embodiment is omitted.
  • FIG. 4 is a cross-sectional view illustrating a semiconductor integrated circuit device according to Modification 2 of the second embodiment.
  • an N-type MOSFET 10A is formed in the P-type well 11
  • a P-type MOSFET 20A is formed in the N-type well 21.
  • an N-type well 41 is provided below the P-type well 11 and the N-type well 21 (at a position deeper than the P-type well 11 and the N-type well 21). 49 is different from the semiconductor integrated circuit device 1A (see FIGS. 2A and 2B).
  • N-type well 21 1 is independent from the N-type well 21 3 (being insulated )
  • the N-type wells 21 1 and 21 2 are connected by an N-type well 41 1 .
  • the N-type well 21 1 and 21 3 which are independent, each individual substrate bias is applied It is possible.
  • the substrate wiring 12 1 and the substrate wiring 12 2, respectively separate substrate bias can be applied.
  • the substrate wiring 22 1 and the substrate wiring 22 2, respectively separate substrate bias can be applied.
  • the P-type well 11 1 in which the N-type MOSFET 10A is formed is formed at a deeper position than the P-type well 11 1 .
  • the N-type well 41 1 is electrically isolated from the P-type well 11 2 other N-type MOSFET10B is formed.
  • N-type well 21 1 P-type MOSFET20A is formed, N-type well 21 by N-type well 41 1 formed at a position deeper than 1, other N-type well P-type MOSFET20B are formed 21 2 And are electrically connected.
  • semiconductor integrated circuit device 1C according to the second modification of the second embodiment also has the same effect as the semiconductor integrated circuit device 1A according to the second embodiment.
  • the third embodiment shows an example in which a plurality of standard cells are arranged adjacent to each other.
  • the description of the same components as those of the already described embodiments is omitted.
  • FIG. 5A is a plan view illustrating a semiconductor integrated circuit device according to the third embodiment.
  • FIG. 5B is a cross-sectional view taken along the line CC of FIG. 5A.
  • FIG. 5C is a cross-sectional view taken along the line DD of FIG. 5A.
  • FIG. 5D is a cross-sectional view taken along line EE of FIG. 5A.
  • the P-type well 11 and the N-type well 21 are the S0 layer
  • the metal wiring layer disposed on the S0 layer via the interlayer insulating layer (not shown) is the M1 layer
  • the interlayer insulating layer is the interlayer insulating layer.
  • the metal wiring layer disposed on the M1 layer via the (not shown) is the M2 layer
  • the metal wiring layer disposed on the M2 layer via the interlayer insulating layer (not shown) is the M3 layer.
  • ... (M1) or the like, and the layers in which guided are formed are indicated.
  • FIG. 5A for convenience, the ground wiring 16, the power supply wiring 26, the input terminal 31, and the output terminal 32 are drawn transparently and the lower layer is seen through.
  • the substrate wirings 12 (S0) and 22 (S0) are shown in a satin pattern.
  • a plurality of standard cells are arranged adjacent to each other. Specifically, three inverter cells 51 are arranged adjacent to each other, and a high booster cell 52 is arranged adjacent to the inverter cells 51. A tap cell 53 is disposed adjacent to the high booster cell 52.
  • the inverter cell 51 and the high booster cell 52 having a width (XX direction) wider than the inverter cell 51 are arranged as the standard cells, but the present invention is not limited to this.
  • the N-type MOSFET 10 and the P-type MOSFET 20 are shown only in one inverter cell 51 as a representative, and the illustration of the other inverter cells 51 is omitted.
  • a set of N-type MOSFET and P-type MOSFET adjacent to each other in YY direction is changed to YY direction.
  • the substrate wirings 12 (S0) of the standard cells are arranged adjacent to each other, so that the substrate wirings 12 (S0) of the standard cells can be easily connected to each other. can do.
  • the substrate wirings 22 (S0) of the standard cells are arranged adjacent to each other, the substrate wirings 22 (S0) of the standard cells can be easily connected to each other.
  • a flip-flop cell, a NAND cell, an inverter cell with a wide gate width, or the like can be arranged in the high booster cell 52.
  • the substrate wiring 12 (M2), the ground wiring 16 (M2), the substrate wiring 22 (M2), and the power wiring 26 (M2), which are power supply trunk lines, are metal wiring layers M2, respectively. It is formed in the Y direction in the layer. These four power trunks can be formed on top of any standard cell. In the present embodiment, an example is shown in which four power supply trunks are formed above the high booster cell 52.
  • the ground wiring 16 (M2) which is one of the power supply trunk lines, is connected to the ground wiring 16 (M1) of the high booster cell 52 on the high booster cell 52 by the through wiring 54.
  • the power supply wiring 26 (M2) which is one of the power supply trunk lines is connected to the power supply wiring 26 (M1) of the high booster cell 52 on the high booster cell 52 by the through wiring 55.
  • the substrate wiring 12 (M2) which is one of the power supply trunk lines, includes the through wiring 56, the metal wiring 57 (M3), the through wiring 58 1 , the metal wiring 57 (M2), the through wiring 58 2 , and the metal wiring 57 (M1). ), and via the through wiring 58 3, and is connected to the P-type diffusion layer 59 containing a P-type impurity of high concentration of tap cell 53 (S0). Further, the P-type diffusion layer 59 (S0) is connected to the substrate wiring 12 (S0) in the tap cell 53.
  • the substrate wiring 22 (M2) which is one of the power supply trunk lines includes a through wiring 66, a metal wiring 67 (M3), a through wiring 68 1 , a metal wiring 67 (M2), a through wiring 68 2 , a metal wiring 67 ( M1), and via the through wiring 683 is connected to the N-type diffusion layer 69 containing N-type impurity of high concentration of tap cell 53 (S0). Further, the N-type diffusion layer 69 (S0) of the tap cell 53 is connected to the substrate wiring 22 (S0) in the tap cell 53.
  • the tap cell 53 can be inserted at any position between adjacent standard cells (any position between a plurality of sets of N-type MOSFET 10 and P-type MOSFET 20).
  • an M4 layer (metal wiring layer) is disposed on the M3 layer via an interlayer insulating layer (not shown), and the substrate wiring 12 (M2), the ground wiring 16 (M2), and the substrate wiring 22 ( M2) and all or part of the power supply wiring 26 (M2) may be formed in the Y direction in the M4 layer.
  • the ground wiring 16 (M2) is a typical example of the first power supply trunk line according to the present invention.
  • the substrate wiring 12 (M2) is a typical example of the first substrate bias trunk line according to the present invention.
  • the power supply wiring 26 (M2) is a typical example of the second power supply trunk line according to the present invention.
  • the substrate wiring 22 (M2) is a typical example of the second substrate bias trunk line according to the present invention.
  • FIG. 6 is a diagram showing an example in which a large number of cells having different sizes are arranged adjacent to each other in the semiconductor integrated circuit device according to the third embodiment. As shown in FIG. 6, by arranging the power supply trunk lines at a predetermined interval, a large number of cells having different sizes can be arranged adjacent to each other in the XX direction and the YY direction.
  • the connection from the substrate wirings 12 (M2) and 22 (M2), which are power supply trunk lines, to the tap cell 53 is performed through metal wirings 57 (M3) and 67 (M3) which are substantially orthogonal to the power supply trunk lines, respectively.
  • the tap cell 53 can be arranged at an arbitrary position rather than below the power supply trunk line.
  • standard cells a combination of an N-type MOSFET and a P-type MOSFET
  • the tap cell 53 can be arranged adjacent to the standard cell.
  • semiconductor integrated circuit device 1D according to the third embodiment also has the same effects as the semiconductor integrated circuit device 1 according to the first embodiment.
  • the effect of the present application will be described in more detail.
  • the area of the semiconductor integrated circuit device can be reduced.
  • the first effect of reducing the size of the standard cell itself for example, the first embodiment and the second embodiment
  • the case where cells of different sizes are arranged adjacent to each other
  • a second effect for example, the third embodiment
  • a case where the present application is applied to a technology having a minimum dimension of 65 nm will be described as an example with specific numerical examples.
  • the minimum dimension is applied to the gate length, but the metal wiring interval is usually about 0.2 ⁇ m minimum. That is, the design grid length is about 0.2 ⁇ m.
  • the standard cell height is typically 9 grids. Therefore, the height of the standard cell is 1.8 ⁇ m.
  • the substrate wiring (substrate wiring) for applying a substrate bias if a wiring (substrate wiring) for applying a substrate bias is to be drawn, the substrate wiring (substrate bias Vbp) of the P-type MOSFET and the N-type MOSFET for each substrate wiring (substrate bias Vbn), one extra wiring is required for each. Therefore, the height of the standard cell is 1.8 ⁇ m to 2.2 ⁇ m.
  • the height of the standard cell is 1.8 ⁇ m. That is, the area reduction effect of the standard cell size in the present application is about 18% (first effect).
  • tap cells for applying a substrate bias are installed every 200 ⁇ m in the 0.2 ⁇ m technology. If this is replaced with 65 nm technology, it is necessary to place tap cells about every 65 ⁇ m.
  • a standard cell having a large circuit scale such as a flip-flop with a scanning function may have a cell width of about 10 ⁇ m. For example, if cells having a cell width of 10 ⁇ m are arranged in a 65 ⁇ m area between adjacent tap cells, six cells are arranged to have a remainder of 5 ⁇ m, so this 5 ⁇ m area becomes a waste area where no cells are placed. Therefore, about 8% of the area is wasted in this example.
  • the standard cell is also arranged in an area overlapping with the area where the power supply trunk line is provided in plan view. Tap cells can be placed adjacent to standard cells. For this reason, in the present application, the above-described waste area does not occur, so that there is an area reduction effect of about 8% (second effect).
  • CMOS circuit In a CMOS circuit, generally, as the chip area increases, the wiring becomes longer, and as a result, the wiring capacity increases. When the wiring capacity increases, the charging / discharging current of the wiring increases or the operation speed of the circuit becomes slow. In the present application, there is an area reduction effect of about 26%, so that low power and high speed equivalent to that are expected. In addition, the reduction of the area increases the number of non-defective chips acquired per wafer and reduces the manufacturing cost per chip, which is very significant industrially.
  • the substrate bias can be stably applied in the present application. This effect will also be described with specific numerical examples.
  • the substrate of the P-type MOSFET is fixed to the power supply potential, and the substrate of the N-type MOSFET is fixed to the ground potential.
  • a tap cell method is used in which the substrate potential is not fixed for each standard cell, and the substrate potential is fixed at a certain interval. In the tap cell method, since it is not necessary to fix the substrate potential for each standard cell, the area of the diffusion layer for fixing the substrate potential can be saved.
  • the substrate potential is fixed through a well resistance having a sheet resistance of about 1 K ohm / ⁇ , and thus the variation in the substrate potential increases accordingly.
  • the substrate potential fluctuates by about 30% of the power supply voltage due to a change in the drain current of the CMOS.
  • the fluctuation in the substrate potential is expected to reduce the operating speed by about 8% to 9%.
  • each substrate wiring is formed of a P-type diffusion layer and an N-type diffusion layer. Since the sheet resistance of each of the P-type diffusion layer and the N-type diffusion layer is about 10 ohms / square or less, it is possible to reduce the fluctuation of the substrate potential by two orders of magnitude compared to the conventional one, and as a result, the operation speed is lowered. It can be almost eliminated. That is, according to the present application, the substrate bias can be applied more stably than in the prior art, and the operation speed can be increased by about 8% to 9% compared to the prior art.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un dispositif de circuit intégré à semi-conducteur qui possède une structure CMOS qui comprend un transistor MOSFET d'un premier type de conductivité et un transistor MOSFET d'un second type de conductivité. Le dispositif de circuit intégré à semi-conducteur comprend : un puits du second type de conductivité; le transistor MOSFET du premier type de conductivité ayant un drain et une source formés sur le puits du second type de conductivité; une couche de diffusion du second type de conductivité formée sur le puits du second type de conductivité; une première ligne d'alimentation électrique, qui est placée sur une couche supérieure de la couche de diffusion du second type de conductivité, et fournit un premier potentiel au transistor MOSFET du premier type de conductivité; un puits du premier type de conductivité; un transistor MOSFET du second type de conductivité ayant un drain et une source formés sur le puits du premier type de conductivité; une couche de diffusion du premier type de conductivité formée sur le puits du premier type de conductivité; et une seconde ligne d'alimentation électrique, qui est placée sur une couche supérieure de la couche de diffusion du premier type de conductivité, et fournit un second potentiel au puits du premier type de conductivité. La couche de diffusion du premier type de conductivité et la couche de diffusion du second type de conductivité sont des couches d'alimentation électrique servant à appliquer respectivement une polarisation de substrat au puits du premier type de conductivité et au puits du second type de conductivité, la couche de diffusion du premier type de conductivité et la seconde ligne d'alimentation électrique sont agencées parallèles l'une à l'autre par intercalation d'une couche d'isolation intercouche entre elles, et ont au moins des parties respectives de celles-ci qui se chevauchent en vue en plan, et la couche de diffusion du second type de conductivité et la première ligne d'alimentation électrique sont agencées parallèles l'une à l'autre par intercalation d'une couche d'isolation intercouche entre elles, et ont au moins des parties respectives de celle-ci qui se chevauchent en vue en plan.
PCT/JP2012/068737 2011-08-01 2012-07-24 Dispositif de circuit intégré à semi-conducteur Ceased WO2013018589A1 (fr)

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US20220335194A1 (en) * 2021-04-14 2022-10-20 Taiwan Semiconductor Manufacturing Company, Limited System and method for back side signal routing

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US11748546B2 (en) * 2021-04-14 2023-09-05 Taiwan Semiconductor Manufacturing Company, Limited System and method for back side signal routing

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