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WO2013017924A3 - Method for correcting misalignment of positions on a first wafer bonded to a second wafer - Google Patents

Method for correcting misalignment of positions on a first wafer bonded to a second wafer Download PDF

Info

Publication number
WO2013017924A3
WO2013017924A3 PCT/IB2012/001404 IB2012001404W WO2013017924A3 WO 2013017924 A3 WO2013017924 A3 WO 2013017924A3 IB 2012001404 W IB2012001404 W IB 2012001404W WO 2013017924 A3 WO2013017924 A3 WO 2013017924A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
positions
correcting misalignment
bonded
correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2012/001404
Other languages
French (fr)
Other versions
WO2013017924A2 (en
Inventor
Arnaud Castex
Alexandre BARTHELEMY
Marcel Broekaart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of WO2013017924A2 publication Critical patent/WO2013017924A2/en
Publication of WO2013017924A3 publication Critical patent/WO2013017924A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • G03F9/7007—Alignment other than original with workpiece
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10P74/23—
    • H10W46/00—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H10P74/203—

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The invention relates to a method for correcting misalignment of positions on a first wafer bonded to a second wafer, the method comprising the application (F4), to coordinates of each position, of a predetermined correction function for the said first wafer, the correction applied by the correction function being a function only of the distance of the position relative to the centre of the first wafer, characterized in that the applied correction varies, over the whole of the first wafer, in a non-linear manner with respect to the distance of the position relative to the centre.
PCT/IB2012/001404 2011-08-02 2012-07-18 Method for correcting misalignment of positions on a first wafer bonded to a second wafer Ceased WO2013017924A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1157069 2011-08-02
FR1157069A FR2978864B1 (en) 2011-08-02 2011-08-02 METHOD FOR CORRECTING POSITIONS DESALIGNMENT ON A FIRST GLUE PLATE ON A SECOND PLATE

Publications (2)

Publication Number Publication Date
WO2013017924A2 WO2013017924A2 (en) 2013-02-07
WO2013017924A3 true WO2013017924A3 (en) 2013-05-23

Family

ID=46614560

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2012/001404 Ceased WO2013017924A2 (en) 2011-08-02 2012-07-18 Method for correcting misalignment of positions on a first wafer bonded to a second wafer

Country Status (3)

Country Link
FR (1) FR2978864B1 (en)
TW (1) TW201316389A (en)
WO (1) WO2013017924A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5763116B2 (en) * 2013-03-25 2015-08-12 株式会社東芝 Manufacturing method of semiconductor device
KR102330321B1 (en) * 2014-12-12 2021-11-23 에이에스엠엘 네델란즈 비.브이. Methods and apparatus for calculating substrate model parameters and controlling lithographic processing
WO2024195192A1 (en) * 2023-03-23 2024-09-26 株式会社Ｓｃｒｅｅｎホールディングス Substrate bonding apparatus and substrate bonding method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030106378A1 (en) * 2001-05-25 2003-06-12 Antonios Giannakopoulos Determining large deformations and stresses of layered and graded structures to include effects of body forces
US20080182344A1 (en) * 2007-01-30 2008-07-31 Steffen Mueller Method and system for determining deformations on a substrate
WO2010006935A2 (en) * 2008-07-14 2010-01-21 Asml Netherlands B.V. Alignment system, lithographic system and method
FR2943177A1 (en) * 2009-03-12 2010-09-17 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE WITH CIRCUIT LAYER REPORT
FR2955654A1 (en) * 2010-01-25 2011-07-29 Soitec Silicon Insulator Technologies SYSTEM AND METHOD FOR EVALUATING INHOMOGENOUS DEFORMATIONS IN MULTILAYER PLATES

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030106378A1 (en) * 2001-05-25 2003-06-12 Antonios Giannakopoulos Determining large deformations and stresses of layered and graded structures to include effects of body forces
US20080182344A1 (en) * 2007-01-30 2008-07-31 Steffen Mueller Method and system for determining deformations on a substrate
WO2010006935A2 (en) * 2008-07-14 2010-01-21 Asml Netherlands B.V. Alignment system, lithographic system and method
FR2943177A1 (en) * 2009-03-12 2010-09-17 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE WITH CIRCUIT LAYER REPORT
FR2955654A1 (en) * 2010-01-25 2011-07-29 Soitec Silicon Insulator Technologies SYSTEM AND METHOD FOR EVALUATING INHOMOGENOUS DEFORMATIONS IN MULTILAYER PLATES

Also Published As

Publication number Publication date
WO2013017924A2 (en) 2013-02-07
FR2978864B1 (en) 2014-02-07
FR2978864A1 (en) 2013-02-08
TW201316389A (en) 2013-04-16

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