WO2013016884A1 - 基于温度补偿的电压基准电路 - Google Patents
基于温度补偿的电压基准电路 Download PDFInfo
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- WO2013016884A1 WO2013016884A1 PCT/CN2011/078830 CN2011078830W WO2013016884A1 WO 2013016884 A1 WO2013016884 A1 WO 2013016884A1 CN 2011078830 W CN2011078830 W CN 2011078830W WO 2013016884 A1 WO2013016884 A1 WO 2013016884A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
Definitions
- the invention relates to a voltage reference circuit, which is suitable for the field of analog IC and digital-analog hybrid IC which require a low temperature coefficient reference voltage, and particularly relates to a voltage reference circuit based on temperature compensation.
- the low temperature coefficient voltage reference circuit is an indispensable part of many analog circuits. Its working principle is: Use positive and negative temperature coefficient voltage weighted superposition to generate low temperature coefficient voltage to reduce the reference voltage with temperature. purpose.
- V V + AV ⁇ 20. ( i ) D n Q10 Dn Q10, Q20 ⁇ where V BE is the PN junction voltage of transistor Q10, and ⁇ ⁇ is the PN junction voltage difference of transistors Q10 and Q20. due to:
- k is the Boltzmann constant
- T is the absolute temperature
- q is the amount of electrons
- n Q is the ratio of the number of transistors Q20 and Q10.
- T is related to T ln(T), and the temperature coefficient of the reference voltage cannot be completely eliminated.
- the conventional reference voltage temperature coefficient produced by the common standard process is about 40 ppmTC (parts per million Celsius), that is, -40 ° C to 85 °. Within the temperature range of C, the reference voltage change rate is:
- the present invention proposes a temperature-compensated voltage reference circuit having a zero temperature coefficient capable of eliminating the influence of T and Tln(T). To overcome the problem that the temperature reference coefficient caused by the correlation between the reference voltage and the T and Tln(T) is not completely eliminated by the conventional reference voltage generating circuit.
- the temperature compensation based voltage reference circuit comprises a positive temperature coefficient generating unit and a negative Temperature coefficient generating unit, temperature compensation circuit, mirror circuit and voltage dividing circuit;
- the positive temperature coefficient generating unit is configured to generate a positive temperature coefficient voltage including a Tln(T) term, and output a current including a positive temperature coefficient of the T term and the Tln(T) term;
- the negative temperature coefficient generating unit is configured to generate a negative temperature coefficient voltage including a T term and a Tln(T) term, and output a current including a positive temperature coefficient of the T term; and the temperature compensation circuit is configured to include the T term And the positive temperature coefficient current of the Tln(T) term is converted into a positive temperature coefficient voltage including the T term and the Tln(T) term, and the negative temperature coefficient voltage generated by the negative temperature coefficient generating unit including the T term and the Tln(T) term is compensated.
- the negative temperature coefficient generating unit and the temperature compensation circuit jointly generate a reference voltage of zero temperature coefficient;
- T is the absolute temperature
- the image circuit is configured to mirror the output current of the negative temperature coefficient generating unit by m times and input to the positive temperature coefficient generating unit;
- the voltage dividing circuit is configured to adjust an output voltage and determine an operating voltage in the positive temperature coefficient generating unit and the negative temperature coefficient generating unit.
- the temperature compensation circuit comprises a resistor R 5, the positive temperature coefficient generation means includes an operational amplifier Al, the transistor Q3, transistor Q4, resistor R 6, resistor R4, the positive input of the operational amplifier A1 termination transistor Q4
- the base the negative input terminal of the operational amplifier A1 is connected to the collector of the transistor Q4, the output of the operational amplifier A1 is connected to the emitter of the transistor Q4, and one end of the R 6 is connected to the negative input terminal of the operational amplifier A1 and the collector of the transistor Q4.
- the other end of the R 6 is grounded, the emitter of the transistor Q4 and the emitter of the transistor Q3 are connected to the resistor R 4 , the collector of the transistor Q3 is connected to one end of the mirror circuit, and the base and the transistor of the transistor Q3 are connected.
- the negative temperature coefficient generating unit includes an operational amplifier A2, a transistor Q1, a transistor Q2, a resistor, a resistor R 2 , and a resistor R 3 ; the emitter of the transistor Q1 is connected to a positive input terminal of the operational amplifier A2, and the operation The positive input terminal of the amplifier A2 is connected to one end of the resistor R 3 , the emitter of the transistor Q2 is connected to the negative input terminal of the operational amplifier A2 through a resistor, and the negative input terminal of the operational amplifier A2 is connected to one end of the resistor R 2 .
- an output terminal of said operational amplifier A2 and a resistor R 5 is connected to one end, the other end of resistor R 2 and the resistor R 5, the other end of the resistor R 3 is connected to the other end of the resistor R and the transistor Q3 of the emitter 2 Connecting, the collector of the transistor Q1 and the transistor Q2 is connected to the other end of the mirror circuit, and the output end of the operational amplifier A2 is connected to the voltage dividing circuit; Further, the image circuit includes a first NMOS transistor M1 and a second NMOS transistor M2.
- the sources of the first NMOS transistor M1 and the second NMOS transistor M2 are grounded, and the first NMOS transistor M1 and the second NMOS transistor M2 are a gate is connected, a gate of the second NMOS transistor M2 is connected to a drain of the second NMOS transistor M2, a drain of the first NMOS transistor M1 is connected to a collector of the transistor Q3, and the second NMOS transistor M2 is connected.
- the gate is connected to the collector of the transistor Q1 and the transistor Q2; further, the voltage dividing circuit includes a resistor R 7 and a resistor R 8 , and the resistor R 8 is connected to an output terminal of the operational amplifier A2, and the resistor R 8 The other end is connected to one end of the resistor R 7 and the bases of the transistor Q1, the transistor Q2, the transistor Q3, and the transistor Q4.
- the other end of the resistor R 7 is the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2.
- a pole connection, the connection point of the operational amplifier A2 and the resistor R 5 , the resistor R 8 is the output terminal Vo of the reference circuit;
- the value of the output reference voltage Vo is determined by the ratio of the resistor R 7 and the resistor R 8 , Vo Where (E g /q) is the bandgap voltage of silicon, and the output reference voltage of different amplitudes is obtained by adjusting the ratio of the resistance R 7 and the resistance; further, the resistor R4 and the resistance satisfy the following relationship:
- the negative temperature coefficient generating unit includes at least one transistor Q1 and at least one transistor Q2, the ratio of the number of all the transistors Q2 and all the transistors Q1 is n, and the positive temperature coefficient is generated.
- the unit includes at least one transistor Q3 and at least one transistor Q4, the ratio of all the transistors Q4 to the number of all the transistors Q3 is p, and the image circuit includes at least one first NMOS transistor M1 and at least one second NMOS transistor M2. , where ⁇ >1, ⁇ >1.
- the invention has the advantages that: the temperature compensation based voltage reference circuit of the invention has the following characteristics compared with the conventional voltage reference circuit:
- the conventional voltage reference circuit uses the T term to compensate the T ln(T) term, and the temperature-compensated voltage reference circuit of the present invention compensates the term by the term, and compensates T ln by using the T ln(T) term. (T), therefore, the compensation of the voltage reference circuit of the present invention is more targeted.
- the conventional voltage reference circuit uses the T term to compensate for the T ln (T) term. Therefore, the output reference voltage is correlated with T and T ln(T) simultaneously, resulting in the temperature coefficient not being completely eliminated, which is about 40 ppmTC, and the present invention
- the voltage reference circuit has an output reference voltage independent of T and T ln(T), so that the circuit of the present invention can obtain a reference voltage of zero temperature coefficient.
- the temperature-compensated voltage reference circuit of the invention has the advantages of strong pertinence, zero temperature coefficient and adjustable output voltage value, effectively overcoming the traditional voltage reference circuit compensation, and the temperature coefficient is not complete. Eliminate the disadvantage of fixed output voltage value.
- Figure 1 is a circuit diagram of a conventional voltage reference circuit
- FIG. 2 is a circuit diagram of Embodiment 1 of a temperature-compensated voltage reference circuit of the present invention
- FIG. 3 is a circuit diagram of Embodiment 2 of a temperature-compensated voltage reference circuit of the present invention
- FIG. 4 is a temperature-compensated voltage reference of the present invention.
- Fig. 5 is a circuit diagram of Embodiment 4 of the temperature compensation based voltage reference circuit of the present invention.
- the temperature compensation based voltage reference circuit provided by the present invention includes a positive temperature coefficient generating unit 1 and a negative temperature coefficient generating unit 2 , temperature compensation circuit 3, mirror circuit 4 and voltage dividing circuit 5;
- the positive temperature coefficient generating unit 1 is configured to generate a positive temperature coefficient voltage including a Tln(T) term, and output a current including a positive temperature coefficient of the T term and the Tln(T) term;
- the negative temperature coefficient generating unit 2 is configured to generate a negative temperature coefficient voltage including a T term and a Tln (T) term, and output a current including a positive temperature coefficient of the T term;
- the temperature compensation circuit 3 is configured to convert a positive temperature coefficient current including a T term and a Tln (T) term into a positive temperature coefficient voltage including a T term and a Tln (T) term, and compensate the inclusion of the negative temperature coefficient generating unit.
- the negative temperature coefficient voltage of the T term and the Tln(T) term, the negative temperature coefficient generating unit and the temperature compensation circuit jointly generate a reference voltage of zero temperature coefficient;
- T is the absolute temperature
- the image circuit 4 is configured to mirror the output current of the negative temperature coefficient generating unit by m times and input to the positive temperature coefficient generating unit;
- the voltage dividing circuit 5 is configured to adjust an output voltage and determine an operating voltage in the positive temperature coefficient generating unit and the negative temperature coefficient generating unit.
- the temperature compensation circuit comprises a resistor R 5, the positive positive temperature coefficient generation means includes an operational amplifier Al, the transistor Q3, transistor Q4, resistor R 6, resistor R4, the operational amplifier A1
- the input terminal is connected to the base of the transistor Q4, the negative input terminal of the operational amplifier A1 is connected to the collector of the transistor Q4, the output of the operational amplifier A1 is connected to the emitter of the transistor Q4, and one end of the R 6 is connected to the negative input terminal of the operational amplifier A1 and
- the collector of the transistor Q4 is connected, the other end of the R 6 is grounded, the emitter of the transistor Q4 and the emitter of the transistor Q3 are connected to the resistor R4, and the collector of the transistor Q3 is connected to one end of the mirror circuit, the transistor Q3 The base is connected to the base of transistor Q4.
- the negative temperature coefficient generating unit includes an operational amplifier A2, a transistor Q1, a transistor Q2, a resistor, a resistor R 2 , a resistor R 3 ; an emitter of the transistor Q1 and a positive input of the operational amplifier A2 terminal is connected, the operational amplifier A2 positive input terminal and one end of resistor R 3 is connected, the emitter of transistor Q2 is connected via a resistor to the negative input terminal of operational amplifier A2, the operational amplifier A2 with the negative input terminal of resistor R 2 is connected to one end, the output end of the operational amplifier A2 is connected to one end of the resistor, the other end of the resistor is connected to the other end of the resistor R 2 and the resistor R 3 , and the other end of the resistor R 2 is connected to the transistor Q3
- the emitter is connected, the collector of the transistor Q1 and the transistor Q2 is connected to the other end of the mirror circuit, and the output of the operational amplifier A2 is connected to the voltage dividing circuit.
- the image circuit includes a first NMOS transistor M1, a second NMOS transistor M2, the sources of the first NMOS transistor M1 and the second NMOS transistor M2 are grounded, and the first NMOS transistor M1, a gate of the second NMOS transistor M2 is connected, and a gate of the second NMOS transistor M2
- the drain of the first NMOS transistor M2 is connected to the collector of the transistor Q3, and the gate of the second NMOS transistor M2 is connected to the collector of the transistor Q1 and the transistor Q2.
- the voltage dividing circuit comprises a resistor R 7 and a resistor R 8 , the resistor R 8 is connected to an output end of the A2, and the other end of the resistor R 8 is connected to one end of the resistor R 7 and a triode QL, the transistor Q2, the transistor Q3, the base of transistor Q4 is connected to the source of the source of the other end of the resistor R 7 and the first NMOS transistor Ml and the second NMOS transistor M2 is connected, the operational amplifier A2 and a resistor R 5
- the connection point of the resistor R 8 is the output terminal Vo of the reference circuit.
- the value of the output reference voltage Vo is determined by the ratio of the resistor R 7 and the resistor R 8 , Vc Where (E g /q) is the bandgap voltage of silicon, and by adjusting the ratio of the resistor R 7 and the resistor R 8 , an output reference voltage of different amplitude is obtained.
- the resistor R 4 and the resistance satisfy the following relationship: ⁇ 3
- the negative temperature coefficient generating unit includes at least one transistor Q1 and at least one transistor Q2, the transistor Q1 and transistor Q2 are composed of the same basic unit transistor, the ratio of the number of all transistors Q2 and all the transistors Q1 is n, and the positive temperature coefficient generating unit includes at least one transistor Q3 and at least one transistor Q4, and the transistor Q3 and The transistor Q4 is composed of the same basic unit transistor, the ratio of all the transistors Q4 to the number of all the transistors Q3 is p, and the image circuit includes at least one first NMOS transistor M1 and at least one second NMOS transistor M2.
- An NMOS transistor M1 and a second NMOS transistor M2 are formed by the same basic unit NMOS transistor, and the ratio of the number of all the first NMOS transistor M1 and the second NMOS transistor M2 is m, where ⁇ >1 and ⁇ >1.
- FIG. 2 A general structure of the present invention is shown in FIG. 2, including two operational amplifiers A1 ⁇ A2, four transistors Q1 ⁇ Q4, two M0S tubes M1 ⁇ M2 and eight resistors.
- the node a, the node b, the node c, and the node d are respectively the base connection point of the transistor Q4, the transistor Q3, the transistor Q2, and the transistor Q1;
- the node e is a common junction of the resistor R 7 and the resistor R 8 and Transistor Q4, Transistor Q3, Triode Tube Q2, the base of the transistor Q1 is connected;
- the node f is the connection point between the positive input terminal of the operational amplifier A2 and the emitter of the transistor Q1, and the node g is the junction of the negative input terminal of the operational amplifier A2 and the common contact of the resistor and the resistor R 2 ,
- the node h is the connection point of the transistor Q4 and the negative input terminal of the operational amplifier A1, and the node i is the
- the PN junction voltage difference between transistor Q1 and transistor Q2 produces a positive temperature coefficient voltage that includes the term T.
- Operational amplifier A2 equalizes the voltage at node f and node g. Therefore, the voltage across the resistor is:
- n is the ratio of the number of transistors Q2 to the number of transistors Q1.
- the PN junction voltage difference between transistor Q3 and transistor Q4 produces a voltage that includes the positive temperature coefficient of the T term and the T ln(T) term, ie, the voltage across R4:
- the operational amplifier A1 equalizes the voltages at node a and node h, ignoring the base current of all transistors, so the voltage across resistor R 6 is:
- the current mirror formed by the first NMOS transistor M1 and the second NMOS transistor M2 mirrors the sum of the collector currents of the transistors Q1 and Q2 by m times, and then serves as the collector current of the transistor Q3 to obtain:
- the transistor Q1 generates a junction voltage including a negative temperature coefficient of the T term and the ⁇ 1 ⁇ ( ⁇ ) term. From the equation (4), the junction voltage of the transistor Q1 can be obtained as follows:
- the voltage across resistor R 8 is:
- V BEQI + V 3 ⁇ 4 + V R5 V B3 ⁇ 4I + I Q2 .R 2 + I (22)
- V is a positive temperature coefficient voltage produced by the resistor R 3
- V is (Î ⁇ ) n items comprising items and T ⁇ 1 ⁇ Temperature coefficient voltage. Available from equations (13) and (19) - (22)
- Vo is the compensated output reference voltage and (E g /q) is the bandgap voltage of silicon. From (15), (17), (24), (26), and (27), you can get:
- the ratio in (29) can be any value, and the ratio of the layout design can be selected according to the specific process)
- (28) Count Calculate the magnitude of the resistor, and substitute the equations (26) and (29) to obtain the resistance values of the resistor R 2 , the resistor R 3 , the resistor R 4 , the resistor R 5 , and the resistor R 6 .
- the compensated output reference voltage can be obtained from (27):
- the compensated output reference voltage is determined by the resistor R 7 and the resistor R 8
- the ratio is determined. Therefore, by adjusting the ratio of the resistor R 7 to the resistor R 8 , an output reference voltage of a different magnitude can be obtained.
- the value of the resistor R 7 is such that Ml and M2 operate in the saturation region, and the transistors Q1 to Q4 operate in the amplification region.
- the temperature compensated voltage reference circuit of the present invention is fabricated using a general purpose silicon gate BiCMOS process.
- Embodiment 3 is a circuit diagram of Embodiment 2 of the temperature compensation based voltage reference circuit of the present invention.
- the difference between this embodiment and Embodiment 1 is that the resistor is connected to the emitter of the transistor Q2, and the resistor R 2 is connected to between the collector of transistor M2 and the drain of the second NMOS transistor Q2, a resistor R 3 connected between the collector of the second NMOS transistor M2 and the drain of the transistor Q1, the positive input terminal of operational amplifier A2 is set in the transistor Q1 between the electrode and the resistor R 3, between the negative input terminal of operational amplifier A2 and the collector of transistor Q2 in the resistor R 2.
- Embodiment 4 is a circuit diagram of Embodiment 3 of the temperature compensation based voltage reference circuit of the present invention. As shown in the figure, the difference between this embodiment and Embodiment 2 is that the transistors Q1, Q2, Q3, and Q4 are of the NPN type; The tube M1 and the second MOS transistor M2 are N-channel enhancement type MOS field effect transistors, and the common connection terminal of the resistor R 5 and the resistor R 7 is grounded.
- Embodiment 5 is a circuit diagram of Embodiment 4 of the temperature compensation based voltage reference circuit of the present invention. As shown in the figure, the difference between this embodiment and Embodiment 1 is only that:
- the transistors Q1, Q2, Q3, and Q4 are of the NPN type;
- the MOS transistor M1 and the second MOS transistor M2 are N-channel enhancement type MOS field effect transistors, and the common connection terminal of the resistor R 5 and the resistor R 7 is grounded.
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Abstract
一种基于温度补偿的电压基准电路,包括正温度系数生成单元(1)、负温度系数生成单元(2)、温度补偿电路(3)、镜像电路(4)和分压电路(5),负温度系数生成单元(2)和温度补偿电路(3)共同产生零温度系数的基准电压,利用T项来补偿T项,利用Tln(T)项来补偿Tln(T)项,使得输出基准电压与T项和Tln(T)项无关,同时可以通过调节分压电路(5)中电阻的比例关系来确定输出电压值,并确定正负温度系数生成单元(2,3)中的工作电压。
Description
基于温度补偿的电压基准电路 技术领域
本发明涉及一种电压基准电路, 适用于需要低温度系数基准电压的模拟 IC 和数模混合 IC领域, 特别涉及一种基于温度补偿的电压基准电路。
背景技术
低温度系数的电压基准电路是许多模拟电路中必不可少的重要部分,其工作 原理是: 采用正负温度系数电压加权叠加的方式, 来产生低温度系数电压, 达到 降低基准电压随温度变化的目的。传统的电压基准由负温度系数的三极管 PN结 电压和正温度系数的三极管 PN结电压差加权叠加得到, 如图 1所示(不考虑电 阻的温度系数),运算放大器 AO使 g0点和 f0点电压相等,可得 1 = 1 则:
其中, k为波尔兹曼常数, T为绝对温度, q为电子的电量, Ie为三极管的 集电极电流, b为比例系数, Eg为硅的带隙能量。 再由 (2) 式可得:
AVBE = VT ( 3 )
BEQio,Q2o T
其中, k为波尔兹曼常数, T为绝对温度, q为电子的电量, nQ为由三极管 Q20与 Q10的个数之比。
由 (2) 式、 (3 ) 式可得:
VBEQ10 ^ + ^ln(IcQio ) -¾ ln(T) -^ T
Q q q Q1° q q (4)
其中,
Ic · 。 AVBE 。^)
(5)
Cqi。 。 Ri。 。 qR^o
得到:
由 (1 ) 式、 (3) 式、 (6) 式得到:
对比 (3) 式和 (6) 式可知, ΔνΒΕ 与 Τ相关, 而 VBE 不但与 T相关, 还与 Tln(T)相关, 因此, 二者相加后, 只能用与 T相关的项来补偿与 T ln(T)相 关的项, 如 (7 ) 式所示。 因此, 传统的电压基准电路, 其基准电压 始终与
T和 T ln(T)相关, 不能完全消除基准电压的温度系数,普通标准工艺制作的传统 基准电压温度系数约为 40ppmTC (百万分之一每摄氏度), 即在 -40°C到 85°C的 温度范围内, 基准电压变化率为:
40 ppm/ °C x [85°C - (- 40°C)] χ 100% = 0.5%。 因此急需一种能够消除 Τ和 Tln(T)影响的具有零温度系数的基于温度补偿 的电压基准电路。来克服传统基准电压产生电路输出基准电压与 T和 Tln(T)相关 导致的温度系数不能完全消除的问题。
发明内容
有鉴于此, 为了解决上述问题,本发明提出一种能够消除 T和 Tln(T)影响的 具有零温度系数的基于温度补偿的电压基准电路。来克服传统基准电压产生电路 输出基准电压与 T和 Tln(T)相关导致的温度系数不能完全消除的问题。
本发明的目的是这样实现的:
本发明提供的基于温度补偿的电压基准电路,包括正温度系数生成单元、负
温度系数生成单元、 温度补偿电路、 镜像电路和分压电路;
所述正温度系数生成单元, 用于产生包含 Tln(T)项的正温度系数电压, 并输 出包含 T项和 Tln(T)项的正温度系数的电流;
所述负温度系数生成单元, 用于产生包含 T项和 Tln(T)项的负温度系数电 压, 并输出包含 T项的正温度系数的电流; 所述温度补偿电路,用于将包含 T项和 Tln(T)项的正温度系数电流转换为包 含 T项和 Tln(T)项的正温度系数电压, 补偿负温度系数生成单元产生的包含 T 项和 Tln(T)项的负温度系数电压,负温度系数生成单元和温度补偿电路共同产生 零温度系数的基准电压;
其中, T为绝对温度;
所述镜像电路, 用于将负温度系数生成单元的输出电流镜像 m倍后输入到 正温度系数生成单元;
所述分压电路, 用于调节输出电压, 并确定正温度系数生成单元、 负温度系 数生成单元中的工作电压。
进一步, 所述温度补偿电路包括电阻 R5, 所述正温度系数生成单元包括运 算放大器 Al、 三极管 Q3、 三极管 Q4、 电阻 R6、 电阻 R4, 所述运算放大器 A1 的正输入端接三极管 Q4的基极, 运算放大器 A1的负输入端接三极管 Q4的集 电极, 运算放大器 A1的输出接三极管 Q4的发射极, 所述 R6的一端与运算放大 器 A1的负输入端及三极管 Q4的集电极连接, 所述 R6的另一端接地, 所述三极 管 Q4的发射极和三极管 Q3的发射极之间接电阻 R4, 三极管 Q3的集电极与镜 像电路的一端连接, 所述三极管 Q3的基极和三极管 Q4的基极连接;
进一步, 所述负温度系数生成单元包括运算放大器 A2、 三极管 Ql、 三极管 Q2、 电阻 、 电阻 R2, 电阻 R3 ; 所述三极管 Q1的发射极与运算放大器 A2的 正输入端连接, 所述运算放大器 A2的正输入端和电阻 R3的一端相接, 三极管 Q2的发射极通过电阻 与运算放大器 A2的负输入端连接,所述运算放大器 A2 的负输入端与电阻 R2的一端连接, 所述运算放大器 A2的输出端与电阻 R5的一 端连接, 所述电阻 R5的另一端与电阻 R2、 电阻 R3的另一端连接, 所述电阻 R2 的另一端与三极管 Q3的发射极连接, 所述三极管 Ql、三极管 Q2的集电极与镜 像电路的另一端连接, 所述运算放大器 A2的输出端与分压电路连接;
进一步, 所述镜像电路包括第一 NMOS管 Ml , 第二 NMOS管 M2, 所述第 一 NMOS管 Ml、 第二 NMOS管 M2的源极均接地, 第一 NMOS管 Ml、 第二 NMOS管 M2的栅极连接, 所述第二 NMOS管 M2的栅极与第二 NMOS管 M2 的漏极连接,所述第一 NMOS管 Ml的漏极与三极管 Q3的集电极连接,所述第 二 NMOS管 M2的栅极与三极管 Ql、 三极管 Q2的集电极连接; 进一步, 所述分压电路包括电阻 R7和电阻 R8, 所述电阻 R8与运算放大器 A2的输出端连接, 所述电阻 R8的另一端与电阻 R7的一端以及三极管 Ql、 三极 管 Q2、三极管 Q3、三极管 Q4的基极连接,所述电阻 R7的另一端与第一 NMOS 管 Ml的源极和第二 NMOS管 M2的源极连接, 运算放大器 A2与电阻 R5、 电 阻 R8的连接点为基准电路的输出端 Vo;
进一步, 所述输出基准电压 Vo 的值由电阻 R7和电阻 R8的比值决定, Vo
, 其中, (Eg /q)为硅的带隙电压, 通过调节电阻 R7和电 阻 的比值, 得到不同幅度的输出基准电压; 进一步, 所述电阻 R4和电阻 满足以下关系:
R4 = 2 ; 进一步, 所述负温度系数生成单元包括至少一个三极管 Q1和至少一个三极 管 Q2, 所述所有的三极管 Q2和所有的三极管 Q1的个数之比为 n, 所述正温度 系数生成单元包括至少一个三极管 Q3和至少一个三极管 Q4, 所述所有的三极 管 Q4与所有的三极管 Q3个数之比为 p,所述镜像电路包括至少一个第一 NMOS 管 Ml和至少一个第二 NMOS管 M2, 其中, η>1, ρ>1。 本发明的优点在于: 本发明的基于温度补偿的电压基准电路, 与传统的电压 基准电路相比, 它具有以下特点:
1. 传统的电压基准电路用 T项来补偿 T ln(T) 项, 而本发明的基于温度补 偿的电压基准电路, 利用 Τ项来补偿 Τ项, 利用 T ln(T) 项来补偿 T ln(T)项, 因 此本发明的电压基准电路的补偿的针对性更强。
2. 传统电压基准电路用 T项来补偿 T ln(T)项, 因此, 输出基准电压与 T和 T ln(T)同时相关, 导致其温度系数不能完全消除, 约为 40ppmTC, 而本发明的 电压基准电路, 其输出基准电压与 T和 T ln(T)无关, 因此本发明电路能够得到 零温度系数的基准电压。
3. 传统的电压基准电路输出电压幅度为硅的带隙电压, 因此其输出电压为 固定值, 而本发明电路的电压基准\^ = (58 / (1 + 1 7 / 1¾8), 可以通过调节电阻 R7和电阻 R8的比例关系, 灵活地确定输出电压值, 因此本发明电路可得到一定 范围的任意输出电压值。
综上所述, 本发明的基于温度补偿的电压基准电路同时具有补偿针对性强、 零温度系数、输出电压值可调的优点,有效克服了传统电压基准电路补偿针对性 弱、 温度系数不能完全消除、 输出电压值固定的缺点。
本发明的其它优点、 目标和特征在某种程度上将在随后的说明书中进行阐 述, 并且在某种程度上,基于对下文的考察研究对本领域技术人员而言将是显而 易见的, 或者可以从本发明的实践中得到教导。本发明的目标和其它优点可以通 过下面的说明书, 权利要求书, 以及附图中所特别指出的结构来实现和获得。
附图说明
为了使本发明的目的、 技术方案和优点更加清楚, 下面将结合附图对本发 明作进一步的详细描述, 其中:
图 1是传统的电压基准电路的电路图;
图 2是本发明的基于温度补偿的电压基准电路的实施例 1电路图; 图 3是本发明的基于温度补偿的电压基准电路的实施例 2电路图; 图 4是本发明的基于温度补偿的电压基准电路的实施例 3电路图; 图 5是本发明的基于温度补偿的电压基准电路的实施例 4电路图。
具体实施方式
以下将结合附图, 对本发明的优选实施例进行详细的描述; 应当理解, 优选 实施例仅为了说明本发明, 而不是为了限制本发明的保护范围。
实施例 1
图 2是本发明的基于温度补偿的电压基准电路的实施例 1电路图,如图所示: 本发明提供的基于温度补偿的电压基准电路, 包括正温度系数生成单元 1、 负温 度系数生成单元 2、 温度补偿电路 3、 镜像电路 4和分压电路 5;
所述正温度系数生成单元 1, 用于产生包含 Tln(T)项的正温度系数电压, 并 输出包含 T项和 Tln(T)项的正温度系数的电流;
所述负温度系数生成单元 2, 用于产生包含 T项和 Tln(T)项的负温度系数电 压, 并输出包含 T项的正温度系数的电流;
所述温度补偿电路 3, 用于将包含 T项和 Tln(T)项的正温度系数电流转换为 包含 T项和 Tln(T)项的正温度系数电压,补偿负温度系数生成单元产生的包含 T 项和 Tln(T)项的负温度系数电压,负温度系数生成单元和温度补偿电路共同产生 零温度系数的基准电压;
其中, T为绝对温度;
所述镜像电路 4,用于将负温度系数生成单元的输出电流镜像 m倍后输入到 正温度系数生成单元;
所述分压电路 5, 用于调节输出电压, 并确定正温度系数生成单元、 负温度 系数生成单元中的工作电压。
作为上述实施例的进一步改进, 所述温度补偿电路包括电阻 R5, 所述正温 度系数生成单元包括运算放大器 Al、三极管 Q3、三极管 Q4、 电阻 R6、 电阻 R4, 所述运算放大器 A1的正输入端接三极管 Q4的基极, 运算放大器 A1的负输入 端接三极管 Q4的集电极, 运算放大器 A1的输出接三极管 Q4的发射极, 所述 R6的一端与运算放大器 A1的负输入端及三极管 Q4的集电极连接,所述 R6的另 一端接地, 所述三极管 Q4的发射极和三极管 Q3的发射极之间接电阻 R4, 三极 管 Q3的集电极与镜像电路的一端连接, 所述三极管 Q3的基极和三极管 Q4的 基极连接。
作为上述实施例的进一步改进, 所述负温度系数生成单元包括运算放大器 A2、 三极管 Ql、 三极管 Q2、 电阻 、 电阻 R2, 电阻 R3 ; 所述三极管 Q1的发 射极与运算放大器 A2的正输入端连接, 所述运算放大器 A2的正输入端和电阻 R3的一端相接,三极管 Q2的发射极通过电阻 与运算放大器 A2的负输入端连 接, 所述运算放大器 A2的负输入端与电阻 R2的一端连接, 所述运算放大器 A2 的输出端与电阻 的一端连接, 所述电阻 的另一端与电阻 R2、 电阻 R3的另 一端连接, 所述电阻 R2的另一端与三极管 Q3的发射极连接, 所述三极管 Ql、 三极管 Q2的集电极与镜像电路的另一端连接, 所述运算放大器 A2的输出端与 分压电路连接。
作为上述实施例的进一步改进,所述镜像电路包括第一 NMOS管 Ml ,第二 NMOS管 M2, 所述第一 NMOS管 Ml、第二 NMOS管 M2的源极均接地, 第一 NMOS管 Ml、 第二 NMOS管 M2的栅极连接, 所述第二 NMOS管 M2的栅极
与第二 NMOS管 M2的漏极连接, 所述第一 NM0S管 Ml的漏极与三极管 Q3 的集电极连接, 所述第二 NMOS管 M2的栅极与三极管 Ql、 三极管 Q2的集电 极连接。
作为上述实施例的进一步改进, 所述分压电路包括电阻 R7和电阻 R8, 所述 电阻 R8与 A2的输出端连接,所述电阻 R8的另一端与电阻 R7的一端以及三极管 Ql、 三极管 Q2、 三极管 Q3、 三极管 Q4的基极连接, 所述电阻 R7的另一端与 第一 NMOS管 Ml的源极和第二 NMOS管 M2的源极连接, 运算放大器 A2与 电阻 R5、 电阻 R8的连接点为基准电路的输出端 Vo。
作为上述实施例的进一步改进,所述输出基准电压 Vo的值由电阻 R7和电阻 R8的比值决定, Vc
, 其中, (Eg /q)为硅的带隙电压, 通过 调节电阻 R7和电阻 R8的比值, 得到不同幅度的输出基准电压。
作为上述实施例的进一步改进, 所述电阻 R4和电阻 满足以下关系: ^ 3 作为上述实施例的进一步改进,所述负温度系数生成单元包括至少一个三极 管 Q1和至少一个三极管 Q2, 所述三极管 Q1和三极管 Q2由相同的基本单元三 极管构成, 所有的三极管 Q2和所有的三极管 Q1的个数之比为 n, 正温度系数 生成单元包括至少一个三极管 Q3和至少一个三极管 Q4,所述三极管 Q3和三极 管 Q4由相同的基本单元三极管构成,所述所有的三极管 Q4与所有的三极管 Q3 个数之比为 p,镜像电路包括至少一个第一 NMOS管 Ml和至少一个第二 NMOS 管 M2, 所述第一 NMOS管 Ml和第二 NMOS管 M2由相同的基本单元 NMOS 管构成, 所有的第一 NMOS管 Ml和第二 NMOS管 M2个数之比为 m, 其中, η>1 , ρ>1。
下面详细描述本发明提供的基于温度补偿的电压基准电路的原理和具体实 施方式:
本发明具体实施的一种总体结构如图 2所示, 包括两个运算放大器 A1~A2、 四个三极管 Q1~Q4、 两个 M0S管 M1~M2和八个电阻
结点 a、 结点 b、 结点 c、 结点 d分别为三极管 Q4、 三极管 Q3、 三极管 Q2、 三极管 Q1的基极连 接点; 结点 e为电阻 R7和电阻 R8的公共接点且与三极管 Q4、 三极管 Q3、 三极
管 Q2、 三极管 Ql的基极连接; 结点 f为运算放大器 A2正输入端与三极管 Q1 发射极连接点, 结点 g为运算放大器 A2负输入端与电阻 和电阻 R2公共接点 的汇合点, 结点 h为三极管 Q4与运算放大器 A1负输入端的连接点, 结点 i为 运算放大器 A2输出端;图 2中的具体连接关系与本说明书的发明内容部分相同, 此处不考虑电阻和 MOS管的温度系数, 它的工作原理如下:
三极管 Q1和三极管 Q2的 PN结电压差产生包含 T项的正温度系数电压, 运算放大器 A2使结点 f和结点 g的电压相等, 因此, 电阻 上的电压为:
I I R k.ln(n )
V¾ = AVBE12 = VT In (-^ ) -VT ln(^) = VT ln(n ·¾ = ^ T (8)
' Is nls q 其中, n为三极管 Q2与三极管 Ql的个数之比。
可得:
I =1 =—— ¾ V0 (11)
Q4 ¾ (Rs + R^ 。
第一 NMOS管 Ml和第二 NMOS管 M2构成的电流镜将三极管 Q1 Q2的集 电极电流之和镜像 m倍后, 作为三极管 Q3的集电极电流, 得:
IQ3 = m. (IQ1 + IQ2) = m-(l + ¾IQ2 ( 12 )
K3 由式 (8) 可得:
V k.ln(n )
i02=^= (13)
由 (12) 式、 (13) 式, 得: m-k-ln(n-— )
由 (9) 式、 (11) 式、 (14) 式, 得:
其中, αΊ = ln( ) ( 17 ) qR4 a,=- (18) qR4
由 (12) 式、 (14) 式、 (16) 式, 得电阻 R5上的电流为:
IR = I + 1 + 1 + Ir =(-^-·α1+α2)·Τ+α3 ·Τ1η(Τ) (19)
5 4 m
电阻 R8上的电压为:
=VBEQI +V¾ +VR5 =VB¾I +IQ2.R2 + I (22) 其中 V 为电阻 R3产生的正温度系数电压, V 为包含 T项和 Τ 1η(Τ)项的正 温度系数电压。
由式 (13) 式、 (19) - (22) 式可得
(23)
(25 ) q
由 (18) 式、 (25) 式, 得:
(26) R4 2 由 (23) 式、 (24) 式、 (25) 式可知, 此时 V .~ ?^ =V = (27 )
° i^ + Rs ¾ q
+r21 -ln(n -r2 3) + r5 1 · (m + 1) · (1 + r2 3 ) · ln(n · r23 )
选定 (29) 式中的电阻比例系数后 (理论上来讲, (29) 式中的比值可为任 意值, 选取时可根据具体工艺选择便于版图设计的比值), 就可通过 (28 ) 式计
算出电阻 的大小, 再代入 (26) 式和 (29) 式, 可得电阻 R2、 电阻 R3、 电阻 R4、 电阻 R5、 电阻 R6的阻值。
由 (30) 式可知, ^表达式中不包含与温度 T相关的项, 因此补偿后的输 出基准电压,温度系数为零;补偿后的输出基准电压\^由电阻 R7和电阻 R8的比 值决定, 因此, 通过调节电阻 R7和电阻 R8的比值, 可以得到不同幅度的输出基 准电压。 其中电阻 R7的取值要使 Ml和 M2工作在饱和区, 三极管 Q1~Q4工作 在放大区。 本发明的基于温度补偿的电压基准电路采用通用硅栅 BiCMOS工艺 制造。
实施例 2
图 3是本发明的基于温度补偿的电压基准电路的实施例 2电路图,如图所示, 本实施例与实施例 1的区别在于: 电阻 接在三极管 Q2的发射极上, 电阻 R2 接在三极管 Q2的集电极与第二 NMOS管 M2漏极之间, 电阻 R3接在三极管 Q1 的集电极与第二 NMOS管 M2漏极之间,运算放大器 A2的正输入端接在三极管 Q1的集电极与电阻 R3之间, 运算放大器 A2的负输入端接在三极管 Q2的集电 极与电阻 R2之间。
实施例 3
图 4是本发明的基于温度补偿的电压基准电路的实施例 3电路图,如图所示, 本实施例与实施例 2的区别在于: 三极管 Ql、 Q2、 Q3、 Q4为 NPN型; 第一 MOS管 Ml和第二 MOS管 M2为 N沟道增强型 MOS场效应管, 电阻 R5和电 阻 R7的公共连接端接地。
实施例 4
图 5是本发明的基于温度补偿的电压基准电路的实施例 4电路图,如图所示, 本实施例与实施例 1的区别仅在于: 三极管 Ql、 Q2、 Q3、 Q4为 NPN型; 第一 MOS管 Ml和第二 MOS管 M2为 N沟道增强型 MOS场效应管, 电阻 R5和电 阻 R7的公共连接端接地。
以上所述仅为本发明的优选实施例, 并不用于限制本发明, 显然, 本领域的
技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。 这 样, 倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之 内, 则本发明也意图包含这些改动和变型在内。
Claims
1. 基于温度补偿的电压基准电路,其特征在于:包括正温度系数生成单元、 负温度系数生成单元、 温度补偿电路、 镜像电路和分压电路; 所述正温度系数生成单元, 用于产生包含 Tln(T)项的正温度系数电压, 并输出包含 T项和 Tln(T)项的正温度系数的电流; 所述负温度系数生成单元, 用于产生包含 T项和 Tln(T)项的负温度系 数电压, 并输出包含 T项的正温度系数的电流; 所述温度补偿电路, 用于将包含 T项和 Tln(T)项的正温度系数电流转 换为包含 T项和 Tln(T)项的正温度系数电压, 补偿负温度系数生成单元产 生的包含 T项和 Tln(T)项的负温度系数电压, 负温度系数生成单元和温度 补偿电路共同产生零温度系数的基准电压; 其中, T为绝对温度; 所述镜像电路, 用于将负温度系数生成单元的输出电流镜像 m倍后输 入到正温度系数生成单元; 所述分压电路, 用于调节输出电压, 并确定正温度系数生成单元、 负 温度系数生成单元中的工作电压。
2. 根据权利要求 1所述的基于温度补偿的电压基准电路, 其特征在于: 所 述温度补偿电路包括电阻 R5,所述正温度系数生成单元包括运算放大器 Al、 三极管 Q3、 三极管 Q4、 电阻 R6、 电阻 R4, 所述运算放大器 A1的正输入端 接三极管 Q4的基极,运算放大器 A1的负输入端接三极管 Q4的集电极,运 算放大器 A1的输出接三极管 Q4的发射极, 所述电阻 R6的一端与运算放大 器 A1的负输入端及三极管 Q4的集电极连接, 所述电阻 R6的另一端接地, 所述三极管 Q4的发射极和三极管 Q3的发射极之间接电阻 R4, 三极管 Q3 的集电极与镜像电路的一端连接, 所述三极管 Q3的基极和三极管 Q4的基 极连接。
3. 根据权利要求 2所述的基于温度补偿的电压基准电路, 其特征在于: 所
述负温度系数生成单元包括运算放大器 A2、 三极管 Ql、 三极管 Q2、 电阻 Ri 电阻 R2, 电阻 R3 ; 所述三极管 Q1的发射极与运算放大器 A2的正输入 端连接, 所述运算放大器 A2的正输入端和电阻 R3的一端相接, 三极管 Q2 的发射极通过电阻 与运算放大器 A2的负输入端连接, 所述运算放大器 A2的负输入端与电阻 R2的一端连接, 所述运算放大器 A2的输出端与电阻 R5的一端连接, 所述电阻 R5的另一端与电阻 R2、 电阻 R3的另一端连接, 所述电阻 R2的另一端与三极管 Q3的发射极连接, 所述三极管 Ql、 三极管 Q2的集电极与镜像电路的另一端连接,所述运算放大器 A2的输出端与分压 电路连接。
4. 根据权利要求 3所述的基于温度补偿的电压基准电路, 其特征在于: 所 述镜像电路包括第一 NMOS管 Ml , 第二 NMOS管 M2, 所述第一 NMOS 管 Ml、 第二 NMOS管 M2的源极均接地, 第一 NMOS管 Ml、第二 NMOS 管 M2的栅极连接, 所述第二 NMOS管 M2的栅极与第二 NMOS管 M2的 漏极连接, 所述第一 NMOS管 Ml的漏极与三极管 Q3的集电极连接, 所述 第二 NMOS管 M2的栅极与三极管 Ql、 三极管 Q2的集电极连接。
5. 根据权利要求 4所述的基于温度补偿的电压基准电路, 其特征在于: 所 述分压电路包括电阻 R7和电阻 R8, 所述电阻 R8与运算放大器 A2的输出端 连接, 所述电阻 R8的另一端与电阻 R7的一端以及三极管 Ql、 三极管 Q2、 三极管 Q3、三极管 Q4的基极连接, 所述电阻 R7的另一端与第一 NMOS管 Ml的源极和第二 NMOS管 M2的源极连接, 运算放大器 A2与电阻 R5、 电 阻 R8的连接点为基准电路的输出端 Vo。
7. 根据权利要求 6所述的基于温度补偿的电压基准电路 , 其特征在于: 所述电阻 R4和电阻 R5满足以下关系: = 。
8. 根据权利要求 7所述的基于温度补偿的电压基准电路, 其特征在于: 所 述负温度系数生成单元包括至少一个三极管 Q1和至少一个三极管 Q2,所述 所有的三极管 Q2和所有的三极管 Q1的个数之比为 n,所述正温度系数生成 单元包括至少一个三极管 Q3和至少一个三极管 Q4, 所述所有的三极管 Q4 与所有的三极管 Q3个数之比为 p, 其中, η>1, ρ>1。
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| US13/993,117 US9128497B2 (en) | 2011-07-29 | 2011-08-24 | Voltage reference circuit based on temperature compensation |
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| CN2011102165876A CN102323847B (zh) | 2011-07-29 | 2011-07-29 | 基于温度补偿的电压基准电路 |
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| US20130328620A1 (en) | 2013-12-12 |
| CN102323847A (zh) | 2012-01-18 |
| CN102323847B (zh) | 2013-11-20 |
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