WO2013060949A1 - Procédé de lissage d'une surface par traitement thermique - Google Patents
Procédé de lissage d'une surface par traitement thermique Download PDFInfo
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- WO2013060949A1 WO2013060949A1 PCT/FR2012/000436 FR2012000436W WO2013060949A1 WO 2013060949 A1 WO2013060949 A1 WO 2013060949A1 FR 2012000436 W FR2012000436 W FR 2012000436W WO 2013060949 A1 WO2013060949 A1 WO 2013060949A1
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- substrate
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- rough surface
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- H10P95/904—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H10P90/1916—
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- H10P95/906—
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- H10W10/181—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H10P30/204—
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- H10P30/208—
Definitions
- the invention relates to a method of smoothing, using a heat treatment, a rough surface of a first substrate comprising on the surface a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In , P and N.
- the substrates made of semiconductor material are generally obtained by sawing an ingot based on the same semiconductor material.
- the sawing process produces substrates having rough surfaces and having structural defects such as dislocations in the crystal lattice.
- This technique generally comprises three steps: a first step of ion implantation of hydrogen and / or rare gases to create a buried fragile layer within the initial substrate, a second step of joining the initial substrate to a receiving substrate ( or stiffener), a third heat treatment step to obtain a fracture at the fragile zone.
- This weakening step can be assisted by an application of mechanical forces.
- the surfaces obtained after fracture especially in the case of transfer of thin layers of gallium alloy and arsenic (GaAs) or indium and phosphorus alloy (InP) may have a high roughness, incompatible with the intended application .
- CMP chemical mechanical polishing
- the patent application FR 2867307 describes an embodiment of a specific heat treatment of healing of the crystalline structure after a fracture step obtained by the Smart Cut TM process.
- This method applies to all semiconductor materials and more particularly to semiconductor based on silicon and germanium alloy (SiGe).
- This heat treatment also has the effect of smoothing the surfaces obtained after fracture while the surfaces are still in contact. Precautions must be taken into contact during this heat treatment, especially in terms of thermal budget (torque time and temperature of the heat treatment) to prevent the two surfaces in contact irreversibly recovering.
- scratches may appear on the faces since the surfaces remain in contact after fracture. Indeed, these scratches can come from the presence of particles or material peaks that appear at the time of the fracture between the facing surfaces.
- the said smoothing method also comprises a step of heating the first substrate in such a way as to partially desorb one of the elements of the said alloy and to reach the saturation vapor pressure of this element in the confinement space and to achieve a sufficient mobility of the surface atoms. to reduce the roughness of the rough surface.
- FIG. schematically and in section, an embodiment of a method of heat treatment of a substrate by pseudo-contact
- FIG. 2 represents, schematically and in section, a first embodiment of a method of smoothing a rough surface of a substrate according to the invention
- FIG. 3 shows schematically and in section, a second embodiment of a method of smoothing a rough surface of a substrate according to the invention
- FIG. 4 and 5 show, schematically and in section, a variant of the second embodiment of a method of smoothing a rough surface of a substrate according to the invention
- FIG. 6A to 6C show, schematically and in section, a nacelle used in one embodiment of a method of smoothing a rough surface of a substrate according to the invention.
- a reliable, practical and inexpensive means for producing substrates comprising a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N having at least one smooth surface devoid of structural defects, is to use a smoothing by heat treatment with standard equipment and atmospheres by creating locally at the surface to be treated an atmosphere avoiding excessive decomposition of this alloy.
- the pseudo-contact method consists in placing a protective substrate 2 on the useful surface Si of a substrate 1 and in thermally treating the substrate 1 thus protected.
- the protective substrate 2 is chosen so as to create with the substrate 1 a local atmosphere, in the vicinity of the useful surface Si, which limits the decomposition of the semiconductor alloy during the heat treatment.
- a local atmosphere in the vicinity of the useful surface Si, which limits the decomposition of the semiconductor alloy during the heat treatment.
- the substrates 1 and 2 are made of GaAs
- a local arsenic saturated atmosphere is created between the two substrates 1 and 2 brought into contact, during the heat treatment. This local atmosphere is generated by a slight temporary GaAs decomposition at each surface of substrates 1 and 2 put in contact.
- the transposition of the pseudo-contact process in the field of surface treatment is not suitable because the thermal smoothing requires a thermal treatment with a large thermal budget.
- this type of heat treatment may cause the adhesion of the two substrates placed one on the other in a pseudo-contact process.
- a substrate comprising a surface to be smoothed can be separated from another substrate by a non-zero distance d during a smoothing heat treatment as detailed in the following example.
- a method of smoothing a rough surface 4 of a first substrate 3 uses a second substrate 6.
- Said rough surface 4 is made of a semiconductor alloy based on a at least two elements selected from Ga, As, Al, In, P, and N.
- said alloy is a III-V type semiconductor alloy.
- the alloy of the rough surface 4 can also be a doped semiconductor alloy.
- the semiconductor alloy may be doped with an element selected from Si, Ge, Cr, Fe, S, Sn and Zn, with an atomic proportion of less than 1 per thousand.
- the second substrate 6 is placed facing the first substrate 3, the two substrates being separated by a distance d at least equal to 10 ⁇ so that the two facing surfaces defining the confinement space can not adhere to each other. the other during heat treatment.
- the two materials forming the two surfaces of the two substrates 3 and 6 opposite are not in direct contact.
- the first 3 and second 6 substrates are not in contact.
- no element or part of the second substrate 6 is in contact with an element or part of the first substrate 3.
- the second substrate 6 is arranged so that the rough surface 4 is separated from a surface of the second substrate 6 of the distance d which is at least 10 ⁇ .
- the portions facing the first and second substrates 3 and 6 thus define a confinement space 5.
- the confinement space 5 is an open space which avoids any problem of overpressure between the two substrates opposite and therefore a weakening of the substrates.
- rough surface is meant a surface having roughness and requiring treatment to reduce its asperities before the use of said surface.
- a rough surface typically has a measured roughness greater than 5 nm RMS.
- the rough surface 4 and the surface of the substrate 6 are separated by a distance of at least 10 ⁇ that for any sample of 1 ⁇ m ⁇ 1 ⁇ m of this rough surface 4, the distance between the average plane of this sample and the average plane of the sample of 1 pm x 1 pm of the surface of the second substrate 6 opposite or at least 10 ⁇ .
- the average plane on a sample being defined by its height z m with respect to an arbitrary reference plane according to the formula:
- the first substrate 3 is then heated so as to partially desorb one of the elements of said semiconductor alloy and to reach a saturation vapor pressure of this element in the confinement space.
- a heat treatment is performed so as to heat the first substrate 3.
- the separation distance d, and the temperature and the duration of the heat treatment are chosen so as to obtain an atmosphere containing a saturating vapor of one of the elements of the semiconductor alloy of the rough surface 4 and to provide mobility to the surface atoms sufficient to reduce the roughness.
- the distance d avoids the bonding of the rough surface 4 and the surface of the second substrate 6 during the implementation of the heat treatment.
- the heat treatment can be performed at a high temperature to obtain a fast and effective smoothing of the rough surface 4, avoiding any risk of sticking.
- the heat treatment for heating the first substrate 3 is carried out at a temperature above 500 ° C.
- This heat treatment must of course be performed at a temperature below the melting temperature of the semiconductor alloy.
- the first 3 and second 6 substrates are not in direct contact and the separation of the rough surface 4 from the surface of the second substrate 6 may be carried out by any known means, preferably by at least one shim having a thickness at least equal to separation distance d.
- a shim having a thickness at least equal to separation distance d.
- the arrangement of the holds is made so as to have an open confinement space.
- shims (not shown in the figures) having a thickness at least equal to the distance d may be disposed on the surface of the second substrate 6.
- the thickness of the shims required, especially the position of these wedges on the second substrate 6, the curvature of the surface (denoted “baw") of the first and second substrates 3 and 6 and variations of thickness of the substrates (denoted "TTV", in English “total thickness variation”).
- the first substrate 3 is then placed on these wedges.
- the wedges are arranged in such a way that they are in contact only with the peripheral edges of the first substrate 3.
- the wedges are chosen so as to avoid any bonding with the first 3 and second 6 substrates.
- the wedges are based on a different material, the material of the first substrate 3, and the material of the second substrate 6.
- the wedges may also be based on a material whose characteristics do not favor the bonding of said material. with the first and second substrates 3 and 6, such as quartz, silicon or silicon carbide (SiC). Furthermore, the wedges may have a surface quality, for example a very rough surface or with a small contact surface, which makes it possible to avoid bonding between the wedges and the first 3 and second 6 substrates. Alternatively, it is possible to provide mechanisms for maintaining substrates 3 and 6. By way of example, substrate suction means may be used to maintain substrates 3 and 6 at a given separation distance d.
- the smoothing method of the rough surface 4 comprises an essential step of heat treatment. This step is performed so as to provide a large thermal budget to the surface atoms. Depending on the nature of the semiconductor alloy of the rough surface 4, a thermal budget sufficiently effective will be chosen so that the surface atoms can acquire mobility to reduce the surface energy and reduce the roughness. Typically for GaAs and ⁇ , the thermal budget will be of the order of, or even greater than, 30 minutes at 700 ° C. and 2 minutes at 1000 ° C.
- the heat treatment step is carried out according to any known method, for example using a conventional tubular furnace or a rapid heat treatment furnace noted RTA (in English "Rapid Thermal Annealing").
- RTA Rapid Thermal Annealing
- the clever arrangement of the substrate 3 with respect to the surface of the second substrate 6, allows the use of a conventional heat treatment for smoothing the rough surface 4.
- the thermal smoothing is carried out in using a heat treatment under conventional atmospheres, for example, neutral atmospheres such as nitrogen (N 2 ), helium (He) or argon (Ar) or a mixture comprising one of these gases, for example a mixture of N 2 and H 2 .
- the semiconductor alloy of the rough surface 4 decomposes by locally creating an atmosphere enriched by at least one of the chemical elements constituting the semiconductor alloy.
- the confinement space 5 then comprises a local atmosphere saturated by this chemical element, which subsequently makes it possible to minimize the decomposition of the rough surface 4.
- the maintenance of the rough surface 4 and the surface of the substrate 6 to at least a distance of 10 ⁇ advantageously allows to avoid any risk of direct bonding between these two surfaces.
- the constraints on the conditions of the smoothing heat treatment are relaxed. In other words, it is possible to implement a heat treatment at a higher temperature or for a longer time without risk of sticking. Increasing the temperature of the heat treatment makes it possible to obtain equivalent or even better quality smoothing with a shorter heat treatment time, which makes the smoothing process less expensive and more efficient.
- the separation distance d between the rough surface 4 and the surface of the second substrate 6 is chosen so as to be as small as possible.
- the effectiveness of the confinement depends on the ability to saturate the confinement space 5 with one element of the semiconductor alloy of the first substrate 3: the greater the distance d, the greater the volume to be saturated.
- the increase in the distance d facilitates the escape of the saturating species towards the outside of the confinement space 5.
- the separation distance d is less than 2 mm, or even 1 mm or 500 nm.
- the roughness of the surface 4 can be reduced while avoiding the decomposition of the alloy of the first substrate 3.
- the second substrate 6 may, for example, be a substrate support, made of thermally stable material with respect to the first substrate 3, that is to say that withstands temperatures above the melting point of the material of the first substrate 3 (about 1238 ° C for GaAs and about 1062 ° C for InP).
- the second substrate 6 is an RTA furnace plate receiving medium, for example, a graphite susceptor comprising a silicon carbide (SiC) alloy coating.
- the heat treatment is carried out at relatively high temperatures, for example between 800 and 1200 ° C for GaAs and between 700 and 1000 ° C for InP.
- the heat treatment is advantageously carried out at a temperature below the melting temperature of the semiconductor alloy of the substrate 3.
- the semiconductor alloy of the first substrate 3 is preferably, a GaAs-based semiconductor alloy, in which case the heat treatment is advantageously carried out at a temperature greater than or equal to 700 ° C., or even greater than 800 ° C. or 900 ° C., but less than its melting temperature, and therefore typically less than 1200 ° C.
- the semiconductor alloy of the first substrate 3 may also be an alloy of InP, in this case the heat treatment is advantageously carried out at a temperature greater than or equal to 600 ° C., or even greater than 700 ° C. or 800 ° C but lower than its melting temperature, and therefore typically less than 1000 ° C.
- the surface of the second substrate 6 comprises a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N.
- the semiconductor alloy of the surface of the second substrate 6 is identical to that of the rough surface 4.
- the surface of the second substrate 6 may be rough, typically it has an RMS roughness greater than 5 nm. According to this embodiment, a faster saturation of the confinement space 5 can be performed, since the surfaces of the first and second substrates 3 and 6 participate in it, thus allowing simultaneous smoothing of the rough surface 4 and the surface of the second substrate 6.
- the separation distance d is of the order of the sum of the respective maximum curvatures of the substrates 3 and 6, to which will be added a margin to take into account the thickness variation of the substrates 3 and 6.
- the maximum curvature is of the order of 20 ⁇ .
- the separation distance d during the smoothing heat treatment will typically be of the order of 50 ⁇ .
- a smoothing method using a heat treatment of a rough GaAs surface has been implemented.
- This surface was obtained following a transfer of a layer of GaAs on a silicon support substrate by the Smart Cut TM process.
- the implantation conditions for GaAs transfer were as follows: co-implantation of 5.10 15 He + / cm 2 at 105 keV and 3.10 16 H 2 + / cm 2 at 160 keV.
- the fracture was obtained at a temperature of the order of 230 ° C.
- the fracture step produced a GaAs surface having a measured roughness of 21 nm RMS.
- the substrates thus obtained were annealed at ambient pressure in a standard RTA furnace under a neutral atmosphere (N2).
- the substrates were arranged in pairs with their GaAs face facing each other.
- the GaAs substrates of each pair were separated by shims having thicknesses between 50 ⁇ and 400 ⁇ .
- the measured surface roughness was decreased for smoothing heat treatment temperatures greater than or equal to 700 ° C.
- the roughness was lowered to 3.2 nm RMS.
- the measured roughness of the GaAs surfaces decreases as the separation distance d decreases. Indeed, the roughness was lowered from 4.6 nm RMS to 3.8 nm RMS and 3.2 nm RMS when the thickness of the shims went from 400 to 220 ⁇ and 50pm.
- GaAs substrates were annealed in a tube furnace under N 2 atmosphere at reduced pressure and at a temperature of 800 ° C for one hour. Each GaAs substrate was placed in a slot of a quartz nacelle before being introduced into the oven. With the slots spaced about 4 mm apart, the GaAs substrates could be annealed in a facing arrangement with a separation distance d of about 4 mm. According to these heat treatment conditions, the surface roughness of the GaAs substrates has been greatly increased thus making it impossible to measure the roughness by interferometry. This sharp increase in the roughness of the annealed GaAs substrates, according to this arrangement, is generated by the decomposition of the surface of the GaAs substrates.
- the separation distance d between the GaAs substrates is too great, it allows the flow of nitrogen gas in the vicinity of the GaAs substrate surfaces and the local saturation with arsenic is no longer possible.
- Similar tests were carried out after transfer of an InP layer by the Smart Cut TM process.
- the fracture step generated two InP rough surfaces, at least one having a measured roughness of 14 nm RMS.
- the two InP surfaces obtained after the fracture step were placed opposite to be separated by wedges of 50 ⁇ .
- a heat treatment in an RTA oven at 700 ° C. for 30 minutes of the two InP surfaces separated by 50 ⁇ spacers made it possible to reduce the roughness to about 4 nm RMS.
- Heat treatment at 800 ° C. for 30 minutes following a "pseudo-contact" configuration resulted in the bonding of the two InP surfaces.
- the rough surfaces are obtained from the same support 7.
- an embrittlement zone 8 is formed inside the support 7
- the weakening zone 8 is advantageously obtained by means of an implantation of a weakening element.
- the support 7 may be formed by bonding a donor wafer 3 'and a receiving wafer 6' after the step of implantation of the weakening element in the donor wafer 3 '. The bonding being performed at the bonding interface 9.
- the support 7 is then separated at the weakening zone 8 to form the first and second substrates 3 and 6.
- the rough surface 4 of the first substrate 3 and the surface of the second substrate 6 are formed by the embrittlement zone 8.
- the embrittlement zone 8 is obtained by means of implantation of hydrogen and / or rare gases, and the step separation is carried out by means of a heat treatment.
- mechanical means are used to maintain the first and second substrates 3 and 6 at a separation distance d greater than 10 ⁇ , preferably of the order of 50 ⁇ .
- These mechanical means may comprise, for example, corners distributed in a substantially regular manner around the periphery of the substrates 3 and 6, preferably at the bevel.
- the mechanical means may also consist of insertion means such as a blade or a guillotine or else suction means arranged on either side of the substrates. Then, a heat treatment for smoothing the surfaces of the substrates 3 and 6 is performed as described above.
- the separation heat treatment and the smoothing heat treatment are carried out in the same furnace.
- the smoothing method according to the invention is advantageously used in combination with the Smart Cut TM process to obtain surfaces of low roughness, in particular GaAs or InP. Such materials may for example be carried on silicon substrates.
- the separation or fracture step is performed collectively.
- a large number of supports 7 to be separated is placed vertically in slots 11 of a nacelle 10, advantageously made of quartz (FIG. 6A).
- the slots 11 of the nacelle 10 are spaced from each other by a distance of up to 4 mm.
- each slot 11 of the nacelle 10 is provided with corners 12, for example distributed substantially uniformly around the periphery of the supports 7, in particular at the bevel.
- the corners 12 are intended to maintain the surfaces obtained (the surfaces of the first 3 and second 6 substrates) after fracture at a separation distance of the order of 50 ⁇ .
- the corners 12 can also be used to induce separation. As illustrated in FIG.
- the oven temperature is high.
- the furnace thus makes it possible to carry out a smoothing heat treatment of the first 3 and second 6 substrates as described above.
- the heat treatment is preferably carried out at 800 ° C. for 30 minutes. This process made it possible to reduce the roughness of 14 nm RMS after the fracture step to 4 nm RMS after the smoothing heat treatment.
- a smoothing heat treatment made it possible to obtain a roughness of the order of 3 nm RMS, against a roughness of 21 nm RMS measured after the step fracture.
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Abstract
Description
Claims
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201280065068.7A CN104011840B (zh) | 2011-10-27 | 2012-10-26 | 通过热处理使表面平滑化的工艺 |
| JP2014537680A JP6333725B2 (ja) | 2011-10-27 | 2012-10-26 | 熱処理によって表面を平滑化するプロセス |
| KR1020147014119A KR102051156B1 (ko) | 2011-10-27 | 2012-10-26 | 가열 처리를 통한 표면 평활화 방법 |
| EP12795492.3A EP2771906B1 (fr) | 2011-10-27 | 2012-10-26 | Procédé de lissage d'une surface par traitement thermique |
| SG11201401842WA SG11201401842WA (en) | 2011-10-27 | 2012-10-26 | Process for smoothing a surface via heat treatment |
| US14/354,716 US8962496B2 (en) | 2011-10-27 | 2012-10-26 | Process for smoothing a surface via heat treatment |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1103276A FR2982071B1 (fr) | 2011-10-27 | 2011-10-27 | Procede de lissage d'une surface par traitement thermique |
| FR11/03276 | 2011-10-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2013060949A1 true WO2013060949A1 (fr) | 2013-05-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/FR2012/000436 Ceased WO2013060949A1 (fr) | 2011-10-27 | 2012-10-26 | Procédé de lissage d'une surface par traitement thermique |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US8962496B2 (fr) |
| EP (1) | EP2771906B1 (fr) |
| JP (1) | JP6333725B2 (fr) |
| KR (1) | KR102051156B1 (fr) |
| CN (1) | CN104011840B (fr) |
| FR (1) | FR2982071B1 (fr) |
| SG (1) | SG11201401842WA (fr) |
| WO (1) | WO2013060949A1 (fr) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3349238B1 (fr) * | 2015-09-11 | 2021-09-01 | Mie University | Procédé de fabrication de substrat semi-conducteur au nitrure |
| CN105679647B (zh) * | 2015-12-31 | 2018-06-29 | 清华大学 | 具有原子级平整表面的衬底的制备方法 |
| WO2019217798A1 (fr) * | 2018-05-11 | 2019-11-14 | The Regents Of The University Of California | Croissance épitaxiale sur un matériau recouvert de phospho-arséniure de gallium sur un substrat à base d'arséniure de gallium |
| FR3093860B1 (fr) * | 2019-03-15 | 2021-03-05 | Soitec Silicon On Insulator | Procédé de transfert d’une couche utile sur un substrat support |
| FR3093858B1 (fr) * | 2019-03-15 | 2021-03-05 | Soitec Silicon On Insulator | Procédé de transfert d’une couche utile sur un substrat support |
| FR3105876B1 (fr) * | 2019-12-30 | 2021-11-26 | Soitec Silicon On Insulator | Procédé de fabrication d’une structure composite comprenant une couche mince en SiC monocristallin sur un substrat support |
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| US4830987A (en) * | 1987-11-19 | 1989-05-16 | Texas Instruments Incorporated | Contactless annealing process using cover slices |
| EP1363322A2 (fr) * | 2002-05-13 | 2003-11-19 | Sumitomo Electric Industries, Ltd. | Substrat monocristallin en GaN, substrat semi-conducteur epitaxial de type nitrure, dispositif semiconducteur de type nitrure et méthodes pour leur fabrications |
| JP2005217374A (ja) * | 2004-02-02 | 2005-08-11 | Sumitomo Electric Ind Ltd | 化合物半導体素子の製造方法 |
| FR2867307A1 (fr) | 2004-03-05 | 2005-09-09 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
| EP1614775A2 (fr) * | 2004-06-29 | 2006-01-11 | Ngk Insulators, Ltd. | Procédé d'améliorer la planétié d'une surface d'un cristal de nitrure de groupe III, substrat pour la croissance épitaxiale et dispositif semi-conducteur |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS57183041A (en) * | 1981-05-06 | 1982-11-11 | Nec Corp | Annealing method for chemical semiconductor |
| JPS5925216A (ja) * | 1982-08-03 | 1984-02-09 | Agency Of Ind Science & Technol | 化合物半導体の熱変形防止方法 |
| JPS6130030A (ja) * | 1984-07-12 | 1986-02-12 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 多元素半導体のアニ−ル方法 |
| JPH0722177B2 (ja) * | 1990-04-26 | 1995-03-08 | 三洋電機株式会社 | ウェハの移し替え装置 |
| US6489241B1 (en) * | 1999-09-17 | 2002-12-03 | Applied Materials, Inc. | Apparatus and method for surface finishing a silicon film |
| JP3852545B2 (ja) * | 1999-11-30 | 2006-11-29 | 株式会社Sumco | 単結晶体の熱処理方法及びその熱処理装置 |
| FR2845523B1 (fr) * | 2002-10-07 | 2005-10-28 | Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee | |
| FR2867310B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
| FR2876841B1 (fr) * | 2004-10-19 | 2007-04-13 | Commissariat Energie Atomique | Procede de realisation de multicouches sur un substrat |
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2011
- 2011-10-27 FR FR1103276A patent/FR2982071B1/fr not_active Expired - Fee Related
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2012
- 2012-10-26 KR KR1020147014119A patent/KR102051156B1/ko active Active
- 2012-10-26 WO PCT/FR2012/000436 patent/WO2013060949A1/fr not_active Ceased
- 2012-10-26 US US14/354,716 patent/US8962496B2/en active Active
- 2012-10-26 EP EP12795492.3A patent/EP2771906B1/fr active Active
- 2012-10-26 SG SG11201401842WA patent/SG11201401842WA/en unknown
- 2012-10-26 CN CN201280065068.7A patent/CN104011840B/zh active Active
- 2012-10-26 JP JP2014537680A patent/JP6333725B2/ja active Active
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| US4830987A (en) * | 1987-11-19 | 1989-05-16 | Texas Instruments Incorporated | Contactless annealing process using cover slices |
| EP1363322A2 (fr) * | 2002-05-13 | 2003-11-19 | Sumitomo Electric Industries, Ltd. | Substrat monocristallin en GaN, substrat semi-conducteur epitaxial de type nitrure, dispositif semiconducteur de type nitrure et méthodes pour leur fabrications |
| JP2005217374A (ja) * | 2004-02-02 | 2005-08-11 | Sumitomo Electric Ind Ltd | 化合物半導体素子の製造方法 |
| FR2867307A1 (fr) | 2004-03-05 | 2005-09-09 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
| EP1614775A2 (fr) * | 2004-06-29 | 2006-01-11 | Ngk Insulators, Ltd. | Procédé d'améliorer la planétié d'une surface d'un cristal de nitrure de groupe III, substrat pour la croissance épitaxiale et dispositif semi-conducteur |
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| ARMIENTO C A ET AL: "CAPLESS RAPID THERMAL ANNEALING OF GAAS IMPLANTED WITH SI USING AN ENHANCED OVERPRESSURE PROXIMITY METHOD", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ECS, vol. 134, no. 8A, 1 August 1987 (1987-08-01), pages 2010 - 2016, XP000840329, ISSN: 0013-4651 * |
| SMITH ET AL.: "Surface topography changes during the growth of GaAs by molecular beam epitaxy", APPLIED PHYSICS LETTERS, vol. 59, no. 25, 1991, XP000601759, DOI: doi:10.1063/1.105706 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104011840A (zh) | 2014-08-27 |
| US20140315394A1 (en) | 2014-10-23 |
| FR2982071A1 (fr) | 2013-05-03 |
| JP2014535171A (ja) | 2014-12-25 |
| SG11201401842WA (en) | 2014-09-26 |
| CN104011840B (zh) | 2016-10-12 |
| EP2771906B1 (fr) | 2015-11-18 |
| KR20140085560A (ko) | 2014-07-07 |
| FR2982071B1 (fr) | 2014-05-16 |
| US8962496B2 (en) | 2015-02-24 |
| JP6333725B2 (ja) | 2018-06-06 |
| KR102051156B1 (ko) | 2019-12-02 |
| EP2771906A1 (fr) | 2014-09-03 |
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