WO2012133470A1 - Phase adjustment circuit and phase adjustment method - Google Patents

Abstract

In order to enable automatic phase adjustment between a plurality of main signals even when phase fluctuation due to the passage of time or environmental changes has occurred, a phase adjustment circuit is provided with: a plurality of phase varying means for respectively changing the phases of two or more main signals; a plurality of processing means for processing the output of each of the phase varying means and outputting the processed results; and a control means for controlling at least one of the phase varying means such that the phase difference between the main signals outputted from the processing means becomes a predetermined value.

Description

Phase adjustment circuit and phase adjustment method

The present invention relates to a phase adjustment circuit and a phase adjustment method.

An amplifier circuit that amplifies an electrical signal may handle a plurality of signals. For example, the differential electrical signal has a relationship in which the logic of two (two) signals is inverted, that is, a balanced relationship. As an amplifying circuit for amplifying the differential signal, a differential amplifying circuit for amplifying two signals simultaneously with one circuit is widely known.
By the way, in order to cope with a signal having a large output amplitude or to simplify the circuit, there are cases where two separate amplification circuits are used to separately amplify two-pole signals. For example, a drive amplification circuit for driving a lithium niobate (LN: LiNbO3) optical modulator having a differential input used in an optical transmitter or the like requires an output amplitude of several V to 10 Vpp. There are many cases. As such a drive amplifier circuit, an individual amplifier circuit capable of obtaining a large output amplitude is often used. Since the electrical signal handled at this time is a differential signal, each electrical signal is in a balanced relationship and the phase of the signal is also synchronized. When a differential amplifier circuit is used as the amplifier circuit, the two-pole signal is differentially amplified, and the output signal has substantially the same phase. However, when amplification is performed separately by individual amplifier circuits, a phase difference may occur in each electrical signal due to differences in signal line lengths, individual differences in amplifier circuits, differences in characteristics, and the like.
In order to make this phase difference in phase, a phase adjustment circuit is known in which means for adjusting the phase is inserted in at least one of the signal lines connected before and after the amplifier circuit so as to cancel the generated phase difference. ing. FIG. 8 shows a configuration example of this phase adjustment circuit. The phase adjustment circuit includes amplification elements 701 and 702 and phase variable circuits 703 and 704. In FIG. 8, reference numerals 705 and 706 indicate input differential signals, and reference numerals 707 and 708 indicate output differential signals 707 and 708, respectively. In the above configuration, only one of the phase variable circuits 703 and 704 may be provided.
Input differential signals 705 and 706 are amplified by amplification elements 701 and 702 through phase variable circuits 703 and 704, respectively, and output as output differential signals 707 and 708. At this time, the phase difference between the output differential signal 707 and the output differential signal 708 caused by the individual difference or characteristic difference between the respective amplification elements 701 and 702 or the difference in signal line length or the like is obtained by the phase variable circuits 703 and 704. It is adjusted to be in phase (equilibrium relationship).
When there is only one of the phase variable circuits 703 and 704, for example, when the phase variable circuit 704 exists only in the system of the amplification element 702 in FIG. 8, the amplification element of the system without the phase variable circuit (that is, the amplification element 701). The output differential signal 707 and the output differential signal 708 can be in phase by adjusting the phase variable circuit of the other system on the basis of the phase of the output signal.
Further, as a related technique, in Patent Document 1, when there is a phase variation due to a circuit in the subsequent stage, the phase difference between the I signal and the Q signal input to the adder is 90 ° in consideration of the phase variation. It is described that it is adjusted so that

JP 2008-193388 A

The phase adjustment circuit shown in FIG. 8 can adjust a phase difference caused by a difference in signal line length, or an individual difference or a characteristic difference among amplifying elements. However, the phase adjustment circuit shown in FIG. 8 can adjust the phase fluctuation caused by the characteristic change of the amplifying element over time and the phase fluctuation caused by environmental conditions (for example, temperature condition), that is, the real-time phase fluctuation. Can not. The reason for this is that in the phase adjustment circuit as shown in FIG. 8, once the phase variable circuit is adjusted, it becomes a fixed delay amount thereafter, so if the phase fluctuation occurs after adjustment, It is not possible.
SUMMARY OF THE INVENTION An object of the present invention is to provide a phase variable circuit and a phase adjustment method capable of automatically performing phase adjustment between a plurality of main signals even when there is a phase variation with time or due to environmental changes. There is to do.

The phase adjustment circuit of the present invention includes a plurality of phase variable means for changing the phases of two or more main signals, and a plurality of processing means for processing the outputs of the phase variable means and outputting the processed results. And control means for controlling at least one of the phase variable means so that the phase difference between the main signals output from the processing means becomes a predetermined value.
The phase adjustment method of the present invention performs a predetermined process on each of two or more main signals, so that the phase difference between the main signals on which the predetermined process has been performed becomes a predetermined value. Control the phase of at least one of the main signals.

According to the present invention, it is possible to automatically perform phase adjustment between a plurality of main signals even when there is a phase fluctuation due to a change over time or due to environmental changes.

It is a figure which shows the structural example of the phase adjustment circuit which concerns on the 1st Embodiment of this invention. FIG. 2 is a diagram for explaining an operation of a phase comparison circuit constituting the phase adjustment circuit shown in FIG. 1. It is a figure explaining the relationship (phase difference = plus) of the output waveform of two LPFs shown in FIG. It is a figure explaining the relationship (phase difference = minus) of the output waveform of two LPFs shown in FIG. It is a figure explaining the relationship (phase difference = zero = in-phase) of the output waveform of two LPFs shown in FIG. It is a figure which shows the structural example of the phase adjustment circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structural example of the phase adjustment circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structural example of a general phase adjustment circuit.

[First Embodiment]
FIG. 1 is a diagram illustrating a configuration example of a phase adjustment circuit 100 according to the first embodiment of the present invention. The operation of the phase adjustment circuit 100 will be described mainly with reference to FIG.
The phase adjustment circuit 100 includes amplification elements 101 and 102 (processing means), phase variable circuits 103 and 104 (phase variable means), a low-frequency oscillation circuit 105 (oscillation means), and signal superposition circuits 106 and 107 (superposition means). And). Further, the phase adjustment circuit 100 includes branch circuits 108 and 109, LPFs 110 and 111 (extraction circuit), a phase comparison circuit 112, and a control circuit 113. LPF is an abbreviation for Low Pass Filter. In FIG. 1, reference numerals 114 and 115 denote input differential signals, and reference numerals 116 and 117 denote output differential signals. The LPFs 110 and 111, the phase comparison circuit 112, and the control circuit 113 constitute a “control unit”.
Bipolar input differential signals 114 and 115 having a balanced relationship are input to the signal superimposing means 106 and 107, respectively.
The low-frequency oscillation circuit 105 outputs an oscillation signal having a frequency lower than the frequency (bit rate) of the input differential signals 114 and 115 (for example, a frequency about 1/10 to 1/100 of the bit rate). Output to the superimposing circuits 106 and 107. Hereinafter, this oscillation signal is basically referred to as a low frequency oscillation signal.
The signal superimposing circuit 106 superimposes the low frequency oscillation signal on the input differential signal 114. The signal superimposing circuit 107 superimposes the low frequency oscillation signal on the input differential signal 115. At this time, the low-frequency oscillation signals superimposed on each of them maintain an in-phase relationship.
Each input differential signal on which the low-frequency oscillation signal is superimposed (post-superimposition input differential signal) passes through the phase variable circuits 103 and 104, respectively. The phase variable circuits 103 and 104 will be described later. Thereafter, the input differential signal after superposition is added to the amplifying elements 101 and 102, respectively, and is amplified to the amplitude required here to become output differential signals 116 and 117. The amplifying elements 101 and 102 amplify not only the differential signal but also the superimposed low-frequency oscillation signal. The output differential signals 116 and 117 pass through the branch circuits 108 and 109. At this time, some output differential signals are branched by the branch circuits 108 and 109 and guided to the LPFs 110 and 111 of the next stage. The cutoff frequency of the LPF is set between the frequency (bit rate) of the output differential signals 116 and 117 and the frequency of the superimposed low-frequency oscillation signal. For this reason, the frequency component corresponding to the bit rate of the output differential signals 116 and 117 is greatly attenuated and cannot pass through the LPFs 110 and 111. On the other hand, the superimposed low-frequency oscillation signal is hardly attenuated, so that it passes through the LPFs 110 and 111 and is output. The low-frequency oscillation signals that have passed through the LPFs 110 and 111 are input to the phase comparison circuit 112.
The phase comparison circuit 112 receives two low-frequency oscillation signals and generates a voltage corresponding to the phase difference between these signals. FIG. 2 is a diagram for explaining the operation of the phase comparison circuit 112. In FIG. 2, the horizontal axis represents the phase difference (deg) between the two input low-frequency oscillation signals. The vertical axis represents the DC (Direct Current) voltage (V) output from the phase comparison circuit 112. Specifically, when the other low-frequency oscillation signal is delayed with respect to the reference low-frequency oscillation signal, the phase comparison circuit 112 generates a positive voltage corresponding to the magnitude of the phase difference. For example, as shown in FIG. 3, when the low-frequency oscillation signal passing through the amplification element 101 is delayed with respect to the low-frequency oscillation signal passing through the amplification element 102, the phase comparison circuit 112 determines the magnitude of the phase difference. A positive voltage is generated accordingly. On the other hand, as shown in FIG. 4, when one low frequency oscillation signal that is a reference is delayed with respect to the other low frequency oscillation signal, the phase comparison circuit 112 generates a negative voltage corresponding to the magnitude of the phase difference. Is generated. As shown in FIG. 5, when the phases of the two low-frequency oscillation signals are in phase, the output voltage of the phase comparison circuit 112 is zero. The output voltage of the phase comparison circuit 112 is given to the control circuit 113.
In the above description, “zero” includes not only true zero but also substantially zero.
In addition, the phase comparison circuit 112 includes, for example, any one of “phase comparison circuit”, “phase comparison circuit + LPF”, and “phase comparison circuit + LPF + amplifier” that constitutes a general PLL (Phase Locked Loop) circuit. can do. Of course, the above is merely an example, and the configuration of the phase comparison circuit 112 may be other circuit configurations.
The control circuit 113 controls the phase variable circuit 104 according to the output voltage from the phase comparison circuit 112 shown in FIG. 2 (for example, a DC voltage in the range of 0 (V) to 12 (V)). Is generated. Specifically, the control circuit 113 decreases the DC voltage when the input voltage is negative, increases the DC voltage when the input voltage is positive, and when the input voltage becomes 0 (V), It has a function of holding a DC voltage.
Each of the phase variable circuits 103 and 104 has a function of delaying the phase of the input signal (post-superimposed input differential signal) by using a DC voltage supplied from the outside as a control signal by a delay amount proportional to the voltage. . The delay amount is associated with a DC voltage given from the outside. For example, when the externally applied DC voltage = 0 (V), the signal delay amount is 0 (deg). When the DC voltage = 1 (V), the signal delay amount is 30 (deg). In the case of DC voltage = 2 (V), the signal delay amount is 60 (deg). Thereafter, this relationship continues, and when the DC voltage = 12 (V), the signal delay amount is 360 (deg). In the present embodiment, it is assumed that the delay amount of the phase variable circuit 103 (that is, the DC voltage as the control signal) is fixed to the initial value. On the other hand, since the delay amount of the phase variable circuit 104 is controlled by the control signal of the control circuit 113, the phase of the output differential signal 117 varies depending on the situation.
Hereinafter, the overall operation of the phase adjustment circuit 100 of the first embodiment will be described mainly with reference to FIG.
First, as an initial setting, it is assumed that the delay amounts of the phase variable circuits 103 and 104 are set to 60 (deg). Therefore, in this case, the DC voltage applied to the phase variable circuit 103 is 2 (V), and this value is fixed without being changed. On the other hand, the initial value of the DC voltage applied to the phase variable circuit 104 is 2 (V), but changes in real time according to the comparison result of the phase comparison circuit 112.
The superimposed input differential signals obtained by superimposing the low-frequency oscillation signals on the input differential signals 114 and 115 are amplified by the amplification elements 101 and 102, respectively. The amplified signals are output as output differential signals 116 and 117, respectively.
Here, it is assumed that the phase of the output differential signal 117 is delayed by 30 (deg) with respect to the output differential signal 116 as shown in FIG. As a result, a phase difference of 30 (deg) is generated between the output differential signal 116 and the output differential signal 117.
At this time, the output of the phase comparison circuit 112 becomes a negative voltage as understood from FIG. Then, the output DC voltage of the control circuit 113 starts to drop from the initial voltage of 2 (V).
When the output DC voltage drops to 1 (V) and the delay amount of the phase variable circuit 104 reaches 30 (deg), the phase difference between the output differential signal 116 and the output differential signal 117 becomes zero (same phase) again. Become. Thereby, the output of the phase comparison circuit 112 becomes 0 (V), and the output DC voltage of the control circuit 113 is held at 1 (V) (that is, 30 (deg)).
By the operation described above, control is performed so that the phase difference between the output differential signal 116 and the output differential signal 117 is always zero (same phase). Here, the phase adjustment process can be executed in real time.
Therefore, according to the first embodiment described above, due to a change in characteristics over time in a predetermined processing circuit (for example, an amplifying element or other circuit) or a change in characteristics due to environmental conditions (such as temperature conditions), Even when a phase variation occurs in the output differential signal, the phase difference between the two-pole output differential signals can always be zero by the above-described control. In other words, according to the first embodiment, it is possible to maintain a balanced relationship between two-pole output differential signals.
Here, when the frequency of the electric main signal is a high frequency of, for example, about 10 GHz or more, it is very difficult to detect the phase of the high-frequency electric main signal. For this reason, a circuit for detecting the phase of such a high-frequency electric main signal requires cost, and there is a problem that the circuit scale increases.
Therefore, the above-described phase adjustment circuit according to the first embodiment includes an oscillating means (low frequency oscillating circuit 105) that generates an oscillation signal having a frequency lower than the frequency of each main signal, and the generated oscillation signal for each main signal. Superimposing means (signal superimposing circuits 106 and 107) for outputting a superimposed main signal superimposed on the signal. The extraction circuit (LPF 110, 111) extracts each oscillation signal from each superimposed main signal processed by each processing means (for example, the amplification elements 101, 102). The phase comparison circuit 112 compares the phases of the extracted oscillation signals and outputs a signal corresponding to the phase difference. The control circuit 113 controls at least one phase variable means based on a signal corresponding to this phase difference.
That is, in the case of this embodiment, a circuit that detects the phase of a low-frequency signal is sufficient, so that the scale and cost of the circuit can be reduced compared to the case of detecting the phase of a high-frequency signal. Note that the frequency of the oscillation signal can be, for example, about 1/10 to 1/100 of the frequency of the electric main signal.
In the first embodiment described above, the phase variable circuit 104 is configured so that the output voltage of the phase comparison circuit 112 is zero (that is, the phase difference between two signals input to the phase comparison circuit 112 is zero). It has been explained that the delay amount is controlled. However, this is merely an example, and in the present embodiment, for example, control is performed so that the phase difference between two signals becomes a predetermined value (which may be said to be within a predetermined range), in other words, It is also possible to control so that the two signals are at least synchronized.
[Second Embodiment]
FIG. 6 is a diagram illustrating a configuration example of a phase adjustment circuit 600 according to the second embodiment of the present invention. The operation of the phase adjustment circuit 100 will be described mainly with reference to FIG.
The phase adjustment circuit 600 includes amplification elements 601 and 602 (predetermined processing circuits), phase variable circuits 603 and 604 (phase variable means), a low-frequency oscillation circuit 605 (oscillation means), and signal superposition circuits 606 and 607 ( Superimposing means). Furthermore, the phase adjustment circuit 600 includes branch circuits 608 and 609, LPFs 610 and 611, phase comparison circuits 612 and 613, and control circuits 614 and 615 (control means). In FIG. 6, reference numerals 616 and 617 indicate input differential signals, and reference numerals 618 and 619 indicate output differential signals.
The difference between the phase adjustment circuit 600 of the second embodiment (FIG. 6) and the phase adjustment circuit 100 of the first embodiment (FIG. 1) is that the phase adjustment circuit 600 further The phase comparison circuit 612 and the control circuit 614 are provided, and the operation of the phase variable circuit 604 is controlled.
The operations of the phase comparison circuits 612 and 613 are the same as those of the phase comparison circuit 112 of the first embodiment. That is, as shown in FIG. 2, the phase comparison circuits 612 and 613 generate an output voltage corresponding to the phase difference between two input signals.
In the first embodiment, the phase comparison circuit 112 performs phase comparison between superimposed low-frequency oscillation signals. However, in the second embodiment, the oscillation signal of the low-frequency oscillation circuit 605 is used as one reference signal. Accordingly, the delay amounts of the phase variable circuits 603 and 604 are controlled so that the phases of the output differential signals 618 and 619 are always synchronized with the phase of the oscillation signal of the low-frequency oscillation circuit 605. As a result of this operation, the phase difference between the output differential signals 618 and 619 is always zero, that is, in phase (equilibrium relationship).
In the first and second embodiments described above, a differential electrical signal is handled as the input electrical main signal. The reason is that the differential electrical signal requires that the two-pole electrical signals always have the same phase in a balanced relationship, and in recent years, in the configuration of an optical transmitter or an optical receiver, many differential signals are used. This is because signals are often handled. However, the electric main signal to be handled is not limited to the differential electric signal. That is, each embodiment described above can be widely applied when it is necessary to maintain a phase difference between two different signals input in a predetermined state (for example, opposite phase).
Furthermore, the number of electric main signals handled does not necessarily have to be two poles, and may be three or more poles. In that case, the phase variable circuit may be controlled so that the phase of each electric main signal is in phase with the reference phase.
In the first and second embodiments described above, the circuits denoted by reference numerals 101, 102, 601, and 602 are not necessarily amplification elements, and may be predetermined processing circuits other than the amplification elements. it can.
In the first and second embodiments described above, the LPFs constituting the extraction circuit (LPFs 110 and 111 in the case of the first embodiment, LPFs 610 and 611 in the case of the second embodiment) are BPF ( Band Pass Filter) may be used. The BPF is a filter that passes only frequency components in a certain band and blocks higher frequency components and lower frequency components. Therefore, the superimposed oscillation signal can be extracted more efficiently from the electrical main signal.
[Third Embodiment]
FIG. 7 is a diagram illustrating a configuration example of a phase adjustment circuit 800 according to the third embodiment of the present invention. The phase adjustment circuit 800 includes processing means, phase variable means 801-1 to 801-n (n is an integer of 2 or more), and control means 802. The processing means processes the outputs of the phase varying means 801-1 to 801-n and outputs the processed results. The phase varying means 801-1 to 801-n have a function of changing the phase of each of the main signals 1 to n (n is an integer of 2 or more). The control unit 802 controls at least one phase variable unit so that the phase difference between the main signals output from the processing units becomes a predetermined value (for example, zero). An example of the processing means is an amplifying element.
According to the third embodiment described above, it is possible to automatically perform phase adjustment between a plurality of main signals even when there is a phase variation with time or due to environmental changes.
The first to third phase adjustment circuits described above can be mounted on, for example, a drive amplification device for driving an optical modulator or the like.
While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2011-0667697 for which it applied on March 25, 2011, and takes in those the indications of all here.

100, 600, 800 Phase adjustment circuit 101, 102, 601, 602 Amplifying element 103, 104, 603, 604, 703, 704 Phase variable circuit 105, 605 Low frequency oscillation circuit 106, 107, 606, 607 Signal superposition circuit 108, 109, 608, 609 Branch circuit 110, 111, 610, 611 LPF
112, 612, 613 Phase comparison circuit 113, 614, 615 Control circuit 801-1 to 801-n Phase variable means 802 Control means

Claims (8)

A plurality of phase variable means for changing the phase of each of the two or more main signals;
A plurality of processing means for processing the output of each phase varying means and outputting the processed results;
Control means for controlling at least one of the phase variable means so that the phase difference between the main signals output from the processing means has a predetermined value;
A phase adjustment circuit comprising: Oscillation means for generating an oscillation signal having a frequency lower than the frequency of each main signal;
Superimposing means for outputting a superimposed main signal in which the oscillation signal is superimposed on each main signal;
Further comprising
The control means includes
An extraction circuit for extracting each oscillation signal from each superimposed main signal processed by each processing means;
The phase comparison between each of the extracted oscillation signals and the phase comparison between each of the extracted oscillation signals and the oscillation signal output from the oscillation means is performed. A phase comparison circuit that outputs a signal corresponding to the phase difference;
The phase adjustment circuit according to claim 1, further comprising: a control circuit that controls at least one of the phase variable units based on a signal corresponding to the phase difference. When the phase comparison between the extracted oscillation signals is performed in the phase comparison circuit, the control circuit controls the phase variable means so that the phases of the extracted oscillation signals are the same. The phase adjustment circuit according to claim 2, wherein: When the phase comparison circuit performs a phase comparison between each extracted oscillation signal and the oscillation signal output from the oscillation means, the control circuit calculates the phase of each extracted oscillation signal and the 3. The phase adjusting circuit according to claim 2, wherein the phase varying means is controlled so that the phase of the oscillation signal output from the oscillating means is in phase. 5. The phase adjustment circuit according to claim 2, wherein the frequency of the oscillation signal is about 1/10 to 1/100 of the frequency of each main signal. 6. The phase adjustment circuit according to claim 1, wherein the main signal is a differential electric signal composed of a bipolar signal. A drive amplification device comprising the phase adjustment circuit according to any one of claims 1 to 6. Performing predetermined processing on each of the two or more main signals;
A phase adjustment method, wherein the phase of at least one of the main signals is controlled so that a phase difference between the main signals on which the predetermined processing has been executed becomes a predetermined value.

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