WO2012102043A1 - Method for driving plasma display panel, and plasma display apparatus - Google Patents

Abstract

A stable write operation is performed during driving of a high-definition large-screen plasma display panel. Provided, therefore, is a drive method for driving a plasma display panel in which a single field is composed of subfields having an initialization period for performing a selective initialization operation in which a downwardly inclined waveform voltage that decreases toward a negative voltage is applied to a scanning electrode, a write period, and a sustain period in which the number of sustain pulses that corresponds to luminance weights is applied to a pair of display electrodes, wherein an upwardly inclined waveform voltage for generating an erase discharge in a discharge cell is applied to the scanning electrode after the final sustain pulse is generated in the sustain period. In a subfield having a relatively high luminance weight generated immediately before a subfield where the luminance weight is relatively low and where the selective initialization operation is performed in the initialization period, the maximum voltage of the upwardly inclined waveform voltage is set to a high voltage greater than the maximum voltage of the upwardly inclined waveform voltage generated in the subfield having the relatively low luminance weight.

Description

Plasma display panel driving method and plasma display device

The present invention relates to a plasma display device using an AC surface discharge type plasma display panel and a driving method of the plasma display panel.

2. Description of the Related Art A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front substrate and a rear substrate that are arranged to face each other.

In the front substrate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs.

The back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.

Then, the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing xenon at a partial pressure ratio of 5% is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.

A subfield method is generally used as a method for displaying an image in an image display area of a panel by combining binary control of light emission and non-light emission in a discharge cell.

In the subfield method, one field is divided into a plurality of subfields having different emission luminances. In each discharge cell, light emission / non-light emission of each subfield is controlled by a combination according to a desired gradation value. Thus, each discharge cell emits light with the emission luminance of one field set to a desired gradation value, and an image composed of various combinations of gradation values is displayed in the image display area of the panel.

In the subfield method, each subfield has an initialization period, an address period, and a sustain period.

In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization operation is performed to generate an initialization discharge in each discharge cell. Thereby, in each discharge cell, wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.

In the address period, the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed. As a result, an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell (hereinafter, these operations are also collectively referred to as “address”). ).

In the sustain period, the number of sustain pulses based on the luminance weight determined for each subfield is alternately applied to the display electrode pairs composed of the scan electrodes and the sustain electrodes. As a result, a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”). Also written as “lit”.) Thereby, in each subfield, each discharge cell is made to emit light with the luminance according to the luminance weight. In this way, each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.

One of the important factors in improving the image display quality on the panel is the improvement in contrast. As one of the subfield methods, a driving method for reducing the light emission not related to gradation display as much as possible and improving the contrast ratio is disclosed (for example, see Patent Document 1).

In this driving method, in the initializing period, a forced initializing operation in which initializing discharge is generated in all discharge cells using a ramp waveform voltage that gradually increases in voltage, and a sustain discharge is generated in the sustain period of the immediately preceding subfield. Any initializing operation of the selective initializing operation for selectively generating the initializing discharge with respect to the discharged cells is performed. Then, the number of times of performing the forced initializing operation is once per field, and the selective initializing operation is performed in the initializing period of the other subfield.

The luminance of the black display area where no sustain discharge occurs (hereinafter abbreviated as “black luminance”) varies depending on light emission not related to image display, for example, light emission caused by initialization discharge. In the driving method described above, light emission in the black display region is only weak light emission when the forced initializing operation for generating the initializing discharge in all the discharge cells is performed. As a result, it is possible to reduce the black luminance and display an image with high contrast.

In addition, the display electrode pairs are divided into a plurality of groups, and the number of times of performing the forced initializing operation is once in a plurality of fields, thereby further reducing the light emission not related to the gradation display and further reducing the black luminance. A driving method for further improving the above is also disclosed (for example, see Patent Document 2).

However, the forced initialization operation has a function of accumulating wall charges necessary for generating an address discharge in the discharge cell in the subsequent address period. In addition, it has a function of generating priming particles for shortening the discharge delay time to surely generate the address discharge. This discharge delay time is the time required for the actual discharge to occur after the voltage applied to the discharge cell exceeds the discharge start voltage. The longer the discharge delay time, the more unstable the generation of discharge. .

Therefore, if the frequency of the forced initialization operation is reduced, the wall charge and priming particles necessary to generate the address discharge are insufficient, the address discharge delay time becomes long, and the address operation becomes unstable. Or, there is a risk of malfunction such as no occurrence of address discharge. In particular, since the sustain discharge does not occur in the discharge cell displaying black, the priming particles are likely to be insufficient, and the address operation is likely to be unstable. Such a phenomenon is likely to occur in a panel with high definition and a finer discharge cell structure.

When the address operation becomes unstable and no sustain discharge occurs in the discharge cells that should emit light, a normal image cannot be displayed on the panel.

JP 2000-242224 A JP 2006-091295 A

The present invention relates to a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and selectively initializing the scan electrode with a falling ramp waveform voltage that decreases toward a negative voltage. This is a panel driving method in which a subfield having an initialization period in which an operation is performed, an address period, and a sustain period in which a number of sustain pulses corresponding to a luminance weight are applied to a display electrode pair is provided in one field. In this driving method, an upward ramp waveform voltage for generating an erasing discharge in the discharge cells is applied to the scan electrodes after the last sustain pulse is generated in the sustain period. Then, in the subfield where the luminance weight is relatively small and the luminance weight generated just before the subfield performing the selective initialization operation in the initialization period is relatively large, the maximum voltage of the upward ramp waveform voltage is The voltage is set to a voltage higher than the maximum voltage of the upward ramp waveform voltage generated in the subfield having a relatively small luminance weight.

This makes it possible to perform a stable writing operation even when driving a high-definition large-screen panel and display a high-quality image on the panel.

Further, in the panel driving method of the present invention, a forced initialization operation in which an up-slope waveform voltage and a down-slope waveform voltage are applied to the scan electrode and a selective initialization operation in which a down-slope waveform voltage is applied to the scan electrode are mixed. The specific cell initialization period may be provided, and the initialization period of the subfield having the relatively small luminance weight may be set as the specific cell initialization period.

In the panel driving method of the present invention, the subfield having the relatively large luminance weight and the subfield having the relatively small luminance weight may be continuously generated in the same field. .

Further, in the panel driving method of the present invention, the voltage applied to the scan electrode is decreased once before the voltage applied to the scan electrode is increased, and the voltage applied to the scan electrode is again reduced. It may be generated by raising.

The present invention also provides a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and a selection to apply a downward ramp waveform voltage that decreases toward a negative voltage to the scan electrode. A driving circuit for driving a panel with a subfield having an initializing period for performing an initializing operation, an address period, and a sustaining period in which a number of sustaining pulses corresponding to the luminance weight are applied to the display electrode pair in one field; Is a plasma display device. In this plasma display device, the drive circuit applies an upward ramp waveform voltage for generating an erasing discharge to the discharge cells after the generation of the last sustain pulse in the sustain period to the scan electrodes. Then, in the subfield where the luminance weight is relatively small and the luminance weight generated just before the subfield performing the selective initialization operation in the initialization period is relatively large, the maximum voltage of the upward ramp waveform voltage is The voltage is set to a voltage higher than the maximum voltage of the upward ramp waveform voltage generated in the subfield having a relatively small luminance weight.

This makes it possible to perform a stable writing operation even when driving a high-definition large-screen panel and display a high-quality image on the panel.

Further, in the plasma display device of the present invention, the driving circuit includes a forced initializing operation for applying the rising ramp waveform voltage and the falling ramp waveform voltage to the scan electrode, and a selective initialization operation for applying the falling ramp waveform voltage to the scan electrode. May be provided, and the initialization period of the subfield having a relatively small luminance weight may be set as the specific cell initialization period.

In the plasma display apparatus of the present invention, the driving circuit continuously generates the subfield having the relatively large luminance weight and the subfield having the relatively small luminance weight in the same field. May be.

Further, in the plasma display device of the present invention, the driving circuit decreases the applied voltage to the scan electrode once before the applied voltage to the scan electrode rises to the maximum voltage, and again, It may be generated by increasing the voltage applied to the scan electrode.

FIG. 1 is an exploded perspective view showing a structure of a panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 2 is an electrode array diagram of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 3 is a diagram showing a driving voltage waveform applied to each electrode of the panel used in the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 4 is a circuit block diagram of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 5 is a circuit diagram schematically showing a configuration of a scan electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 6 is a timing chart for explaining the operation of the driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 7 is a diagram showing a driving voltage waveform applied to each electrode of the panel used in the plasma display device in accordance with the second exemplary embodiment of the present invention.

Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

The protective layer 26 is formed of a material mainly composed of magnesium oxide (MgO), which is a material having high electron emission performance, in order to easily generate discharge in the discharge cell.

The protective layer 26 may be composed of a single layer or may be composed of a plurality of layers. Moreover, the structure which particle | grains exist on a layer may be sufficient.

A plurality of data electrodes 32 are formed on the rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and a discharge space is formed in the gap between the front substrate 21 and the rear substrate 31. Provide. And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon (Ne) and xenon (Xe) is sealed in the discharge space inside as a discharge gas.

The discharge space is divided into a plurality of sections by partition walls 34, and discharge cells constituting pixels are formed at the intersections of the display electrode pairs 24 and the data electrodes 32. A color image is displayed on the panel 10 by discharging and emitting (lighting) these discharge cells.

In the panel 10, three continuous discharge cells arranged in the extending direction of the display electrode pair 24, that is, discharge cells that emit red (R), and discharge cells that emit green (G), One pixel is composed of three discharge cells, ie, discharge cells emitting blue (B).

Note that the structure of the panel 10 is not limited to the above-described structure, and may be, for example, provided with a stripe-shaped partition wall.

FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

The panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) extended in the horizontal direction (row direction and line direction) and n sustain electrodes SU1 to SUn (FIG. 1). Are arranged, and m data electrodes D1 to Dm (data electrode 32 in FIG. 1) extending in the vertical direction (column direction) are arranged.

Then, one discharge cell is formed in a region where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dj (j = 1 to m). That is, m discharge cells are formed on one display electrode pair 24, and m / 3 pixels are formed. Then, m × n discharge cells are formed in the discharge space, and an area where m × n discharge cells are formed becomes an image display area of the panel 10. For example, in a panel having 1920 × 1080 pixels, m = 1920 × 3 and n = 1080. In the present embodiment, n = 1080, but the present invention is not limited to this value.

Next, a method for driving the panel 10 of the plasma display apparatus according to the present embodiment will be described. Note that the plasma display device in this embodiment performs gradation display by a subfield method. In the subfield method, one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield. Each subfield has an initialization period, an address period, and a sustain period. An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.

The luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”. Therefore, various gradations can be displayed and images can be displayed by selectively causing each subfield to emit light in a combination according to the image signal.

In the present embodiment, one field is divided into 10 subfields (subfield SF1, subfield SF2,..., Subfield SF10), and the luminance weight increases in the later subfield. An example will be described in which each subfield has a luminance weight of (1, 2, 3, 6, 11, 18, 30, 44, 60, 80).

In this embodiment, with this configuration, a red image signal (R signal), a green image signal (G signal), and a blue image signal (B signal) are displayed in 256 gradations from 0 to 255, respectively. Can do.

In the initialization period, an initialization discharge is generated, and an initialization operation is performed to form wall charges necessary for the subsequent address discharge on each electrode. The initializing operation at this time includes a forced initializing operation in which initializing discharge is generated in all the discharge cells, and an initializing discharge selectively with respect to the discharge cells in which the sustain discharge is generated in the sustain period of the immediately preceding subfield. And a selective initialization operation that generates

In the address period, an address operation is performed in which an address discharge is selectively generated in the discharge cells to emit light to form wall charges necessary for the sustain discharge.

In the sustain period, a number of sustain pulses corresponding to the luminance weight determined in advance for each subfield are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cell in which the address discharge is generated. A sustain operation for emitting light from the cell is performed.

In the present embodiment, among the plurality of subfields constituting one field, the “specific cell initialization operation” is performed in the initialization period of one subfield, and all the subfields in the initialization period of the other subfields. A selective initialization operation is performed in the discharge cell.

The specific cell initializing operation is an initializing operation in which a forced initializing operation is performed in a specific discharge cell and a selective initializing operation is performed in another discharge cell. Therefore, in the initialization period in which the specific cell initializing operation is performed, an initializing waveform for performing the forced initializing operation is applied to the specific discharge cell, and the initial stage for performing the selective initializing operation is performed on the other discharge cells. Apply the waveform.

Hereinafter, the initialization waveform for performing the forced initialization operation is referred to as “forced initialization waveform”, and the initialization waveform for performing the selective initialization operation is referred to as “selective initialization waveform”. An initialization period in which the specific cell initialization operation is performed is referred to as a “specific cell initialization period”, and a subfield having the specific cell initialization period is referred to as a “specific cell initialization subfield”. In addition, an initialization period in which a selective initialization operation is performed in all discharge cells is referred to as a “selective initialization period”, and a subfield having the selective initialization period is referred to as a “selective initialization subfield”.

In this embodiment, the first subfield (subfield SF1) of each field is a specific cell initialization subfield, and the other subfields (subfield SF2 to subfield SF10) are selective initialization subfields. .

In the present embodiment, the luminance weight is increased in the field as the subfield occurs later in time.

In the present embodiment, one field includes one subfield group including a plurality of subfields whose luminance weight increases as the subfield occurs later in time.

However, in the present embodiment, the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

FIG. 3 is a diagram showing drive voltage waveforms applied to the respective electrodes of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention.

FIG. 3 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SC2 that performs the address operation second in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform applied to is shown.

FIG. 3 shows drive voltage waveforms in a subfield SF1 which is a specific cell initialization subfield and subfields SF2 and subsequent subfields SF2 which are selective initialization subfields. The specific cell initialization subfield and the selective initialization subfield differ in the waveform shape of the drive voltage applied to scan electrode SC1 through scan electrode SCn in the initialization period 2.

Also, FIG. 3 shows two fields. In one field, a forced initializing waveform is applied to scan electrode SC1 and a selective initializing waveform is applied to scan electrode SC2 in the initializing period (specific cell initializing period) of subfield SF1, which is a specific cell initializing subfield. To do. In the other field, a forced initializing waveform is applied to scan electrode SC2 during the initializing period of subfield SF1, and a selective initializing waveform is applied to scan electrode SC1.

The drive voltage waveform in the subfield after subfield SF3 is substantially the same as the drive voltage waveform in subfield SF2 except that the number of sustain pulses generated in the sustain period is different.

However, in the subfield SF10, the waveform shape of the rising ramp waveform voltage for generating the erasing discharge is different from the rising ramp waveform voltage for generating the erasing discharge in the other subfields. Details of this will be described later.

In addition, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from each electrode based on image data (data indicating lighting / non-lighting for each subfield).

First, the subfield SF1, which is a specific cell initialization subfield, will be described.

In the present embodiment, in the specific cell initialization subfield (subfield SF1) of the first field, the first, third, fifth,... A forced initialization waveform for performing a forced initialization operation is applied to the (1 + 2 × N) th (N is an integer of 0 or more) scan electrode SC (1 + 2 × N). Then, the second, fourth, sixth,... From the top in terms of arrangement, the (2 + 2 × N) th (N is an integer of 0 or more) scan electrode SC (2 + 2 × N). Applies a selective initialization waveform for performing a selective initialization operation.

In the specific cell initialization subfield (subfield SF1) of the second field, the (2 + 2 × N) th (2, +4, 6th,... A forced initialization waveform for performing a forced initialization operation is applied to scan electrodes SC (2 + 2 × N), where N is an integer of 0 or more. Then, the first, third, fifth,... From the top in terms of arrangement, the (1 + 2 × N) th (N is an integer of 0 or more) scan electrode SC (1 + 2 × N). Applies a selective initialization waveform for performing a selective initialization operation.

FIG. 3 shows the scan electrode SC1 as a representative example of the scan electrode SC (1 + 2 × N), and the scan electrode SC2 as a representative example of the scan electrode SC (2 + 2 × N).

In the first half of the initialization period Ti1 of the subfield SF1 in which the specific cell initialization operation is performed, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage 0 (V) is applied to the sustain electrodes SU1 to SUn. ) Is applied. Scan electrode SC (1 + 2 × N) (for example, scan electrode SC1) to which a forced initialization waveform is applied is applied with voltage Vi1 after voltage 0 (V) is applied, and gradually from voltage Vi1 to voltage Vi2. Apply a rising ramp waveform voltage (eg, with a slope of about 5 V / μsec).

At this time, the voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to the sustain electrode SU (1 + 2 × N) (that is, a voltage at which no discharge occurs in the discharge cell), and the voltage Vi2 is set to the sustain electrode SU (1 + 2). XN) is set to a voltage exceeding the discharge start voltage (that is, a voltage at which discharge occurs in the discharge cell regardless of whether there is a previous discharge).

While the rising ramp waveform voltage rises, the scan electrode SC (1 + 2 × N) and the sustain electrode SU (1 + 2 × N) of each discharge cell, and the scan electrode SC (1 + 2 × N) and the data electrodes D1˜ A weak initializing discharge is continuously generated between the data electrodes Dm. At this time, the phosphor layer 35 of the discharge cell emits light slightly.

Then, negative wall voltage is accumulated on scan electrode SC (1 + 2 × N), and on data electrode D1 to data electrode Dm and sustain electrode SU (1 + 2 × N) intersecting scan electrode SC (1 + 2 × N). The positive wall voltage is accumulated in. Furthermore, priming particles that shorten the discharge delay time of the address discharge (the length of time from when the voltage applied to the discharge cell exceeds the discharge start voltage to when the discharge occurs in the discharge cell) are also generated.

The wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer 25 covering the electrode, the protective layer 26, the phosphor layer 35, and the like.

In the latter half of the initialization period Ti1 of the subfield SF1, the positive voltage Ve is applied to the sustain electrodes SU1 to SUn, and the voltage 0 (V) is applied to the data electrodes D1 to Dm. Scan electrode SC (1 + 2 × N) (for example, scan electrode SC1, scan electrode SC3, scan electrode SC5,...) Gradually (eg, about −2.5 V) from voltage Vi3 to negative voltage Vi4. Apply a falling ramp waveform voltage (with a slope of / μsec).

The voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to the sustain electrode SU (1 + 2 × N), and the voltage Vi4 is set to a voltage higher than the discharge start voltage with respect to the sustain electrode SU (1 + 2 × N).

While this downward ramp waveform voltage is applied to scan electrode SC (1 + 2 × N), scan electrode SC (1 + 2 × N) and sustain electrode SU (1 + 2 × N) of each discharge cell and scan electrode SC ( 1 + 2 × N) and weak initialization discharges are generated between the data electrodes D1 to Dm.

Thus, the negative wall voltage on scan electrode SC (1 + 2 × N), the positive wall voltage on sustain electrode SU (1 + 2 × N), and data electrode D1 intersecting with scan electrode SC (1 + 2 × N). The positive wall voltage on the data electrode Dm is adjusted to a voltage suitable for the write operation in the write period. Furthermore, priming particles that shorten the discharge delay time of the address discharge are also generated.

The above voltage waveform is a forced initializing waveform that generates an initializing discharge in the discharge cell regardless of the operation of the immediately preceding subfield. The operation for applying the forced initialization waveform to the scan electrode 22 is the forced initialization operation. Then, in the subfield SF1 of the first field, the initialization operation in the discharge cell formed on the (1 + 2 × N) -th scan electrode SC (1 + 2 × N) from the top is the previous sub-field SF1. The forced initializing operation generates an initializing discharge in the discharge cells regardless of the field operation.

On the other hand, voltage Vi1 is applied to scan electrode SC (2 + 2 × N) (for example, scan electrode SC2, scan electrode SC4, scan electrode SC6,...) In the first half of initialization period Ti1 of subfield SF1. First, an upward ramp waveform voltage that gently rises from the voltage 0 (V) toward the voltage Vi5 is applied. This upward ramp waveform voltage is a voltage waveform that continues to rise for the same time at the same gradient as the upward ramp waveform voltage applied to scan electrode SC (1 + 2 × N). Therefore, the voltage Vi5 is equal to the voltage obtained by subtracting the voltage Vi1 from the voltage Vi2.

At this time, each voltage is set so that the voltage Vi5 is lower than the discharge start voltage with respect to the sustain electrode SU (2 + 2 × N). As a result, no discharge is substantially generated in the discharge cell to which this upward ramp waveform voltage is applied.

In the latter half of the initializing period Ti1 of the subfield SF1, a downward ramp waveform voltage similar to the downward ramp waveform voltage applied to the scan electrode SC (1 + 2 × N) is applied to the scan electrode SC (2 + 2 × N).

In the discharge cell in which the sustain discharge is generated in the sustain period of the immediately preceding subfield (subfield SF10 in FIG. 3) while the downward ramp waveform voltage is applied to scan electrode SC (2 + 2 × N), weak initialization is performed. Discharge occurs. Due to this initialization discharge, the negative wall voltage of scan electrode 22, the positive wall voltage on sustain electrode 23, and the positive wall voltage on data electrode 32 are suitable for the write operation in the write period. Adjusted to the desired voltage.

Thus, the wall voltage in the discharge cell is adjusted to a wall voltage suitable for the address operation. Furthermore, priming particles that shorten the discharge delay time of the address discharge are also generated.

On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period of the immediately preceding subfield (subfield SF10), the initializing discharge does not occur and the previous wall voltage is maintained.

The above voltage waveform is a selective initialization waveform in which an initializing discharge is selectively generated in a discharge cell that has performed an address operation in the address period Tw of the immediately preceding subfield. The operation of applying the selective initialization waveform to the scan electrode 22 is the selective initialization operation. Then, in the subfield SF1 of the first field, the initialization operation in the discharge cell formed on the (2 + 2 × N) th scan electrode SC (2 + 2 × N) from the top is arranged immediately before. This is a selective initializing operation in which initializing discharge is selectively generated in the discharge cells in which the address operation is performed in the subfield address period.

Thus, the specific cell initialization operation in the initialization period Ti1 of the specific cell initialization subfield (subfield SF1) is completed. In the initialization period Ti1 of the specific cell initialization subfield, the discharge cells that perform the forced initialization operation and the discharge cells that perform the selective initialization operation coexist.

Next, the writing period Tw will be described.

In the address period Tw of the subfield SF1, the voltage 0 (V) is applied to the data electrodes D1 to Dm and the voltage Ve is applied to the sustain electrodes SU1 to SUn following the latter half of the initialization period Ti1. To do. Then, voltage Vc is applied to scan electrode SC1 through scan electrode SCn.

Next, a scan pulse of the negative voltage Va is applied to the scan electrode SC1 in the first row where the address operation is performed first. Then, an address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 exceeds the discharge start voltage, and a discharge occurs between the data electrode Dk and the scan electrode SC1.

In addition, since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, discharge is not likely to occur between sustain electrode SU1 and scan electrode SC1, but discharge is likely to occur.

Thus, a discharge is generated between the sustain electrode SU1 and the scan electrode SC1 in a region intersecting the data electrode Dk, induced by a discharge generated between the data electrode Dk and the scan electrode SC1. Thus, an address discharge is generated in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Is accumulated.

In this way, in the first row, an address operation is performed in which an address discharge is generated in the discharge cells to emit light and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode 32 and the scan electrode SC1 to which the address pulse is not applied does not exceed the discharge start voltage, so the address discharge does not occur.

Next, a scan pulse is applied to the scan electrode SC2 that performs the second address operation, and an address pulse is applied to the data electrode Dk that corresponds to the discharge cell that should emit light in the second row that performs the address operation. In the discharge cells to which the scan pulse and the address pulse are simultaneously applied, an address discharge is generated and an address operation is performed.

The above address operation is sequentially performed until the discharge cell in the n-th row, and the address period Tw ends. In this manner, in the address period Tw, address discharge is selectively generated in the discharge cells to emit light, and wall charges necessary for generating the sustain discharge in the subsequent sustain period Ts1 are formed in the discharge cells.

Next, the maintenance period Ts1 will be described.

In the sustain period Ts1 of the subfield SF1, the voltage 0 (V) is applied to the data electrodes D1 to Dm. Then, voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn, and a sustain pulse of positive voltage Vs is applied to scan electrode SC1 through scan electrode SCn.

In the discharge cell that has generated the address discharge, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. And the fluorescent substance layer 35 light-emits with the ultraviolet-ray which generate | occur | produced by this discharge.

Also, due to this discharge, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Furthermore, a positive wall voltage is also accumulated on the data electrode Dk. The positive wall voltage on the data electrode Dk is a wall voltage necessary for generating an address discharge in the next subfield.

In the discharge cells in which no address discharge has occurred in the address period Tw, no sustain discharge occurs, and the wall voltage at the end of the initialization period Ti1 is maintained.

Subsequently, voltage 0 (V) is applied to scan electrode SC1 through scan electrode SCn, and a sustain pulse of voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. In a discharge cell that has generated a sustain discharge immediately before, the voltage difference between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage.

As a result, a sustain discharge is generated again between the sustain electrode SUi and the scan electrode SCi, and the phosphor layer 35 emits light by the ultraviolet rays generated by this discharge. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi.

Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. By doing so, sustain discharge is continuously generated in the discharge cells that have generated address discharge in the address period.

After all sustain pulses are generated in sustain period Ts1, that is, after the last sustain pulse is generated in sustain period Ts1, sustain electrode SU1 to sustain electrode SUn and data electrode D1 to data electrode Dm have a voltage of 0 (V ) Is applied to scan electrode SC1 through scan electrode SCn with a gentle gradient (for example, a gradient of about 5 V / μsec) until voltage Vr1 is reached from voltage 0 (V), which is the base potential and less than the discharge start voltage. Apply a rising ramp waveform voltage.

By setting the voltage Vr1 to a voltage exceeding the discharge start voltage, a weak discharge is generated between the sustain electrode SUi and the scan electrode SCi of the discharge cell that has generated the sustain discharge. This weak discharge is continuously generated during a period in which the voltage applied to scan electrode SC1 through scan electrode SCn rises above the discharge start voltage.

The charged particles generated by this weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. That is, the discharge generated by this upward ramp waveform voltage works as an erasing discharge. Thereby, in the discharge cell in which the sustain discharge has occurred, a part or all of the wall voltage on scan electrode SCi and sustain electrode SUi is erased while the positive wall voltage on data electrode Dk remains.

In the present embodiment, the voltage Vr1 is set to a voltage lower than the sustain pulse voltage Vs.

When the increasing voltage reaches the predetermined voltage Vr1, the voltage applied to scan electrode SC1 through scan electrode SCn is decreased to voltage 0 (V). Thus, the maintenance operation in the maintenance period Ts1 is completed.

In the initialization period Ti2 of the subfield SF2, the voltage 0 (V) is applied to the data electrode D1 to the data electrode Dm, and the voltage Ve is applied to the sustain electrode SU1 to the sustain electrode SUn.

Scan electrode SC1 to scan electrode SCn have a voltage that gradually falls from voltage Vi3 ′ (for example, voltage 0 (V) that is the base potential), which is less than the discharge start voltage, to negative voltage Vi4 that exceeds the discharge start voltage. Apply ramp waveform voltage.

The gradient of the downward ramp waveform voltage may be the same as the gradient of the downward ramp waveform voltage generated in the initialization period Ti1 of the subfield SF1, and an example thereof is a numerical value of about −2.5 V / μsec. Can be mentioned.

Thereby, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the sustain period Ts1 of the immediately preceding subfield (subfield SF1 in FIG. 3). Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened, and the wall voltage on data electrode Dk is also adjusted to a value suitable for the write operation.

On the other hand, in a discharge cell that did not generate a sustain discharge in the sustain period Ts1 of the immediately preceding subfield, the initialization discharge does not occur and the wall charge at the end of the immediately preceding subfield initialization period Ti1 is maintained. In this way, the initialization operation in the subfield SF2 is completed.

As described above, the initializing operation in the subfield SF2 is a selective initializing operation in which the initializing discharge is generated only in the discharge cells that generate the address discharge in the address period Tw of the immediately preceding subfield and generate the sustain discharge in the sustain period Ts1. It becomes.

The selective initialization waveform generated in the initialization period Ti1 of the subfield SF1 and the selective initialization waveform generated in the initialization period Ti2 of the subfield SF2 have different waveform shapes. However, the selective initializing waveform generated in the initializing period Ti1 of the subfield SF1 does not generate discharge in the first half of the initializing period Ti1, and the operation in the second half of the initializing period Ti1 is performed in the initializing period of the subfield SF2. This is substantially equivalent to the selective initialization operation in Ti2. Therefore, in the present embodiment, the initialization waveform applied to the discharge cells that are not subjected to the forced initialization operation in the initialization period Ti1 of the subfield SF1 is the selective initialization waveform.

In the address period Tw of the subfield SF2, the same drive voltage waveform as that in the address period Tw of the subfield SF1 is applied to each electrode.

In sustain period Ts1 of subfield SF2, as in sustain period Ts1 of subfield SF1, the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn. To do. Then, after generation of the last sustain pulse in sustain period Ts1, an upward ramp waveform voltage that gradually rises from voltage 0 (V) to voltage Vr1 is generated and applied to scan electrode SC1 through scan electrode SCn to generate erase discharge. To do.

In each subfield from subfield SF3 to subfield SF9, a drive voltage waveform similar to that in subfield SF2 is applied to each electrode except for the number of sustain pulses generated in sustain period Ts1.

In the initialization period Ti2 and address period Tw of the subfield SF10 that is the final subfield of one field, the same drive voltage waveform as that of the subfield SF2 is applied to each electrode. Further, in the sustain period Ts2 of the subfield SF10, the sustain pulses similar to the sustain pulse in the sustain period Ts1 of the subfield SF2 are alternately applied to the display electrode pairs 24, except for the number of sustain pulses generated.

However, the rising ramp waveform voltage for the erasing discharge generated in the sustain period Ts2 of the subfield SF10 has a waveform shape different from the rising ramp waveform voltage for the erasing discharge generated in the sustaining period Ts1 of the subfield SF2.

In sustain period Ts2 of subfield SF10, the rising ramp waveform voltage that gradually increases from voltage 0 (V) to voltage Vr2 (for example, with a gradient of about 5 V / μsec) after generation of the last sustain pulse in sustain period Ts2 is applied. It is generated and applied to scan electrode SC1 through scan electrode SCn. In the present embodiment, the voltage Vr2 is set to a voltage higher than the voltage Vr1.

That is, in the sustain period Ts2 of the subfield SF10, the rising ramp waveform voltage rising from the voltage 0 (V) to the voltage Vr2 higher than the voltage Vr1 is generated and applied to the scan electrodes SC1 to SCn. Thus, an erasing discharge is generated in the discharge cell that has generated the sustain discharge, and a part or all of the wall voltage on the scan electrode SCi and the sustain electrode SUi is erased.

In the present embodiment, the voltage Vr2 is set higher than the voltage Vs of the sustain pulse.

The above is the outline of the drive voltage waveform applied to each electrode of panel 10 when displaying an image in the present embodiment.

In this embodiment, the magnitude of the voltage applied to each electrode is, for example, voltage Vi1 = 147 (V), voltage Vi2 = 362 (V), voltage Vi3 = 215 (V), voltage Vi4 = −180 ( V), voltage Vi5 = 215 (V), voltage Vc = −58 (V), voltage Va = −205 (V), voltage Vs = 215 (V), voltage Vr1 = 203 (V), voltage Vr2 = 255 (V) V), voltage Ve = 155 (V), and voltage Vd = 58 (V).

For example, the gradient of the rising ramp waveform voltage applied to scan electrodes SC1 to SCn is 5 (V / μsec), and the gradient of the falling ramp waveform voltage is −2.5 (V / μsec).

However, the specific numerical values such as the voltage value, time, and gradient described above are merely examples, and the present invention is not limited to the numerical values described above for each voltage value, time, gradient, and the like. Each voltage value, time, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device. For example, the voltage Vi5 = the voltage Vi3 may be used.

In the present embodiment, one field is composed of 10 subfields (subfield SF1 to subfield SF10), and each subfield has a luminance weight so that the luminance weight increases as the subfield occurs later in time. Is set.

Therefore, if a plurality of subfields that are temporally continuous so that the luminance weight becomes larger as a subfield that occurs later in time is defined as one subfield group, in this embodiment, one field is subfield SF1. To subfield SF10 can be regarded as being composed of one subfield group consisting of ten subfields.

In this embodiment, the luminance weight is relatively small, and the sub-field having a relatively large luminance weight generated immediately before the sub-field where the selective initialization operation is performed in the initialization period is used for erasing discharge. The maximum voltage of the rising ramp waveform voltage that is generated is set to a voltage that is higher than the maximum voltage of the rising ramp waveform voltage for erasing discharge that occurs in a subfield having a relatively small luminance weight.

In the present embodiment, the above-described subfield having a relatively small luminance weight and performing the selective initialization operation in the initialization period has the luminance weight “1”, and the specific cell initialization operation is performed in the initialization period. This is a subfield SF1 for performing. The subfield having the relatively large luminance weight is the subfield SF10 having the luminance weight “80”.

In other words, in the present embodiment, the maximum voltage of the rising ramp waveform voltage generated for erasing discharge in the sustain period of the subfield generated at the end of one subfield group is set as voltage Vr2. Then, voltage Vr2 is set to a voltage higher than voltage Vr1, which is the maximum voltage of the rising ramp waveform voltage generated for erasing discharge in the sustain period of the other subfield.

That is, in the present embodiment, in the sustain period of subfield SF10, the maximum voltage of the rising ramp waveform voltage generated for erasing discharge is set to voltage Vr2, and in the sustain period of each subfield from subfield SF1 to subfield SF9. The maximum voltage of the rising ramp waveform voltage generated for erasing discharge is defined as voltage Vr1. Then, the voltage Vr2 is set to a voltage higher than the voltage Vr1.

This is due to the following reasons.

In this embodiment, each discharge cell performs a forced initializing operation only once in a plurality of consecutive fields (for example, two consecutive fields in this embodiment). As a result, each discharge cell reduces the frequency of occurrence of the forced initializing operation and reduces light emission not related to gradation display, as compared with the configuration in which the forced initializing operation is performed once per field. Thus, the plasma display device 40 in the present embodiment reduces the black luminance in the display image and performs image display with high contrast.

However, as described above, if the frequency of the forced initializing operation is reduced, the wall charges and priming particles necessary for generating the address discharge are insufficient, the address operation becomes unstable, or the address discharge is not generated. There is a risk of malfunction such as not occurring.

In a discharge cell that has generated a sustain discharge, an initializing discharge occurs during the initializing period of the next subfield. The wall charge accumulated in the discharge cell is adjusted to a wall voltage suitable for the address operation by the initialization discharge. Therefore, a stable address operation can be performed in the address period of the next subfield in the discharge cell in which the sustain discharge has occurred.

However, in a discharge cell in which no sustain discharge has occurred, if the next subfield is a selective initialization subfield, initialization discharge does not occur during the selective initialization period. In such a discharge cell, when an address discharge or a sustain discharge occurs in an adjacent discharge cell, a wall charge in the discharge cell is reduced, and a phenomenon that the address operation becomes unstable occurs. This phenomenon is called “charge loss phenomenon”. The charge loss phenomenon is likely to occur in a panel with high definition and a finer discharge cell structure.

Therefore, the inventors of the present application investigated the charge loss phenomenon. Then, it was confirmed that in a discharge cell in which two or more subfields that do not perform the address operation and do not generate the initialization discharge are continuously generated, the probability of the address failure occurring increases.

And as a result of further detailed investigation, the following phenomenon was clarified.

In the following, a subfield in which no address operation is performed and no initialization discharge occurs is referred to as a “non-light emitting subfield”. Further, the following “target cell” is a discharge cell in which two or more non-light-emitting subfields are continuously generated.

In the first non-emission subfield of the target cell, when an address discharge occurs in the discharge cell adjacent to the target cell, a weak address discharge occurs in the target cell even though no address pulse is applied. There are things to do. This weak address discharge is an erroneous address discharge.

す る と If an erroneous address discharge occurs in the target cell, it will also occur during the subsequent sustain period. However, this discharge is a weak discharge and disappears without growing into a sustain discharge. Then, when this discharge occurs, a positive wall voltage is accumulated on the data electrode 32. However, since this wall voltage is generated by weak discharge, it is smaller than the normal wall voltage accumulated when normal sustain discharge occurs.

In the discharge cell that performs the address operation in the next subfield, the address pulse is applied to the data electrode 32, so the probability that the address discharge will normally occur is high.

However, the target cell does not perform the write operation in the next subfield. For this reason, when an address discharge occurs in a discharge cell adjacent to the target cell, the target cell may be affected by the address discharge and an erroneous address discharge may occur again. However, this erroneous address discharge is a weaker discharge than the previous erroneous address discharge. Therefore, even if this erroneous address discharge occurs, no discharge occurs in the subsequent sustain period.

As a result, a negative wall voltage remains on the data electrode 32. Therefore, after that, there is a possibility that the address discharge cannot be generated until the forced initialization operation is performed.

For the reasons described above, in a discharge cell in which two or more non-light-emitting subfields that do not perform an address operation and do not generate an initialization discharge are generated in succession, the probability that an address failure will occur increases.

In plasma display device 40 according to the present exemplary embodiment, each discharge cell is initialized by either a forced initializing operation or a selective initializing operation in initializing period Ti1 of subfield SF1, which is a specific cell initializing subfield. Perform the action. For a plurality of subfields constituting one field, the luminance weight is set in each subfield such that the luminance weight increases as the subfield occurs later in time.

Therefore, the subfield immediately before the subfield SF1 having the smallest luminance weight “1” is the last subfield of one field, and is the subfield having the largest luminance weight “80”.

When displaying a general moving image on the panel 10, it has been confirmed that the subfield with a smaller luminance weight has a higher probability of light emission, and the subfield with a larger luminance weight has a lower probability of light emission.

Therefore, with the subfield configuration shown as an example in the present embodiment, the probability that subfield SF9 and subfield SF10 having relatively large luminance weights emit light is relatively low, and subweights having relatively small luminance weights. The probability that the field SF1 emits light is relatively high. Therefore, the probability that the subfield SF9 and the subfield SF10 are non-light emitting subfields and the subfield SF1 is a light emitting subfield is relatively high.

If the subfield SF9 and the subfield SF10 are continuously non-light-emitting subfields, in the discharge cell that performs the selective initialization operation in the initialization period Ti1 of the subfield SF1 that is the specific cell initialization subfield, There is a possibility that the address discharge cannot be generated for the reason described above.

Therefore, in the present embodiment, it is generated due to the erase discharge in the sustain period of the subfield immediately before the specific cell initialization subfield, that is, the last subfield of one field (subfield SF10 in the present embodiment). The maximum voltage of the rising ramp waveform voltage is defined as voltage Vr2. The voltage Vr2 is a voltage that is the maximum voltage of the rising ramp waveform voltage generated for the erasing discharge in the sustain period of the other subfield (in this embodiment, each subfield from subfield SF1 to subfield SF9). A voltage higher than Vr1 is set.

As a result, for example, the subfield SF9 and the subfield SF10 are continuously non-light emitting subfields, and the discharge cells that may cause a write failure in the subsequent subfield SF1 remain on the data electrode 32. The negative wall voltage can be inverted to prevent the occurrence of write failure in the subsequent subfield SF1.

That is, even in the plasma display device 40 that performs the forced initializing operation only once in a plurality of fields in each discharge cell, it is possible to prevent the occurrence of an address failure and stably generate an address discharge.

As described above, in the plasma display device 40 according to the present embodiment, the luminance weight is relatively small, and the subfield (in this embodiment, the luminance weight “1” is selected during the initialization period). ”And a subfield having a relatively large luminance weight (subfield SF1 in the present embodiment, which is generated immediately before the subfield SF1 in which the specific cell initializing operation is performed in the initializing period). In SF10), the voltage Vr2 which is the maximum voltage of the rising ramp waveform voltage generated for the erasing discharge is the maximum voltage of the rising ramp waveform voltage for the erasing discharge generated in the subfield having a relatively small luminance weight. A voltage higher than a certain voltage Vr1 is set.

In other words, the voltage Vr2, which is the maximum voltage of the rising ramp waveform voltage generated for the erase discharge in the sustain period Ts2 of the last subfield (subfield SF10 in the present embodiment) of the subfield group, is set to the other subfields. Set to a voltage higher than voltage Vr1, which is the maximum voltage of the rising ramp waveform voltage generated for erasing discharge in sustain period Ts1 of the field (in this embodiment, each subfield from subfield SF1 to subfield SF9). To do.

Thereby, in the plasma display device 40, it is possible to stably generate an address discharge and display an image with high contrast and high image display quality on the panel 10.

For the reason described above, for the discharge cell to which the selective initialization waveform is applied in the initialization period Ti1 (specific cell initialization period) of the subfield SF1, the sustain period Ts2 (for example, the subfield SF) immediately before the subfield SF1 is applied. The maximum voltage of the rising ramp waveform voltage generated for erasing discharge in the sustain period Ts2) of SF10 is defined as voltage Vr2. However, in the discharge cell to which the forced initializing waveform is applied in the initializing period Ti1 (specific cell initializing period) of the subfield SF1, since the initializing discharge is forcibly generated, the sustain period immediately before the subfield SF1 is generated. The maximum voltage of the rising ramp waveform voltage generated for erasing discharge in Ts2 (for example, sustain period Ts2 of subfield SF10) may not be voltage Vr2. For example, the maximum voltage of the upward ramp waveform voltage may be the voltage Vr1.

Note that it is not desirable to set the maximum voltage of the rising ramp waveform voltage generated for the erase discharge to the voltage Vr2 in the sustain period of all the subfields. When the maximum voltage of the rising ramp waveform voltage increases, the erase operation becomes excessive, and the wall charges in the discharge cells are excessively erased. For this reason, it is difficult for the address discharge to occur in the subsequent address period, and it becomes difficult to set the voltage of the drive voltage waveform during the address operation.

Next, the configuration of the plasma display device in the present embodiment will be described. In the following description, the operation of conducting the switching element is represented as “on”, and the operation of shutting off is represented as “off”.

FIG. 4 is a circuit block diagram of plasma display device 40 in accordance with the first exemplary embodiment of the present invention.

The plasma display device 40 includes a panel 10 and a drive circuit that drives the panel 10. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit (not shown) that supplies necessary power to each circuit block. It has.

The image signal processing circuit 41 assigns a gradation value to each discharge cell based on the input image signal. Then, the gradation value is converted into image data indicating light emission / non-light emission for each subfield.

For example, when the input image signal sig includes an R signal, a G signal, and a B signal, R, G, and B gradation values (in one field) are assigned to each discharge cell based on the R signal, the G signal, and the B signal. Assigned gradation value). Alternatively, when the input image signal sig includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal), the luminance signal and R, G, and B signals are calculated based on the saturation signal, and thereafter, R, G, and B gradation values are assigned to the respective discharge cells. Then, the R, G, and B gradation values assigned to each discharge cell are converted into image data indicating light emission / non-light emission for each subfield.

The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal. Then, the generated timing signal is supplied to each circuit block (image signal processing circuit 41, data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, etc.).

Scan electrode drive circuit 43 has an initialization waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown). The initialization waveform generating circuit generates an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn during the initialization period. The sustain pulse generation circuit generates a sustain pulse to be applied to scan electrode SC1 through scan electrode SCn during the sustain period. The scan pulse generating circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period. Scan electrode driving circuit 43 drives scan electrode SC1 through scan electrode SCn based on the timing signal supplied from timing generation circuit 45, respectively.

The data electrode drive circuit 42 converts the data for each subfield constituting the image data into address pulses corresponding to the data electrodes D1 to Dm. Then, based on the timing signal supplied from the timing generation circuit 45, an address pulse is applied to each of the data electrodes D1 to Dm.

Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve (not shown), and drives sustain electrode SU1 through sustain electrode SUn based on the timing signal supplied from timing generation circuit 45.

FIG. 5 is a circuit diagram schematically showing a configuration of scan electrode drive circuit 43 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention.

The scan electrode drive circuit 43 includes a sustain pulse generation circuit 50, a ramp waveform voltage generation circuit 60, and a scan pulse generation circuit 70. Each circuit block operates based on the timing signal supplied from the timing generation circuit 45, but details of the timing signal path are omitted in FIG. The voltage input to the scan pulse generation circuit 70 is referred to as “reference potential A”.

Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59. The power recovery circuit 51 includes a power recovery capacitor, a plurality of switching elements, a plurality of backflow prevention diodes, and a plurality of resonance inductors.

The power recovery circuit 51 recovers the power stored in the panel 10 from the panel 10 through LC resonance between the interelectrode capacitance of the panel 10 and the inductor, and stores it in the capacitor. Then, the recovered power is LC-resonated between the interelectrode capacitance of the panel 10 and the inductor, supplied again from the capacitor to the panel 10, and reused as power for driving the scan electrodes SC1 to SCn.

Switching element Q55 clamps scan electrode SC1 through scan electrode SCn to voltage Vs, and switching element Q56 clamps scan electrode SC1 through scan electrode SCn to voltage 0 (V). The switching element Q59 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

Thus, sustain pulse generating circuit 50 generates a sustain pulse of voltage Vs applied to scan electrode SC1 through scan electrode SCn.

Scan pulse generation circuit 70 includes switching element Q71H1 to switching element Q71Hn, switching element Q71L1 to switching element Q71Ln, switching element Q72, a power source that generates negative voltage Va, and a power source E71 that generates voltage Vp. Then, the voltage Vp (Vc = Va + Vp) is generated by superimposing the voltage Vp on the reference potential A of the scan pulse generation circuit 70, and is applied to scan electrode SC1 through scan electrode SCn while switching between voltage Va and voltage Vc. A scan pulse is generated. For example, when the voltage Va = −205 (V) and the voltage Vp = 147 (V), the voltage Vc = −58 (V).

Scan pulse generation circuit 70 sequentially applies scan pulses to scan electrode SC1 through scan electrode SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain period. That is, the reference potential A is output to scan electrode SC1 through scan electrode SCn.

The ramp waveform voltage generation circuit 60 includes a Miller integration circuit 61, a Miller integration circuit 62, and a Miller integration circuit 63, and generates the ramp waveform voltage shown in FIG.

Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. Then, by applying a constant voltage to the input terminal IN61 (giving a constant voltage difference between two circles shown as the input terminal IN61), an upward ramp waveform voltage that gradually increases toward the voltage Vt is obtained. appear.

In the present embodiment, the voltage Vi2 is set to be equal to a voltage obtained by superimposing the voltage Vp on the voltage Vt. That is, when Miller integrating circuit 61 is operated, switching element Q72 and switching elements Q71L1 to Q71Ln are turned off, switching elements Q71H1 to switching element Q71Hn are turned on, and the upward slope generated in Miller integrating circuit 61 is generated. A voltage Vp of the power supply E71 is superimposed on the waveform voltage to generate an upslope waveform voltage having a forced initialization waveform.

Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode Di62 for preventing backflow. Then, by applying a constant voltage to the input terminal IN62 (giving a constant voltage difference between two circles shown as the input terminal IN62), an upward ramp waveform voltage that gradually increases toward the voltage Vr1 is obtained. appear.

Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63. Then, by applying a constant voltage to the input terminal IN63 (giving a constant voltage difference between the two circles shown as the input terminal IN63), a downward ramp waveform voltage that gently falls toward the voltage Vi4 is obtained. appear.

Note that the switching element Q69 is a separation switch, and prevents a current from flowing back through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

Note that these switching elements and transistors can be configured using generally known semiconductor elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the respective switching elements and transistors generated by the timing generation circuit 45.

Next, the operation of the drive circuit in the present embodiment, mainly the scan electrode drive circuit 43, will be described.

In the present embodiment, in the driving voltage waveform shown in FIG. 3, the voltage Vi1 is equal to the voltage Vp, the voltage Vi2 is equal to the voltage (Vt + Vp), the voltage Vi3 is equal to the voltage Vs, and the voltage Vc is equal to the voltage (Va + Vp). It shall be equal.

However, these voltages are not limited to the above-described numerical values, and are desirably set as appropriate according to the characteristics of the panel 10 and the specifications of the plasma display device.

FIG. 6 is a timing chart for explaining the operation of the driving circuit of the plasma display device 40 according to the first embodiment of the present invention.

In FIG. 6, in the initialization period Ti1, the scan electrode 22 to which the forced initialization waveform is applied is the scan electrode SC1, and the scan electrode 22 to which the selective initialization waveform is applied is the scan electrode SC2.

In FIG. 6, among the switching elements Q71H1 to Q71Hn, the switching element corresponding to the scan electrode SC1 is referred to as a switching element Q71H1, and the switching element corresponding to the scan electrode SC1 is referred to as a switching element Q71H1. Similarly, of switching elements Q71L1 to Q71Ln, the switching element corresponding to scan electrode SC1 is referred to as switching element Q71L1, and the switching element corresponding to scan electrode SC1 is referred to as switching element Q71L1.

In the drive voltage waveform shown in FIG. 6, the waveform shape of the rising ramp waveform voltage having the maximum voltage as the voltage Vr2 is different from the waveform shape of the rising ramp waveform voltage having the maximum voltage as the voltage Vr2 shown in FIG. However, in the present embodiment, the same effect as described above can be obtained with any upward ramp waveform voltage.

For example, it may be difficult to generate an upward ramp waveform voltage that increases with a constant gradient from the voltage 0 (V) to the voltage Vr2 as shown in FIG. FIG. 6 shows an example of generating an upslope waveform voltage that can achieve the same effect as described above even in such a case.

In the first half of the initialization period Ti1 of the subfield SF1, first, the switching element Q56 of the scan electrode drive circuit 43 is turned on to apply the voltage 0 (V) to the scan electrode SC1 and the scan electrode SC1.

Next, switching element Q56 is turned off, and switching element Q71L1 is turned off, switching element Q71H1 is turned on, and voltage Vp is applied to scan electrode SC1 to which a forced initialization waveform is applied. On the other hand, the voltage 0 (V) is kept applied to the scan electrode SC2 to which the selective initialization waveform is applied without performing the forced initialization operation.

Next, a constant voltage is applied to the input terminal IN61 of the Miller integrating circuit 61, and the voltage of the reference potential A is gradually raised to the voltage Vt. Since a voltage obtained by superimposing the voltage Vp on the reference potential A is applied to the scan electrode SC1 to which the forced initializing waveform is applied, an ascending waveform that gently rises from the voltage Vp to the voltage (Vt + Vp). A voltage can be applied.

On the other hand, since reference potential A is applied to scan electrode SC2 to which no forced initialization waveform is applied, an upward ramp waveform voltage that gradually rises from voltage 0 (V) to voltage Vt is applied to scan electrode SC2. Can do.

In the latter half of the initializing period Ti1 of the subsequent subfield SF1, the switching element Q71H1 of the scan electrode driving circuit 43 is turned off, the switching element Q71L1 is turned on, the switching element Q55 and the switching element Q59 are turned on, and the scan electrode A voltage Vs is applied to SC1 and scan electrode SC2.

Thereafter, the switching element Q69 is turned off and a constant voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 to operate the Miller integrating circuit 63, so that the scanning electrode SC1 and the scanning electrode SC2 are gradually applied from the voltage Vs to the voltage Vi4. A falling ramp waveform voltage is applied.

In the writing period Tw of the subfield SF1, the transistor Q63 of the Miller integrating circuit 63 of the scan electrode driving circuit 43 is turned off, the switching element Q72 is turned on, and the voltage of the reference potential A is set to the voltage Va. Then, switching element Q71L1 and switching element Q71L2 are turned off, switching element Q71H1 and switching element Q71H2 are turned on, and voltage (Va + Vp), that is, voltage Vc is applied to scan electrode SC1 and scan electrode SC2.

Next, switching element Q71H1 is turned off, switching element Q71L1 is turned on, and a scan pulse that is displaced from voltage Vc to voltage Va is applied to scan electrode SC1.

After a certain time (after completion of the write operation in the first row), the switching element Q71H1 is turned on, the switching element Q71L1 is turned off, and the voltage applied to the scan electrode SC1 is returned to the voltage Vc. In this way, a scan pulse is applied to scan electrode SC1.

Next, switching element Q71H2 is turned off, switching element Q71L2 is turned on, and a scan pulse that is displaced from voltage Vc to voltage Va is applied to scan electrode SC2.

After a certain time (after completion of the write operation in the second row), the switching element Q71H2 is turned on, the switching element Q71L2 is turned off, and the voltage applied to the scan electrode SC2 is returned to the voltage Vc. In this way, a scan pulse is applied to scan electrode SC2.

In the same manner, scan pulses are sequentially applied to the scan electrode 22 until the scan electrode SCn is reached.

Thereafter, switching element Q72, switching element Q71H1, and switching element Q71H2 are turned off, and switching element Q56, switching element Q69, switching element Q71L1, and switching element Q71L2 are turned on, respectively, and voltage 0 ( V) is applied. Thus, the writing period ends.

In the sustain period Ts1 of the subfield SF1, the sustain pulse generation circuit 50 of the scan electrode driving circuit 43 is used to apply the number of sustain pulses corresponding to the luminance weight to scan electrode SC1 to scan electrode SCn.

Then, after all the sustain pulses in the sustain period are generated, the switching element Q56 of the scan electrode drive circuit 43 is turned off. At the same time, a constant voltage is applied to input terminal IN62 of Miller integrating circuit 62 to operate Miller integrating circuit 62, and an upward ramp waveform voltage that gradually rises to voltage Vr1 is applied to scan electrode SC1 through scan electrode SCn. . The voltage Vr1 is a voltage lower than the voltage Vs (eg, voltage Vr1 = voltage Vs−12 (V)).

In the initialization period Ti2 of the subfield SF2, the switching element Q71L1 to the switching element Q71Ln of the scan electrode driving circuit 43 are turned on, and the switching element Q71H1 to the switching element Q71Hn are kept off, and the input terminal IN63 of the Miller integrating circuit 63 is constant. Apply a voltage of. Miller integrating circuit 63 is thus operated, and a downward ramp waveform voltage that gently falls to voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn.

In the sustain period Ts2 of the subfield SF10, the sustain pulse generation circuit 50 of the scan electrode driving circuit 43 is used to apply the number of sustain pulses corresponding to the luminance weight to the scan electrodes SC1 to SCn.

Then, after all the sustain pulses in the sustain period are generated, the switching element Q56 of the scan electrode drive circuit 43 is turned off. At the same time, a constant voltage is applied to input terminal IN62 of Miller integrating circuit 62 to operate Miller integrating circuit 62, and an upward ramp waveform voltage that gradually rises to voltage Vr1 is applied to scan electrode SC1 through scan electrode SCn. . The voltage Vr1 is a voltage lower than the voltage Vs (eg, voltage Vr1 = voltage Vs−12 (V)).

Thereafter, switching element Q56 is turned on to apply voltage 0 (V) to scan electrode SC1 through scan electrode SCn. Thereafter, switching element Q56 is turned off.

Next, switching element Q71L1 to switching element Q71Ln are turned off, switching element Q71H1 to switching element Q71Hn are turned on, and voltage Vp is applied to scan electrode SC1 to scan electrode SCn.

Then, a constant voltage is applied to the input terminal IN62 of the Miller integrating circuit 62 to operate the Miller integrating circuit 62. As a result, an upward ramp waveform voltage that gradually rises from voltage Vp is applied to scan electrode SC1 through scan electrode SCn.

Then, when the voltage applied to scan electrode SC1 through scan electrode SCn reaches voltage Vr2, the voltage of input terminal IN62 of Miller integrating circuit 62 is turned off to stop the operation of Miller integrating circuit 62.

Thus, an upward ramp waveform voltage that rises to a voltage Vr2 higher than the voltage Vr1 is applied to scan electrode SC1 through scan electrode SCn.

Thereafter, switching element Q71H1 to switching element Q71Hn are turned off, and switching element Q71L1 to switching element Q71Ln are turned on.

Thus, in the present embodiment, the drive voltage waveforms shown in FIG. 3 are generated using data electrode drive circuit 42, scan electrode drive circuit 43, and sustain electrode drive circuit 44, and data electrodes D1 to D Dm is applied to each of scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.

That is, in the sustain period, the number of sustain pulses corresponding to a predetermined luminance weight is generated and applied alternately to the scan electrode 22 and the sustain electrode 23.

In sustain period Ts1 of subfields other than the final subfield (in this embodiment, each subfield from subfield SF1 to subfield SF9), after the last sustain pulse in the sustain period is generated, the voltage rises to voltage Vr1. An upward ramp waveform voltage is generated and applied to the scan electrode 22.

Then, in the sustain period Ts2 of the subfield (subfield SF10 in the present embodiment) that is the last subfield of one field and has the largest luminance weight, after the last sustain pulse in the sustain period is generated, An upward ramp waveform voltage rising to Vr1 is generated and applied to the scan electrode 22. When the rising ramp waveform voltage reaches the voltage Vr1, the voltage applied to the scan electrode 22 is once returned to the voltage 0 (V). Thereafter, a positive voltage (for example, voltage Vp) is applied to the scan electrode 22, and an upward ramp waveform voltage rising from the positive voltage to the voltage Vr 2 is generated and applied to the scan electrode 22.

For example, if it is difficult to generate an upward ramp waveform voltage that increases at a constant gradient from the voltage 0 (V) to the voltage Vr2 as shown in FIG. As described above, even when the rising ramp waveform voltage is generated in such a waveform shape that the voltage applied to the scan electrode 22 once decreases to 0 (V) while the voltage increases from the voltage 0 (V) to the voltage Vr2. It doesn't matter. Even in such a case, the same effect as described above can be obtained.

As described above, in this embodiment, each discharge cell performs a forced initialization operation only once in a plurality of consecutive fields (for example, two consecutive fields in this embodiment). Thereby, in the plasma display device 40, compared with the configuration in which the forced initialization operation is performed once in one field, the frequency of the forced initialization operation is reduced, and the light emission not related to the gradation display is reduced. It is possible to reduce black luminance in the display image and display an image with high contrast.

Further, in the present embodiment, in the sustain period Ts2 of the subfield (subfield SF10 in the present embodiment) which is the last subfield of one field and has the largest luminance weight, the uplink generated due to the erasing discharge is generated. The maximum voltage of the ramp waveform voltage is set to voltage Vr2, and the ramp waveform voltage generated for erasing discharge in the sustain period of the other subfield (in this embodiment, each subfield from subfield SF1 to subfield SF9) The maximum voltage is set to voltage Vr1. Then, the voltage Vr2 is set to a voltage higher than the voltage Vr1.

Thus, even in a subfield configuration in which a forced initialization operation is performed only once in a plurality of consecutive fields, address discharge can be generated stably.

That is, when the panel 10 is driven by a driving method in which a forced initializing operation is performed only once in a plurality of consecutive fields in each discharge cell, the last two subfields of one field (for example, the subfield SF9 and the subfield) Even if SF10) is a continuous non-light-emitting subfield, the address discharge can be stably generated in the discharge cell that performs the selective initializing operation in the initializing period Ti1 of the subfield SF1 that is the specific cell initializing subfield. Can do.

In the present embodiment, one field is composed of 10 subfields (subfield SF1 to subfield SF10), and the luminance weight increases in each subfield as the subfield occurs later in time. The luminance weight is set. Therefore, if a plurality of subfields that are temporally continuous so that the luminance weight becomes larger as a subfield that occurs later in time is defined as one subfield group, in this embodiment, one field is subfield SF1. To subfield SF10 can be regarded as being composed of one subfield group consisting of ten subfields. Therefore, it can be said that subfield SF10 is the last subfield of one subfield group.

(Embodiment 2)
In the first embodiment, when the panel 10 is driven by a driving method in which a forced initializing operation is performed only once in a plurality of consecutive fields in each discharge cell, the last two subfields (for example, subfields) Even if SF9 and subfield SF10) are consecutive non-light-emitting subfields, the address discharge can be stably performed in the discharge cell that performs the selective initializing operation in the initializing period Ti1 of the subfield SF1 that is the specific cell initializing subfield. The drive voltage waveform for generating the above has been described.

However, the present invention is not limited to this configuration. The present invention is a subfield configuration in which a subfield with a small luminance weight is generated after a subfield with a large luminance weight is continuously generated and an initialization discharge is not generated in the subfield with the small luminance weight. With the same configuration as described above, the same effect as described above can be obtained.

In addition to the subfield configuration shown in the first embodiment, such a subfield configuration includes, for example, a subdevice designed to suppress flicker when an image is displayed on the panel 10 using a PAL image signal. There is a field structure.

In this embodiment, an example in which the configuration shown in Embodiment 1 is applied to a subfield configuration designed to suppress flicker when an image is displayed on the panel 10 using a PAL image signal will be described. .

In the present embodiment, the configuration of the plasma display device is the same as the configuration of the plasma display device 40 shown in the first embodiment, and a description thereof will be omitted.

In the present embodiment, the subfield configuration is different from the subfield configuration shown in the first embodiment.

In the present embodiment, one field is composed of 14 subfields (subfield SF1 to subfield SF14), and each subfield is (1, 2, 4, 8, 20, 32, 56, 4, 12). , 16, 16, 20, 32, 32) will be described.

As described above, in the present embodiment, the luminance weight of the plurality of subfields constituting one field increases from the subfield SF1 to the subfield SF7, and the luminance weight temporarily decreases from the subfield SF7 to the subfield SF8. The luminance weight increases again from subfield SF8 to subfield SF14.

Therefore, if a plurality of subfields that are temporally continuous such that the luminance weight increases as a subfield that occurs later in time is defined as one subfield group, in this embodiment, one field is subfield SF1. To subfield SF7, and a subfield group consisting of seven subfields and a subfield group consisting of seven subfields from subfield SF8 to subfield SF14. be able to.

Such a sub-field configuration has a flicker (image flicker) when an image signal with a low field frequency (number of fields generated per second) is displayed on the panel 10, such as a PAL image signal. It is effective in suppressing the occurrence.

FIG. 7 is a diagram showing drive voltage waveforms applied to each electrode of the panel used in the plasma display device in accordance with the second exemplary embodiment of the present invention.

FIG. 7 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SC2 that performs the address operation second in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform applied to is shown.

FIG. 7 shows the drive voltage waveforms of two subfields having different waveform shapes of the drive voltages applied to scan electrode SC1 through scan electrode SCn during the initialization period. These two subfields are a subfield SF1 that is an all-cell initializing subfield and a subfield after the subfield SF2 that is a selective initializing subfield.

The all-cell initializing subfield refers to initializing discharge cells in all the discharge cells in the image display area of the panel 10 by applying a forced initializing waveform to all the scan electrodes SC1 to SCn in the initializing period. A subfield that occurs. Hereinafter, the initialization period of the all-cell initialization subfield is also referred to as “all-cell initialization period”.

The drive voltage waveform in the subfield after subfield SF3 is substantially the same as the drive voltage waveform in subfield SF2 except that the number of sustain pulses generated in the sustain period is different.

However, in the subfield SF7, the waveform shape of the rising ramp waveform voltage for generating the erasing discharge is different from the rising ramp waveform voltage for generating the erasing discharge in the other subfields.

First, the subfield SF1, which is an all-cell initialization subfield, will be described.

In the initializing period Ti1 of the subfield SF1, the forced initializing waveform shown in the first embodiment is applied to all the scan electrodes SC1 to SCn.

That is, in the first half of the initialization period Ti1, a voltage of 0 (V) is applied to the data electrode D1 to the data electrode Dm and the sustain electrode SU1 to the sustain electrode SUn. Voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn. Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.

Further, an upward ramp waveform voltage that gently rises from voltage Vi1 to voltage Vi2 is applied to scan electrode SC1 through scan electrode SCn.

While the rising ramp waveform voltage is rising, between scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and between scan electrode SC1 through scan electrode SCn and data electrode D1 through data electrode Dm. In each case, a weak initializing discharge is continuously generated. Negative wall voltage is accumulated on scan electrode SC1 through scan electrode SCn, and positive wall voltage is accumulated on data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn. In addition, priming particles that help generate subsequent discharge are also generated.

In the latter half of the initialization period Ti1, positive voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage 0 (V) is applied as the first voltage to data electrode D1 through data electrode Dm. A downward ramp waveform voltage that gently decreases from voltage Vi3 toward negative voltage Vi4 is applied to scan electrode SC1 through scan electrode SCn.

The voltage Vi3 is set to a voltage lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn, and the voltage Vi4 is set to a voltage exceeding the discharge start voltage.

While a downward ramp waveform voltage is applied to scan electrode SC1 through scan electrode SCn, scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and scan electrode SC1 through scan electrode SCn and data electrode D1 through A weak initializing discharge is generated between each data electrode Dm.

Then, the negative wall voltage on scan electrode SC1 through scan electrode SCn and the positive wall voltage on sustain electrode SU1 through sustain electrode SUn are weakened, and the positive wall voltage on data electrode D1 through data electrode Dm is used for the write operation. It is adjusted to a suitable value. In addition, priming particles that help generate subsequent discharge are also generated.

Thus, the all-cell initializing operation for generating the initializing discharge in all the discharge cells is completed.

In the address period Tw of the subfield SF1, the same drive voltage waveform as that in the address period Tw shown in the first embodiment is applied to each electrode. That is, a scan pulse is sequentially applied to scan electrode SC1 through scan electrode SCn, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to a discharge cell to emit light. Thus, an address discharge is generated in the discharge cell to emit light, and wall charges necessary for the subsequent sustain discharge are formed.

In the sustain period Ts1 of the subfield SF1, a drive voltage waveform similar to that in the sustain period Ts1 described in the first embodiment is applied to each electrode. That is, the number of sustain pulses corresponding to the luminance weight is generated and applied alternately to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and the luminance weight is applied to the discharge cells that have caused the address discharge. The number of times of sustain discharge is generated.

Then, after the last sustain pulse is generated in sustain period Ts1, an upward ramp waveform voltage rising from voltage 0 (V) to voltage Vr1 is generated and applied to scan electrode SC1 through scan electrode SCn. Thereby, an erasing discharge is generated in the discharge cell that has generated the sustain discharge, and the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi are weakened.

In the initialization period Ti2 of the subfield SF2, the selective initialization waveform shown in the first embodiment is applied to all the scan electrodes SC1 to SCn.

That is, in the initialization period Ti2, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage Ve is applied to the sustain electrodes SU1 to SUn. Scan electrode SC1 through scan electrode SCn gradually decrease from voltage Vi3 ′ (eg, voltage 0 (V), which is the base potential), which is less than the discharge start voltage, to negative voltage Vi4 that exceeds the discharge start voltage. Apply a downward ramp waveform voltage.

As a result, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the sustain period of the immediately preceding subfield (subfield SF1 in FIG. 7). Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened, and the wall voltage on data electrode Dk is also adjusted to a value suitable for the write operation.

On the other hand, in the discharge cells that did not generate the sustain discharge in the sustain period of the immediately preceding subfield, the initialization discharge does not occur, and the wall charge at the end of the immediately preceding subfield initialization period is maintained. In this way, the initialization operation in the subfield SF2 is completed.

As described above, the initializing operation in subfield SF2 is a selective initializing operation in which initializing discharge is generated only in the discharge cells in which the address discharge is generated in the address period of the immediately preceding subfield and the sustain discharge is generated in the sustain period. .

In the address period Tw and the sustain period Ts1 of the subfield SF2, the same drive voltage waveform as that in the address period and the sustain period of the subfield SF1 is applied to each electrode, except for the number of sustain pulses.

In each subfield from subfield SF3 to subfield SF6, the drive voltage waveform similar to that in subfield SF2 is applied to each electrode except for the number of sustain pulses generated in sustain period Ts1.

In the initialization period Ti2 and address period Tw of the subfield SF7 that is the final subfield of the first subfield group, the same drive voltage waveform as that of the subfield SF2 is applied to each electrode. Further, in the sustain period Ts2 of the subfield SF7, a sustain pulse similar to the sustain pulse in the sustain period Ts1 of the subfield SF2 is alternately applied to the display electrode pair 24, except for the number of sustain pulses generated.

However, the rising ramp waveform voltage for the erasing discharge generated in the sustain period Ts2 of the subfield SF7 has a waveform shape different from the rising ramp waveform voltage for the erasing discharge generated in the sustaining period Ts1 of the subfield SF2.

In sustain period Ts2 of subfield SF7, after the generation of the last sustain pulse in sustain period Ts2, an upward ramp waveform voltage that gradually rises from voltage 0 (V) to voltage Vr2 is generated and applied to scan electrode SC1 through scan electrode SCn. Apply. Then, the voltage Vr2 is set to a voltage higher than the voltage Vr1.

In each subfield from subfield SF8 to subfield SF14, which is the second subfield group, the same drive voltage waveform as in subfield SF2 is applied to each electrode except for the number of sustain pulses generated in sustain period Ts1. To do.

In such a subfield configuration, the selective initialization operation is performed in the initialization period Ti1 of the subfield SF8 which is the first subfield of the second subfield group.

Also, in the first subfield group, the luminance weight is set in each subfield so that the luminance weight increases as the subfield occurs later in time.

Therefore, the subfield immediately before the subfield SF8 is the last subfield of the first subfield group, and is the subfield having the largest luminance weight in the subfield group.

As described above, when a general moving image is displayed on the panel 10, it is confirmed that a subfield with a smaller luminance weight has a higher probability of light emission, and a subfield with a larger luminance weight has a lower probability of light emission.

Therefore, in the subfield configuration shown as an example in the present embodiment, the probability that subfield SF6 and subfield SF7 having relatively large luminance weights emit light is relatively low, and subfield SF8 having a small luminance weight has The probability of emitting light is relatively high. Therefore, there is a relatively high probability that subfield SF6 and subfield SF7 are non-light emitting subfields, and subfield SF8 is a light emitting subfield.

If the subfield SF6 and the subfield SF7 are continuously non-light emitting subfields, the initializing discharge does not occur in the initializing period Ti2 of the subfield SF8 that is the selective initializing subfield, and for the reason described above. There is a possibility that the address discharge cannot be generated.

Therefore, in this embodiment, in order to erase discharge in a subfield having a relatively small luminance weight and a relatively large luminance weight generated immediately before the subfield in which the selective initializing operation is performed in the initializing period. The voltage Vr2 that is the maximum voltage of the rising ramp waveform voltage that is generated is set to a voltage that is higher than the voltage Vr1 that is the maximum voltage of the rising ramp waveform voltage for the erasing discharge that occurs in the subfield having a relatively small luminance weight. To do.

In the present embodiment, the above-described subfield having a relatively small luminance weight and performing the selective initialization operation in the initialization period has the luminance weight “4”, and performs the selective initialization operation in the initialization period. This is the subfield SF8 to be performed. The subfield having a relatively large luminance weight is the subfield SF7 having the luminance weight “56”.

In other words, in the present embodiment, in the sustain period of the subfield immediately before the second subfield group, that is, the last subfield of the first subfield group (subfield SF7 in the present embodiment). The maximum voltage of the rising ramp waveform voltage generated for erasing discharge is defined as voltage Vr2. Voltage Vr2 is generated due to erasing discharge in the sustain period of other subfields (in this embodiment, subfields SF1 to SF6 and subfield SF8 to subfield SF14). A voltage higher than the voltage Vr1, which is the maximum voltage of the ramp waveform voltage, is set.

As a result, for example, the subfield SF6 and the subfield SF7 continuously become non-light-emitting subfields, and the discharge cells that may cause a write failure in the subsequent subfield SF8 remain on the data electrode 32. The negative wall voltage is inverted, and the occurrence of write failure can be prevented in the subsequent subfield SF8.

In FIG. 7, the configuration for generating the rising ramp waveform voltage having the maximum voltage Vr2 in the last subfield SF7 of the first subfield group has been described. However, the present invention is not limited to this configuration. For example, in the last subfield SF14 of the second subfield group, an upward ramp waveform voltage whose maximum voltage is the voltage Vr2 may be generated. This is particularly effective in a subfield configuration in which the subfield SF1 is a specific cell initialization subfield because the forced initialization operation is performed only once in a plurality of consecutive fields.

In the present invention, the number of subfields constituting one field, subfields to be forced initialization subfields, luminance weights of each subfield, and the like are not limited to the above-described numerical values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

The driving voltage waveforms shown in FIGS. 3, 6, and 7 are merely examples in the embodiment of the present invention, and the present invention is not limited to these driving voltage waveforms.

The configuration of the drive circuit shown in FIGS. 4 and 5 is merely an example in the embodiment of the present invention, and the present invention is not limited to these circuit configurations.

Note that each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.

In the embodiment of the present invention, an example in which one field is composed of 10 subfields or 14 subfields has been described. However, in the present invention, the number of subfields constituting one field is not limited to the above number. For example, by increasing the number of subfields, the number of gradations that can be displayed on the panel 10 can be further increased. Alternatively, the time required for driving panel 10 can be shortened by reducing the number of subfields.

In the embodiment of the present invention, an example in which one pixel is constituted by discharge cells of three colors of red, green, and blue has been described. However, a panel in which one pixel is constituted by discharge cells of four colors or more. However, it is possible to apply the configuration shown in the embodiment of the present invention, and the same effect can be obtained.

The specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 24 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with panel specifications, panel characteristics, plasma display device specifications, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Also, the number of subfields constituting one field, the luminance weight of each subfield, etc. are not limited to the values shown in the embodiment of the present invention, and the subfield configuration is based on the image signal or the like. The structure to switch may be sufficient.

The present invention can perform a stable writing operation even when driving a high-definition large-screen panel, and can display a high-quality image on the panel. It is useful as a plasma display device.

DESCRIPTION OF SYMBOLS 10 Panel 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25,33 Dielectric layer 26 Protective layer 31 Back substrate 32 Data electrode 34 Partition 35 Phosphor layer 40 Plasma display device 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50 Sustain pulse generation circuit 51 Power recovery circuit 60 Ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 Scan pulse generation circuit Di62 Diodes Q55, Q56, Q59, Q69, Q72, Q71H1 to Q71Hn, Q71L1 to Q71Ln Switching elements C61, C62, C63 Capacitors R61, R62, R63 Resistors Q61, Q62, Q63 Transistors IN61, IN62, N63 input terminal E71 power Ti1, Ti2 initialization period Tw write period Ts1, Ts2 sustain period

Claims (8)

Selective initializing operation for applying a downward ramp waveform voltage, which decreases toward a negative voltage, to the scan electrode in a plasma display panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode A plasma display panel driving method in which a subfield having an initializing period, a writing period, and a sustain period in which a number of sustain pulses corresponding to a luminance weight are applied to the display electrode pair is provided in one field. There,
After the generation of the last sustain pulse in the sustain period, an upward ramp waveform voltage for generating an erasing discharge in the discharge cell is applied to the scan electrode,
In a subfield having a relatively small luminance weight and a relatively large luminance weight generated immediately before the subfield performing the selective initialization operation in the initialization period, the maximum voltage of the upward ramp waveform voltage is A method for driving a plasma display panel, wherein the voltage is set to be higher than a maximum voltage of the upward ramp waveform voltage generated in a subfield having a relatively small luminance weight. A specific cell initialization period in which a forced initializing operation for applying an upward ramp waveform voltage and the downward ramp waveform voltage to the scan electrode and a selective initialization operation for applying the downward ramp waveform voltage to the scan electrode are mixed; 2. The method of driving a plasma display panel according to claim 1, wherein an initialization period of a subfield having a relatively small luminance weight is set as the specific cell initialization period. 2. The method of claim 1, wherein the subfield having the relatively large luminance weight and the subfield having the relatively small luminance weight are successively generated in the same field. . The rising ramp waveform voltage is generated by once decreasing the applied voltage to the scan electrode and again increasing the applied voltage to the scan electrode before the applied voltage to the scan electrode rises to the maximum voltage. The method of driving a plasma display panel according to claim 1. A plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode;
An initializing period for performing a selective initializing operation in which a downward ramp waveform voltage that decreases toward a negative voltage is applied to the scan electrode, an address period, and a number of sustain pulses corresponding to the luminance weight are applied to the display electrode pair And a driving circuit for driving the plasma display panel with a subfield having a sustaining period in one field,
The drive circuit is
After the generation of the last sustain pulse in the sustain period, an upward ramp waveform voltage for generating an erasing discharge in the discharge cell is applied to the scan electrode,
In a subfield having a relatively small luminance weight and a relatively large luminance weight generated immediately before the subfield performing the selective initialization operation in the initialization period, the maximum voltage of the upward ramp waveform voltage is A plasma display apparatus, wherein a voltage higher than a maximum voltage of the upward ramp waveform voltage generated in a subfield having a relatively small luminance weight is set. The drive circuit is
A specific cell initialization period in which a forced initializing operation for applying an upward ramp waveform voltage and the downward ramp waveform voltage to the scan electrode and a selective initialization operation for applying the downward ramp waveform voltage to the scan electrode are mixed; 6. The plasma display apparatus according to claim 5, wherein an initialization period of a subfield having a relatively small luminance weight is set as the specific cell initialization period. The drive circuit is
The plasma display apparatus as claimed in claim 5, wherein the subfield having a relatively large luminance weight and the subfield having a relatively small luminance weight are successively generated in the same field. The drive circuit is
The rising ramp waveform voltage is generated by once decreasing the applied voltage to the scan electrode and again increasing the applied voltage to the scan electrode before the applied voltage to the scan electrode rises to the maximum voltage. The plasma display device according to claim 5, wherein:

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