JP2010266652A - Plasma display panel driving method and plasma display device - Google Patents

Abstract

An object of the present invention is to increase the contrast by reducing the black luminance of a display image, and to improve the image display quality by displaying the gradation of a dark area in the display image more finely while preventing the occurrence of unlit cells.
A scan electrode for applying a forced initializing waveform for generating an initializing discharge in a discharge cell and an uninitializing waveform for not generating an initializing discharge in the discharge cell during an initializing period of a specific cell initializing subfield In the selective initialization subfield, a ramp pulse that rises from the base potential to a predetermined potential is applied to all the scan electrodes without applying a sustain pulse to the display electrode pair during the sustain period. There is a light emission subfield to be applied, and an address pulse is not applied to the discharge cell to which an address pulse is applied in the address period of any subfield after the light emission subfield during the address period of the light emission subfield.
[Selection] Figure 8

Description

  The present invention relates to a driving method of a plasma display panel and a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other. A dielectric layer and a protective layer are formed so as to cover the display electrode pairs. In the back plate, a plurality of parallel data electrodes are formed on a back glass substrate, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. . And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition. Then, the front plate and the back plate are arranged to face each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed. In the sealed internal discharge space, for example, a discharge gas containing 5% xenon in a partial pressure ratio is sealed. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  A subfield method is generally used as a method for driving the panel. In the subfield method, one field is divided into a plurality of subfields, and light emission and non-light emission of each discharge cell are controlled in each subfield. Then, gradation display is performed by controlling the number of times of light emission generated in one field.

  Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell. Thus, wall charges necessary for the subsequent address operation are formed in each discharge cell, and priming particles (excited particles for generating the address discharge) for stably generating the address discharge are generated.

  In the address period, a scan pulse is sequentially applied to the scan electrode, and an address pulse corresponding to an image signal to be displayed is selectively applied to the data electrode. Thereby, in the discharge cell to emit light, an address discharge is generated between the scan electrode and the data electrode to form wall charges (hereinafter, this operation is also referred to as “address”).

  In the sustain period, sustain pulses of the number of times determined for each subfield are alternately applied to the display electrode pair including the scan electrode and the sustain electrode. Thereby, a sustain discharge is generated in the discharge cell in which the wall charge is formed by the address discharge, and the phosphor layer of the discharge cell is caused to emit light. In this way, an image is displayed in the image display area of the panel.

  One of the important factors for improving the image display quality in the panel is an improvement in contrast. As one of the subfield methods, a driving method is disclosed in which light emission not related to gradation display is reduced as much as possible to improve the contrast ratio.

  In this driving method, an initialization operation is performed in which an initializing discharge is generated in all the discharge cells in an initializing period of one subfield among a plurality of subfields constituting one field. Further, in the initializing period of the other subfield, an initializing operation is performed in which initializing discharge is selectively performed on the discharge cells in which the sustain discharge has been performed in the immediately preceding sustain period.

  The luminance of the black display area where no sustain discharge is generated (hereinafter abbreviated as “black luminance”) varies depending on light emission not related to image display, for example, light emission generated by initialization discharge. However, in the driving method described above, light emission in the black display region is only weak light emission when the initialization operation is performed on all the discharge cells. Thereby, it is possible to reduce the black luminance and display an image with high contrast (for example, refer to Patent Document 1).

  Also, an initializing period in which an initializing waveform having a rising portion having a gradually increasing gradually inclined portion and a falling portion having a gradually decreasing gradually inclined portion is applied to the discharge cells discharged in the sustain period. And a period in which weak discharge is generated between the sustain electrodes and the scan electrodes for all discharge cells immediately before any initializing period of one field, thereby reducing black luminance and improving black visibility. A technique for improving the technique is disclosed (for example, see Patent Document 2).

  In addition, a technique is disclosed in which, after the sustain pulse is applied to the display electrode pair in the sustain period, a rising ramp voltage is applied to the sustain electrode to erase wall charges in the discharge cell (for example, Patent Documents). 3).

JP 2000-242224 A JP 2004-37883 A JP 2004-348140 A

  As described above, for example, in the technique described in Patent Document 1, the initializing operation for generating the initializing discharge in all the discharge cells is performed once in one field, so that all the discharge cells are in each subfield. Compared with the case where the initialization discharge is generated, the black luminance of the display image can be reduced and the contrast can be increased.

  However, in recent years, there has been a demand for further improvement in image display quality with the increase in the screen size and definition of the panel.

  The present invention has been made in view of such a demand, and while reducing the black luminance of the display image to increase the contrast and preventing the occurrence of unlit cells, the gradation of the dark region in the display image is made finer. It is an object of the present invention to provide a panel driving method and a plasma display device that can display and improve image display quality.

  According to the panel driving method of the present invention, a panel including a plurality of discharge cells each having a display electrode pair and a data electrode each including a scan electrode and a sustain electrode is applied to a data electrode by applying a scan pulse to the scan electrode and the scan electrode. In the address period, an address pulse is generated by selectively applying an address pulse and a discharge cell to emit light, and a sustain pulse is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell in which the address discharge has occurred. A driving method of a panel in which a plurality of subfields having a sustain period are provided in one field, and one field is configured to have a specific cell initializing subfield and a selective initializing subfield to display gray scales. In the initializing period of the specific cell initializing subfield, a scan electrode for applying a forced initializing waveform for generating an initializing discharge in the discharge cell, and a discharge cell A scan electrode that applies a non-initializing waveform that does not generate an initializing discharge coexists, and during the initializing period of the selective initializing subfield, only the discharge cells that have generated a sustaining discharge in the sustaining period of the immediately preceding subfield are initialized. A selective initialization waveform for generating a crystallization discharge is applied to all the scan electrodes, and a sustain pulse is not applied to the display electrode pair during the sustain period in the selective initialization subfield, and rises from a base potential to a predetermined potential. There is a fine emission subfield that applies a ramp voltage to all the scan electrodes, and a discharge cell that applies an address pulse in the write period of any subfield after the fine emission subfield has an address in the emission period of the fine emission subfield. A write pulse is not applied.

  Thereby, the frequency of performing the forced initializing operation in each discharge cell can be made once in a plurality of fields, and the light emission subfield is caused to emit light with a light emission luminance lower than the light emission luminance due to one sustain discharge. Therefore, while reducing the black luminance of the display image to increase the contrast and preventing the occurrence of unlit cells, the gradation of the dark area in the display image can be displayed more finely to display the image of the plasma display device. Quality can be improved.

  In addition, the panel driving method of the present invention includes a panel having a plurality of discharge cells each having a display electrode pair and a data electrode each including a scan electrode and a sustain electrode, and applying a scan pulse to the scan period and the scan electrode. An address period in which an address pulse is selectively applied to a data electrode to generate an address discharge in a discharge cell to emit light, and a sustain pulse is alternately applied to a display electrode pair to sustain a discharge cell in which an address discharge has occurred A plurality of subfields each having a sustain period for generating grayscales are provided in one field, and one field is driven to have a configuration including a specific cell initializing subfield and a selective initializing subfield, thereby driving a panel for grayscale display. In the initialization period of the specific cell initialization subfield, a scan electrode for applying a forced initialization waveform for generating an initialization discharge in the discharge cell, and a discharge In the initializing period of the selective initializing subfield, only the discharge cells that generated the sustaining discharge in the sustaining period of the immediately preceding subfield are mixed with scan electrodes that apply non-initializing waveforms that do not generate initializing discharge. A selective initializing waveform for generating an initializing discharge is applied to all the scan electrodes, and in the selective initializing subfield, no sustain pulse is applied to the display electrode pair during the sustain period, from the base potential to a predetermined potential. There is a light emitting subfield that applies a rising ramp voltage to all the scan electrodes, and the discharge cells that apply the address pulse during the addressing period of the light emitting subfield have an addressing period of all subfields after the light emitting subfield. No writing pulse is applied.

  Thereby, the frequency of performing the forced initializing operation in each discharge cell can be made once in a plurality of fields, and the light emission subfield is caused to emit light with a light emission luminance lower than the light emission luminance due to one sustain discharge. Therefore, while reducing the black luminance of the display image to increase the contrast and preventing the occurrence of unlit cells, the gradation of the dark area in the display image can be displayed more finely to display the image of the plasma display device. Quality can be improved.

  In the panel driving method of the present invention, a non-initializing field having a non-initializing subfield for applying a non-initializing waveform to all scan electrodes and a selective initializing subfield in the initializing period is provided and specified. A configuration may be adopted in which a field having a cell initialization subfield and a non-initialization field are periodically switched. As a result, the frequency of performing the forced initialization operation in each discharge cell can be further reduced, and the black luminance of the display image can be further reduced.

  The plasma display device of the present invention includes a plurality of discharge cells having display electrode pairs and data electrodes each including a scan electrode and a sustain electrode, and a plurality of subfields having an initialization period, an address period, and a sustain period in one field. A panel in which one field has a specific cell initialization subfield and a selection initialization subfield, and one of the selection initialization subfields is a light emission subfield and performs gradation display, and an address period A data electrode driving circuit that selectively applies an address pulse to the data electrode and selectively applies an address pulse to the discharge cell, and a sustain electrode driving circuit that applies a sustain pulse to the sustain electrode during the sustain period, During the initializing period of the cell initializing subfield, a forced initializing waveform that generates initializing discharge is applied to the discharge cell. A discharge in which a sustain discharge is generated in the sustain period of the immediately preceding subfield in the initializing period of the selective initializing subfield by mixing electrodes and a scan electrode that applies a non-initializing waveform that does not generate an initializing discharge in the discharge cell A scan electrode drive that applies a selective initializing waveform that generates an initializing discharge only to the cells to all the scan electrodes, applies a scan pulse to the scan electrodes during the address period, and applies a sustain pulse to the scan electrodes during the sustain period The sustain electrode drive circuit and the scan electrode drive circuit do not apply sustain pulses to the sustain electrode and the scan electrode in the sustain period of the slightly light-emitting subfield, and the scan electrode drive circuit maintains the sustain period of the slightly light-emitting subfield. In addition, a ramp voltage that rises from the base potential to a predetermined potential is applied to all the scan electrodes, and the data electrode drive circuit causes one of the sub-fields after the light emission subfield to be The discharge cells to apply a write pulse to the address period of the field, characterized in that the writing period of the fine light-emitting sub-field is not applied to the write pulse.

  Thereby, the frequency of performing the forced initializing operation in each discharge cell can be made once in a plurality of fields, and the light emission subfield is caused to emit light with a light emission luminance lower than the light emission luminance due to one sustain discharge. Therefore, while reducing the black luminance of the display image to increase the contrast and preventing the occurrence of unlit cells, the gradation of the dark area in the display image can be displayed more finely to display the image of the plasma display device. Quality can be improved.

  The plasma display device of the present invention includes a plurality of discharge cells having display electrode pairs and data electrodes each including a scan electrode and a sustain electrode, and includes a subfield having an initialization period, an address period, and a sustain period in one field. And a panel for gradation display with one of the selected initialization subfields as a light emission subfield, and writing. A data electrode driving circuit that selectively applies an address pulse to the data electrode during a period and selectively applies an address pulse to the discharge cell; and a sustain electrode driving circuit that applies a sustain pulse to the sustain electrode during a sustain period; During the initializing period of the specific cell initializing subfield, a forced initializing waveform that generates initializing discharge is applied to the discharge cell. A scan electrode and a scan electrode that applies a non-initializing waveform that does not generate an initializing discharge are mixed in the discharge cell, and a sustaining discharge is generated in the sustaining period of the immediately preceding subfield during the initializing period of the selective initializing subfield. A scan electrode that applies a selective initialization waveform that generates an initializing discharge only to the discharge cells to all the scan electrodes, applies a scan pulse to the scan electrodes during the address period, and applies a sustain pulse to the scan electrodes during the sustain period And the sustain electrode drive circuit and the scan electrode drive circuit do not apply sustain pulses to the sustain electrode and the scan electrode in the sustain period of the light emission subfield, and the scan electrode drive circuit maintains the light emission subfield. In this period, a ramp voltage that rises from the base potential to a predetermined potential is applied to all the scan electrodes, and the data electrode driving circuit The discharge cells to apply a write pulse, characterized in that the writing period of all subfields of the fine light-emitting sub-field since no application of address pulse.

  Thereby, the frequency of performing the forced initializing operation in each discharge cell can be made once in a plurality of fields, and the light emission subfield is caused to emit light with a light emission luminance lower than the light emission luminance due to one sustain discharge. Therefore, while reducing the black luminance of the display image to increase the contrast and preventing the occurrence of unlit cells, the gradation of the dark area in the display image can be displayed more finely to display the image of the plasma display device. Quality can be improved.

  According to the present invention, the black luminance of the display image is reduced to increase the contrast, and the gradation of dark areas in the display image is displayed more finely while preventing the occurrence of non-lighted cells, thereby improving the image display quality. It is possible to provide a panel driving method and a plasma display device capable of achieving the above.

It is a disassembled perspective view which shows the structure of the panel in one embodiment of this invention. It is an electrode array figure of the panel. It is a wave form diagram which shows an example of the drive voltage waveform applied to each electrode of the panel. It is a figure which shows an example of the generation pattern of the forced initialization waveform and non-initialization waveform in one embodiment of this invention. It is a circuit block diagram of the plasma display apparatus in one embodiment of the present invention. It is a circuit diagram which shows the example of 1 structure of the scanning electrode drive circuit of the plasma display apparatus. 6 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the initialization period of the specific cell initialization subfield according to the embodiment of the present invention. It is a figure which shows correspondence of the light emission / non-light emission of each subfield in each gradation value in one embodiment of this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed on a glass front plate 21. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed of a material mainly composed of magnesium oxide (MgO) having a large secondary electron emission coefficient and excellent durability.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween. And the outer peripheral part is sealed with sealing materials, such as glass frit. A mixed gas of neon and xenon is sealed as a discharge gas in the discharge space inside. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. The panel 10 includes n scan electrodes SC1 to SCn (scan electrodes 22 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrodes 23 in FIG. 1) arranged in the row direction. Yes. Then, m data electrodes D1 to Dm (data electrodes 32 in FIG. 1) that are long in the column direction are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects with one data electrode Dk (k = 1 to m). Therefore, m × n discharge cells are formed in the discharge space. A region where m × n discharge cells are formed becomes a display region of the panel 10.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. In the plasma display device in the present embodiment, panel 10 is driven by the subfield method. In this subfield method, one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24. In the address period of each subfield, an address discharge is generated in the discharge cell to emit light, thereby controlling light emission / non-light emission of each discharge cell for each subfield. In this way, gradation display is performed by driving the panel 10.

  In the present embodiment, one field is composed of nine subfields (first SF, second SF,..., Ninth SF). Then, luminance weights (1, 2, 4, 8, 16, 32, 64, 128) are set in the second SF to the ninth SF subfields, respectively. Further, the configuration is such that a smaller luminance weight is set. In the present embodiment, the luminance weight smaller than the luminance weight “1” is expressed as luminance weight “0.25”. However, the luminance weight “0.25” does not mean that the luminance luminance is ¼ of the luminance weight “1”, but simply indicates that the luminance luminance is lower than the luminance weight “1”. Not too much. The details of the first SF having the luminance weight “0.25” will be described later.

  In the present embodiment, a forced initializing operation that generates an initializing discharge in a discharge cell regardless of the operation of the immediately preceding subfield and an uninitializing operation that does not generate an initializing discharge in the discharge cell are selectively performed. When a subfield having an initialization period (hereinafter referred to as “specific cell initialization subfield”) is performed (hereinafter referred to as “specific cell initialization operation”), the immediately preceding subfield is performed. A subfield having an initializing period for performing a selective initializing operation for generating an initializing discharge only in a discharge cell that has generated a sustaining discharge in the sustaining period (hereinafter referred to as “selective initializing subfield”), A subfield having an initializing period in which non-initializing operation is performed in the discharge cells (that is, initializing discharge is not generated in all discharge cells) (hereinafter referred to as “non-initializing subfield”). In other words, in the initializing period of the specific cell initializing subfield, the scan electrode 22 for applying a forced initializing waveform for generating an initializing discharge in the discharge cell is generated. And a scanning electrode 22 that applies a non-initializing waveform that does not generate an initializing discharge in the discharge cells are mixed so that an initializing discharge is generated only in a specific discharge cell. This is to reduce the light emission not related to the light as much as possible and improve the contrast ratio.

  The black luminance changes due to light emission not related to image display. Therefore, it is possible to reduce black luminance by reducing light emission not related to image display. Main light emission not related to image display is light emission due to initialization discharge. However, the selective initialization operation described above does not substantially affect the brightness of the black luminance because no discharge occurs in the discharge cells that did not generate the sustain discharge in the immediately preceding subfield. On the other hand, the forced initializing operation described above generates an initializing discharge in the discharge cell regardless of the operation of the immediately preceding subfield, and thus affects the brightness of black luminance.

  That is, the black luminance, which is the luminance of the black display area where no sustain discharge is generated, changes according to the frequency of the forced initialization operation. Therefore, if the frequency of performing the forced initialization operation in each discharge cell is reduced, the black luminance of the display image can be reduced and the contrast ratio can be improved.

  Therefore, in the present embodiment, the second SF is a specific cell initialization subfield or a non-initialization subfield, and the first SF and the third SF to the ninth SF are selection initialization subfields. Then, the discharge cells that perform the forced initializing operation are set in the field so that the frequency of performing the forced initializing operation in each discharge cell is once in a plurality of fields (in this embodiment, for example, once in every six fields). Change every time.

  Thereby, the frequency with which the forced initialization operation is performed in each discharge cell can be made once in a plurality of fields (for example, 6 fields). Therefore, compared with the configuration in which the forced initialization operation is performed once in each field, the configuration in which the forced initialization operation is performed once in a plurality of fields reduces the black luminance in the display image. , Can increase the contrast.

  Hereinafter, a field having a specific cell initialization subfield (for example, 2nd SF) and a plurality of selective initialization subfields (for example, 1st SF, 3rd SF to 9th SF) will be referred to as “specific cell initialization”. A field having a non-initializing subfield (for example, second SF) and a plurality of selective initializing subfields (for example, first SF, third SF to ninth SF) is referred to as “field”. This is called “field”.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  Next, taking a specific cell initialization field as an example, a specific example of a drive voltage waveform in the present embodiment will be described.

  FIG. 3 is a waveform diagram showing an example of a drive voltage waveform applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SC2 that performs the address operation second in the address period, and scan electrode SCn that performs the address operation last in the address period (for example, scan electrode SC1080). ), Drive voltage waveforms of sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm.

  FIG. 3 shows driving voltage waveforms of two subfields, that is, a second subfield (second SF) that is a specific cell initialization subfield and a first subfield (first SF) that is a selective initialization subfield. And mainly. Although not shown in the figure, in the present embodiment, it is assumed that subfields other than the second SF are selective initialization subfields.

  In addition, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from each electrode based on subfield data (data indicating light emission / non-light emission for each subfield).

  First, the second SF, which is a specific cell initialization subfield, will be described.

  In FIG. 3, the (1 + 3 × N) th (N is an integer) scan electrode SC (1 + 3 × N) from the top in terms of arrangement is initialized to a discharge cell regardless of the operation of the immediately preceding subfield. A configuration is shown in which a forced initializing waveform that generates discharge is applied, and a non-initializing waveform that does not generate initializing discharge in the discharge cells is applied to the other scan electrodes 22.

  In the first half of the initialization period of the second SF, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm. Then, a voltage Vi1 is applied to the scan electrode SC (1 + 3 × N), and a ramp voltage (hereinafter referred to as “a slope of about 0.5 V / μsec) gradually increases from the voltage Vi1 to the voltage Vi2. L1) (referred to as “up-ramp voltage”). At this time, voltage Vi1 is set to a voltage equal to or lower than the discharge start voltage for sustain electrode SU (1 + 3 × N), and voltage Vi2 is set to a voltage exceeding the discharge start voltage for sustain electrode SU (1 + 3 × N).

  While the rising ramp voltage L1 rises, between scan electrode SC (1 + 3 × N) and sustain electrode SU (1 + 3 × N), scan electrode SC (1 + 3 × N), data electrode D1 to data electrode Dm, In each period, a weak initializing discharge occurs continuously. Then, a negative wall voltage is accumulated on scan electrode SC (1 + 3 × N), and data electrode D1 to data electrode Dm and intersecting sustain electrode SU (1 + 3 × N) intersect with scan electrode SC (1 + 3 × N). A positive wall voltage is accumulated in the upper part. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, the voltage applied to scan electrode SC (1 + 3 × N) is lowered from voltage Vi2 to voltage Vi3 that is lower than voltage Vi2. Positive voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm. Then, a ramp voltage (hereinafter referred to as “down-ramp voltage”) that gradually decreases (for example, with a gradient of about −0.5 V / μsec) from the voltage Vi3 to the negative voltage Vi4 is applied to the scan electrode SC (1 + 3 × N). L2) is applied. At this time, voltage Vi3 is set to a voltage equal to or lower than the discharge start voltage with respect to sustain electrode SU (1 + 3 × N), and voltage Vi4 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU (1 + 3 × N).

  During this time, weak initialization is performed between scan electrode SC (1 + 3 × N) and sustain electrode SU (1 + 3 × N), and between scan electrode SC (1 + 3 × N) and data electrode D1 to data electrode Dm. Discharge occurs. Then, the negative wall voltage above scan electrode SC (1 + 3 × N) and the positive wall voltage above sustain electrode SU (1 + 3 × N) are weakened, and data electrodes D1 to D1 intersecting scan electrode SC (1 + 3 × N). The positive wall voltage on the data electrode Dm is adjusted to a value suitable for the write operation.

  The above waveform is a forced initializing waveform that generates an initializing discharge in the discharge cell regardless of the operation of the immediately preceding subfield. The above-described operation performed by applying the forced initialization waveform to the scan electrode 22 is the forced initialization operation.

  On the other hand, the voltage Vi1 is not applied to the scan electrodes 22 other than the scan electrode SC (1 + 3 × N) in the first half of the initialization period of the second SF, and remains at 0 (V), and the voltage Vi2 from 0 (V). An up-ramp voltage L1 'that gradually rises toward' is applied. This up-ramp voltage L1 'has the same slope as the up-ramp voltage L1, and continues to rise for the same time as the up-ramp voltage L1. Therefore, the voltage Vi2 'is equal to a voltage obtained by subtracting the voltage Vi1 from the voltage Vi2. At this time, each voltage and the up-ramp voltage L <b> 1 ′ are set so that the voltage Vi <b> 2 ′ is equal to or lower than the discharge start voltage with respect to the sustain electrode 23. Thereby, substantially no discharge is generated in the discharge cell to which the up-ramp voltage L1 'is applied.

  In the latter half of the initialization period, the down-ramp voltage L2 is applied to the scan electrodes 22 other than the scan electrode SC (1 + 3 × N) as well as the scan electrode SC (1 + 3 × N).

  The above waveform is a non-initializing waveform in which initializing discharge does not occur in the discharge cell. The above-described operation performed by applying the non-initializing waveform to the scan electrode 22 is the non-initializing operation.

  The forced initialization waveform in the present invention is not limited to the waveform described above. The forced initializing waveform may be any waveform as long as the initializing discharge is generated in the discharge cell regardless of the operation of the immediately preceding subfield. Further, the uninitialized waveform in the present invention is not limited to the waveform described above. The non-initialization waveform shown in the present embodiment is merely an example of a waveform that does not generate an initialization discharge in a discharge cell. For example, a waveform that does not generate an initialization discharge, such as a 0 (V) clamp waveform. Any waveform may be used.

  As described above, a forced initializing waveform is applied to a predetermined scanning electrode 22 (for example, scanning electrode SC (1 + 3 × N)), and a non-initializing waveform is applied to the other scanning electrode 22 to force a specific discharge cell. The initializing operation is performed, and the specific cell initializing operation in the initializing period of the specific cell initializing subfield in which the non-initializing operation is performed in other discharge cells is completed.

  In the subsequent address period, scan pulse voltage Va is sequentially applied to scan electrode SC1 through scan electrode SCn, and data electrode Dk (k = k = corresponding to the discharge cell to be lit) is applied to data electrode D1 through data electrode Dm. 1 to m) is applied with a positive address pulse voltage Vd to selectively generate an address discharge in each discharge cell.

  Specifically, voltage Ve is first applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vcc is applied to scan electrode SC1 through scan electrode SCn.

  Then, a negative scan pulse voltage Va is applied to the first (first row) scan electrode SC1 from the top in terms of arrangement, and a discharge cell to emit light in the first row among the data electrodes D1 to Dm. The positive address pulse voltage Vd is applied to the data electrode Dk (k = 1 to m). At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd−voltage Va) between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1. The difference is added and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. Further, since voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is maintained at the difference between the externally applied voltages (voltage Ve−voltage Va). The difference between the wall voltage on the electrode SU1 and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of data electrode D1 to data electrode Dm to which scan pulse SC1 is not applied with address pulse voltage Vd does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission.

  Specifically, first, positive sustain pulse voltage Vs is applied to scan electrode SC1 through scan electrode SCn, and a ground potential serving as a base potential, that is, 0 (V), is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the sum of the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi to sustain pulse voltage Vs. The discharge start voltage is exceeded.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. Note that no sustain discharge occurs in the discharge cells in which no address discharge has occurred during the address period.

  Subsequently, 0 (V) as the base potential is applied to scan electrode SC1 through scan electrode SCn, and sustain pulse voltage Vs is applied to sustain electrode SU1 through sustain electrode SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage, so that a sustain discharge occurs again between sustain electrode SUi and scan electrode SCi, and the sustain cell is maintained. Negative wall voltage is accumulated on electrode SUi, and positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn, and a potential difference is generated between the electrodes of display electrode pair 24. give. As a result, the sustain discharge is continuously generated in the discharge cells that have caused the address discharge in the address period.

  Then, after the sustain pulse is generated in the sustain period, 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm, and scan electrode SC1 through scan electrode SCn are supplied with the base potential. A ramp voltage (hereinafter referred to as “erase ramp voltage”) L3 that gently rises from a certain 0 (V) to a voltage Vers that is a predetermined potential (for example, with a gradient of about 10 V / μsec) is applied. Note that the voltage Vers which is a predetermined potential is set to a voltage exceeding the discharge start voltage. Thereby, a weak discharge is continuously generated between the sustain electrode SUi and the scan electrode SCi of the discharge cell in which the sustain discharge has occurred. The charged particles generated by the weak discharge are accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to reduce the voltage difference between the sustain electrode SUi and the scan electrode SCi. Go. As a result, while the positive wall voltage on the data electrode Dk remains, the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi are the difference between the voltage applied to the scan electrode SCi and the discharge start voltage, for example ( The voltage Vers minus the discharge start voltage).

  Thereafter, the voltage applied to scan electrode SC1 through scan electrode SCn is returned to 0 (V), and the sustain operation in the sustain period ends.

  Next, the selective initialization subfield will be described using the third SF as an example.

  In the initialization period of the third SF, the selective initialization waveform is applied to all the scan electrodes 22. The selective initialization waveform in the present embodiment is a drive voltage waveform in which the first half of the forced initialization waveform is omitted. Specifically, voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and 0 (V) is applied to data electrode D1 through data electrode Dm. Scan electrode SC1 to scan electrode SCn receive down-ramp voltage L4 that decreases from the voltage (for example, 0 (V)) lower than the discharge start voltage toward negative voltage Vi4 at the same gradient as down-ramp voltage L2. Apply.

  As a result, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the immediately preceding subfield (second SF in FIG. 3), and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. The wall voltage above the data electrode Dk (k = 1 to m) is also adjusted to a value suitable for the write operation.

  The waveform described above is a selective initialization waveform in which an initializing discharge is generated only in a discharge cell that has generated a sustaining discharge in the sustaining period of the immediately preceding subfield. The above-described operation performed by applying the selective initialization waveform to all the scan electrodes 22 is the selective initialization operation.

  This completes the selective initialization operation in the initialization period of the selective initialization subfield.

  The selective initialization waveform in the present invention is not limited to the waveform described above. The selective initialization waveform may be any waveform as long as it generates a reset discharge only in a discharge cell that has generated a sustain discharge in the sustain period of the immediately preceding subfield. For example, in the present embodiment, the configuration in which the down-ramp voltage L4 is generated with the same gradient has been described. However, the down-ramp voltage L4 is divided into a plurality of periods, and the gradient is changed in each period to generate the down-ramp voltage L4. It is good also as a structure.

  In the address period of the third SF, a drive voltage waveform similar to that in the address period of the second SF is applied to each electrode. Further, in the sustain period of the third SF, the same drive voltage waveform as that in the sustain period of the second SF is applied to each electrode except for the number of sustain pulses generated.

  In the subfields after the fourth SF, the same drive voltage waveform as that of the third SF is applied to each electrode except for the number of sustain pulses generated in the sustain period.

  Next, the first SF with the luminance weight “0.25” will be described. In the present embodiment, the subfield having the luminance weight “0.25” is also referred to as “slight emission subfield” because light emission in the sustain period is weaker than light emission by the sustain pulse. In the present embodiment, not the specific cell initialization subfield but the selective initialization subfield is a light emission subfield.

  In the present embodiment, the first SF is a light emission subfield and a selective initialization subfield. Therefore, in the initializing period of the first SF, a driving voltage waveform similar to that of the initializing period of the third SF is applied to each electrode. In the first SF address period, the same drive voltage waveform as in the second SF and third SF address periods is applied to each electrode.

  In the sustain period of the first SF, the sustain pulse is not generated, but only the erase ramp voltage L3 is generated and applied to the scan electrodes SC1 to SCn, and only the weak discharge due to the erase ramp voltage L3 is generated.

  Specifically, while maintaining the data electrode D1 to the data electrode Dm and the sustain electrode SU1 to the sustain electrode SUn at 0 (V), the base potential is gradually reduced from 0 (V) to the predetermined voltage Vers ( For example, an erasing ramp voltage L3 that rises (with a gradient of about 10 V / μsec) is generated and applied to scan electrode SC1 through scan electrode SCn.

  Then, in the discharge cell in which the address discharge has occurred in the address period, the voltage difference between the scan electrode SCi and the sustain electrode SUi is changed to the difference between the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi. The voltage L3 is added. As a result, the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage while erasing ramp voltage L3 is rising, and a weak discharge occurs between scan electrode SCi and sustain electrode SUi. When the increasing voltage reaches voltage Vers, the voltage applied to scan electrode SC1 through scan electrode SCn is decreased to 0 (V). Thus, the first SF maintenance period ends.

  In the present embodiment, in this way, weak light emission in which the light emission luminance is lower than the light emission luminance for one sustain pulse is generated in the sustain period of the first SF, and the first SF is emitted more than the luminance weight “1”. The luminance weight “0.25” is low. However, as described above, the luminance weight “0.25” does not mean that the luminance luminance is ¼ of the luminance weight “1”, but the luminance luminance is simply higher than the luminance weight “1”. It just represents low.

  As a result, it is possible to use the light emission subfield having a light emission luminance lower than the luminance weight “1” for image display. Therefore, it is possible to display the gradation of the dark region in the display image more finely than in the configuration not using the fine light emission subfield, and the image display quality in the plasma display device 1 can be further improved. .

  The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  FIG. 4 is a diagram showing an example of generation patterns of forced initialization waveforms and non-initialization waveforms according to the embodiment of the present invention. FIG. 4 shows an example of generation patterns of forced initializing waveforms and non-initializing waveforms when the frequency of performing the forced initializing operation in each discharge cell is once every six fields. In FIG. 4, the horizontal axis represents the field, and the vertical axis represents the scanning electrode 22. In the example shown in FIG. 4, the second SF is set as the specific cell initialization subfield or the non-initialization subfield described above, and the remaining subfields (first SF, third SF to ninth SF) are set as the selective initialization subfield described above. A field.

  Further, “◯” shown in FIG. 4 indicates that the forced initialization operation is performed in the initialization period of the second SF, that is, the forced initialization waveform having the up-ramp voltage L1 and the down-ramp voltage L2 shown in FIG. “×” indicates that the above-described non-initialization operation is performed in the initialization period of the second SF, that is, the up-ramp voltage L1 ′ and the down-ramp voltage L2 shown in FIG. This indicates that a non-initializing waveform having the following is applied to the scan electrode 22.

  Hereinafter, scan electrode SCi to scan electrode SCi + 2 and j field to j + 5 field will be described as examples.

  First, in the second SF of the j field, a forced initialization waveform is applied to scan electrode SCi, and a non-initialization waveform is applied to scan electrode SCi + 1 and scan electrode SCi + 2.

  In the subsequent second SF of the j + 1 field, a non-initializing waveform is applied to all the scan electrodes 22.

  In the subsequent second SF of j + 2 field, a forced initialization waveform is applied to scan electrode SCi + 1, and a non-initialization waveform is applied to scan electrode SCi and scan electrode SCi + 2.

  In the subsequent second SF of the j + 3 field, an uninitialized waveform is applied to all the scan electrodes 22.

  In the subsequent second SF of j + 4 field, a forced initialization waveform is applied to scan electrode SCi + 2, and a non-initialization waveform is applied to scan electrode SCi and scan electrode SCi + 1.

  In the subsequent second SF of j + 5 field, the uninitialized waveform is applied to all the scan electrodes 22.

  Thus, one of the repeated operations in scan electrode SCi to scan electrode SCi + 2 is completed. The same operation as described above is performed for the other scan electrodes 22 and thereafter, the same operation as described above is repeated in each field. In the configuration shown in FIG. 4, j field, j + 2 field, j + 4 field,... Are specific cell initialization fields, and j + 1 field, j + 3 field, j + 5 field,. Become.

  As described above, in the example shown in FIG. 4, the forced initializing waveform and the non-initializing waveform are selectively generated so that the number of times that the forced initializing operation is performed in each discharge cell is once in six fields. 10 is driven. This reduces the frequency of performing the forced initialization operation in each discharge cell as compared with the configuration in which the forced initialization operation is performed in all the discharge cells for each field (in the example illustrated in FIG. 4, the frequency is reduced to 1/6). And the black luminance of the display image can be reduced.

  Further, in the configuration in which the forced initialization waveforms are generated so that the number of scan electrodes 22 to which the forced initialization waveforms are applied is equal to each other in each specific cell initialization subfield as shown in FIG. Compared to a configuration in which all the discharge cells are forcibly initialized in one field and uninitialized in all the discharge cells in the remaining five fields, a fine flicker called “flicker” appears in the display image. Generation | occurrence | production can be reduced.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 5 is a circuit block diagram of plasma display device 1 according to one embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode driving circuit 42, a scanning electrode driving circuit 43, a sustain electrode driving circuit 44, a timing generation circuit 45, and a power source that supplies power necessary for each circuit block. A circuit (not shown) is provided.

  The image signal processing circuit 41 converts the input image signal sig into subfield data indicating light emission / non-light emission for each subfield according to the number of pixels of the panel 10.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and each circuit block (image signal processing circuit 41, data electrode driving circuit 42). To the scan electrode drive circuit 43 and the sustain electrode drive circuit 44).

  The data electrode driving circuit 42 converts the subfield data for each subfield into signals corresponding to the data electrodes D1 to Dm, and based on the timing signals supplied from the timing generation circuit 45, the data electrodes D1 to data. The electrode Dm is driven.

  Scan electrode driving circuit 43 is an initialization waveform generating circuit for generating an initialization waveform to be applied to scan electrode SC1 to scan electrode SCn in the initialization period, and a sustain pulse to be applied to scan electrode SC1 to scan electrode SCn in the sustain period. And a plurality of scan electrode driving ICs (hereinafter abbreviated as “scan ICs”), and a scan for generating scan pulses to be applied to scan electrode SC1 through scan electrode SCn in the address period It has a pulse generation circuit. Then, each scan electrode SC1 to scan electrode SCn is driven based on the timing signal supplied from the timing generation circuit 45.

  Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve, and drives sustain electrode SU1 through sustain electrode SUn based on a timing signal supplied from timing generation circuit 45.

  Next, details and operation of the scan electrode drive circuit 43 will be described.

  FIG. 6 is a circuit diagram showing a configuration example of scan electrode driving circuit 43 of plasma display device 1 in accordance with the exemplary embodiment of the present invention. The scan electrode drive circuit 43 includes a sustain pulse generation circuit 50 that generates a sustain pulse, an initialization waveform generation circuit 51 that generates an initialization waveform, and a scan pulse generation circuit 52 that generates a scan pulse. Each output terminal is connected to each of scan electrode SC1 to scan electrode SCn of panel 10. In the present embodiment, the voltage input to scan pulse generating circuit 52 is referred to as “reference potential A”. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for cutting off the switching element is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”.

  In FIG. 6, when a circuit using the negative voltage Va (for example, the Miller integrating circuit 54) is operated, the circuit, the sustain pulse generating circuit 50, and a circuit using the voltage Vr (for example, A separation circuit using a switching element Q7 for electrically separating the Miller integration circuit 53) and a circuit using the voltage Vers (for example, the Miller integration circuit 55) is shown. Further, when a circuit using the voltage Vr (for example, the Miller integrating circuit 53) is operated, the circuit and a circuit using the voltage Vers having a voltage lower than the voltage Vr (for example, the Miller integrating circuit 55) 2 shows a separation circuit using a switching element Q6 for electrically separating the two.

  Sustain pulse generation circuit 50 includes a power recovery circuit and a clamp circuit that are generally used. Based on a timing signal output from timing generation circuit 45, sustain pulse generation circuit 50 switches a switching element provided therein to generate a sustain pulse. . In FIG. 6, details of the signal path of the timing signal are omitted.

  Scan pulse generation circuit 52 includes switching elements QH1 to QHn and switching elements QL1 to QLn for applying a scan pulse to each of n scan electrodes SC1 to SCn. One terminal of the switching element QHj (j = 1 to n) and one terminal of the switching element QLj are connected to each other, and the connecting portion serves as an output terminal of the scan pulse generating circuit 52, and is connected to the scan electrode SCj. It is connected. The other terminal of the switching element QHj is an input terminal INb, and the other terminal of the switching element QLj is an input terminal INa. Switching element QH1 to switching element QHn and switching element QL1 to switching element QLn are integrated into a plurality of ICs for each of a plurality of outputs. This IC is a scanning IC.

  The scan pulse generation circuit 52 includes a switching element Q5 for connecting the reference potential A to the negative voltage Va in the address period, a power supply VSC for generating the voltage Vc in which the voltage Vsc is superimposed on the reference potential A, a diode D31 and a capacitor C31. The voltage Vc is connected to the input terminals INb of the switching elements QH1 to QHn, and the reference potential A is connected to the input terminals INa of the switching elements QL1 to QLn.

  In the scan pulse generation circuit 52 configured as described above, in the address period, the switching element Q5 is turned on to make the reference potential A equal to the negative voltage Va, and the negative voltage Va is applied to the input terminal INa. A voltage Vc (voltage Vcc shown in FIG. 3) which is equal to voltage Va + voltage Vsc is applied to INb. Then, based on the subfield data, for the scan electrode SCi to which the scan pulse is applied, the switching element QHi is turned off and the switching element QLi is turned on, so that the negative polarity is applied to the scan electrode SCi via the switching element QLi. For the scan electrode SCh to which the scan pulse voltage Va is applied and no scan pulse is applied (h is 1 to n excluding i), the switching element QLh is turned off and the switching element QHh is turned on. Thus, the voltage Va + voltage Vsc is applied to the scan electrode SCh via the switching element QHh.

  Scan pulse generation circuit 52 is controlled by timing generation circuit 45 to output the voltage waveform of sustain pulse generation circuit 50 during the sustain period.

  Initialization waveform generation circuit 51 includes Miller integration circuit 53, Miller integration circuit 54, and Miller integration circuit 55. In FIG. 6, the input terminal of Miller integrating circuit 53 is shown as input terminal IN1, the input terminal of Miller integrating circuit 54 is shown as input terminal IN2, and the input terminal of Miller integrating circuit 55 is shown as input terminal IN3. Miller integrating circuit 53 and Miller integrating circuit 55 are ramp voltage generating circuits that generate rising ramp voltages, and Miller integrating circuit 54 is a ramp voltage generating circuit that generates falling ramp voltages.

  Miller integrating circuit 53 has switching element Q1, capacitor C1, and resistor R1, and during initialization operation, reference potential A of scan electrode driving circuit 43 is gradually ramped up to voltage Vi2 ′ (for example, 0.5 V). To increase the ramp voltage L1 ′.

  Miller integrating circuit 55 includes switching element Q3, capacitor C3, and resistor R3, and at the end of the sustain period, reference potential A reaches voltage Vers with a steeper slope (eg, 10 V / μsec) than up-ramp voltage L1. The erasing ramp voltage L3 is generated by raising the voltage.

  Miller integrating circuit 54 has switching element Q2, capacitor C2, and resistor R2, and during initializing operation, reference potential A is gradually ramped up to voltage Vi4 (for example, with a gradient of −0.5 V / μsec). The down ramp voltage L2 and the down ramp voltage L4 are generated by lowering.

  Next, an operation for generating a forced initialization waveform and a non-initialization waveform in the initialization period of the specific cell initialization subfield will be described with reference to FIG.

  FIG. 7 is a timing chart for explaining an example of the operation of scan electrode drive circuit 43 in the initialization period of the specific cell initialization subfield in one embodiment of the present invention. In this drawing, the scan electrode 22 to which the forced initializing waveform is applied is represented as “scan electrode SCx”, and the scan electrode 22 to which the non-initializing waveform is applied is represented as “scan electrode SCy”.

  Although the description of the operation of scan electrode driving circuit 43 when generating the selective initialization waveform in the selective initialization subfield is omitted, the operation of generating down-ramp voltage L4, which is the selective initialization waveform, is shown in FIG. It is assumed that the operation is the same as that for generating the down-ramp voltage L2 shown in FIG. The non-initializing operation in the non-initializing subfield is an operation in which a non-initializing waveform is generated and applied to all the scan electrodes 22 in the initializing period. The description of the operation of the electrode drive circuit 43 is also omitted. FIG. 7 also shows an operation for generating the erase ramp voltage L3.

  In FIG. 7, the initialization period is divided into four periods indicated by periods T <b> 1 to T <b> 4, and each period is described. The periods for generating the erase ramp voltage L <b> 3 are indicated as periods T <b> 11 and T <b> 12. Hereinafter, it is assumed that the voltage Vi1 is equal to the voltage Vsc, the voltage Vi2 is equal to the voltage Vsc + the voltage Vr, the voltage Vi2 ′ is equal to the voltage Vr, and the voltage Vi3 is the voltage Vs used when generating the sustain pulse. In the following description, it is assumed that the voltage Vi4 is equal to the negative voltage Va. In the drawing, a signal for turning on the switching element is represented as “Hi” and a signal for turning off the switching element is represented as “Lo”.

  FIG. 7 shows an example in which the voltage Vs is set to a voltage value higher than the voltage Vsc, but the voltage Vs and the voltage Vsc may be equal to each other, or the voltage Vs The voltage value may be lower than the voltage Vsc.

  First, before entering the period T1, the clamp circuit of the sustain pulse generating circuit 50 is operated to set the reference potential A to 0 (V), the switching elements QH1 to QHn are turned off, and the switching elements QL1 to QLn are turned on. Turn on and apply the reference potential A, that is, 0 (V) to scan electrode SC1 through scan electrode SCn. Further, the switching element Q6 is turned off, and the Miller integrating circuit 55 is electrically separated. Although not shown, the switching element Q7 is turned on.

(Period T1)
In the period T1, the switching element QHx connected to the scan electrode SCx is turned on and the switching element QLx is turned off. Thus, the voltage Vc (that is, the voltage Vc = the voltage Vsc) obtained by superimposing the voltage Vsc on the reference potential A (0 (V) at this time) is applied to the scan electrode SCx to which the forced initialization waveform is applied.

  On the other hand, switching element QHy connected to scan electrode SCy remains off, and switching element QLy remains on. Thereby, the reference potential A, that is, 0 (V) is applied to the scan electrode SCy to which the uninitialized waveform is applied.

(Period T2)
In the period T2, the switching elements QH1 to QHn and the switching elements QL1 to QLn maintain the same state as the period T1. That is, switching element QHx connected to scan electrode SCx is kept on, switching element QLx is kept off, switching element QHy connected to scan electrode SCy is kept off, and switching element QLy is kept on.

  Next, the input terminal IN1 of the Miller integrating circuit 53 that generates the up-ramp voltage L1 'is set to "Hi". Specifically, a predetermined constant current is input to the input terminal IN1. As a result, a constant current flows toward the capacitor C1, the source voltage of the switching element Q1 rises in a ramp shape, and the reference potential A starts to rise in a ramp shape from 0 (V). This voltage increase can be continued while the input terminal IN1 is set to “Hi” or until the reference potential A reaches the voltage Vr.

  At this time, a constant current input to the input terminal IN1 is generated so that the gradient of the ramp voltage becomes a desired value (for example, 0.5 V / μsec). In this way, the up-ramp voltage L1 'rising from 0 (V) toward the voltage Vi2' (equal to the voltage Vr in the present embodiment) is generated.

  Since the switching element QHy is off and the switching element QLy is on, the up-ramp voltage L1 'is applied to the scan electrode SCy as it is.

  On the other hand, since switching element QHx is on and switching element QLx is off, scan electrode SCx has a voltage Vsc superimposed on this up-ramp voltage L1 ′, that is, voltage Vi1 (in this embodiment, equal to voltage Vsc). ) To the voltage Vi2 (in this embodiment, equal to the voltage Vsc + the voltage Vr), the rising ramp voltage L1 is applied.

(Period T3)
In the period T3, the input terminal IN1 is set to “Lo”. Specifically, the constant current input to the input terminal IN1 is stopped. Thus, the operation of Miller integrating circuit 53 is stopped. Further, switching element QH1 to switching element QHn are turned off, switching element QL1 to switching element QLn are turned on, and reference potential A is applied to scan electrode SC1 to scan electrode SCn. At the same time, the clamp circuit of sustain pulse generating circuit 50 is operated to set reference potential A to voltage Vs. Thereby, the voltage of scan electrode SC1 through scan electrode SCn is reduced to voltage Vi3 (equal to voltage Vs in the present embodiment).

(Period T4)
In the period T4, the switching elements QH1 to QHn and the switching elements QL1 to QLn maintain the same state as the period T3. Although not shown, the switching element Q7 is turned off.

  Next, the input terminal IN2 of the Miller integrating circuit 54 that generates the down-ramp voltage L2 is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN2. As a result, a constant current flows toward the capacitor C2, the drain voltage of the switching element Q2 starts to decrease in a ramp shape, and the output voltage of the scan electrode driving circuit 43 also decreases in a ramp shape toward the negative voltage Vi4. start. This voltage drop can be continued while the input terminal IN2 is set to “Hi” or until the reference potential A reaches the voltage Va.

  At this time, a constant current input to the input terminal IN2 is generated so that the gradient of the ramp voltage becomes a desired value (for example, −0.5 V / μsec).

  When the output voltage of the scan electrode driving circuit 43 reaches the negative voltage Vi4 (equal to the voltage Va in this embodiment), the input terminal IN2 is set to “Lo”. Specifically, the constant current input to the input terminal IN2 is stopped. Thus, the operation of Miller integrating circuit 54 is stopped.

  Thus, the ramp-down voltage L2 that decreases from the voltage Vi3 (equal to the voltage Vs in the present embodiment) toward the negative voltage Vi4 is generated and applied to the scan electrodes SC1 to SCn.

  When the operation of Miller integrating circuit 54 is stopped by setting input terminal IN2 to “Lo”, switching element Q5 is turned on and reference potential A is set to voltage Va. At the same time, switching elements QH1 to QHn are turned on, and switching elements QL1 to QLn are turned off. Thus, the voltage Vc obtained by superimposing the voltage Vsc on the reference potential A, that is, the voltage Vcc (in this embodiment, equal to the voltage Va + the voltage Vsc) is applied to the scan electrodes SC1 to SCn to prepare for the subsequent address period.

  In this embodiment, the forced initializing waveform and the non-initializing waveform are generated in the initializing period of the specific cell initializing subfield in this way. Then, by controlling switching element QH1 to switching element QHn and switching element QL1 to switching element QLn, a forced initialization waveform is applied to scan electrode SCx, and a non-initialization waveform is applied to scan electrode SCy. As described above, the forced initializing waveform and the non-initializing waveform can be selectively applied to the scan electrode 22. Similarly, only the non-initializing waveform can be generated and applied to all the scanning electrodes 22 in the initializing period of the non-initializing subfield.

  The down-ramp voltage L2 and the down-ramp voltage L4 may be configured to decrease to the voltage Va as shown in FIG. 7, but the decreasing voltage reaches, for example, a voltage obtained by superimposing the voltage Vset2 on the voltage Va. At this point, the descent may be stopped. Further, the down-ramp voltage L2 and the down-ramp voltage L4 may be configured to increase immediately after reaching a preset voltage. For example, when the decreasing voltage reaches a preset low voltage, Thereafter, the voltage may be maintained for a certain period.

  Next, an operation for generating the erase ramp voltage L3 will be described.

(Period T11)
In period T11, switching element QH1 to switching element QHn are turned off, switching element QL1 to switching element QLn are turned on, and reference potential A is connected to scan electrode SC1 to scan electrode SCn. Further, the switching element Q6 is turned on, and the Miller integrating circuit 55 is connected to the reference potential A.

  Next, the input terminal IN3 of the Miller integrating circuit 55 that generates the erasing ramp voltage L3 is set to “Hi”. Specifically, a predetermined constant current is input to the input terminal IN3. Thus, a constant current flows toward the capacitor C3, the source voltage of the switching element Q3 increases in a ramp shape, and the reference potential A starts to increase in a ramp shape from 0 (V). This voltage increase can be continued while the input terminal IN3 is set to “Hi” or until the reference potential A reaches the voltage Vers.

  At this time, a constant current input to the input terminal IN3 is generated so that the gradient of the ramp voltage becomes a desired value (for example, 10 V / μsec). Thus, the erase ramp voltage L3 rising from 0 (V) toward the voltage Vers is generated and applied to scan electrode SC1 through scan electrode SCn. The voltage Vers may be a voltage equal to or higher than the voltage Vs, or may be a voltage equal to or lower than the voltage Vs.

(Period T12)
After the erasing ramp voltage L3 reaches the voltage Vers, the input terminal IN3 is set to “Lo”. Specifically, the constant current input to the input terminal IN3 is stopped. Thus, the operation of Miller integrating circuit 55 is stopped. At the same time, the switching element Q6 is turned off. Although not shown, the clamp circuit of sustain pulse generating circuit 50 is operated to connect reference potential A to 0 (V). As a result, the voltage of scan electrode SC1 through scan electrode SCn drops to 0 (V), which is the base potential.

  As described above, the scan electrode driving circuit 43 generates the rising ramp voltage L1, the rising ramp voltage L1 ', the falling ramp voltage L2, and the erasing ramp voltage L3.

  Next, a combination of light emission in each subfield in the present embodiment will be described.

  As described above, in this embodiment, the frequency of performing the forced initialization operation in each discharge cell is set to once in a plurality of fields (for example, 6 fields). As a result, the black luminance in the display image is reduced and the contrast is increased as compared with the configuration in which the forced initialization operation is performed at a rate of once per field.

  However, when the black luminance is reduced, the emission luminance when the total number of sustain pulses generated in one field is 0 (tone value “0”) and the total number of sustain pulses generated in one field are 1 (tone value “ 1 "), the ratio to the light emission luminance is larger than when the black luminance is high (for example, a configuration in which the forced initialization operation is performed once per field).

  Then, the brightness difference between the gradation value “0” and the gradation value “1” in the display image with reduced black luminance is determined by the user so that the gradation value “0” and the gradation in the display image with high black luminance are obtained. It is recognized that the luminance difference is larger than the value “1”, and it is felt that the smoothness and fineness in the dark area of the display image are impaired.

  Therefore, as described above, in this embodiment, the luminance weight in which the emission luminance is reduced from the luminance weight “1” so that the black luminance can be reduced without impairing the smoothness and fineness in the dark area of the display image. A first SF of “0.25” is provided so that gradation values between gradation value “0” and gradation value “1” can be displayed.

  Here, if the wall charge remaining in the discharge cell is insufficient during the address period, an address failure occurs due to the lack of wall charge during the address operation, and the sustain discharge does not occur (hereinafter, the sustain discharge occurs regardless of the presence or absence of the address operation). A discharge cell that does not occur may be referred to as a “non-lighted cell”).

  In the discharge cell in which the weak discharge is generated by the erase lamp voltage L3 in the first SF, the wall charge is reduced by the weak discharge. Then, since the forced initializing operation is not performed in the discharge cell that performs the non-initializing operation, when the weak discharge due to the erasing ramp voltage L3 occurs in the first SF and the wall charge is reduced, the address continues in the state of the wall charge. It will move to the period. As a result, the wall charges are insufficient, writing failure occurs, and the discharge cells may become unlit cells.

  Therefore, in the present embodiment, in a discharge cell that generates a weak discharge with the erase lamp voltage L3 in the first SF, in all the subfields after the first SF of the field (in the present embodiment, the second SF to the ninth SF). It is assumed that no address discharge is generated and no sustain discharge is generated. Further, in a discharge cell that generates a sustain discharge in any one of the subfields after the first SF (second SF to ninth SF in this embodiment), an address discharge is generated in the first SF of the field. It is assumed that the weak discharge due to the erase lamp voltage L3 is not generated.

  FIG. 8 is a diagram showing the correspondence between light emission and non-light emission of each subfield at each gradation value in one embodiment of the present invention. In FIG. 8, “1” indicates that a write operation is performed, and “0” indicates that a write operation is not performed.

  In the present embodiment, as shown in FIG. 8, the luminance weight “0.25” is displayed only when a gradation value larger than the gradation value “0” and less than the gradation value “1” is displayed. It is assumed that an address operation is performed in 1SF to generate a weak discharge due to the erase lamp voltage L3. Then, when a gradation value of gradation value “1” or higher is displayed, the writing operation is not performed in the first SF.

  As a result, in the discharge cells that generate weak discharge due to the erasing ramp voltage L3 in the first SF, the address operation is not performed in the subfields after the first SF of the field, so that generation of unlit cells can be prevented.

  Thus, in the driving method of the panel 10 that reduces the frequency of the forced initialization operation and reduces the black luminance in the display image, the gradation of the dark region is displayed more finely while reducing the occurrence of unlit cells. Is possible.

  Since the emission luminance of the first SF is weak compared to the emission luminance of the other subfields, there is no problem even if the first SF is not emitted when emitting light in any of the subfields after the second SF. Absent.

  In order to display a gradation value between the gradation value “0” and the gradation value “1” (shown as gradation value “0.25” in FIG. 8), the following method is used. Can be used. When the image signal is 8 bits, the image signal has 256 gradation levels from a gradation value “0” to a gradation value “255”. Therefore, for example, in the image signal processing circuit 41, the image signal is temporarily expanded to 10 bits to obtain 1024 levels of gradation from the gradation value “0” to the gradation value “1023”. Perform signal processing. Only the first SF with the luminance weight “0.25” is emitted for the gradation values from the gradation value “1” to the gradation value “3”. For the gradation value “4” or more, each gradation value is divided by 4, for example, any decimal gradation value from the gradation value “1” to the gradation value “255” is rounded down. As shown in FIG. 8, the subfields of the second SF to the ninth SF are made to emit light or not emit light according to each gradation value. For example, if such a method is used, each discharge cell can be caused to emit light by dividing into gradation values for emitting only the first SF and gradation values for emitting the second to ninth SFs.

  As described above, in the present embodiment, the frequency of performing the forced initializing operation in each discharge cell is reduced to once in a plurality of fields (for example, once in 6 fields), and the weakness caused by the erase ramp voltage L3. One light emitting subfield that generates only discharge is provided in one field. In a discharge cell that generates a weak discharge due to the erasing lamp voltage L3 in the low light emission subfield, the address operation is not performed in all the subfields after the low light emission subfield of the field, and no sustain discharge is generated. . Further, in a discharge cell that generates a sustain discharge in any one of the subfields after the light emission subfield, an address discharge is not generated in the light emission subfield of that field, and a weak discharge caused by the erase lamp voltage L3. Shall not be generated.

  As a result, it is possible to reduce the black luminance in the display image and increase the contrast, and to perform image display using the subfield of the luminance weight “0.25” whose emission luminance is lower than the luminance weight “1”. While preventing the generation of non-lighted cells, it is possible to display the gradation of the dark region in the display image more finely and improve the image display quality in the plasma display device 1.

  The light emission luminance of each subfield is actually “light emission luminance due to address discharge + light emission luminance during the sustain period”. In a subfield having a large luminance weight, the light emission luminance in the sustain period is high, so that the proportion of the light emission luminance due to the address discharge in the light emission luminance of the subfield is substantially negligible. However, in a subfield with a small luminance weight, the emission luminance in the sustain period is low, so the proportion of the emission luminance due to address discharge in the emission luminance of that subfield is relatively high. Accordingly, the light emission luminance of the first SF having the luminance weight “0.25” is actually a brightness obtained by adding “light emission luminance due to address discharge” to “light emission luminance due to weak discharge of the erase lamp voltage L3”.

  In this embodiment, the erase ramp voltage L3 generated during the sustain period of the first SF has the same waveform shape as the erase ramp voltage L3 generated at the end of the sustain period of the other subfields, but they are different from each other. It may be a wave shape.

  In the present invention, the subfields constituting the field are not limited to the above-described three types of subfields: the specific cell initialization subfield, the non-initialization subfield, and the selective initialization subfield. For example, an all-cell initializing subfield for performing a forced initializing operation on all discharge cells is further provided. In addition to the above-described two types of fields (specific cell initializing field and non-initializing field), a new field (for example, An all-cell initialization field may be provided in which the second SF is an all-cell initialization subfield and another subfield is a selective initialization subfield.

  In the present embodiment, an example in which the non-initialized field and the specific cell initializing field are alternately generated has been described. However, for example, all the fields may be used as the specific cell initializing field. Alternatively, the all-cell initialization field may be generated periodically.

  Note that the generation pattern of the forced initialization waveform and the non-initialization waveform in the specific cell initialization subfield shown in the present embodiment is merely an example, and the present invention has no configuration. It is not limited to. Any configuration other than that shown in the present embodiment may be used as long as it can change the frequency of occurrence of the forced initialization waveform.

  Note that the timing chart shown in FIG. 7 is merely an example in the embodiment of the present invention, and the present invention is not limited to these timing charts.

  In the embodiment of the present invention, scan electrode SC1 to scan electrode SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is a scan electrode belonging to the first scan electrode group. Of the panel by so-called two-phase driving, which includes a first address period in which a scan pulse is applied to each of the first and second address periods in which a scan pulse is applied to each of the scan electrodes belonging to the second scan electrode group. The present invention can also be applied to a driving method.

  In the embodiment of the present invention, the scan electrode and the scan electrode are adjacent to each other, and the sustain electrode and the sustain electrode are adjacent to each other, that is, the arrangement of the electrodes provided on the front plate is “... , Scan electrode, sustain electrode, sustain electrode, scan electrode, scan electrode,...

  Note that the specific numerical values shown in the present embodiment, for example, the gradient of each ramp voltage of the up-ramp voltage L1, the down-ramp voltage L2, the erase ramp voltage L3, and the down-ramp voltage L4 are 50 of the display electrode pair 1080. It is set based on the characteristics of the inch panel and is merely an example of the embodiment. The present invention is not limited to these numerical values, and is desirably set optimally according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  The present invention can improve the image display quality by reducing the black luminance of the display image to increase the contrast and preventing the occurrence of non-lighted cells and displaying the gradation of the dark area in the display image more finely. Therefore, it is useful as a panel driving method and a plasma display device.

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 50 sustain pulse generation circuit 51 initialization waveform generation circuit 52 scan pulse generation circuit 53, 54, 55 Miller integration circuit Q1, Q2, Q3, Q5 , Q6, Q7, QH1 to QHn, QL1 to QLn Switching element C1, C2, C3, C31 Capacitor D31 Diode R1, R2, R3 Resistance L1 Up-ramp voltage L2, L4 Down-ramp voltage L3 Erase lamp voltage

Claims (5)

A plasma display panel having a plurality of discharge cells each having a display electrode pair and a data electrode each consisting of a scan electrode and a sustain electrode, and an initializing period, a scan pulse is applied to the scan electrode, and the data electrode is selectively An address period in which an address pulse is applied to generate an address discharge in a discharge cell to emit light, and a sustain period in which a sustain pulse is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell. A method of driving a plasma display panel in which a plurality of subfields having a plurality of subfields are provided in one field, and one field is configured to have a specific cell initializing subfield and a selective initializing subfield to display gray scales. And
In the initializing period of the specific cell initializing subfield, a scan electrode that applies a forced initializing waveform for generating an initializing discharge in the discharge cell, and a non-initializing waveform that does not generate an initializing discharge in the discharge cell are provided. In the initializing period of the selective initializing subfield, a selective initializing waveform for generating an initializing discharge only in the discharge cell in which the sustaining discharge has occurred in the sustaining period of the immediately preceding subfield is present. Applied to all the scanning electrodes,
In the selective initialization subfield, the light emission sub-field in which, during the sustain period, the sustain pulse is not applied to the display electrode pair, and a ramp voltage that rises from a base potential to a predetermined potential is applied to all the scan electrodes. There are fields,
The plasma display panel is characterized in that the address pulse is not applied to the discharge cells to which the address pulse is applied in the address period of any subfield after the light emission subfield. Driving method. A plasma display panel having a plurality of discharge cells each having a display electrode pair and a data electrode each consisting of a scan electrode and a sustain electrode, and an initializing period, a scan pulse is applied to the scan electrode, and the data electrode is selectively An address period in which an address pulse is applied to generate an address discharge in a discharge cell to emit light, and a sustain period in which a sustain pulse is alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell. A method of driving a plasma display panel in which a plurality of subfields having a plurality of subfields are provided in one field, and one field is configured to have a specific cell initializing subfield and a selective initializing subfield to display gray scales. And
In the initializing period of the specific cell initializing subfield, a scan electrode that applies a forced initializing waveform for generating an initializing discharge in the discharge cell, and a non-initializing waveform that does not generate an initializing discharge in the discharge cell are provided. In the initializing period of the selective initializing subfield, a selective initializing waveform for generating an initializing discharge only in the discharge cell in which the sustaining discharge has occurred in the sustaining period of the immediately preceding subfield is present. Applied to all the scanning electrodes,
In the selective initialization subfield, the light emission sub-field in which, during the sustain period, the sustain pulse is not applied to the display electrode pair, and a ramp voltage that rises from a base potential to a predetermined potential is applied to all the scan electrodes. There are fields,
The plasma display panel is characterized in that the address pulse is not applied to the discharge cells to which the address pulse is applied in the address period of the slightly light-emitting subfield in the address period of all subfields after the light-emitting subfield. Driving method. A field having the non-initializing subfield for applying the non-initializing waveform to all the scan electrodes in the initializing period and the selective initializing subfield, and having the specific cell initializing subfield 3. The method according to claim 1, wherein the non-initialized field is generated by periodically switching between the non-initialized field and the non-initialized field. A plurality of discharge cells having display electrode pairs and data electrodes each consisting of a scan electrode and a sustain electrode are provided, and a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field, and one field is an initial stage of a specific cell. A plasma display panel configured to display a gradation using one of the selective initialization subfields as a light emission subfield, and a configuration having a display subfield and a selection initialization subfield;
A data electrode driving circuit for selectively applying an address pulse to the data electrode and selectively applying the address pulse to the discharge cell during the address period;
A sustain electrode driving circuit for applying a sustain pulse to the sustain electrode during the sustain period;
In the initializing period of the specific cell initializing subfield, a scan electrode that applies a forced initializing waveform that generates initializing discharge to the discharge cell and a non-initializing waveform that does not generate initializing discharge are applied to the discharge cell. In the initializing period of the selective initializing subfield, all of the selective initializing waveforms that generate initializing discharges only in the discharge cells that have generated sustain discharges in the sustaining period of the immediately preceding subfield are mixed in the initializing period of the selective initializing subfield. A scan electrode driving circuit that applies a scan pulse to the scan electrode, applies a scan pulse to the scan electrode in the address period, and applies a sustain pulse to the scan electrode in the sustain period;
The sustain electrode drive circuit and the scan electrode drive circuit do not apply the sustain pulse to the sustain electrode and the scan electrode in the sustain period of the light emission subfield,
The scan electrode driving circuit applies a ramp voltage, which rises from a base potential to a predetermined potential, to all the scan electrodes during the sustain period of the low light emission subfield,
The data electrode driving circuit does not apply the address pulse to the discharge cell to which the address pulse is applied in the address period of any subfield after the light emission subfield during the address period of the light emission subfield. A plasma display device. A plurality of discharge cells having display electrode pairs and data electrodes each consisting of a scan electrode and a sustain electrode are provided, and a plurality of subfields having an initialization period, an address period, and a sustain period are provided in one field, and one field is an initial stage of a specific cell. A plasma display panel configured to display a gradation using one of the selective initialization subfields as a light emission subfield, and a configuration having a display subfield and a selection initialization subfield;
A data electrode driving circuit for selectively applying an address pulse to the data electrode and selectively applying the address pulse to the discharge cell during the address period;
A sustain electrode driving circuit for applying a sustain pulse to the sustain electrode during the sustain period;
In the initializing period of the specific cell initializing subfield, a scan electrode that applies a forced initializing waveform that generates initializing discharge to the discharge cell and a non-initializing waveform that does not generate initializing discharge are applied to the discharge cell. In the initializing period of the selective initializing subfield, all of the selective initializing waveforms that generate initializing discharges only in the discharge cells that have generated sustain discharges in the sustaining period of the immediately preceding subfield are mixed in the initializing period of the selective initializing subfield. A scan electrode driving circuit that applies a scan pulse to the scan electrode, applies a scan pulse to the scan electrode in the address period, and applies a sustain pulse to the scan electrode in the sustain period;
The sustain electrode drive circuit and the scan electrode drive circuit do not apply the sustain pulse to the sustain electrode and the scan electrode in the sustain period of the light emission subfield,
The scan electrode driving circuit applies a ramp voltage, which rises from a base potential to a predetermined potential, to all the scan electrodes during the sustain period of the low light emission subfield,
The data electrode driving circuit does not apply the address pulse to the discharge cells to which the address pulse is applied in the address period of the light emission subfield during the address period of all subfields after the light emission subfield. A characteristic plasma display device.

Images